[ceph.git] / ceph / src / spdk / intel-ipsec-mb / avx / mb_mgr_hmac_flush_avx.asm

;;
;; Copyright (c) 2012-2018, Intel Corporation
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;;     * Redistributions of source code must retain the above copyright notice,
;;       this list of conditions and the following disclaimer.
;;     * Redistributions in binary form must reproduce the above copyright
;;       notice, this list of conditions and the following disclaimer in the
;;       documentation and/or other materials provided with the distribution.
;;     * Neither the name of Intel Corporation nor the names of its contributors
;;       may be used to endorse or promote products derived from this software
;;       without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;

%include "os.asm"
%include "job_aes_hmac.asm"
%include "mb_mgr_datastruct.asm"
%include "reg_sizes.asm"

extern sha1_mult_avx

section .data
default rel

align 16
byteswap:	;ddq 0x0c0d0e0f08090a0b0405060700010203
	dq 0x0405060700010203, 0x0c0d0e0f08090a0b
x80:		;ddq 0x00000000000000000000000000000080
	dq 0x0000000000000080, 0x0000000000000000
x00:		;ddq 0x00000000000000000000000000000000
	dq 0x0000000000000000, 0x0000000000000000

len_masks:
	;ddq 0x0000000000000000000000000000FFFF
	dq 0x000000000000FFFF, 0x0000000000000000
	;ddq 0x000000000000000000000000FFFF0000
	dq 0x00000000FFFF0000, 0x0000000000000000
	;ddq 0x00000000000000000000FFFF00000000
	dq 0x0000FFFF00000000, 0x0000000000000000
	;ddq 0x0000000000000000FFFF000000000000
	dq 0xFFFF000000000000, 0x0000000000000000
one:	dq  1
two:	dq  2
three:	dq  3

section .text

%if 1
%ifdef LINUX
%define arg1	rdi
%define arg2	rsi
%else
%define arg1	rcx
%define arg2	rdx
%endif

%define state	arg1
%define job	arg2
%define len2	arg2


; idx needs to be in rbx, rbp, r12-r15
%define idx             rbp

%define unused_lanes    rbx
%define lane_data       rbx
%define tmp2		rbx

%define job_rax         rax
%define	tmp1		rax
%define size_offset     rax
%define tmp             rax
%define start_offset    rax

%define tmp3		arg1

%define extra_blocks    arg2
%define p               arg2

%define tmp4		r8

%endif

; This routine clobbers rbx, rbp
struc STACK
_gpr_save:	resq	2
_rsp_save:	resq	1
endstruc

%define APPEND(a,b) a %+ b

; JOB* flush_job_hmac_avx(MB_MGR_HMAC_SHA_1_OOO *state)
; arg 1 : rcx : state
MKGLOBAL(flush_job_hmac_avx,function,internal)
flush_job_hmac_avx:

        mov	rax, rsp
        sub	rsp, STACK_size
        and	rsp, -16

	mov	[rsp + _gpr_save + 8*0], rbx
	mov	[rsp + _gpr_save + 8*1], rbp
	mov	[rsp + _rsp_save], rax	; original SP

	mov	unused_lanes, [state + _unused_lanes]
	bt	unused_lanes, 32+7
	jc	return_null

	; find a lane with a non-null job
	xor	idx, idx
	cmp	qword [state + _ldata + 1 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [rel one]
	cmp	qword [state + _ldata + 2 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [rel two]
	cmp	qword [state + _ldata + 3 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [rel three]

copy_lane_data:
	; copy valid lane (idx) to empty lanes
	vmovdqa	xmm0, [state + _lens]
	mov	tmp, [state + _args_data_ptr + PTR_SZ*idx]

%assign I 0
%rep 4
	cmp	qword [state + _ldata + I * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	jne	APPEND(skip_,I)
	mov	[state + _args_data_ptr + PTR_SZ*I], tmp
	vpor	xmm0, xmm0, [rel len_masks + 16*I]
APPEND(skip_,I):
%assign I (I+1)
%endrep

	vmovdqa	[state + _lens], xmm0

	vphminposuw	xmm1, xmm0
	vpextrw	DWORD(len2), xmm1, 0	; min value
	vpextrw	DWORD(idx), xmm1, 1	; min index (0...3)
	cmp	len2, 0
	je	len_is_0

	vpshuflw xmm1, xmm1, 0
	vpsubw	xmm0, xmm0, xmm1
	vmovdqa	[state + _lens], xmm0

	; "state" and "args" are the same address, arg1
	; len is arg2
	call	sha1_mult_avx
	; state is intact

len_is_0:
	; process completed job "idx"
	imul	lane_data, idx, _HMAC_SHA1_LANE_DATA_size
	lea	lane_data, [state + _ldata + lane_data]
	mov	DWORD(extra_blocks), [lane_data + _extra_blocks]
	cmp	extra_blocks, 0
	jne	proc_extra_blocks
	cmp	dword [lane_data + _outer_done], 0
	jne	end_loop

proc_outer:
	mov	dword [lane_data + _outer_done], 1
	mov	DWORD(size_offset), [lane_data + _size_offset]
	mov	qword [lane_data + _extra_block + size_offset], 0
	mov	word [state + _lens + 2*idx], 1
	lea	tmp, [lane_data + _outer_block]
	mov	job, [lane_data + _job_in_lane]
	mov	[state + _args_data_ptr + PTR_SZ*idx], tmp

        ;; idx determines which column
        ;; read off from consecutive rows
	vmovd	xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 0*SHA1_DIGEST_ROW_SIZE]
	vpinsrd	xmm0, xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 1*SHA1_DIGEST_ROW_SIZE], 1
	vpinsrd	xmm0, xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 2*SHA1_DIGEST_ROW_SIZE], 2
	vpinsrd	xmm0, xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 3*SHA1_DIGEST_ROW_SIZE], 3
	vpshufb	xmm0, xmm0, [rel byteswap]
	mov	DWORD(tmp),  [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 4*SHA1_DIGEST_ROW_SIZE]
	bswap	DWORD(tmp)
	vmovdqa	[lane_data + _outer_block], xmm0
	mov	[lane_data + _outer_block + 4*4], DWORD(tmp)

	mov	tmp, [job + _auth_key_xor_opad]
	vmovdqu	xmm0, [tmp]
	mov	DWORD(tmp),  [tmp + 4*4]
	vmovd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 0*SHA1_DIGEST_ROW_SIZE], xmm0
	vpextrd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 1*SHA1_DIGEST_ROW_SIZE], xmm0, 1
	vpextrd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 2*SHA1_DIGEST_ROW_SIZE], xmm0, 2
	vpextrd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 3*SHA1_DIGEST_ROW_SIZE], xmm0, 3
	mov	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 4*SHA1_DIGEST_ROW_SIZE], DWORD(tmp)
	jmp	copy_lane_data

	align	16
proc_extra_blocks:
	mov	DWORD(start_offset), [lane_data + _start_offset]
	mov	[state + _lens + 2*idx], WORD(extra_blocks)
	lea	tmp, [lane_data + _extra_block + start_offset]
	mov	[state + _args_data_ptr + PTR_SZ*idx], tmp
	mov	dword [lane_data + _extra_blocks], 0
	jmp	copy_lane_data

return_null:
	xor	job_rax, job_rax
	jmp	return

	align	16
end_loop:
	mov	job_rax, [lane_data + _job_in_lane]
	mov	qword [lane_data + _job_in_lane], 0
	or	dword [job_rax + _status], STS_COMPLETED_HMAC
	mov	unused_lanes, [state + _unused_lanes]
	shl	unused_lanes, 8
	or	unused_lanes, idx
	mov	[state + _unused_lanes], unused_lanes

	mov	p, [job_rax + _auth_tag_output]

	; copy 12 bytes
	mov	DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 0*SHA1_DIGEST_ROW_SIZE]
	mov	DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 1*SHA1_DIGEST_ROW_SIZE]
	bswap	DWORD(tmp2)
	bswap	DWORD(tmp4)
	mov	[p + 0*4], DWORD(tmp2)
	mov	[p + 1*4], DWORD(tmp4)
	mov	DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 2*SHA1_DIGEST_ROW_SIZE]
	bswap	DWORD(tmp2)
	mov	[p + 2*4], DWORD(tmp2)

        cmp     qword [job_rax + _auth_tag_output_len_in_bytes], 12
        je      return

        ;; copy remaining 8 bytes to return 20 byte digest
        mov	DWORD(tmp2),  [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 3*SHA1_DIGEST_ROW_SIZE]
        mov	DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 4*SHA1_DIGEST_ROW_SIZE]
        bswap	DWORD(tmp2)
        bswap	DWORD(tmp4)
        mov	[p + 3*SHA1_DIGEST_WORD_SIZE], DWORD(tmp2)
        mov	[p + 4*SHA1_DIGEST_WORD_SIZE], DWORD(tmp4)

return:

	mov	rbx, [rsp + _gpr_save + 8*0]
	mov	rbp, [rsp + _gpr_save + 8*1]
	mov	rsp, [rsp + _rsp_save]	; original SP

	ret

%ifdef LINUX
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
Commit	Line	Data
11fdf7f2 TL	1	;;
	2	;; Copyright (c) 2012-2018, Intel Corporation
	3	;;
	4	;; Redistribution and use in source and binary forms, with or without
	5	;; modification, are permitted provided that the following conditions are met:
	6	;;
	7	;; * Redistributions of source code must retain the above copyright notice,
	8	;; this list of conditions and the following disclaimer.
	9	;; * Redistributions in binary form must reproduce the above copyright
	10	;; notice, this list of conditions and the following disclaimer in the
	11	;; documentation and/or other materials provided with the distribution.
	12	;; * Neither the name of Intel Corporation nor the names of its contributors
	13	;; may be used to endorse or promote products derived from this software
	14	;; without specific prior written permission.
	15	;;
	16	;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	19	;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
	20	;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	21	;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	22	;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	23	;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	24	;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	25	;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	;;
	27
	28	%include "os.asm"
	29	%include "job_aes_hmac.asm"
	30	%include "mb_mgr_datastruct.asm"
	31	%include "reg_sizes.asm"
	32
	33	extern sha1_mult_avx
	34
	35	section .data
	36	default rel
	37
	38	align 16
	39	byteswap: ;ddq 0x0c0d0e0f08090a0b0405060700010203
	40	dq 0x0405060700010203, 0x0c0d0e0f08090a0b
	41	x80: ;ddq 0x00000000000000000000000000000080
	42	dq 0x0000000000000080, 0x0000000000000000
	43	x00: ;ddq 0x00000000000000000000000000000000
	44	dq 0x0000000000000000, 0x0000000000000000
	45
	46	len_masks:
	47	;ddq 0x0000000000000000000000000000FFFF
	48	dq 0x000000000000FFFF, 0x0000000000000000
	49	;ddq 0x000000000000000000000000FFFF0000
	50	dq 0x00000000FFFF0000, 0x0000000000000000
	51	;ddq 0x00000000000000000000FFFF00000000
	52	dq 0x0000FFFF00000000, 0x0000000000000000
	53	;ddq 0x0000000000000000FFFF000000000000
	54	dq 0xFFFF000000000000, 0x0000000000000000
	55	one: dq 1
	56	two: dq 2
	57	three: dq 3
	58
	59	section .text
	60
	61	%if 1
	62	%ifdef LINUX
	63	%define arg1 rdi
	64	%define arg2 rsi
65	%else
66	%define arg1 rcx
67	%define arg2 rdx
68	%endif
69
70	%define state arg1
71	%define job arg2
72	%define len2 arg2
73
74
75	; idx needs to be in rbx, rbp, r12-r15
76	%define idx rbp
77
78	%define unused_lanes rbx
79	%define lane_data rbx
80	%define tmp2 rbx
81
82	%define job_rax rax
83	%define tmp1 rax
84	%define size_offset rax
85	%define tmp rax
86	%define start_offset rax
87
88	%define tmp3 arg1
89
90	%define extra_blocks arg2
91	%define p arg2
92
93	%define tmp4 r8
94
95	%endif
96
97	; This routine clobbers rbx, rbp
98	struc STACK
99	_gpr_save: resq 2
100	_rsp_save: resq 1
101	endstruc
102
103	%define APPEND(a,b) a %+ b
104
105	; JOB* flush_job_hmac_avx(MB_MGR_HMAC_SHA_1_OOO *state)
106	; arg 1 : rcx : state
107	MKGLOBAL(flush_job_hmac_avx,function,internal)
108	flush_job_hmac_avx:
109
110	mov rax, rsp
111	sub rsp, STACK_size
112	and rsp, -16
113
114	mov [rsp + _gpr_save + 8*0], rbx
115	mov [rsp + _gpr_save + 8*1], rbp
116	mov [rsp + _rsp_save], rax ; original SP
117
118	mov unused_lanes, [state + _unused_lanes]
119	bt unused_lanes, 32+7
120	jc return_null
121
122	; find a lane with a non-null job
123	xor idx, idx
124	cmp qword [state + _ldata + 1 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
125	cmovne idx, [rel one]
126	cmp qword [state + _ldata + 2 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
127	cmovne idx, [rel two]
128	cmp qword [state + _ldata + 3 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
129	cmovne idx, [rel three]
130
131	copy_lane_data:
132	; copy valid lane (idx) to empty lanes
133	vmovdqa xmm0, [state + _lens]
134	mov tmp, [state + _args_data_ptr + PTR_SZ*idx]
135
136	%assign I 0
137	%rep 4
138	cmp qword [state + _ldata + I * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
139	jne APPEND(skip_,I)
140	mov [state + _args_data_ptr + PTR_SZ*I], tmp
141	vpor xmm0, xmm0, [rel len_masks + 16*I]
142	APPEND(skip_,I):
143	%assign I (I+1)
144	%endrep
145
146	vmovdqa [state + _lens], xmm0
147
148	vphminposuw xmm1, xmm0
149	vpextrw DWORD(len2), xmm1, 0 ; min value
150	vpextrw DWORD(idx), xmm1, 1 ; min index (0...3)
151	cmp len2, 0
152	je len_is_0
153
154	vpshuflw xmm1, xmm1, 0
155	vpsubw xmm0, xmm0, xmm1
156	vmovdqa [state + _lens], xmm0
157
158	; "state" and "args" are the same address, arg1
159	; len is arg2
160	call sha1_mult_avx
161	; state is intact
162
163	len_is_0:
164	; process completed job "idx"
165	imul lane_data, idx, _HMAC_SHA1_LANE_DATA_size
166	lea lane_data, [state + _ldata + lane_data]
167	mov DWORD(extra_blocks), [lane_data + _extra_blocks]
168	cmp extra_blocks, 0
169	jne proc_extra_blocks
170	cmp dword [lane_data + _outer_done], 0
171	jne end_loop
172
173	proc_outer:
174	mov dword [lane_data + _outer_done], 1
175	mov DWORD(size_offset), [lane_data + _size_offset]
176	mov qword [lane_data + _extra_block + size_offset], 0
177	mov word [state + _lens + 2*idx], 1
178	lea tmp, [lane_data + _outer_block]
179	mov job, [lane_data + _job_in_lane]
180	mov [state + _args_data_ptr + PTR_SZ*idx], tmp
181
182	;; idx determines which column
183	;; read off from consecutive rows
184	vmovd xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 0SHA1_DIGEST_ROW_SIZE]
185	vpinsrd xmm0, xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 1SHA1_DIGEST_ROW_SIZE], 1
186	vpinsrd xmm0, xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 2SHA1_DIGEST_ROW_SIZE], 2
187	vpinsrd xmm0, xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 3SHA1_DIGEST_ROW_SIZE], 3
188	vpshufb xmm0, xmm0, [rel byteswap]
189	mov DWORD(tmp), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 4SHA1_DIGEST_ROW_SIZE]
190	bswap DWORD(tmp)
191	vmovdqa [lane_data + _outer_block], xmm0
192	mov [lane_data + _outer_block + 4*4], DWORD(tmp)
193
194	mov tmp, [job + _auth_key_xor_opad]
195	vmovdqu xmm0, [tmp]
196	mov DWORD(tmp), [tmp + 4*4]
197	vmovd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 0SHA1_DIGEST_ROW_SIZE], xmm0
198	vpextrd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 1SHA1_DIGEST_ROW_SIZE], xmm0, 1
199	vpextrd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 2SHA1_DIGEST_ROW_SIZE], xmm0, 2
200	vpextrd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 3SHA1_DIGEST_ROW_SIZE], xmm0, 3
201	mov [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 4SHA1_DIGEST_ROW_SIZE], DWORD(tmp)
202	jmp copy_lane_data
203
204	align 16
205	proc_extra_blocks:
206	mov DWORD(start_offset), [lane_data + _start_offset]
207	mov [state + _lens + 2*idx], WORD(extra_blocks)
208	lea tmp, [lane_data + _extra_block + start_offset]
209	mov [state + _args_data_ptr + PTR_SZ*idx], tmp
210	mov dword [lane_data + _extra_blocks], 0
211	jmp copy_lane_data
212
213	return_null:
214	xor job_rax, job_rax
215	jmp return
216
217	align 16
218	end_loop:
219	mov job_rax, [lane_data + _job_in_lane]
220	mov qword [lane_data + _job_in_lane], 0
221	or dword [job_rax + _status], STS_COMPLETED_HMAC
222	mov unused_lanes, [state + _unused_lanes]
223	shl unused_lanes, 8
224	or unused_lanes, idx
225	mov [state + _unused_lanes], unused_lanes
226
227	mov p, [job_rax + _auth_tag_output]
228
229	; copy 12 bytes
230	mov DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 0SHA1_DIGEST_ROW_SIZE]
231	mov DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 1SHA1_DIGEST_ROW_SIZE]
11fdf7f2 TL	232	bswap DWORD(tmp2)
11fdf7f2 TL	233	bswap DWORD(tmp4)
11fdf7f2 TL	234	mov [p + 0*4], DWORD(tmp2)
11fdf7f2 TL	235	mov [p + 1*4], DWORD(tmp4)
9f95a23c TL	236	mov DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 2SHA1_DIGEST_ROW_SIZE]
	237	bswap DWORD(tmp2)
	238	mov [p + 2*4], DWORD(tmp2)
	239
	240	cmp qword [job_rax + _auth_tag_output_len_in_bytes], 12
	241	je return
	242
	243	;; copy remaining 8 bytes to return 20 byte digest
	244	mov DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 3SHA1_DIGEST_ROW_SIZE]
	245	mov DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 4SHA1_DIGEST_ROW_SIZE]
	246	bswap DWORD(tmp2)
	247	bswap DWORD(tmp4)
	248	mov [p + 3*SHA1_DIGEST_WORD_SIZE], DWORD(tmp2)
	249	mov [p + 4*SHA1_DIGEST_WORD_SIZE], DWORD(tmp4)
11fdf7f2 TL	250
	251	return:
	252
	253	mov rbx, [rsp + _gpr_save + 8*0]
	254	mov rbp, [rsp + _gpr_save + 8*1]
	255	mov rsp, [rsp + _rsp_save] ; original SP
	256
	257	ret
	258
	259	%ifdef LINUX
	260	section .note.GNU-stack noalloc noexec nowrite progbits
	261	%endif