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Commit | Line | Data |
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5a9fdfec FB |
1 | /* |
2 | * defines common to all virtual CPUs | |
5fafdf24 | 3 | * |
5a9fdfec FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
5a9fdfec FB |
18 | */ |
19 | #ifndef CPU_ALL_H | |
20 | #define CPU_ALL_H | |
21 | ||
7d99a001 | 22 | #include "qemu-common.h" |
b3c4bbe5 | 23 | #include "qemu-tls.h" |
1ad2134f | 24 | #include "cpu-common.h" |
fae001f5 | 25 | #include "memory_mapping.h" |
25ae9c1d | 26 | #include "dump.h" |
0ac4bd56 | 27 | |
5fafdf24 TS |
28 | /* some important defines: |
29 | * | |
0ac4bd56 FB |
30 | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned |
31 | * memory accesses. | |
5fafdf24 | 32 | * |
e2542fe2 | 33 | * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and |
0ac4bd56 | 34 | * otherwise little endian. |
5fafdf24 | 35 | * |
0ac4bd56 | 36 | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) |
5fafdf24 | 37 | * |
0ac4bd56 FB |
38 | * TARGET_WORDS_BIGENDIAN : same for target cpu |
39 | */ | |
40 | ||
e2542fe2 | 41 | #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) |
f193c797 FB |
42 | #define BSWAP_NEEDED |
43 | #endif | |
44 | ||
45 | #ifdef BSWAP_NEEDED | |
46 | ||
47 | static inline uint16_t tswap16(uint16_t s) | |
48 | { | |
49 | return bswap16(s); | |
50 | } | |
51 | ||
52 | static inline uint32_t tswap32(uint32_t s) | |
53 | { | |
54 | return bswap32(s); | |
55 | } | |
56 | ||
57 | static inline uint64_t tswap64(uint64_t s) | |
58 | { | |
59 | return bswap64(s); | |
60 | } | |
61 | ||
62 | static inline void tswap16s(uint16_t *s) | |
63 | { | |
64 | *s = bswap16(*s); | |
65 | } | |
66 | ||
67 | static inline void tswap32s(uint32_t *s) | |
68 | { | |
69 | *s = bswap32(*s); | |
70 | } | |
71 | ||
72 | static inline void tswap64s(uint64_t *s) | |
73 | { | |
74 | *s = bswap64(*s); | |
75 | } | |
76 | ||
77 | #else | |
78 | ||
79 | static inline uint16_t tswap16(uint16_t s) | |
80 | { | |
81 | return s; | |
82 | } | |
83 | ||
84 | static inline uint32_t tswap32(uint32_t s) | |
85 | { | |
86 | return s; | |
87 | } | |
88 | ||
89 | static inline uint64_t tswap64(uint64_t s) | |
90 | { | |
91 | return s; | |
92 | } | |
93 | ||
94 | static inline void tswap16s(uint16_t *s) | |
95 | { | |
96 | } | |
97 | ||
98 | static inline void tswap32s(uint32_t *s) | |
99 | { | |
100 | } | |
101 | ||
102 | static inline void tswap64s(uint64_t *s) | |
103 | { | |
104 | } | |
105 | ||
106 | #endif | |
107 | ||
108 | #if TARGET_LONG_SIZE == 4 | |
109 | #define tswapl(s) tswap32(s) | |
110 | #define tswapls(s) tswap32s((uint32_t *)(s)) | |
0a962c02 | 111 | #define bswaptls(s) bswap32s(s) |
f193c797 FB |
112 | #else |
113 | #define tswapl(s) tswap64(s) | |
114 | #define tswapls(s) tswap64s((uint64_t *)(s)) | |
0a962c02 | 115 | #define bswaptls(s) bswap64s(s) |
f193c797 FB |
116 | #endif |
117 | ||
61382a50 FB |
118 | /* CPU memory access without any memory or io remapping */ |
119 | ||
83d73968 FB |
120 | /* |
121 | * the generic syntax for the memory accesses is: | |
122 | * | |
123 | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) | |
124 | * | |
125 | * store: st{type}{size}{endian}_{access_type}(ptr, val) | |
126 | * | |
127 | * type is: | |
128 | * (empty): integer access | |
129 | * f : float access | |
5fafdf24 | 130 | * |
83d73968 FB |
131 | * sign is: |
132 | * (empty): for floats or 32 bit size | |
133 | * u : unsigned | |
134 | * s : signed | |
135 | * | |
136 | * size is: | |
137 | * b: 8 bits | |
138 | * w: 16 bits | |
139 | * l: 32 bits | |
140 | * q: 64 bits | |
5fafdf24 | 141 | * |
83d73968 FB |
142 | * endian is: |
143 | * (empty): target cpu endianness or 8 bit access | |
144 | * r : reversed target cpu endianness (not implemented yet) | |
145 | * be : big endian (not implemented yet) | |
146 | * le : little endian (not implemented yet) | |
147 | * | |
148 | * access_type is: | |
149 | * raw : host memory access | |
150 | * user : user mode access using soft MMU | |
151 | * kernel : kernel mode access using soft MMU | |
152 | */ | |
2df3b95d | 153 | |
cbbab922 | 154 | /* target-endianness CPU memory access functions */ |
2df3b95d FB |
155 | #if defined(TARGET_WORDS_BIGENDIAN) |
156 | #define lduw_p(p) lduw_be_p(p) | |
157 | #define ldsw_p(p) ldsw_be_p(p) | |
158 | #define ldl_p(p) ldl_be_p(p) | |
159 | #define ldq_p(p) ldq_be_p(p) | |
160 | #define ldfl_p(p) ldfl_be_p(p) | |
161 | #define ldfq_p(p) ldfq_be_p(p) | |
162 | #define stw_p(p, v) stw_be_p(p, v) | |
163 | #define stl_p(p, v) stl_be_p(p, v) | |
164 | #define stq_p(p, v) stq_be_p(p, v) | |
165 | #define stfl_p(p, v) stfl_be_p(p, v) | |
166 | #define stfq_p(p, v) stfq_be_p(p, v) | |
167 | #else | |
168 | #define lduw_p(p) lduw_le_p(p) | |
169 | #define ldsw_p(p) ldsw_le_p(p) | |
170 | #define ldl_p(p) ldl_le_p(p) | |
171 | #define ldq_p(p) ldq_le_p(p) | |
172 | #define ldfl_p(p) ldfl_le_p(p) | |
173 | #define ldfq_p(p) ldfq_le_p(p) | |
174 | #define stw_p(p, v) stw_le_p(p, v) | |
175 | #define stl_p(p, v) stl_le_p(p, v) | |
176 | #define stq_p(p, v) stq_le_p(p, v) | |
177 | #define stfl_p(p, v) stfl_le_p(p, v) | |
178 | #define stfq_p(p, v) stfq_le_p(p, v) | |
5a9fdfec FB |
179 | #endif |
180 | ||
61382a50 FB |
181 | /* MMU memory access macros */ |
182 | ||
53a5960a | 183 | #if defined(CONFIG_USER_ONLY) |
0e62fd79 AJ |
184 | #include <assert.h> |
185 | #include "qemu-types.h" | |
186 | ||
53a5960a PB |
187 | /* On some host systems the guest address space is reserved on the host. |
188 | * This allows the guest address space to be offset to a convenient location. | |
189 | */ | |
379f6698 PB |
190 | #if defined(CONFIG_USE_GUEST_BASE) |
191 | extern unsigned long guest_base; | |
192 | extern int have_guest_base; | |
68a1c816 | 193 | extern unsigned long reserved_va; |
379f6698 | 194 | #define GUEST_BASE guest_base |
18e9ea8a | 195 | #define RESERVED_VA reserved_va |
379f6698 PB |
196 | #else |
197 | #define GUEST_BASE 0ul | |
18e9ea8a | 198 | #define RESERVED_VA 0ul |
379f6698 | 199 | #endif |
53a5960a PB |
200 | |
201 | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ | |
8d9dde94 | 202 | #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE)) |
b9f83121 RH |
203 | |
204 | #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS | |
205 | #define h2g_valid(x) 1 | |
206 | #else | |
207 | #define h2g_valid(x) ({ \ | |
208 | unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ | |
39879bbb AG |
209 | (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \ |
210 | (!RESERVED_VA || (__guest < RESERVED_VA)); \ | |
b9f83121 RH |
211 | }) |
212 | #endif | |
213 | ||
0e62fd79 AJ |
214 | #define h2g(x) ({ \ |
215 | unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ | |
216 | /* Check if given address fits target address space */ \ | |
b9f83121 | 217 | assert(h2g_valid(x)); \ |
0e62fd79 AJ |
218 | (abi_ulong)__ret; \ |
219 | }) | |
53a5960a PB |
220 | |
221 | #define saddr(x) g2h(x) | |
222 | #define laddr(x) g2h(x) | |
223 | ||
224 | #else /* !CONFIG_USER_ONLY */ | |
c27004ec FB |
225 | /* NOTE: we use double casts if pointers and target_ulong have |
226 | different sizes */ | |
27b0dc16 SW |
227 | #define saddr(x) (uint8_t *)(intptr_t)(x) |
228 | #define laddr(x) (uint8_t *)(intptr_t)(x) | |
53a5960a PB |
229 | #endif |
230 | ||
231 | #define ldub_raw(p) ldub_p(laddr((p))) | |
232 | #define ldsb_raw(p) ldsb_p(laddr((p))) | |
233 | #define lduw_raw(p) lduw_p(laddr((p))) | |
234 | #define ldsw_raw(p) ldsw_p(laddr((p))) | |
235 | #define ldl_raw(p) ldl_p(laddr((p))) | |
236 | #define ldq_raw(p) ldq_p(laddr((p))) | |
237 | #define ldfl_raw(p) ldfl_p(laddr((p))) | |
238 | #define ldfq_raw(p) ldfq_p(laddr((p))) | |
239 | #define stb_raw(p, v) stb_p(saddr((p)), v) | |
240 | #define stw_raw(p, v) stw_p(saddr((p)), v) | |
241 | #define stl_raw(p, v) stl_p(saddr((p)), v) | |
242 | #define stq_raw(p, v) stq_p(saddr((p)), v) | |
243 | #define stfl_raw(p, v) stfl_p(saddr((p)), v) | |
244 | #define stfq_raw(p, v) stfq_p(saddr((p)), v) | |
c27004ec FB |
245 | |
246 | ||
5fafdf24 | 247 | #if defined(CONFIG_USER_ONLY) |
61382a50 FB |
248 | |
249 | /* if user mode, no other memory access functions */ | |
250 | #define ldub(p) ldub_raw(p) | |
251 | #define ldsb(p) ldsb_raw(p) | |
252 | #define lduw(p) lduw_raw(p) | |
253 | #define ldsw(p) ldsw_raw(p) | |
254 | #define ldl(p) ldl_raw(p) | |
255 | #define ldq(p) ldq_raw(p) | |
256 | #define ldfl(p) ldfl_raw(p) | |
257 | #define ldfq(p) ldfq_raw(p) | |
258 | #define stb(p, v) stb_raw(p, v) | |
259 | #define stw(p, v) stw_raw(p, v) | |
260 | #define stl(p, v) stl_raw(p, v) | |
261 | #define stq(p, v) stq_raw(p, v) | |
262 | #define stfl(p, v) stfl_raw(p, v) | |
263 | #define stfq(p, v) stfq_raw(p, v) | |
264 | ||
e141ab52 | 265 | #ifndef CONFIG_TCG_PASS_AREG0 |
61382a50 FB |
266 | #define ldub_code(p) ldub_raw(p) |
267 | #define ldsb_code(p) ldsb_raw(p) | |
268 | #define lduw_code(p) lduw_raw(p) | |
269 | #define ldsw_code(p) ldsw_raw(p) | |
270 | #define ldl_code(p) ldl_raw(p) | |
bc98a7ef | 271 | #define ldq_code(p) ldq_raw(p) |
e141ab52 BS |
272 | #else |
273 | #define cpu_ldub_code(env1, p) ldub_raw(p) | |
274 | #define cpu_ldsb_code(env1, p) ldsb_raw(p) | |
275 | #define cpu_lduw_code(env1, p) lduw_raw(p) | |
276 | #define cpu_ldsw_code(env1, p) ldsw_raw(p) | |
277 | #define cpu_ldl_code(env1, p) ldl_raw(p) | |
278 | #define cpu_ldq_code(env1, p) ldq_raw(p) | |
279 | #endif | |
61382a50 FB |
280 | |
281 | #define ldub_kernel(p) ldub_raw(p) | |
282 | #define ldsb_kernel(p) ldsb_raw(p) | |
283 | #define lduw_kernel(p) lduw_raw(p) | |
284 | #define ldsw_kernel(p) ldsw_raw(p) | |
285 | #define ldl_kernel(p) ldl_raw(p) | |
bc98a7ef | 286 | #define ldq_kernel(p) ldq_raw(p) |
0ac4bd56 FB |
287 | #define ldfl_kernel(p) ldfl_raw(p) |
288 | #define ldfq_kernel(p) ldfq_raw(p) | |
61382a50 FB |
289 | #define stb_kernel(p, v) stb_raw(p, v) |
290 | #define stw_kernel(p, v) stw_raw(p, v) | |
291 | #define stl_kernel(p, v) stl_raw(p, v) | |
292 | #define stq_kernel(p, v) stq_raw(p, v) | |
0ac4bd56 FB |
293 | #define stfl_kernel(p, v) stfl_raw(p, v) |
294 | #define stfq_kernel(p, vt) stfq_raw(p, v) | |
61382a50 FB |
295 | |
296 | #endif /* defined(CONFIG_USER_ONLY) */ | |
297 | ||
5a9fdfec FB |
298 | /* page related stuff */ |
299 | ||
03875444 | 300 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
5a9fdfec FB |
301 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
302 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) | |
303 | ||
c6d50674 SW |
304 | /* ??? These should be the larger of uintptr_t and target_ulong. */ |
305 | extern uintptr_t qemu_real_host_page_size; | |
306 | extern uintptr_t qemu_host_page_size; | |
307 | extern uintptr_t qemu_host_page_mask; | |
5a9fdfec | 308 | |
83fb7adf | 309 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
5a9fdfec FB |
310 | |
311 | /* same as PROT_xxx */ | |
312 | #define PAGE_READ 0x0001 | |
313 | #define PAGE_WRITE 0x0002 | |
314 | #define PAGE_EXEC 0x0004 | |
315 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) | |
316 | #define PAGE_VALID 0x0008 | |
317 | /* original state of the write flag (used when tracking self-modifying | |
318 | code */ | |
5fafdf24 | 319 | #define PAGE_WRITE_ORG 0x0010 |
2e9a5713 PB |
320 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
321 | /* FIXME: Code that sets/uses this is broken and needs to go away. */ | |
50a9569b | 322 | #define PAGE_RESERVED 0x0020 |
2e9a5713 | 323 | #endif |
5a9fdfec | 324 | |
b480d9b7 | 325 | #if defined(CONFIG_USER_ONLY) |
5a9fdfec | 326 | void page_dump(FILE *f); |
5cd2c5b6 | 327 | |
b480d9b7 PB |
328 | typedef int (*walk_memory_regions_fn)(void *, abi_ulong, |
329 | abi_ulong, unsigned long); | |
5cd2c5b6 RH |
330 | int walk_memory_regions(void *, walk_memory_regions_fn); |
331 | ||
53a5960a PB |
332 | int page_get_flags(target_ulong address); |
333 | void page_set_flags(target_ulong start, target_ulong end, int flags); | |
3d97b40b | 334 | int page_check_range(target_ulong start, target_ulong len, int flags); |
b480d9b7 | 335 | #endif |
5a9fdfec | 336 | |
9349b4f9 AF |
337 | CPUArchState *cpu_copy(CPUArchState *env); |
338 | CPUArchState *qemu_get_cpu(int cpu); | |
c5be9f08 | 339 | |
f5c848ee JK |
340 | #define CPU_DUMP_CODE 0x00010000 |
341 | ||
9349b4f9 | 342 | void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf, |
7fe48483 | 343 | int flags); |
9349b4f9 | 344 | void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf, |
9a78eead | 345 | int flags); |
7fe48483 | 346 | |
9349b4f9 | 347 | void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) |
2c80e423 | 348 | GCC_FMT_ATTR(2, 3); |
9349b4f9 AF |
349 | extern CPUArchState *first_cpu; |
350 | DECLARE_TLS(CPUArchState *,cpu_single_env); | |
4a2dd92d | 351 | #define cpu_single_env tls_var(cpu_single_env) |
db1a4972 | 352 | |
9c76219e RH |
353 | /* Flags for use in ENV->INTERRUPT_PENDING. |
354 | ||
355 | The numbers assigned here are non-sequential in order to preserve | |
356 | binary compatibility with the vmstate dump. Bit 0 (0x0001) was | |
357 | previously used for CPU_INTERRUPT_EXIT, and is cleared when loading | |
358 | the vmstate dump. */ | |
359 | ||
360 | /* External hardware interrupt pending. This is typically used for | |
361 | interrupts from devices. */ | |
362 | #define CPU_INTERRUPT_HARD 0x0002 | |
363 | ||
364 | /* Exit the current TB. This is typically used when some system-level device | |
365 | makes some change to the memory mapping. E.g. the a20 line change. */ | |
366 | #define CPU_INTERRUPT_EXITTB 0x0004 | |
367 | ||
368 | /* Halt the CPU. */ | |
369 | #define CPU_INTERRUPT_HALT 0x0020 | |
370 | ||
371 | /* Debug event pending. */ | |
372 | #define CPU_INTERRUPT_DEBUG 0x0080 | |
373 | ||
374 | /* Several target-specific external hardware interrupts. Each target/cpu.h | |
375 | should define proper names based on these defines. */ | |
376 | #define CPU_INTERRUPT_TGT_EXT_0 0x0008 | |
377 | #define CPU_INTERRUPT_TGT_EXT_1 0x0010 | |
378 | #define CPU_INTERRUPT_TGT_EXT_2 0x0040 | |
379 | #define CPU_INTERRUPT_TGT_EXT_3 0x0200 | |
380 | #define CPU_INTERRUPT_TGT_EXT_4 0x1000 | |
381 | ||
382 | /* Several target-specific internal interrupts. These differ from the | |
07f35073 | 383 | preceding target-specific interrupts in that they are intended to |
9c76219e RH |
384 | originate from within the cpu itself, typically in response to some |
385 | instruction being executed. These, therefore, are not masked while | |
386 | single-stepping within the debugger. */ | |
387 | #define CPU_INTERRUPT_TGT_INT_0 0x0100 | |
388 | #define CPU_INTERRUPT_TGT_INT_1 0x0400 | |
389 | #define CPU_INTERRUPT_TGT_INT_2 0x0800 | |
d362e757 | 390 | #define CPU_INTERRUPT_TGT_INT_3 0x2000 |
9c76219e | 391 | |
d362e757 | 392 | /* First unused bit: 0x4000. */ |
9c76219e | 393 | |
3125f763 RH |
394 | /* The set of all bits that should be masked when single-stepping. */ |
395 | #define CPU_INTERRUPT_SSTEP_MASK \ | |
396 | (CPU_INTERRUPT_HARD \ | |
397 | | CPU_INTERRUPT_TGT_EXT_0 \ | |
398 | | CPU_INTERRUPT_TGT_EXT_1 \ | |
399 | | CPU_INTERRUPT_TGT_EXT_2 \ | |
400 | | CPU_INTERRUPT_TGT_EXT_3 \ | |
401 | | CPU_INTERRUPT_TGT_EXT_4) | |
98699967 | 402 | |
ec6959d0 | 403 | #ifndef CONFIG_USER_ONLY |
9349b4f9 | 404 | typedef void (*CPUInterruptHandler)(CPUArchState *, int); |
ec6959d0 JK |
405 | |
406 | extern CPUInterruptHandler cpu_interrupt_handler; | |
407 | ||
9349b4f9 | 408 | static inline void cpu_interrupt(CPUArchState *s, int mask) |
ec6959d0 JK |
409 | { |
410 | cpu_interrupt_handler(s, mask); | |
411 | } | |
412 | #else /* USER_ONLY */ | |
9349b4f9 | 413 | void cpu_interrupt(CPUArchState *env, int mask); |
ec6959d0 JK |
414 | #endif /* USER_ONLY */ |
415 | ||
9349b4f9 | 416 | void cpu_reset_interrupt(CPUArchState *env, int mask); |
68a79315 | 417 | |
9349b4f9 | 418 | void cpu_exit(CPUArchState *s); |
3098dba0 | 419 | |
9349b4f9 | 420 | bool qemu_cpu_has_work(CPUArchState *env); |
6a4955a8 | 421 | |
a1d1bb31 AL |
422 | /* Breakpoint/watchpoint flags */ |
423 | #define BP_MEM_READ 0x01 | |
424 | #define BP_MEM_WRITE 0x02 | |
425 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
06d55cc1 | 426 | #define BP_STOP_BEFORE_ACCESS 0x04 |
6e140f28 | 427 | #define BP_WATCHPOINT_HIT 0x08 |
a1d1bb31 | 428 | #define BP_GDB 0x10 |
2dc9f411 | 429 | #define BP_CPU 0x20 |
a1d1bb31 | 430 | |
9349b4f9 | 431 | int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, |
a1d1bb31 | 432 | CPUBreakpoint **breakpoint); |
9349b4f9 AF |
433 | int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); |
434 | void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); | |
435 | void cpu_breakpoint_remove_all(CPUArchState *env, int mask); | |
436 | int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, | |
a1d1bb31 | 437 | int flags, CPUWatchpoint **watchpoint); |
9349b4f9 | 438 | int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, |
a1d1bb31 | 439 | target_ulong len, int flags); |
9349b4f9 AF |
440 | void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); |
441 | void cpu_watchpoint_remove_all(CPUArchState *env, int mask); | |
60897d36 EI |
442 | |
443 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ | |
444 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
445 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
446 | ||
9349b4f9 AF |
447 | void cpu_single_step(CPUArchState *env, int enabled); |
448 | void cpu_state_reset(CPUArchState *s); | |
449 | int cpu_is_stopped(CPUArchState *env); | |
450 | void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data); | |
4c3a88a2 | 451 | |
5fafdf24 | 452 | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
9fddaa0c | 453 | #define CPU_LOG_TB_IN_ASM (1 << 1) |
f193c797 FB |
454 | #define CPU_LOG_TB_OP (1 << 2) |
455 | #define CPU_LOG_TB_OP_OPT (1 << 3) | |
456 | #define CPU_LOG_INT (1 << 4) | |
457 | #define CPU_LOG_EXEC (1 << 5) | |
458 | #define CPU_LOG_PCALL (1 << 6) | |
fd872598 | 459 | #define CPU_LOG_IOPORT (1 << 7) |
9fddaa0c | 460 | #define CPU_LOG_TB_CPU (1 << 8) |
eca1bdf4 | 461 | #define CPU_LOG_RESET (1 << 9) |
f193c797 FB |
462 | |
463 | /* define log items */ | |
464 | typedef struct CPULogItem { | |
465 | int mask; | |
466 | const char *name; | |
467 | const char *help; | |
468 | } CPULogItem; | |
469 | ||
c7cd6a37 | 470 | extern const CPULogItem cpu_log_items[]; |
f193c797 | 471 | |
34865134 FB |
472 | void cpu_set_log(int log_flags); |
473 | void cpu_set_log_filename(const char *filename); | |
f193c797 | 474 | int cpu_str_to_log_mask(const char *str); |
34865134 | 475 | |
b3755a91 PB |
476 | #if !defined(CONFIG_USER_ONLY) |
477 | ||
4fcc562b PB |
478 | /* Return the physical page corresponding to a virtual one. Use it |
479 | only for debugging because no protection checks are done. Return -1 | |
480 | if no page found. */ | |
9349b4f9 | 481 | target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr); |
4fcc562b | 482 | |
33417e70 FB |
483 | /* memory API */ |
484 | ||
edf75d59 | 485 | extern int phys_ram_fd; |
c227f099 | 486 | extern ram_addr_t ram_size; |
f471a17e | 487 | |
cd19cfa2 HY |
488 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ |
489 | #define RAM_PREALLOC_MASK (1 << 0) | |
490 | ||
f471a17e | 491 | typedef struct RAMBlock { |
7c637366 | 492 | struct MemoryRegion *mr; |
f471a17e AW |
493 | uint8_t *host; |
494 | ram_addr_t offset; | |
495 | ram_addr_t length; | |
cd19cfa2 | 496 | uint32_t flags; |
cc9e98cb | 497 | char idstr[256]; |
f471a17e | 498 | QLIST_ENTRY(RAMBlock) next; |
04b16653 AW |
499 | #if defined(__linux__) && !defined(TARGET_S390X) |
500 | int fd; | |
501 | #endif | |
f471a17e AW |
502 | } RAMBlock; |
503 | ||
504 | typedef struct RAMList { | |
505 | uint8_t *phys_dirty; | |
85d59fef | 506 | QLIST_HEAD(, RAMBlock) blocks; |
f471a17e AW |
507 | } RAMList; |
508 | extern RAMList ram_list; | |
edf75d59 | 509 | |
c902760f MT |
510 | extern const char *mem_path; |
511 | extern int mem_prealloc; | |
512 | ||
0f459d16 PB |
513 | /* Flags stored in the low bits of the TLB virtual address. These are |
514 | defined so that fast path ram access is all zeros. */ | |
515 | /* Zero if TLB entry is valid. */ | |
516 | #define TLB_INVALID_MASK (1 << 3) | |
517 | /* Set if TLB entry references a clean RAM page. The iotlb entry will | |
518 | contain the page physical address. */ | |
519 | #define TLB_NOTDIRTY (1 << 4) | |
520 | /* Set if TLB entry is an IO callback. */ | |
521 | #define TLB_MMIO (1 << 5) | |
522 | ||
055403b2 | 523 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); |
b3755a91 PB |
524 | #endif /* !CONFIG_USER_ONLY */ |
525 | ||
9349b4f9 | 526 | int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr, |
b3755a91 PB |
527 | uint8_t *buf, int len, int is_write); |
528 | ||
fae001f5 WC |
529 | #if defined(CONFIG_HAVE_GET_MEMORY_MAPPING) |
530 | int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env); | |
31a2207a | 531 | bool cpu_paging_enabled(CPUArchState *env); |
fae001f5 WC |
532 | #else |
533 | static inline int cpu_get_memory_mapping(MemoryMappingList *list, | |
534 | CPUArchState *env) | |
535 | { | |
536 | return -1; | |
537 | } | |
31a2207a WC |
538 | |
539 | static inline bool cpu_paging_enabled(CPUArchState *env) | |
540 | { | |
541 | return true; | |
542 | } | |
fae001f5 WC |
543 | #endif |
544 | ||
9fecbed0 WC |
545 | typedef int (*write_core_dump_function)(void *buf, size_t size, void *opaque); |
546 | #if defined(CONFIG_HAVE_CORE_DUMP) | |
547 | int cpu_write_elf64_note(write_core_dump_function f, CPUArchState *env, | |
548 | int cpuid, void *opaque); | |
549 | int cpu_write_elf32_note(write_core_dump_function f, CPUArchState *env, | |
550 | int cpuid, void *opaque); | |
90166b71 WC |
551 | int cpu_write_elf64_qemunote(write_core_dump_function f, CPUArchState *env, |
552 | void *opaque); | |
553 | int cpu_write_elf32_qemunote(write_core_dump_function f, CPUArchState *env, | |
554 | void *opaque); | |
25ae9c1d | 555 | int cpu_get_dump_info(ArchDumpInfo *info); |
9fecbed0 WC |
556 | #else |
557 | static inline int cpu_write_elf64_note(write_core_dump_function f, | |
558 | CPUArchState *env, int cpuid, | |
559 | void *opaque) | |
560 | { | |
561 | return -1; | |
562 | } | |
563 | ||
564 | static inline int cpu_write_elf32_note(write_core_dump_function f, | |
565 | CPUArchState *env, int cpuid, | |
566 | void *opaque) | |
567 | { | |
568 | return -1; | |
569 | } | |
90166b71 WC |
570 | |
571 | static inline int cpu_write_elf64_qemunote(write_core_dump_function f, | |
572 | CPUArchState *env, | |
573 | void *opaque) | |
574 | { | |
575 | return -1; | |
576 | } | |
577 | ||
578 | static inline int cpu_write_elf32_qemunote(write_core_dump_function f, | |
579 | CPUArchState *env, | |
580 | void *opaque) | |
581 | { | |
582 | return -1; | |
583 | } | |
25ae9c1d WC |
584 | |
585 | static inline int cpu_get_dump_info(ArchDumpInfo *info) | |
586 | { | |
587 | return -1; | |
588 | } | |
9fecbed0 WC |
589 | #endif |
590 | ||
5a9fdfec | 591 | #endif /* CPU_ALL_H */ |