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darwin-user/main.c: Drop unused cpu_single_env definition
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5a9fdfec
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1/*
2 * defines common to all virtual CPUs
5fafdf24 3 *
5a9fdfec
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4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
5a9fdfec
FB
18 */
19#ifndef CPU_ALL_H
20#define CPU_ALL_H
21
7d99a001 22#include "qemu-common.h"
1ad2134f 23#include "cpu-common.h"
0ac4bd56 24
5fafdf24
TS
25/* some important defines:
26 *
0ac4bd56
FB
27 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
28 * memory accesses.
5fafdf24 29 *
e2542fe2 30 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
0ac4bd56 31 * otherwise little endian.
5fafdf24 32 *
0ac4bd56 33 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
5fafdf24 34 *
0ac4bd56
FB
35 * TARGET_WORDS_BIGENDIAN : same for target cpu
36 */
37
e2542fe2 38#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
f193c797
FB
39#define BSWAP_NEEDED
40#endif
41
42#ifdef BSWAP_NEEDED
43
44static inline uint16_t tswap16(uint16_t s)
45{
46 return bswap16(s);
47}
48
49static inline uint32_t tswap32(uint32_t s)
50{
51 return bswap32(s);
52}
53
54static inline uint64_t tswap64(uint64_t s)
55{
56 return bswap64(s);
57}
58
59static inline void tswap16s(uint16_t *s)
60{
61 *s = bswap16(*s);
62}
63
64static inline void tswap32s(uint32_t *s)
65{
66 *s = bswap32(*s);
67}
68
69static inline void tswap64s(uint64_t *s)
70{
71 *s = bswap64(*s);
72}
73
74#else
75
76static inline uint16_t tswap16(uint16_t s)
77{
78 return s;
79}
80
81static inline uint32_t tswap32(uint32_t s)
82{
83 return s;
84}
85
86static inline uint64_t tswap64(uint64_t s)
87{
88 return s;
89}
90
91static inline void tswap16s(uint16_t *s)
92{
93}
94
95static inline void tswap32s(uint32_t *s)
96{
97}
98
99static inline void tswap64s(uint64_t *s)
100{
101}
102
103#endif
104
105#if TARGET_LONG_SIZE == 4
106#define tswapl(s) tswap32(s)
107#define tswapls(s) tswap32s((uint32_t *)(s))
0a962c02 108#define bswaptls(s) bswap32s(s)
f193c797
FB
109#else
110#define tswapl(s) tswap64(s)
111#define tswapls(s) tswap64s((uint64_t *)(s))
0a962c02 112#define bswaptls(s) bswap64s(s)
f193c797
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113#endif
114
61382a50
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115/* CPU memory access without any memory or io remapping */
116
83d73968
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117/*
118 * the generic syntax for the memory accesses is:
119 *
120 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
121 *
122 * store: st{type}{size}{endian}_{access_type}(ptr, val)
123 *
124 * type is:
125 * (empty): integer access
126 * f : float access
5fafdf24 127 *
83d73968
FB
128 * sign is:
129 * (empty): for floats or 32 bit size
130 * u : unsigned
131 * s : signed
132 *
133 * size is:
134 * b: 8 bits
135 * w: 16 bits
136 * l: 32 bits
137 * q: 64 bits
5fafdf24 138 *
83d73968
FB
139 * endian is:
140 * (empty): target cpu endianness or 8 bit access
141 * r : reversed target cpu endianness (not implemented yet)
142 * be : big endian (not implemented yet)
143 * le : little endian (not implemented yet)
144 *
145 * access_type is:
146 * raw : host memory access
147 * user : user mode access using soft MMU
148 * kernel : kernel mode access using soft MMU
149 */
2df3b95d 150
cbbab922 151/* target-endianness CPU memory access functions */
2df3b95d
FB
152#if defined(TARGET_WORDS_BIGENDIAN)
153#define lduw_p(p) lduw_be_p(p)
154#define ldsw_p(p) ldsw_be_p(p)
155#define ldl_p(p) ldl_be_p(p)
156#define ldq_p(p) ldq_be_p(p)
157#define ldfl_p(p) ldfl_be_p(p)
158#define ldfq_p(p) ldfq_be_p(p)
159#define stw_p(p, v) stw_be_p(p, v)
160#define stl_p(p, v) stl_be_p(p, v)
161#define stq_p(p, v) stq_be_p(p, v)
162#define stfl_p(p, v) stfl_be_p(p, v)
163#define stfq_p(p, v) stfq_be_p(p, v)
164#else
165#define lduw_p(p) lduw_le_p(p)
166#define ldsw_p(p) ldsw_le_p(p)
167#define ldl_p(p) ldl_le_p(p)
168#define ldq_p(p) ldq_le_p(p)
169#define ldfl_p(p) ldfl_le_p(p)
170#define ldfq_p(p) ldfq_le_p(p)
171#define stw_p(p, v) stw_le_p(p, v)
172#define stl_p(p, v) stl_le_p(p, v)
173#define stq_p(p, v) stq_le_p(p, v)
174#define stfl_p(p, v) stfl_le_p(p, v)
175#define stfq_p(p, v) stfq_le_p(p, v)
5a9fdfec
FB
176#endif
177
61382a50
FB
178/* MMU memory access macros */
179
53a5960a 180#if defined(CONFIG_USER_ONLY)
0e62fd79
AJ
181#include <assert.h>
182#include "qemu-types.h"
183
53a5960a
PB
184/* On some host systems the guest address space is reserved on the host.
185 * This allows the guest address space to be offset to a convenient location.
186 */
379f6698
PB
187#if defined(CONFIG_USE_GUEST_BASE)
188extern unsigned long guest_base;
189extern int have_guest_base;
68a1c816 190extern unsigned long reserved_va;
379f6698 191#define GUEST_BASE guest_base
18e9ea8a 192#define RESERVED_VA reserved_va
379f6698
PB
193#else
194#define GUEST_BASE 0ul
18e9ea8a 195#define RESERVED_VA 0ul
379f6698 196#endif
53a5960a
PB
197
198/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
199#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
b9f83121
RH
200
201#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
202#define h2g_valid(x) 1
203#else
204#define h2g_valid(x) ({ \
205 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
206 __guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS); \
207})
208#endif
209
0e62fd79
AJ
210#define h2g(x) ({ \
211 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
212 /* Check if given address fits target address space */ \
b9f83121 213 assert(h2g_valid(x)); \
0e62fd79
AJ
214 (abi_ulong)__ret; \
215})
53a5960a
PB
216
217#define saddr(x) g2h(x)
218#define laddr(x) g2h(x)
219
220#else /* !CONFIG_USER_ONLY */
c27004ec
FB
221/* NOTE: we use double casts if pointers and target_ulong have
222 different sizes */
53a5960a
PB
223#define saddr(x) (uint8_t *)(long)(x)
224#define laddr(x) (uint8_t *)(long)(x)
225#endif
226
227#define ldub_raw(p) ldub_p(laddr((p)))
228#define ldsb_raw(p) ldsb_p(laddr((p)))
229#define lduw_raw(p) lduw_p(laddr((p)))
230#define ldsw_raw(p) ldsw_p(laddr((p)))
231#define ldl_raw(p) ldl_p(laddr((p)))
232#define ldq_raw(p) ldq_p(laddr((p)))
233#define ldfl_raw(p) ldfl_p(laddr((p)))
234#define ldfq_raw(p) ldfq_p(laddr((p)))
235#define stb_raw(p, v) stb_p(saddr((p)), v)
236#define stw_raw(p, v) stw_p(saddr((p)), v)
237#define stl_raw(p, v) stl_p(saddr((p)), v)
238#define stq_raw(p, v) stq_p(saddr((p)), v)
239#define stfl_raw(p, v) stfl_p(saddr((p)), v)
240#define stfq_raw(p, v) stfq_p(saddr((p)), v)
c27004ec
FB
241
242
5fafdf24 243#if defined(CONFIG_USER_ONLY)
61382a50
FB
244
245/* if user mode, no other memory access functions */
246#define ldub(p) ldub_raw(p)
247#define ldsb(p) ldsb_raw(p)
248#define lduw(p) lduw_raw(p)
249#define ldsw(p) ldsw_raw(p)
250#define ldl(p) ldl_raw(p)
251#define ldq(p) ldq_raw(p)
252#define ldfl(p) ldfl_raw(p)
253#define ldfq(p) ldfq_raw(p)
254#define stb(p, v) stb_raw(p, v)
255#define stw(p, v) stw_raw(p, v)
256#define stl(p, v) stl_raw(p, v)
257#define stq(p, v) stq_raw(p, v)
258#define stfl(p, v) stfl_raw(p, v)
259#define stfq(p, v) stfq_raw(p, v)
260
261#define ldub_code(p) ldub_raw(p)
262#define ldsb_code(p) ldsb_raw(p)
263#define lduw_code(p) lduw_raw(p)
264#define ldsw_code(p) ldsw_raw(p)
265#define ldl_code(p) ldl_raw(p)
bc98a7ef 266#define ldq_code(p) ldq_raw(p)
61382a50
FB
267
268#define ldub_kernel(p) ldub_raw(p)
269#define ldsb_kernel(p) ldsb_raw(p)
270#define lduw_kernel(p) lduw_raw(p)
271#define ldsw_kernel(p) ldsw_raw(p)
272#define ldl_kernel(p) ldl_raw(p)
bc98a7ef 273#define ldq_kernel(p) ldq_raw(p)
0ac4bd56
FB
274#define ldfl_kernel(p) ldfl_raw(p)
275#define ldfq_kernel(p) ldfq_raw(p)
61382a50
FB
276#define stb_kernel(p, v) stb_raw(p, v)
277#define stw_kernel(p, v) stw_raw(p, v)
278#define stl_kernel(p, v) stl_raw(p, v)
279#define stq_kernel(p, v) stq_raw(p, v)
0ac4bd56
FB
280#define stfl_kernel(p, v) stfl_raw(p, v)
281#define stfq_kernel(p, vt) stfq_raw(p, v)
61382a50
FB
282
283#endif /* defined(CONFIG_USER_ONLY) */
284
5a9fdfec
FB
285/* page related stuff */
286
03875444 287#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
5a9fdfec
FB
288#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
289#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
290
53a5960a 291/* ??? These should be the larger of unsigned long and target_ulong. */
83fb7adf 292extern unsigned long qemu_real_host_page_size;
83fb7adf
FB
293extern unsigned long qemu_host_page_size;
294extern unsigned long qemu_host_page_mask;
5a9fdfec 295
83fb7adf 296#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
5a9fdfec
FB
297
298/* same as PROT_xxx */
299#define PAGE_READ 0x0001
300#define PAGE_WRITE 0x0002
301#define PAGE_EXEC 0x0004
302#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
303#define PAGE_VALID 0x0008
304/* original state of the write flag (used when tracking self-modifying
305 code */
5fafdf24 306#define PAGE_WRITE_ORG 0x0010
2e9a5713
PB
307#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
308/* FIXME: Code that sets/uses this is broken and needs to go away. */
50a9569b 309#define PAGE_RESERVED 0x0020
2e9a5713 310#endif
5a9fdfec 311
b480d9b7 312#if defined(CONFIG_USER_ONLY)
5a9fdfec 313void page_dump(FILE *f);
5cd2c5b6 314
b480d9b7
PB
315typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
316 abi_ulong, unsigned long);
5cd2c5b6
RH
317int walk_memory_regions(void *, walk_memory_regions_fn);
318
53a5960a
PB
319int page_get_flags(target_ulong address);
320void page_set_flags(target_ulong start, target_ulong end, int flags);
3d97b40b 321int page_check_range(target_ulong start, target_ulong len, int flags);
b480d9b7 322#endif
5a9fdfec 323
c5be9f08 324CPUState *cpu_copy(CPUState *env);
950f1472 325CPUState *qemu_get_cpu(int cpu);
c5be9f08 326
f5c848ee
JK
327#define CPU_DUMP_CODE 0x00010000
328
9a78eead 329void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 330 int flags);
9a78eead
SW
331void cpu_dump_statistics(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
332 int flags);
7fe48483 333
a5e50b26 334void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
2c80e423 335 GCC_FMT_ATTR(2, 3);
f0aca822 336extern CPUState *first_cpu;
e2f22898 337extern CPUState *cpu_single_env;
db1a4972 338
9c76219e
RH
339/* Flags for use in ENV->INTERRUPT_PENDING.
340
341 The numbers assigned here are non-sequential in order to preserve
342 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
343 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
344 the vmstate dump. */
345
346/* External hardware interrupt pending. This is typically used for
347 interrupts from devices. */
348#define CPU_INTERRUPT_HARD 0x0002
349
350/* Exit the current TB. This is typically used when some system-level device
351 makes some change to the memory mapping. E.g. the a20 line change. */
352#define CPU_INTERRUPT_EXITTB 0x0004
353
354/* Halt the CPU. */
355#define CPU_INTERRUPT_HALT 0x0020
356
357/* Debug event pending. */
358#define CPU_INTERRUPT_DEBUG 0x0080
359
360/* Several target-specific external hardware interrupts. Each target/cpu.h
361 should define proper names based on these defines. */
362#define CPU_INTERRUPT_TGT_EXT_0 0x0008
363#define CPU_INTERRUPT_TGT_EXT_1 0x0010
364#define CPU_INTERRUPT_TGT_EXT_2 0x0040
365#define CPU_INTERRUPT_TGT_EXT_3 0x0200
366#define CPU_INTERRUPT_TGT_EXT_4 0x1000
367
368/* Several target-specific internal interrupts. These differ from the
369 preceeding target-specific interrupts in that they are intended to
370 originate from within the cpu itself, typically in response to some
371 instruction being executed. These, therefore, are not masked while
372 single-stepping within the debugger. */
373#define CPU_INTERRUPT_TGT_INT_0 0x0100
374#define CPU_INTERRUPT_TGT_INT_1 0x0400
375#define CPU_INTERRUPT_TGT_INT_2 0x0800
376
377/* First unused bit: 0x2000. */
378
3125f763
RH
379/* The set of all bits that should be masked when single-stepping. */
380#define CPU_INTERRUPT_SSTEP_MASK \
381 (CPU_INTERRUPT_HARD \
382 | CPU_INTERRUPT_TGT_EXT_0 \
383 | CPU_INTERRUPT_TGT_EXT_1 \
384 | CPU_INTERRUPT_TGT_EXT_2 \
385 | CPU_INTERRUPT_TGT_EXT_3 \
386 | CPU_INTERRUPT_TGT_EXT_4)
98699967 387
ec6959d0
JK
388#ifndef CONFIG_USER_ONLY
389typedef void (*CPUInterruptHandler)(CPUState *, int);
390
391extern CPUInterruptHandler cpu_interrupt_handler;
392
393static inline void cpu_interrupt(CPUState *s, int mask)
394{
395 cpu_interrupt_handler(s, mask);
396}
397#else /* USER_ONLY */
398void cpu_interrupt(CPUState *env, int mask);
399#endif /* USER_ONLY */
400
b54ad049 401void cpu_reset_interrupt(CPUState *env, int mask);
68a79315 402
3098dba0
AJ
403void cpu_exit(CPUState *s);
404
f3e27037 405bool qemu_cpu_has_work(CPUState *env);
6a4955a8 406
a1d1bb31
AL
407/* Breakpoint/watchpoint flags */
408#define BP_MEM_READ 0x01
409#define BP_MEM_WRITE 0x02
410#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
06d55cc1 411#define BP_STOP_BEFORE_ACCESS 0x04
6e140f28 412#define BP_WATCHPOINT_HIT 0x08
a1d1bb31 413#define BP_GDB 0x10
2dc9f411 414#define BP_CPU 0x20
a1d1bb31
AL
415
416int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
417 CPUBreakpoint **breakpoint);
418int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags);
419void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
420void cpu_breakpoint_remove_all(CPUState *env, int mask);
421int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
422 int flags, CPUWatchpoint **watchpoint);
423int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
424 target_ulong len, int flags);
425void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
426void cpu_watchpoint_remove_all(CPUState *env, int mask);
60897d36
EI
427
428#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
429#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
430#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
431
c33a346e 432void cpu_single_step(CPUState *env, int enabled);
d95dc32d 433void cpu_reset(CPUState *s);
3ae9501c 434int cpu_is_stopped(CPUState *env);
e82bcec2 435void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);
4c3a88a2 436
5fafdf24 437#define CPU_LOG_TB_OUT_ASM (1 << 0)
9fddaa0c 438#define CPU_LOG_TB_IN_ASM (1 << 1)
f193c797
FB
439#define CPU_LOG_TB_OP (1 << 2)
440#define CPU_LOG_TB_OP_OPT (1 << 3)
441#define CPU_LOG_INT (1 << 4)
442#define CPU_LOG_EXEC (1 << 5)
443#define CPU_LOG_PCALL (1 << 6)
fd872598 444#define CPU_LOG_IOPORT (1 << 7)
9fddaa0c 445#define CPU_LOG_TB_CPU (1 << 8)
eca1bdf4 446#define CPU_LOG_RESET (1 << 9)
f193c797
FB
447
448/* define log items */
449typedef struct CPULogItem {
450 int mask;
451 const char *name;
452 const char *help;
453} CPULogItem;
454
c7cd6a37 455extern const CPULogItem cpu_log_items[];
f193c797 456
34865134
FB
457void cpu_set_log(int log_flags);
458void cpu_set_log_filename(const char *filename);
f193c797 459int cpu_str_to_log_mask(const char *str);
34865134 460
b3755a91
PB
461#if !defined(CONFIG_USER_ONLY)
462
4fcc562b
PB
463/* Return the physical page corresponding to a virtual one. Use it
464 only for debugging because no protection checks are done. Return -1
465 if no page found. */
466target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
467
33417e70
FB
468/* memory API */
469
edf75d59 470extern int phys_ram_fd;
c227f099 471extern ram_addr_t ram_size;
f471a17e 472
cd19cfa2
HY
473/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
474#define RAM_PREALLOC_MASK (1 << 0)
475
f471a17e
AW
476typedef struct RAMBlock {
477 uint8_t *host;
478 ram_addr_t offset;
479 ram_addr_t length;
cd19cfa2 480 uint32_t flags;
cc9e98cb 481 char idstr[256];
f471a17e 482 QLIST_ENTRY(RAMBlock) next;
04b16653
AW
483#if defined(__linux__) && !defined(TARGET_S390X)
484 int fd;
485#endif
f471a17e
AW
486} RAMBlock;
487
488typedef struct RAMList {
489 uint8_t *phys_dirty;
85d59fef 490 QLIST_HEAD(, RAMBlock) blocks;
f471a17e
AW
491} RAMList;
492extern RAMList ram_list;
edf75d59 493
c902760f
MT
494extern const char *mem_path;
495extern int mem_prealloc;
496
edf75d59 497/* physical memory access */
0f459d16
PB
498
499/* MMIO pages are identified by a combination of an IO device index and
500 3 flags. The ROMD code stores the page ram offset in iotlb entry,
501 so only a limited number of ids are avaiable. */
502
98699967 503#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
edf75d59 504
0f459d16
PB
505/* Flags stored in the low bits of the TLB virtual address. These are
506 defined so that fast path ram access is all zeros. */
507/* Zero if TLB entry is valid. */
508#define TLB_INVALID_MASK (1 << 3)
509/* Set if TLB entry references a clean RAM page. The iotlb entry will
510 contain the page physical address. */
511#define TLB_NOTDIRTY (1 << 4)
512/* Set if TLB entry is an IO callback. */
513#define TLB_MMIO (1 << 5)
514
74576198
AL
515#define VGA_DIRTY_FLAG 0x01
516#define CODE_DIRTY_FLAG 0x02
74576198 517#define MIGRATION_DIRTY_FLAG 0x08
0a962c02 518
1ccde1cb 519/* read dirty bit (return 0 or 1) */
c227f099 520static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
1ccde1cb 521{
f471a17e 522 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
0a962c02
FB
523}
524
ca39b46e
YT
525static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr)
526{
f471a17e 527 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS];
ca39b46e
YT
528}
529
c227f099 530static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
0a962c02
FB
531 int dirty_flags)
532{
f471a17e 533 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
1ccde1cb
FB
534}
535
c227f099 536static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
1ccde1cb 537{
f471a17e 538 ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
1ccde1cb
FB
539}
540
ca39b46e
YT
541static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr,
542 int dirty_flags)
543{
f471a17e 544 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] |= dirty_flags;
ca39b46e
YT
545}
546
547static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start,
548 int length,
549 int dirty_flags)
550{
551 int i, mask, len;
552 uint8_t *p;
553
554 len = length >> TARGET_PAGE_BITS;
555 mask = ~dirty_flags;
f471a17e 556 p = ram_list.phys_dirty + (start >> TARGET_PAGE_BITS);
ca39b46e
YT
557 for (i = 0; i < len; i++) {
558 p[i] &= mask;
559 }
560}
561
c227f099 562void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
0a962c02 563 int dirty_flags);
04c504cc 564void cpu_tlb_update_dirty(CPUState *env);
1ccde1cb 565
74576198
AL
566int cpu_physical_memory_set_dirty_tracking(int enable);
567
568int cpu_physical_memory_get_dirty_tracking(void);
569
c227f099
AL
570int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
571 target_phys_addr_t end_addr);
2bec46dc 572
e5896b12
AP
573int cpu_physical_log_start(target_phys_addr_t start_addr,
574 ram_addr_t size);
575
576int cpu_physical_log_stop(target_phys_addr_t start_addr,
577 ram_addr_t size);
578
055403b2 579void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
b3755a91
PB
580#endif /* !CONFIG_USER_ONLY */
581
582int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
583 uint8_t *buf, int len, int is_write);
584
5a9fdfec 585#endif /* CPU_ALL_H */