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cpu-common.h: Remove unnecessary guard on including targphys.h
[qemu.git] / cpu-common.h
CommitLineData
1ad2134f
PB
1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H 1
3
07f35073 4/* CPU interfaces that are target independent. */
1ad2134f 5
37b76cfd 6#include "targphys.h"
37b76cfd
PB
7
8#ifndef NEED_CPU_H
9#include "poison.h"
10#endif
11
1ad2134f 12#include "bswap.h"
f6f3fbca 13#include "qemu-queue.h"
1ad2134f 14
b3755a91
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15#if !defined(CONFIG_USER_ONLY)
16
dd310534
AG
17enum device_endian {
18 DEVICE_NATIVE_ENDIAN,
19 DEVICE_BIG_ENDIAN,
20 DEVICE_LITTLE_ENDIAN,
21};
22
1ad2134f 23/* address in the RAM (different from a physical address) */
f15fbc4b
AP
24#if defined(CONFIG_XEN_BACKEND) && TARGET_PHYS_ADDR_BITS == 64
25typedef uint64_t ram_addr_t;
26# define RAM_ADDR_MAX UINT64_MAX
27# define RAM_ADDR_FMT "%" PRIx64
28#else
53576999
SW
29typedef uintptr_t ram_addr_t;
30# define RAM_ADDR_MAX UINTPTR_MAX
31# define RAM_ADDR_FMT "%" PRIxPTR
f15fbc4b 32#endif
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33
34/* memory API */
35
c227f099
AL
36typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
37typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
1ad2134f 38
cd19cfa2 39void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
1ad2134f 40/* This should only be used for ram local to a device. */
c227f099 41void *qemu_get_ram_ptr(ram_addr_t addr);
8ab934f9 42void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size);
b2e0a138
MT
43/* Same but slower, to use for migration, where the order of
44 * RAMBlocks must not change. */
45void *qemu_safe_ram_ptr(ram_addr_t addr);
050a0ddf 46void qemu_put_ram_ptr(void *addr);
1ad2134f 47/* This should not be used by devices. */
e890261f
MT
48int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
49ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
c5705a77 50void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
1ad2134f 51
c227f099 52void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1ad2134f 53 int len, int is_write);
c227f099 54static inline void cpu_physical_memory_read(target_phys_addr_t addr,
3bad9814 55 void *buf, int len)
1ad2134f
PB
56{
57 cpu_physical_memory_rw(addr, buf, len, 0);
58}
c227f099 59static inline void cpu_physical_memory_write(target_phys_addr_t addr,
3bad9814 60 const void *buf, int len)
1ad2134f 61{
3bad9814 62 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
1ad2134f 63}
c227f099
AL
64void *cpu_physical_memory_map(target_phys_addr_t addr,
65 target_phys_addr_t *plen,
1ad2134f 66 int is_write);
c227f099
AL
67void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
68 int is_write, target_phys_addr_t access_len);
1ad2134f
PB
69void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
70void cpu_unregister_map_client(void *cookie);
71
76f35538
WC
72#ifndef CONFIG_USER_ONLY
73bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr);
74#endif
75
6842a08e
BS
76/* Coalesced MMIO regions are areas where write operations can be reordered.
77 * This usually implies that write operations are side-effect free. This allows
78 * batching which can make a major impact on performance when using
79 * virtualization.
80 */
6842a08e
BS
81void qemu_flush_coalesced_mmio_buffer(void);
82
c227f099 83uint32_t ldub_phys(target_phys_addr_t addr);
1e78bcc1
AG
84uint32_t lduw_le_phys(target_phys_addr_t addr);
85uint32_t lduw_be_phys(target_phys_addr_t addr);
1e78bcc1
AG
86uint32_t ldl_le_phys(target_phys_addr_t addr);
87uint32_t ldl_be_phys(target_phys_addr_t addr);
1e78bcc1
AG
88uint64_t ldq_le_phys(target_phys_addr_t addr);
89uint64_t ldq_be_phys(target_phys_addr_t addr);
c227f099 90void stb_phys(target_phys_addr_t addr, uint32_t val);
1e78bcc1
AG
91void stw_le_phys(target_phys_addr_t addr, uint32_t val);
92void stw_be_phys(target_phys_addr_t addr, uint32_t val);
1e78bcc1
AG
93void stl_le_phys(target_phys_addr_t addr, uint32_t val);
94void stl_be_phys(target_phys_addr_t addr, uint32_t val);
1e78bcc1
AG
95void stq_le_phys(target_phys_addr_t addr, uint64_t val);
96void stq_be_phys(target_phys_addr_t addr, uint64_t val);
c227f099 97
21673cde
BS
98#ifdef NEED_CPU_H
99uint32_t lduw_phys(target_phys_addr_t addr);
100uint32_t ldl_phys(target_phys_addr_t addr);
101uint64_t ldq_phys(target_phys_addr_t addr);
102void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
103void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
104void stw_phys(target_phys_addr_t addr, uint32_t val);
105void stl_phys(target_phys_addr_t addr, uint32_t val);
106void stq_phys(target_phys_addr_t addr, uint64_t val);
107#endif
108
c227f099 109void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1ad2134f
PB
110 const uint8_t *buf, int len);
111
0e0df1e2
AK
112extern struct MemoryRegion io_mem_ram;
113extern struct MemoryRegion io_mem_rom;
114extern struct MemoryRegion io_mem_unassigned;
115extern struct MemoryRegion io_mem_notdirty;
1ad2134f 116
b3755a91
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117#endif
118
1ad2134f 119#endif /* !CPU_COMMON_H */