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1ad2134f PB |
1 | #ifndef CPU_COMMON_H |
2 | #define CPU_COMMON_H 1 | |
3 | ||
4 | /* CPU interfaces that are target indpendent. */ | |
5 | ||
6 | #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) | |
7 | #define WORDS_ALIGNED | |
8 | #endif | |
9 | ||
10 | #include "bswap.h" | |
f6f3fbca | 11 | #include "qemu-queue.h" |
1ad2134f | 12 | |
b3755a91 PB |
13 | #if !defined(CONFIG_USER_ONLY) |
14 | ||
1ad2134f | 15 | /* address in the RAM (different from a physical address) */ |
c227f099 | 16 | typedef unsigned long ram_addr_t; |
1ad2134f PB |
17 | |
18 | /* memory API */ | |
19 | ||
c227f099 AL |
20 | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
21 | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); | |
1ad2134f | 22 | |
c227f099 AL |
23 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
24 | ram_addr_t size, | |
25 | ram_addr_t phys_offset, | |
26 | ram_addr_t region_offset); | |
27 | static inline void cpu_register_physical_memory(target_phys_addr_t start_addr, | |
28 | ram_addr_t size, | |
29 | ram_addr_t phys_offset) | |
1ad2134f PB |
30 | { |
31 | cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); | |
32 | } | |
33 | ||
c227f099 AL |
34 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); |
35 | ram_addr_t qemu_ram_alloc(ram_addr_t); | |
36 | void qemu_ram_free(ram_addr_t addr); | |
1ad2134f | 37 | /* This should only be used for ram local to a device. */ |
c227f099 | 38 | void *qemu_get_ram_ptr(ram_addr_t addr); |
1ad2134f | 39 | /* This should not be used by devices. */ |
c227f099 | 40 | ram_addr_t qemu_ram_addr_from_host(void *ptr); |
1ad2134f | 41 | |
d60efc6b BS |
42 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
43 | CPUWriteMemoryFunc * const *mem_write, | |
1ad2134f PB |
44 | void *opaque); |
45 | void cpu_unregister_io_memory(int table_address); | |
46 | ||
c227f099 | 47 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
1ad2134f | 48 | int len, int is_write); |
c227f099 | 49 | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
1ad2134f PB |
50 | uint8_t *buf, int len) |
51 | { | |
52 | cpu_physical_memory_rw(addr, buf, len, 0); | |
53 | } | |
c227f099 | 54 | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
1ad2134f PB |
55 | const uint8_t *buf, int len) |
56 | { | |
57 | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); | |
58 | } | |
c227f099 AL |
59 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
60 | target_phys_addr_t *plen, | |
1ad2134f | 61 | int is_write); |
c227f099 AL |
62 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
63 | int is_write, target_phys_addr_t access_len); | |
1ad2134f PB |
64 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); |
65 | void cpu_unregister_map_client(void *cookie); | |
66 | ||
f6f3fbca MT |
67 | struct CPUPhysMemoryClient; |
68 | typedef struct CPUPhysMemoryClient CPUPhysMemoryClient; | |
69 | struct CPUPhysMemoryClient { | |
70 | void (*set_memory)(struct CPUPhysMemoryClient *client, | |
71 | target_phys_addr_t start_addr, | |
72 | ram_addr_t size, | |
73 | ram_addr_t phys_offset); | |
74 | int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client, | |
75 | target_phys_addr_t start_addr, | |
76 | target_phys_addr_t end_addr); | |
77 | int (*migration_log)(struct CPUPhysMemoryClient *client, | |
78 | int enable); | |
79 | QLIST_ENTRY(CPUPhysMemoryClient) list; | |
80 | }; | |
81 | ||
82 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *); | |
83 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *); | |
84 | ||
6842a08e BS |
85 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
86 | * This usually implies that write operations are side-effect free. This allows | |
87 | * batching which can make a major impact on performance when using | |
88 | * virtualization. | |
89 | */ | |
90 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
91 | ||
92 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
93 | ||
94 | void qemu_flush_coalesced_mmio_buffer(void); | |
95 | ||
c227f099 AL |
96 | uint32_t ldub_phys(target_phys_addr_t addr); |
97 | uint32_t lduw_phys(target_phys_addr_t addr); | |
98 | uint32_t ldl_phys(target_phys_addr_t addr); | |
99 | uint64_t ldq_phys(target_phys_addr_t addr); | |
100 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val); | |
101 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val); | |
102 | void stb_phys(target_phys_addr_t addr, uint32_t val); | |
103 | void stw_phys(target_phys_addr_t addr, uint32_t val); | |
104 | void stl_phys(target_phys_addr_t addr, uint32_t val); | |
105 | void stq_phys(target_phys_addr_t addr, uint64_t val); | |
106 | ||
107 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, | |
1ad2134f PB |
108 | const uint8_t *buf, int len); |
109 | ||
110 | #define IO_MEM_SHIFT 3 | |
111 | ||
112 | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ | |
113 | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ | |
114 | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) | |
115 | #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT) | |
116 | ||
117 | /* Acts like a ROM when read and like a device when written. */ | |
118 | #define IO_MEM_ROMD (1) | |
119 | #define IO_MEM_SUBPAGE (2) | |
120 | #define IO_MEM_SUBWIDTH (4) | |
121 | ||
b3755a91 PB |
122 | #endif |
123 | ||
1ad2134f | 124 | #endif /* !CPU_COMMON_H */ |