]> git.proxmox.com Git - qemu.git/blame - cpu-defs.h
Alpha architecture emulation core.
[qemu.git] / cpu-defs.h
CommitLineData
ab93bbe2
FB
1/*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef CPU_DEFS_H
21#define CPU_DEFS_H
22
23#include "config.h"
24#include <setjmp.h>
ed1c0bcb
FB
25#include <inttypes.h>
26#include "osdep.h"
ab93bbe2 27
35b66fc4
FB
28#ifndef TARGET_LONG_BITS
29#error TARGET_LONG_BITS must be defined before including this header
30#endif
31
ab6d960f 32#ifndef TARGET_PHYS_ADDR_BITS
4f2ac237 33#if TARGET_LONG_BITS >= HOST_LONG_BITS
ab6d960f 34#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
4f2ac237
FB
35#else
36#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
37#endif
ab6d960f
FB
38#endif
39
35b66fc4
FB
40#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
41
ab6d960f 42/* target_ulong is the type of a virtual address */
35b66fc4
FB
43#if TARGET_LONG_SIZE == 4
44typedef int32_t target_long;
45typedef uint32_t target_ulong;
c27004ec 46#define TARGET_FMT_lx "%08x"
b62b461b 47#define TARGET_FMT_ld "%d"
35b66fc4
FB
48#elif TARGET_LONG_SIZE == 8
49typedef int64_t target_long;
50typedef uint64_t target_ulong;
26a76461 51#define TARGET_FMT_lx "%016" PRIx64
b62b461b 52#define TARGET_FMT_ld "%" PRId64
35b66fc4
FB
53#else
54#error TARGET_LONG_SIZE undefined
55#endif
56
ab6d960f 57/* target_phys_addr_t is the type of a physical address (its size can
4f2ac237
FB
58 be different from 'target_ulong'). We have sizeof(target_phys_addr)
59 = max(sizeof(unsigned long),
60 sizeof(size_of_target_physical_address)) because we must pass a
61 host pointer to memory operations in some cases */
62
ab6d960f
FB
63#if TARGET_PHYS_ADDR_BITS == 32
64typedef uint32_t target_phys_addr_t;
65#elif TARGET_PHYS_ADDR_BITS == 64
66typedef uint64_t target_phys_addr_t;
67#else
68#error TARGET_PHYS_ADDR_BITS undefined
69#endif
70
ff7b8f5b
FB
71/* address in the RAM (different from a physical address) */
72typedef unsigned long ram_addr_t;
73
f193c797
FB
74#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
75
2be0071f
FB
76#define EXCP_INTERRUPT 0x10000 /* async interruption */
77#define EXCP_HLT 0x10001 /* hlt instruction reached */
78#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
5a1e3cfc 79#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
ab93bbe2 80#define MAX_BREAKPOINTS 32
6658ffb8 81#define MAX_WATCHPOINTS 32
ab93bbe2 82
a316d335
FB
83#define TB_JMP_CACHE_BITS 12
84#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
85
b362e5e0
PB
86/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
87 addresses on the same page. The top bits are the same. This allows
88 TLB invalidation to quickly clear a subset of the hash table. */
89#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
90#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
91#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
92#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
93
84b7b8e7
FB
94#define CPU_TLB_BITS 8
95#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
ab93bbe2
FB
96
97typedef struct CPUTLBEntry {
db8d7466
FB
98 /* bit 31 to TARGET_PAGE_BITS : virtual address
99 bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
100 zone number
101 bit 3 : indicates that the entry is invalid
102 bit 2..0 : zero
103 */
84b7b8e7
FB
104 target_ulong addr_read;
105 target_ulong addr_write;
106 target_ulong addr_code;
db8d7466 107 /* addend to virtual address to get physical address */
4f2ac237 108 target_phys_addr_t addend;
ab93bbe2
FB
109} CPUTLBEntry;
110
6fa4cea9
JM
111/* Alpha has 4 different running levels */
112#if defined(TARGET_ALPHA)
113#define NB_MMU_MODES 4
114#elif defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
115#define NB_MMU_MODES 3
116#else
117#define NB_MMU_MODES 2
118#endif
119
a316d335
FB
120#define CPU_COMMON \
121 struct TranslationBlock *current_tb; /* currently executing TB */ \
122 /* soft mmu support */ \
123 /* in order to avoid passing too many arguments to the memory \
124 write helpers, we store some rarely used information in the CPU \
125 context) */ \
126 unsigned long mem_write_pc; /* host pc at which the memory was \
127 written */ \
128 target_ulong mem_write_vaddr; /* target virtual addr at which the \
129 memory was written */ \
130 /* 0 = kernel, 1 = user */ \
6fa4cea9 131 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
a316d335
FB
132 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
133 \
134 /* from this point: preserved by CPU reset */ \
135 /* ice debug support */ \
136 target_ulong breakpoints[MAX_BREAKPOINTS]; \
137 int nb_breakpoints; \
138 int singlestep_enabled; \
139 \
6658ffb8
PB
140 struct { \
141 target_ulong vaddr; \
142 int is_ram; \
143 } watchpoint[MAX_WATCHPOINTS]; \
144 int nb_watchpoints; \
145 int watchpoint_hit; \
146 \
6a00d601
FB
147 void *next_cpu; /* next CPU sharing TB cache */ \
148 int cpu_index; /* CPU index (informative) */ \
a316d335
FB
149 /* user data */ \
150 void *opaque;
151
ab93bbe2 152#endif