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Commit | Line | Data |
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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
5fafdf24 | 3 | * |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
7d13299d | 5 | * |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 | 16 | * You should have received a copy of the GNU Lesser General Public |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
7d13299d | 18 | */ |
e4533c7a | 19 | #include "config.h" |
93ac68bc | 20 | #include "exec.h" |
956034d7 | 21 | #include "disas.h" |
7cb69cae | 22 | #include "tcg.h" |
7ba1e619 | 23 | #include "kvm.h" |
1d93f0f0 | 24 | #include "qemu-barrier.h" |
7d13299d | 25 | |
fbf9eeb3 FB |
26 | #if !defined(CONFIG_SOFTMMU) |
27 | #undef EAX | |
28 | #undef ECX | |
29 | #undef EDX | |
30 | #undef EBX | |
31 | #undef ESP | |
32 | #undef EBP | |
33 | #undef ESI | |
34 | #undef EDI | |
35 | #undef EIP | |
36 | #include <signal.h> | |
84778508 | 37 | #ifdef __linux__ |
fbf9eeb3 FB |
38 | #include <sys/ucontext.h> |
39 | #endif | |
84778508 | 40 | #endif |
fbf9eeb3 | 41 | |
dfe5fff3 | 42 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
572a9d4a BS |
43 | // Work around ugly bugs in glibc that mangle global register contents |
44 | #undef env | |
45 | #define env cpu_single_env | |
46 | #endif | |
47 | ||
36bdbe54 FB |
48 | int tb_invalidated_flag; |
49 | ||
f0667e66 | 50 | //#define CONFIG_DEBUG_EXEC |
9de5e440 | 51 | //#define DEBUG_SIGNAL |
7d13299d | 52 | |
6a4955a8 AL |
53 | int qemu_cpu_has_work(CPUState *env) |
54 | { | |
55 | return cpu_has_work(env); | |
56 | } | |
57 | ||
e4533c7a FB |
58 | void cpu_loop_exit(void) |
59 | { | |
1c3569fe | 60 | env->current_tb = NULL; |
e4533c7a FB |
61 | longjmp(env->jmp_env, 1); |
62 | } | |
bfed01fc | 63 | |
fbf9eeb3 FB |
64 | /* exit the current TB from a signal handler. The host registers are |
65 | restored in a state compatible with the CPU emulator | |
66 | */ | |
5fafdf24 | 67 | void cpu_resume_from_signal(CPUState *env1, void *puc) |
fbf9eeb3 FB |
68 | { |
69 | #if !defined(CONFIG_SOFTMMU) | |
84778508 | 70 | #ifdef __linux__ |
fbf9eeb3 | 71 | struct ucontext *uc = puc; |
84778508 BS |
72 | #elif defined(__OpenBSD__) |
73 | struct sigcontext *uc = puc; | |
74 | #endif | |
fbf9eeb3 FB |
75 | #endif |
76 | ||
77 | env = env1; | |
78 | ||
79 | /* XXX: restore cpu registers saved in host registers */ | |
80 | ||
81 | #if !defined(CONFIG_SOFTMMU) | |
82 | if (puc) { | |
83 | /* XXX: use siglongjmp ? */ | |
84778508 | 84 | #ifdef __linux__ |
60e99246 AJ |
85 | #ifdef __ia64 |
86 | sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL); | |
87 | #else | |
fbf9eeb3 | 88 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); |
60e99246 | 89 | #endif |
84778508 BS |
90 | #elif defined(__OpenBSD__) |
91 | sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); | |
92 | #endif | |
fbf9eeb3 FB |
93 | } |
94 | #endif | |
9a3ea654 | 95 | env->exception_index = -1; |
fbf9eeb3 FB |
96 | longjmp(env->jmp_env, 1); |
97 | } | |
98 | ||
2e70f6ef PB |
99 | /* Execute the code without caching the generated code. An interpreter |
100 | could be used if available. */ | |
101 | static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb) | |
102 | { | |
103 | unsigned long next_tb; | |
104 | TranslationBlock *tb; | |
105 | ||
106 | /* Should never happen. | |
107 | We only end up here when an existing TB is too long. */ | |
108 | if (max_cycles > CF_COUNT_MASK) | |
109 | max_cycles = CF_COUNT_MASK; | |
110 | ||
111 | tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, | |
112 | max_cycles); | |
113 | env->current_tb = tb; | |
114 | /* execute the generated code */ | |
115 | next_tb = tcg_qemu_tb_exec(tb->tc_ptr); | |
1c3569fe | 116 | env->current_tb = NULL; |
2e70f6ef PB |
117 | |
118 | if ((next_tb & 3) == 2) { | |
119 | /* Restore PC. This may happen if async event occurs before | |
120 | the TB starts executing. */ | |
622ed360 | 121 | cpu_pc_from_tb(env, tb); |
2e70f6ef PB |
122 | } |
123 | tb_phys_invalidate(tb, -1); | |
124 | tb_free(tb); | |
125 | } | |
126 | ||
8a40a180 FB |
127 | static TranslationBlock *tb_find_slow(target_ulong pc, |
128 | target_ulong cs_base, | |
c068688b | 129 | uint64_t flags) |
8a40a180 FB |
130 | { |
131 | TranslationBlock *tb, **ptb1; | |
8a40a180 | 132 | unsigned int h; |
41c1b1c9 PB |
133 | tb_page_addr_t phys_pc, phys_page1, phys_page2; |
134 | target_ulong virt_page2; | |
3b46e624 | 135 | |
8a40a180 | 136 | tb_invalidated_flag = 0; |
3b46e624 | 137 | |
8a40a180 | 138 | /* find translated block using physical mappings */ |
41c1b1c9 | 139 | phys_pc = get_page_addr_code(env, pc); |
8a40a180 FB |
140 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
141 | phys_page2 = -1; | |
142 | h = tb_phys_hash_func(phys_pc); | |
143 | ptb1 = &tb_phys_hash[h]; | |
144 | for(;;) { | |
145 | tb = *ptb1; | |
146 | if (!tb) | |
147 | goto not_found; | |
5fafdf24 | 148 | if (tb->pc == pc && |
8a40a180 | 149 | tb->page_addr[0] == phys_page1 && |
5fafdf24 | 150 | tb->cs_base == cs_base && |
8a40a180 FB |
151 | tb->flags == flags) { |
152 | /* check next page if needed */ | |
153 | if (tb->page_addr[1] != -1) { | |
5fafdf24 | 154 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
8a40a180 | 155 | TARGET_PAGE_SIZE; |
41c1b1c9 | 156 | phys_page2 = get_page_addr_code(env, virt_page2); |
8a40a180 FB |
157 | if (tb->page_addr[1] == phys_page2) |
158 | goto found; | |
159 | } else { | |
160 | goto found; | |
161 | } | |
162 | } | |
163 | ptb1 = &tb->phys_hash_next; | |
164 | } | |
165 | not_found: | |
2e70f6ef PB |
166 | /* if no translated code available, then translate it now */ |
167 | tb = tb_gen_code(env, pc, cs_base, flags, 0); | |
3b46e624 | 168 | |
8a40a180 | 169 | found: |
2c90fe2b KB |
170 | /* Move the last found TB to the head of the list */ |
171 | if (likely(*ptb1)) { | |
172 | *ptb1 = tb->phys_hash_next; | |
173 | tb->phys_hash_next = tb_phys_hash[h]; | |
174 | tb_phys_hash[h] = tb; | |
175 | } | |
8a40a180 FB |
176 | /* we add the TB in the virtual pc hash table */ |
177 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; | |
8a40a180 FB |
178 | return tb; |
179 | } | |
180 | ||
181 | static inline TranslationBlock *tb_find_fast(void) | |
182 | { | |
183 | TranslationBlock *tb; | |
184 | target_ulong cs_base, pc; | |
6b917547 | 185 | int flags; |
8a40a180 FB |
186 | |
187 | /* we record a subset of the CPU state. It will | |
188 | always be the same before a given translated block | |
189 | is executed. */ | |
6b917547 | 190 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); |
bce61846 | 191 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
551bd27f TS |
192 | if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || |
193 | tb->flags != flags)) { | |
8a40a180 FB |
194 | tb = tb_find_slow(pc, cs_base, flags); |
195 | } | |
196 | return tb; | |
197 | } | |
198 | ||
7d13299d FB |
199 | /* main execution loop */ |
200 | ||
1a28cac3 MT |
201 | volatile sig_atomic_t exit_request; |
202 | ||
e4533c7a | 203 | int cpu_exec(CPUState *env1) |
7d13299d | 204 | { |
1d9000e8 | 205 | volatile host_reg_t saved_env_reg; |
8a40a180 | 206 | int ret, interrupt_request; |
8a40a180 | 207 | TranslationBlock *tb; |
c27004ec | 208 | uint8_t *tc_ptr; |
d5975363 | 209 | unsigned long next_tb; |
8c6939c0 | 210 | |
eda48c34 PB |
211 | if (env1->halted) { |
212 | if (!cpu_has_work(env1)) { | |
213 | return EXCP_HALTED; | |
214 | } | |
215 | ||
216 | env1->halted = 0; | |
217 | } | |
5a1e3cfc | 218 | |
5fafdf24 | 219 | cpu_single_env = env1; |
6a00d601 | 220 | |
24ebf5f3 PB |
221 | /* the access to env below is actually saving the global register's |
222 | value, so that files not including target-xyz/exec.h are free to | |
223 | use it. */ | |
224 | QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env)); | |
225 | saved_env_reg = (host_reg_t) env; | |
1d93f0f0 | 226 | barrier(); |
c27004ec | 227 | env = env1; |
e4533c7a | 228 | |
c629a4bc | 229 | if (unlikely(exit_request)) { |
1a28cac3 | 230 | env->exit_request = 1; |
1a28cac3 MT |
231 | } |
232 | ||
ecb644f4 | 233 | #if defined(TARGET_I386) |
6792a57b JK |
234 | /* put eflags in CPU temporary format */ |
235 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
236 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
237 | CC_OP = CC_OP_EFLAGS; | |
238 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
93ac68bc | 239 | #elif defined(TARGET_SPARC) |
e6e5906b PB |
240 | #elif defined(TARGET_M68K) |
241 | env->cc_op = CC_OP_FLAGS; | |
242 | env->cc_dest = env->sr & 0xf; | |
243 | env->cc_x = (env->sr >> 4) & 1; | |
ecb644f4 TS |
244 | #elif defined(TARGET_ALPHA) |
245 | #elif defined(TARGET_ARM) | |
246 | #elif defined(TARGET_PPC) | |
81ea0e13 | 247 | #elif defined(TARGET_LM32) |
b779e29e | 248 | #elif defined(TARGET_MICROBLAZE) |
6af0bf9c | 249 | #elif defined(TARGET_MIPS) |
fdf9b3e8 | 250 | #elif defined(TARGET_SH4) |
f1ccf904 | 251 | #elif defined(TARGET_CRIS) |
10ec5117 | 252 | #elif defined(TARGET_S390X) |
fdf9b3e8 | 253 | /* XXXXX */ |
e4533c7a FB |
254 | #else |
255 | #error unsupported target CPU | |
256 | #endif | |
3fb2ded1 | 257 | env->exception_index = -1; |
9d27abd9 | 258 | |
7d13299d | 259 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
260 | for(;;) { |
261 | if (setjmp(env->jmp_env) == 0) { | |
dfe5fff3 | 262 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
9ddff3d2 | 263 | #undef env |
6792a57b | 264 | env = cpu_single_env; |
9ddff3d2 BS |
265 | #define env cpu_single_env |
266 | #endif | |
3fb2ded1 FB |
267 | /* if an exception is pending, we execute it here */ |
268 | if (env->exception_index >= 0) { | |
269 | if (env->exception_index >= EXCP_INTERRUPT) { | |
270 | /* exit request from the cpu execution loop */ | |
271 | ret = env->exception_index; | |
272 | break; | |
72d239ed AJ |
273 | } else { |
274 | #if defined(CONFIG_USER_ONLY) | |
3fb2ded1 | 275 | /* if user mode only, we simulate a fake exception |
9f083493 | 276 | which will be handled outside the cpu execution |
3fb2ded1 | 277 | loop */ |
83479e77 | 278 | #if defined(TARGET_I386) |
5fafdf24 TS |
279 | do_interrupt_user(env->exception_index, |
280 | env->exception_is_int, | |
281 | env->error_code, | |
3fb2ded1 | 282 | env->exception_next_eip); |
eba01623 FB |
283 | /* successfully delivered */ |
284 | env->old_exception = -1; | |
83479e77 | 285 | #endif |
3fb2ded1 FB |
286 | ret = env->exception_index; |
287 | break; | |
72d239ed | 288 | #else |
83479e77 | 289 | #if defined(TARGET_I386) |
3fb2ded1 FB |
290 | /* simulate a real cpu exception. On i386, it can |
291 | trigger new exceptions, but we do not handle | |
292 | double or triple faults yet. */ | |
5fafdf24 TS |
293 | do_interrupt(env->exception_index, |
294 | env->exception_is_int, | |
295 | env->error_code, | |
d05e66d2 | 296 | env->exception_next_eip, 0); |
678dde13 TS |
297 | /* successfully delivered */ |
298 | env->old_exception = -1; | |
ce09776b FB |
299 | #elif defined(TARGET_PPC) |
300 | do_interrupt(env); | |
81ea0e13 MW |
301 | #elif defined(TARGET_LM32) |
302 | do_interrupt(env); | |
b779e29e EI |
303 | #elif defined(TARGET_MICROBLAZE) |
304 | do_interrupt(env); | |
6af0bf9c FB |
305 | #elif defined(TARGET_MIPS) |
306 | do_interrupt(env); | |
e95c8d51 | 307 | #elif defined(TARGET_SPARC) |
f2bc7e7f | 308 | do_interrupt(env); |
b5ff1b31 FB |
309 | #elif defined(TARGET_ARM) |
310 | do_interrupt(env); | |
fdf9b3e8 FB |
311 | #elif defined(TARGET_SH4) |
312 | do_interrupt(env); | |
eddf68a6 JM |
313 | #elif defined(TARGET_ALPHA) |
314 | do_interrupt(env); | |
f1ccf904 TS |
315 | #elif defined(TARGET_CRIS) |
316 | do_interrupt(env); | |
0633879f PB |
317 | #elif defined(TARGET_M68K) |
318 | do_interrupt(0); | |
72d239ed | 319 | #endif |
301d2908 | 320 | env->exception_index = -1; |
83479e77 | 321 | #endif |
3fb2ded1 | 322 | } |
5fafdf24 | 323 | } |
9df217a3 | 324 | |
b5fc09ae | 325 | next_tb = 0; /* force lookup of first TB */ |
3fb2ded1 | 326 | for(;;) { |
68a79315 | 327 | interrupt_request = env->interrupt_request; |
e1638bd8 | 328 | if (unlikely(interrupt_request)) { |
329 | if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { | |
330 | /* Mask out external interrupts for this step. */ | |
331 | interrupt_request &= ~(CPU_INTERRUPT_HARD | | |
332 | CPU_INTERRUPT_FIQ | | |
333 | CPU_INTERRUPT_SMI | | |
334 | CPU_INTERRUPT_NMI); | |
335 | } | |
6658ffb8 PB |
336 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
337 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; | |
338 | env->exception_index = EXCP_DEBUG; | |
339 | cpu_loop_exit(); | |
340 | } | |
a90b7318 | 341 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
b779e29e | 342 | defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ |
81ea0e13 | 343 | defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) |
a90b7318 AZ |
344 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
345 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; | |
346 | env->halted = 1; | |
347 | env->exception_index = EXCP_HLT; | |
348 | cpu_loop_exit(); | |
349 | } | |
350 | #endif | |
68a79315 | 351 | #if defined(TARGET_I386) |
b09ea7d5 GN |
352 | if (interrupt_request & CPU_INTERRUPT_INIT) { |
353 | svm_check_intercept(SVM_EXIT_INIT); | |
354 | do_cpu_init(env); | |
355 | env->exception_index = EXCP_HALTED; | |
356 | cpu_loop_exit(); | |
357 | } else if (interrupt_request & CPU_INTERRUPT_SIPI) { | |
358 | do_cpu_sipi(env); | |
359 | } else if (env->hflags2 & HF2_GIF_MASK) { | |
db620f46 FB |
360 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
361 | !(env->hflags & HF_SMM_MASK)) { | |
362 | svm_check_intercept(SVM_EXIT_SMI); | |
363 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; | |
364 | do_smm_enter(); | |
365 | next_tb = 0; | |
366 | } else if ((interrupt_request & CPU_INTERRUPT_NMI) && | |
367 | !(env->hflags2 & HF2_NMI_MASK)) { | |
368 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
369 | env->hflags2 |= HF2_NMI_MASK; | |
370 | do_interrupt(EXCP02_NMI, 0, 0, 0, 1); | |
371 | next_tb = 0; | |
79c4f6b0 HY |
372 | } else if (interrupt_request & CPU_INTERRUPT_MCE) { |
373 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
374 | do_interrupt(EXCP12_MCHK, 0, 0, 0, 0); | |
375 | next_tb = 0; | |
db620f46 FB |
376 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
377 | (((env->hflags2 & HF2_VINTR_MASK) && | |
378 | (env->hflags2 & HF2_HIF_MASK)) || | |
379 | (!(env->hflags2 & HF2_VINTR_MASK) && | |
380 | (env->eflags & IF_MASK && | |
381 | !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { | |
382 | int intno; | |
383 | svm_check_intercept(SVM_EXIT_INTR); | |
384 | env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); | |
385 | intno = cpu_get_pic_interrupt(env); | |
93fcfe39 | 386 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); |
dfe5fff3 | 387 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
9ddff3d2 BS |
388 | #undef env |
389 | env = cpu_single_env; | |
390 | #define env cpu_single_env | |
391 | #endif | |
db620f46 FB |
392 | do_interrupt(intno, 0, 0, 0, 1); |
393 | /* ensure that no TB jump will be modified as | |
394 | the program flow was changed */ | |
395 | next_tb = 0; | |
0573fbfc | 396 | #if !defined(CONFIG_USER_ONLY) |
db620f46 FB |
397 | } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && |
398 | (env->eflags & IF_MASK) && | |
399 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
400 | int intno; | |
401 | /* FIXME: this should respect TPR */ | |
402 | svm_check_intercept(SVM_EXIT_VINTR); | |
db620f46 | 403 | intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); |
93fcfe39 | 404 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); |
db620f46 | 405 | do_interrupt(intno, 0, 0, 0, 1); |
d40c54d6 | 406 | env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
db620f46 | 407 | next_tb = 0; |
907a5b26 | 408 | #endif |
db620f46 | 409 | } |
68a79315 | 410 | } |
ce09776b | 411 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
412 | #if 0 |
413 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
d84bda46 | 414 | cpu_reset(env); |
9fddaa0c FB |
415 | } |
416 | #endif | |
47103572 | 417 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
e9df014c JM |
418 | ppc_hw_interrupt(env); |
419 | if (env->pending_interrupts == 0) | |
420 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
b5fc09ae | 421 | next_tb = 0; |
ce09776b | 422 | } |
81ea0e13 MW |
423 | #elif defined(TARGET_LM32) |
424 | if ((interrupt_request & CPU_INTERRUPT_HARD) | |
425 | && (env->ie & IE_IE)) { | |
426 | env->exception_index = EXCP_IRQ; | |
427 | do_interrupt(env); | |
428 | next_tb = 0; | |
429 | } | |
b779e29e EI |
430 | #elif defined(TARGET_MICROBLAZE) |
431 | if ((interrupt_request & CPU_INTERRUPT_HARD) | |
432 | && (env->sregs[SR_MSR] & MSR_IE) | |
433 | && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) | |
434 | && !(env->iflags & (D_FLAG | IMM_FLAG))) { | |
435 | env->exception_index = EXCP_IRQ; | |
436 | do_interrupt(env); | |
437 | next_tb = 0; | |
438 | } | |
6af0bf9c FB |
439 | #elif defined(TARGET_MIPS) |
440 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
4cdc1cd1 | 441 | cpu_mips_hw_interrupts_pending(env)) { |
6af0bf9c FB |
442 | /* Raise it */ |
443 | env->exception_index = EXCP_EXT_INTERRUPT; | |
444 | env->error_code = 0; | |
445 | do_interrupt(env); | |
b5fc09ae | 446 | next_tb = 0; |
6af0bf9c | 447 | } |
e95c8d51 | 448 | #elif defined(TARGET_SPARC) |
d532b26c IK |
449 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
450 | if (cpu_interrupts_enabled(env) && | |
451 | env->interrupt_index > 0) { | |
452 | int pil = env->interrupt_index & 0xf; | |
453 | int type = env->interrupt_index & 0xf0; | |
454 | ||
455 | if (((type == TT_EXTINT) && | |
456 | cpu_pil_allowed(env, pil)) || | |
457 | type != TT_EXTINT) { | |
458 | env->exception_index = env->interrupt_index; | |
459 | do_interrupt(env); | |
460 | next_tb = 0; | |
461 | } | |
462 | } | |
e95c8d51 FB |
463 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
464 | //do_interrupt(0, 0, 0, 0, 0); | |
465 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
a90b7318 | 466 | } |
b5ff1b31 FB |
467 | #elif defined(TARGET_ARM) |
468 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
469 | && !(env->uncached_cpsr & CPSR_F)) { | |
470 | env->exception_index = EXCP_FIQ; | |
471 | do_interrupt(env); | |
b5fc09ae | 472 | next_tb = 0; |
b5ff1b31 | 473 | } |
9ee6e8bb PB |
474 | /* ARMv7-M interrupt return works by loading a magic value |
475 | into the PC. On real hardware the load causes the | |
476 | return to occur. The qemu implementation performs the | |
477 | jump normally, then does the exception return when the | |
478 | CPU tries to execute code at the magic address. | |
479 | This will cause the magic PC value to be pushed to | |
480 | the stack if an interrupt occured at the wrong time. | |
481 | We avoid this by disabling interrupts when | |
482 | pc contains a magic address. */ | |
b5ff1b31 | 483 | if (interrupt_request & CPU_INTERRUPT_HARD |
9ee6e8bb PB |
484 | && ((IS_M(env) && env->regs[15] < 0xfffffff0) |
485 | || !(env->uncached_cpsr & CPSR_I))) { | |
b5ff1b31 FB |
486 | env->exception_index = EXCP_IRQ; |
487 | do_interrupt(env); | |
b5fc09ae | 488 | next_tb = 0; |
b5ff1b31 | 489 | } |
fdf9b3e8 | 490 | #elif defined(TARGET_SH4) |
e96e2044 TS |
491 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
492 | do_interrupt(env); | |
b5fc09ae | 493 | next_tb = 0; |
e96e2044 | 494 | } |
eddf68a6 JM |
495 | #elif defined(TARGET_ALPHA) |
496 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
497 | do_interrupt(env); | |
b5fc09ae | 498 | next_tb = 0; |
eddf68a6 | 499 | } |
f1ccf904 | 500 | #elif defined(TARGET_CRIS) |
1b1a38b0 | 501 | if (interrupt_request & CPU_INTERRUPT_HARD |
fb9fb692 EI |
502 | && (env->pregs[PR_CCS] & I_FLAG) |
503 | && !env->locked_irq) { | |
1b1a38b0 EI |
504 | env->exception_index = EXCP_IRQ; |
505 | do_interrupt(env); | |
506 | next_tb = 0; | |
507 | } | |
508 | if (interrupt_request & CPU_INTERRUPT_NMI | |
509 | && (env->pregs[PR_CCS] & M_FLAG)) { | |
510 | env->exception_index = EXCP_NMI; | |
f1ccf904 | 511 | do_interrupt(env); |
b5fc09ae | 512 | next_tb = 0; |
f1ccf904 | 513 | } |
0633879f PB |
514 | #elif defined(TARGET_M68K) |
515 | if (interrupt_request & CPU_INTERRUPT_HARD | |
516 | && ((env->sr & SR_I) >> SR_I_SHIFT) | |
517 | < env->pending_level) { | |
518 | /* Real hardware gets the interrupt vector via an | |
519 | IACK cycle at this point. Current emulated | |
520 | hardware doesn't rely on this, so we | |
521 | provide/save the vector when the interrupt is | |
522 | first signalled. */ | |
523 | env->exception_index = env->pending_vector; | |
524 | do_interrupt(1); | |
b5fc09ae | 525 | next_tb = 0; |
0633879f | 526 | } |
68a79315 | 527 | #endif |
9d05095e FB |
528 | /* Don't use the cached interupt_request value, |
529 | do_interrupt may have updated the EXITTB flag. */ | |
b5ff1b31 | 530 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bf3e8bf1 FB |
531 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
532 | /* ensure that no TB jump will be modified as | |
533 | the program flow was changed */ | |
b5fc09ae | 534 | next_tb = 0; |
bf3e8bf1 | 535 | } |
be214e6c AJ |
536 | } |
537 | if (unlikely(env->exit_request)) { | |
538 | env->exit_request = 0; | |
539 | env->exception_index = EXCP_INTERRUPT; | |
540 | cpu_loop_exit(); | |
3fb2ded1 | 541 | } |
a73b1fd9 | 542 | #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC) |
8fec2b8c | 543 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
3fb2ded1 | 544 | /* restore flags in standard format */ |
ecb644f4 | 545 | #if defined(TARGET_I386) |
a7812ae4 | 546 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
93fcfe39 | 547 | log_cpu_state(env, X86_DUMP_CCOP); |
3fb2ded1 | 548 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e6e5906b PB |
549 | #elif defined(TARGET_M68K) |
550 | cpu_m68k_flush_flags(env, env->cc_op); | |
551 | env->cc_op = CC_OP_FLAGS; | |
552 | env->sr = (env->sr & 0xffe0) | |
553 | | env->cc_dest | (env->cc_x << 4); | |
93fcfe39 | 554 | log_cpu_state(env, 0); |
e4533c7a | 555 | #else |
a73b1fd9 | 556 | log_cpu_state(env, 0); |
e4533c7a | 557 | #endif |
3fb2ded1 | 558 | } |
a73b1fd9 | 559 | #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */ |
d5975363 | 560 | spin_lock(&tb_lock); |
8a40a180 | 561 | tb = tb_find_fast(); |
d5975363 PB |
562 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
563 | doing it in tb_find_slow */ | |
564 | if (tb_invalidated_flag) { | |
565 | /* as some TB could have been invalidated because | |
566 | of memory exceptions while generating the code, we | |
567 | must recompute the hash index here */ | |
568 | next_tb = 0; | |
2e70f6ef | 569 | tb_invalidated_flag = 0; |
d5975363 | 570 | } |
f0667e66 | 571 | #ifdef CONFIG_DEBUG_EXEC |
93fcfe39 AL |
572 | qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
573 | (long)tb->tc_ptr, tb->pc, | |
574 | lookup_symbol(tb->pc)); | |
9d27abd9 | 575 | #endif |
8a40a180 FB |
576 | /* see if we can patch the calling TB. When the TB |
577 | spans two pages, we cannot safely do a direct | |
578 | jump. */ | |
040f2fb2 | 579 | if (next_tb != 0 && tb->page_addr[1] == -1) { |
b5fc09ae | 580 | tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb); |
3fb2ded1 | 581 | } |
d5975363 | 582 | spin_unlock(&tb_lock); |
55e8b85e | 583 | |
584 | /* cpu_interrupt might be called while translating the | |
585 | TB, but before it is linked into a potentially | |
586 | infinite loop and becomes env->current_tb. Avoid | |
587 | starting execution if there is a pending interrupt. */ | |
b0052d15 JK |
588 | env->current_tb = tb; |
589 | barrier(); | |
590 | if (likely(!env->exit_request)) { | |
2e70f6ef | 591 | tc_ptr = tb->tc_ptr; |
3fb2ded1 | 592 | /* execute the generated code */ |
dfe5fff3 | 593 | #if defined(__sparc__) && !defined(CONFIG_SOLARIS) |
572a9d4a | 594 | #undef env |
2e70f6ef | 595 | env = cpu_single_env; |
572a9d4a BS |
596 | #define env cpu_single_env |
597 | #endif | |
2e70f6ef | 598 | next_tb = tcg_qemu_tb_exec(tc_ptr); |
2e70f6ef | 599 | if ((next_tb & 3) == 2) { |
bf20dc07 | 600 | /* Instruction counter expired. */ |
2e70f6ef PB |
601 | int insns_left; |
602 | tb = (TranslationBlock *)(long)(next_tb & ~3); | |
603 | /* Restore PC. */ | |
622ed360 | 604 | cpu_pc_from_tb(env, tb); |
2e70f6ef PB |
605 | insns_left = env->icount_decr.u32; |
606 | if (env->icount_extra && insns_left >= 0) { | |
607 | /* Refill decrementer and continue execution. */ | |
608 | env->icount_extra += insns_left; | |
609 | if (env->icount_extra > 0xffff) { | |
610 | insns_left = 0xffff; | |
611 | } else { | |
612 | insns_left = env->icount_extra; | |
613 | } | |
614 | env->icount_extra -= insns_left; | |
615 | env->icount_decr.u16.low = insns_left; | |
616 | } else { | |
617 | if (insns_left > 0) { | |
618 | /* Execute remaining instructions. */ | |
619 | cpu_exec_nocache(insns_left, tb); | |
620 | } | |
621 | env->exception_index = EXCP_INTERRUPT; | |
622 | next_tb = 0; | |
623 | cpu_loop_exit(); | |
624 | } | |
625 | } | |
626 | } | |
b0052d15 | 627 | env->current_tb = NULL; |
4cbf74b6 FB |
628 | /* reset soft MMU for next block (it can currently |
629 | only be set by a memory fault) */ | |
50a518e3 | 630 | } /* for(;;) */ |
7d13299d | 631 | } |
3fb2ded1 FB |
632 | } /* for(;;) */ |
633 | ||
7d13299d | 634 | |
e4533c7a | 635 | #if defined(TARGET_I386) |
9de5e440 | 636 | /* restore flags in standard format */ |
a7812ae4 | 637 | env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
e4533c7a | 638 | #elif defined(TARGET_ARM) |
b7bcbe95 | 639 | /* XXX: Save/restore host fpu exception state?. */ |
93ac68bc | 640 | #elif defined(TARGET_SPARC) |
67867308 | 641 | #elif defined(TARGET_PPC) |
81ea0e13 | 642 | #elif defined(TARGET_LM32) |
e6e5906b PB |
643 | #elif defined(TARGET_M68K) |
644 | cpu_m68k_flush_flags(env, env->cc_op); | |
645 | env->cc_op = CC_OP_FLAGS; | |
646 | env->sr = (env->sr & 0xffe0) | |
647 | | env->cc_dest | (env->cc_x << 4); | |
b779e29e | 648 | #elif defined(TARGET_MICROBLAZE) |
6af0bf9c | 649 | #elif defined(TARGET_MIPS) |
fdf9b3e8 | 650 | #elif defined(TARGET_SH4) |
eddf68a6 | 651 | #elif defined(TARGET_ALPHA) |
f1ccf904 | 652 | #elif defined(TARGET_CRIS) |
10ec5117 | 653 | #elif defined(TARGET_S390X) |
fdf9b3e8 | 654 | /* XXXXX */ |
e4533c7a FB |
655 | #else |
656 | #error unsupported target CPU | |
657 | #endif | |
1057eaa7 PB |
658 | |
659 | /* restore global registers */ | |
1d93f0f0 | 660 | barrier(); |
24ebf5f3 | 661 | env = (void *) saved_env_reg; |
1057eaa7 | 662 | |
6a00d601 | 663 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
5fafdf24 | 664 | cpu_single_env = NULL; |
7d13299d FB |
665 | return ret; |
666 | } | |
6dbad63e | 667 | |
fbf9eeb3 FB |
668 | /* must only be called from the generated code as an exception can be |
669 | generated */ | |
670 | void tb_invalidate_page_range(target_ulong start, target_ulong end) | |
671 | { | |
dc5d0b3d FB |
672 | /* XXX: cannot enable it yet because it yields to MMU exception |
673 | where NIP != read address on PowerPC */ | |
674 | #if 0 | |
fbf9eeb3 FB |
675 | target_ulong phys_addr; |
676 | phys_addr = get_phys_addr_code(env, start); | |
677 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); | |
dc5d0b3d | 678 | #endif |
fbf9eeb3 FB |
679 | } |
680 | ||
1a18c71b | 681 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 682 | |
6dbad63e FB |
683 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
684 | { | |
685 | CPUX86State *saved_env; | |
686 | ||
687 | saved_env = env; | |
688 | env = s; | |
a412ac57 | 689 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 690 | selector &= 0xffff; |
5fafdf24 | 691 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
c27004ec | 692 | (selector << 4), 0xffff, 0); |
a513fe19 | 693 | } else { |
5d97559d | 694 | helper_load_seg(seg_reg, selector); |
a513fe19 | 695 | } |
6dbad63e FB |
696 | env = saved_env; |
697 | } | |
9de5e440 | 698 | |
6f12a2a6 | 699 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32) |
d0a1ffc9 FB |
700 | { |
701 | CPUX86State *saved_env; | |
702 | ||
703 | saved_env = env; | |
704 | env = s; | |
3b46e624 | 705 | |
6f12a2a6 | 706 | helper_fsave(ptr, data32); |
d0a1ffc9 FB |
707 | |
708 | env = saved_env; | |
709 | } | |
710 | ||
6f12a2a6 | 711 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32) |
d0a1ffc9 FB |
712 | { |
713 | CPUX86State *saved_env; | |
714 | ||
715 | saved_env = env; | |
716 | env = s; | |
3b46e624 | 717 | |
6f12a2a6 | 718 | helper_frstor(ptr, data32); |
d0a1ffc9 FB |
719 | |
720 | env = saved_env; | |
721 | } | |
722 | ||
e4533c7a FB |
723 | #endif /* TARGET_I386 */ |
724 | ||
67b915a5 FB |
725 | #if !defined(CONFIG_SOFTMMU) |
726 | ||
3fb2ded1 | 727 | #if defined(TARGET_I386) |
0b5c1ce8 NF |
728 | #define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code) |
729 | #else | |
730 | #define EXCEPTION_ACTION cpu_loop_exit() | |
731 | #endif | |
3fb2ded1 | 732 | |
b56dad1c | 733 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
734 | the effective address of the memory exception. 'is_write' is 1 if a |
735 | write caused the exception and otherwise 0'. 'old_set' is the | |
736 | signal set which should be restored */ | |
2b413144 | 737 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
5fafdf24 | 738 | int is_write, sigset_t *old_set, |
bf3e8bf1 | 739 | void *puc) |
9de5e440 | 740 | { |
a513fe19 FB |
741 | TranslationBlock *tb; |
742 | int ret; | |
68a79315 | 743 | |
83479e77 FB |
744 | if (cpu_single_env) |
745 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 746 | #if defined(DEBUG_SIGNAL) |
5fafdf24 | 747 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
bf3e8bf1 | 748 | pc, address, is_write, *(unsigned long *)old_set); |
9de5e440 | 749 | #endif |
25eb4484 | 750 | /* XXX: locking issue */ |
53a5960a | 751 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
fd6ce8f6 FB |
752 | return 1; |
753 | } | |
fbf9eeb3 | 754 | |
3fb2ded1 | 755 | /* see if it is an MMU fault */ |
0b5c1ce8 | 756 | ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); |
68016c62 FB |
757 | if (ret < 0) |
758 | return 0; /* not an MMU fault */ | |
759 | if (ret == 0) | |
760 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
761 | /* now we have a real cpu fault */ | |
762 | tb = tb_find_pc(pc); | |
763 | if (tb) { | |
764 | /* the PC is inside the translated code. It means that we have | |
765 | a virtual CPU fault */ | |
766 | cpu_restore_state(tb, env, pc, puc); | |
767 | } | |
68016c62 | 768 | |
68016c62 FB |
769 | /* we restore the process signal mask as the sigreturn should |
770 | do it (XXX: use sigsetjmp) */ | |
771 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
0b5c1ce8 | 772 | EXCEPTION_ACTION; |
e6e5906b | 773 | |
e6e5906b | 774 | /* never comes here */ |
67867308 FB |
775 | return 1; |
776 | } | |
6af0bf9c | 777 | |
2b413144 FB |
778 | #if defined(__i386__) |
779 | ||
d8ecc0b9 FB |
780 | #if defined(__APPLE__) |
781 | # include <sys/ucontext.h> | |
782 | ||
783 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip)) | |
784 | # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno) | |
785 | # define ERROR_sig(context) ((context)->uc_mcontext->es.err) | |
d39bb24a | 786 | # define MASK_sig(context) ((context)->uc_sigmask) |
78cfb07f JL |
787 | #elif defined (__NetBSD__) |
788 | # include <ucontext.h> | |
789 | ||
790 | # define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) | |
791 | # define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) | |
792 | # define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) | |
793 | # define MASK_sig(context) ((context)->uc_sigmask) | |
794 | #elif defined (__FreeBSD__) || defined(__DragonFly__) | |
795 | # include <ucontext.h> | |
796 | ||
797 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip)) | |
798 | # define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) | |
799 | # define ERROR_sig(context) ((context)->uc_mcontext.mc_err) | |
800 | # define MASK_sig(context) ((context)->uc_sigmask) | |
d39bb24a BS |
801 | #elif defined(__OpenBSD__) |
802 | # define EIP_sig(context) ((context)->sc_eip) | |
803 | # define TRAP_sig(context) ((context)->sc_trapno) | |
804 | # define ERROR_sig(context) ((context)->sc_err) | |
805 | # define MASK_sig(context) ((context)->sc_mask) | |
d8ecc0b9 FB |
806 | #else |
807 | # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) | |
808 | # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) | |
809 | # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) | |
d39bb24a | 810 | # define MASK_sig(context) ((context)->uc_sigmask) |
d8ecc0b9 FB |
811 | #endif |
812 | ||
5fafdf24 | 813 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 814 | void *puc) |
9de5e440 | 815 | { |
5a7b542b | 816 | siginfo_t *info = pinfo; |
78cfb07f JL |
817 | #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__) |
818 | ucontext_t *uc = puc; | |
819 | #elif defined(__OpenBSD__) | |
d39bb24a BS |
820 | struct sigcontext *uc = puc; |
821 | #else | |
9de5e440 | 822 | struct ucontext *uc = puc; |
d39bb24a | 823 | #endif |
9de5e440 | 824 | unsigned long pc; |
bf3e8bf1 | 825 | int trapno; |
97eb5b14 | 826 | |
d691f669 FB |
827 | #ifndef REG_EIP |
828 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
829 | #define REG_EIP EIP |
830 | #define REG_ERR ERR | |
831 | #define REG_TRAPNO TRAPNO | |
d691f669 | 832 | #endif |
d8ecc0b9 FB |
833 | pc = EIP_sig(uc); |
834 | trapno = TRAP_sig(uc); | |
ec6338ba FB |
835 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
836 | trapno == 0xe ? | |
837 | (ERROR_sig(uc) >> 1) & 1 : 0, | |
d39bb24a | 838 | &MASK_sig(uc), puc); |
2b413144 FB |
839 | } |
840 | ||
bc51c5c9 FB |
841 | #elif defined(__x86_64__) |
842 | ||
b3efe5c8 | 843 | #ifdef __NetBSD__ |
d397abbd BS |
844 | #define PC_sig(context) _UC_MACHINE_PC(context) |
845 | #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) | |
846 | #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) | |
847 | #define MASK_sig(context) ((context)->uc_sigmask) | |
848 | #elif defined(__OpenBSD__) | |
849 | #define PC_sig(context) ((context)->sc_rip) | |
850 | #define TRAP_sig(context) ((context)->sc_trapno) | |
851 | #define ERROR_sig(context) ((context)->sc_err) | |
852 | #define MASK_sig(context) ((context)->sc_mask) | |
78cfb07f JL |
853 | #elif defined (__FreeBSD__) || defined(__DragonFly__) |
854 | #include <ucontext.h> | |
855 | ||
856 | #define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip)) | |
857 | #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) | |
858 | #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) | |
859 | #define MASK_sig(context) ((context)->uc_sigmask) | |
b3efe5c8 | 860 | #else |
d397abbd BS |
861 | #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) |
862 | #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) | |
863 | #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) | |
864 | #define MASK_sig(context) ((context)->uc_sigmask) | |
b3efe5c8 BS |
865 | #endif |
866 | ||
5a7b542b | 867 | int cpu_signal_handler(int host_signum, void *pinfo, |
bc51c5c9 FB |
868 | void *puc) |
869 | { | |
5a7b542b | 870 | siginfo_t *info = pinfo; |
bc51c5c9 | 871 | unsigned long pc; |
78cfb07f | 872 | #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__) |
b3efe5c8 | 873 | ucontext_t *uc = puc; |
d397abbd BS |
874 | #elif defined(__OpenBSD__) |
875 | struct sigcontext *uc = puc; | |
b3efe5c8 BS |
876 | #else |
877 | struct ucontext *uc = puc; | |
878 | #endif | |
bc51c5c9 | 879 | |
d397abbd | 880 | pc = PC_sig(uc); |
5fafdf24 | 881 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
d397abbd BS |
882 | TRAP_sig(uc) == 0xe ? |
883 | (ERROR_sig(uc) >> 1) & 1 : 0, | |
884 | &MASK_sig(uc), puc); | |
bc51c5c9 FB |
885 | } |
886 | ||
e58ffeb3 | 887 | #elif defined(_ARCH_PPC) |
2b413144 | 888 | |
83fb7adf FB |
889 | /*********************************************************************** |
890 | * signal context platform-specific definitions | |
891 | * From Wine | |
892 | */ | |
893 | #ifdef linux | |
894 | /* All Registers access - only for local access */ | |
895 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) | |
896 | /* Gpr Registers access */ | |
897 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
898 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ | |
899 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ | |
900 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ | |
901 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ | |
902 | # define LR_sig(context) REG_sig(link, context) /* Link register */ | |
903 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ | |
904 | /* Float Registers access */ | |
905 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) | |
906 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) | |
907 | /* Exception Registers access */ | |
908 | # define DAR_sig(context) REG_sig(dar, context) | |
909 | # define DSISR_sig(context) REG_sig(dsisr, context) | |
910 | # define TRAP_sig(context) REG_sig(trap, context) | |
911 | #endif /* linux */ | |
912 | ||
58d9b1e0 JL |
913 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
914 | #include <ucontext.h> | |
915 | # define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) | |
916 | # define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) | |
917 | # define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) | |
918 | # define XER_sig(context) ((context)->uc_mcontext.mc_xer) | |
919 | # define LR_sig(context) ((context)->uc_mcontext.mc_lr) | |
920 | # define CR_sig(context) ((context)->uc_mcontext.mc_cr) | |
921 | /* Exception Registers access */ | |
922 | # define DAR_sig(context) ((context)->uc_mcontext.mc_dar) | |
923 | # define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) | |
924 | # define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) | |
925 | #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ | |
926 | ||
83fb7adf FB |
927 | #ifdef __APPLE__ |
928 | # include <sys/ucontext.h> | |
929 | typedef struct ucontext SIGCONTEXT; | |
930 | /* All Registers access - only for local access */ | |
931 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) | |
932 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) | |
933 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) | |
934 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) | |
935 | /* Gpr Registers access */ | |
936 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) | |
937 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ | |
938 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ | |
939 | # define CTR_sig(context) REG_sig(ctr, context) | |
940 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ | |
941 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ | |
942 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ | |
943 | /* Float Registers access */ | |
944 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) | |
945 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) | |
946 | /* Exception Registers access */ | |
947 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ | |
948 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) | |
949 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ | |
950 | #endif /* __APPLE__ */ | |
951 | ||
5fafdf24 | 952 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 953 | void *puc) |
2b413144 | 954 | { |
5a7b542b | 955 | siginfo_t *info = pinfo; |
58d9b1e0 JL |
956 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
957 | ucontext_t *uc = puc; | |
958 | #else | |
25eb4484 | 959 | struct ucontext *uc = puc; |
58d9b1e0 | 960 | #endif |
25eb4484 | 961 | unsigned long pc; |
25eb4484 FB |
962 | int is_write; |
963 | ||
83fb7adf | 964 | pc = IAR_sig(uc); |
25eb4484 FB |
965 | is_write = 0; |
966 | #if 0 | |
967 | /* ppc 4xx case */ | |
83fb7adf | 968 | if (DSISR_sig(uc) & 0x00800000) |
25eb4484 FB |
969 | is_write = 1; |
970 | #else | |
83fb7adf | 971 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
25eb4484 FB |
972 | is_write = 1; |
973 | #endif | |
5fafdf24 | 974 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bf3e8bf1 | 975 | is_write, &uc->uc_sigmask, puc); |
2b413144 FB |
976 | } |
977 | ||
2f87c607 FB |
978 | #elif defined(__alpha__) |
979 | ||
5fafdf24 | 980 | int cpu_signal_handler(int host_signum, void *pinfo, |
2f87c607 FB |
981 | void *puc) |
982 | { | |
5a7b542b | 983 | siginfo_t *info = pinfo; |
2f87c607 FB |
984 | struct ucontext *uc = puc; |
985 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
986 | uint32_t insn = *pc; | |
987 | int is_write = 0; | |
988 | ||
8c6939c0 | 989 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
990 | switch (insn >> 26) { |
991 | case 0x0d: // stw | |
992 | case 0x0e: // stb | |
993 | case 0x0f: // stq_u | |
994 | case 0x24: // stf | |
995 | case 0x25: // stg | |
996 | case 0x26: // sts | |
997 | case 0x27: // stt | |
998 | case 0x2c: // stl | |
999 | case 0x2d: // stq | |
1000 | case 0x2e: // stl_c | |
1001 | case 0x2f: // stq_c | |
1002 | is_write = 1; | |
1003 | } | |
1004 | ||
5fafdf24 | 1005 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bf3e8bf1 | 1006 | is_write, &uc->uc_sigmask, puc); |
2f87c607 | 1007 | } |
8c6939c0 FB |
1008 | #elif defined(__sparc__) |
1009 | ||
5fafdf24 | 1010 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 1011 | void *puc) |
8c6939c0 | 1012 | { |
5a7b542b | 1013 | siginfo_t *info = pinfo; |
8c6939c0 FB |
1014 | int is_write; |
1015 | uint32_t insn; | |
dfe5fff3 | 1016 | #if !defined(__arch64__) || defined(CONFIG_SOLARIS) |
c9e1e2b0 BS |
1017 | uint32_t *regs = (uint32_t *)(info + 1); |
1018 | void *sigmask = (regs + 20); | |
8c6939c0 | 1019 | /* XXX: is there a standard glibc define ? */ |
c9e1e2b0 BS |
1020 | unsigned long pc = regs[1]; |
1021 | #else | |
84778508 | 1022 | #ifdef __linux__ |
c9e1e2b0 BS |
1023 | struct sigcontext *sc = puc; |
1024 | unsigned long pc = sc->sigc_regs.tpc; | |
1025 | void *sigmask = (void *)sc->sigc_mask; | |
84778508 BS |
1026 | #elif defined(__OpenBSD__) |
1027 | struct sigcontext *uc = puc; | |
1028 | unsigned long pc = uc->sc_pc; | |
1029 | void *sigmask = (void *)(long)uc->sc_mask; | |
1030 | #endif | |
c9e1e2b0 BS |
1031 | #endif |
1032 | ||
8c6939c0 FB |
1033 | /* XXX: need kernel patch to get write flag faster */ |
1034 | is_write = 0; | |
1035 | insn = *(uint32_t *)pc; | |
1036 | if ((insn >> 30) == 3) { | |
1037 | switch((insn >> 19) & 0x3f) { | |
1038 | case 0x05: // stb | |
d877fa5a | 1039 | case 0x15: // stba |
8c6939c0 | 1040 | case 0x06: // sth |
d877fa5a | 1041 | case 0x16: // stha |
8c6939c0 | 1042 | case 0x04: // st |
d877fa5a | 1043 | case 0x14: // sta |
8c6939c0 | 1044 | case 0x07: // std |
d877fa5a BS |
1045 | case 0x17: // stda |
1046 | case 0x0e: // stx | |
1047 | case 0x1e: // stxa | |
8c6939c0 | 1048 | case 0x24: // stf |
d877fa5a | 1049 | case 0x34: // stfa |
8c6939c0 | 1050 | case 0x27: // stdf |
d877fa5a BS |
1051 | case 0x37: // stdfa |
1052 | case 0x26: // stqf | |
1053 | case 0x36: // stqfa | |
8c6939c0 | 1054 | case 0x25: // stfsr |
d877fa5a BS |
1055 | case 0x3c: // casa |
1056 | case 0x3e: // casxa | |
8c6939c0 FB |
1057 | is_write = 1; |
1058 | break; | |
1059 | } | |
1060 | } | |
5fafdf24 | 1061 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
bf3e8bf1 | 1062 | is_write, sigmask, NULL); |
8c6939c0 FB |
1063 | } |
1064 | ||
1065 | #elif defined(__arm__) | |
1066 | ||
5fafdf24 | 1067 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 1068 | void *puc) |
8c6939c0 | 1069 | { |
5a7b542b | 1070 | siginfo_t *info = pinfo; |
8c6939c0 FB |
1071 | struct ucontext *uc = puc; |
1072 | unsigned long pc; | |
1073 | int is_write; | |
3b46e624 | 1074 | |
48bbf11b | 1075 | #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) |
5c49b363 AZ |
1076 | pc = uc->uc_mcontext.gregs[R15]; |
1077 | #else | |
4eee57f5 | 1078 | pc = uc->uc_mcontext.arm_pc; |
5c49b363 | 1079 | #endif |
8c6939c0 FB |
1080 | /* XXX: compute is_write */ |
1081 | is_write = 0; | |
5fafdf24 | 1082 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
8c6939c0 | 1083 | is_write, |
f3a9676a | 1084 | &uc->uc_sigmask, puc); |
8c6939c0 FB |
1085 | } |
1086 | ||
38e584a0 FB |
1087 | #elif defined(__mc68000) |
1088 | ||
5fafdf24 | 1089 | int cpu_signal_handler(int host_signum, void *pinfo, |
38e584a0 FB |
1090 | void *puc) |
1091 | { | |
5a7b542b | 1092 | siginfo_t *info = pinfo; |
38e584a0 FB |
1093 | struct ucontext *uc = puc; |
1094 | unsigned long pc; | |
1095 | int is_write; | |
3b46e624 | 1096 | |
38e584a0 FB |
1097 | pc = uc->uc_mcontext.gregs[16]; |
1098 | /* XXX: compute is_write */ | |
1099 | is_write = 0; | |
5fafdf24 | 1100 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
38e584a0 | 1101 | is_write, |
bf3e8bf1 | 1102 | &uc->uc_sigmask, puc); |
38e584a0 FB |
1103 | } |
1104 | ||
b8076a74 FB |
1105 | #elif defined(__ia64) |
1106 | ||
1107 | #ifndef __ISR_VALID | |
1108 | /* This ought to be in <bits/siginfo.h>... */ | |
1109 | # define __ISR_VALID 1 | |
b8076a74 FB |
1110 | #endif |
1111 | ||
5a7b542b | 1112 | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
b8076a74 | 1113 | { |
5a7b542b | 1114 | siginfo_t *info = pinfo; |
b8076a74 FB |
1115 | struct ucontext *uc = puc; |
1116 | unsigned long ip; | |
1117 | int is_write = 0; | |
1118 | ||
1119 | ip = uc->uc_mcontext.sc_ip; | |
1120 | switch (host_signum) { | |
1121 | case SIGILL: | |
1122 | case SIGFPE: | |
1123 | case SIGSEGV: | |
1124 | case SIGBUS: | |
1125 | case SIGTRAP: | |
fd4a43e4 | 1126 | if (info->si_code && (info->si_segvflags & __ISR_VALID)) |
b8076a74 FB |
1127 | /* ISR.W (write-access) is bit 33: */ |
1128 | is_write = (info->si_isr >> 33) & 1; | |
1129 | break; | |
1130 | ||
1131 | default: | |
1132 | break; | |
1133 | } | |
1134 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, | |
1135 | is_write, | |
60e99246 | 1136 | (sigset_t *)&uc->uc_sigmask, puc); |
b8076a74 FB |
1137 | } |
1138 | ||
90cb9493 FB |
1139 | #elif defined(__s390__) |
1140 | ||
5fafdf24 | 1141 | int cpu_signal_handler(int host_signum, void *pinfo, |
90cb9493 FB |
1142 | void *puc) |
1143 | { | |
5a7b542b | 1144 | siginfo_t *info = pinfo; |
90cb9493 FB |
1145 | struct ucontext *uc = puc; |
1146 | unsigned long pc; | |
6a1621b9 RH |
1147 | uint16_t *pinsn; |
1148 | int is_write = 0; | |
3b46e624 | 1149 | |
90cb9493 | 1150 | pc = uc->uc_mcontext.psw.addr; |
6a1621b9 RH |
1151 | |
1152 | /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead | |
1153 | of the normal 2 arguments. The 3rd argument contains the "int_code" | |
1154 | from the hardware which does in fact contain the is_write value. | |
1155 | The rt signal handler, as far as I can tell, does not give this value | |
1156 | at all. Not that we could get to it from here even if it were. */ | |
1157 | /* ??? This is not even close to complete, since it ignores all | |
1158 | of the read-modify-write instructions. */ | |
1159 | pinsn = (uint16_t *)pc; | |
1160 | switch (pinsn[0] >> 8) { | |
1161 | case 0x50: /* ST */ | |
1162 | case 0x42: /* STC */ | |
1163 | case 0x40: /* STH */ | |
1164 | is_write = 1; | |
1165 | break; | |
1166 | case 0xc4: /* RIL format insns */ | |
1167 | switch (pinsn[0] & 0xf) { | |
1168 | case 0xf: /* STRL */ | |
1169 | case 0xb: /* STGRL */ | |
1170 | case 0x7: /* STHRL */ | |
1171 | is_write = 1; | |
1172 | } | |
1173 | break; | |
1174 | case 0xe3: /* RXY format insns */ | |
1175 | switch (pinsn[2] & 0xff) { | |
1176 | case 0x50: /* STY */ | |
1177 | case 0x24: /* STG */ | |
1178 | case 0x72: /* STCY */ | |
1179 | case 0x70: /* STHY */ | |
1180 | case 0x8e: /* STPQ */ | |
1181 | case 0x3f: /* STRVH */ | |
1182 | case 0x3e: /* STRV */ | |
1183 | case 0x2f: /* STRVG */ | |
1184 | is_write = 1; | |
1185 | } | |
1186 | break; | |
1187 | } | |
5fafdf24 | 1188 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
c4b89d18 TS |
1189 | is_write, &uc->uc_sigmask, puc); |
1190 | } | |
1191 | ||
1192 | #elif defined(__mips__) | |
1193 | ||
5fafdf24 | 1194 | int cpu_signal_handler(int host_signum, void *pinfo, |
c4b89d18 TS |
1195 | void *puc) |
1196 | { | |
9617efe8 | 1197 | siginfo_t *info = pinfo; |
c4b89d18 TS |
1198 | struct ucontext *uc = puc; |
1199 | greg_t pc = uc->uc_mcontext.pc; | |
1200 | int is_write; | |
3b46e624 | 1201 | |
c4b89d18 TS |
1202 | /* XXX: compute is_write */ |
1203 | is_write = 0; | |
5fafdf24 | 1204 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
c4b89d18 | 1205 | is_write, &uc->uc_sigmask, puc); |
90cb9493 FB |
1206 | } |
1207 | ||
f54b3f92 AJ |
1208 | #elif defined(__hppa__) |
1209 | ||
1210 | int cpu_signal_handler(int host_signum, void *pinfo, | |
1211 | void *puc) | |
1212 | { | |
1213 | struct siginfo *info = pinfo; | |
1214 | struct ucontext *uc = puc; | |
f57040be RH |
1215 | unsigned long pc = uc->uc_mcontext.sc_iaoq[0]; |
1216 | uint32_t insn = *(uint32_t *)pc; | |
1217 | int is_write = 0; | |
1218 | ||
1219 | /* XXX: need kernel patch to get write flag faster. */ | |
1220 | switch (insn >> 26) { | |
1221 | case 0x1a: /* STW */ | |
1222 | case 0x19: /* STH */ | |
1223 | case 0x18: /* STB */ | |
1224 | case 0x1b: /* STWM */ | |
1225 | is_write = 1; | |
1226 | break; | |
1227 | ||
1228 | case 0x09: /* CSTWX, FSTWX, FSTWS */ | |
1229 | case 0x0b: /* CSTDX, FSTDX, FSTDS */ | |
1230 | /* Distinguish from coprocessor load ... */ | |
1231 | is_write = (insn >> 9) & 1; | |
1232 | break; | |
1233 | ||
1234 | case 0x03: | |
1235 | switch ((insn >> 6) & 15) { | |
1236 | case 0xa: /* STWS */ | |
1237 | case 0x9: /* STHS */ | |
1238 | case 0x8: /* STBS */ | |
1239 | case 0xe: /* STWAS */ | |
1240 | case 0xc: /* STBYS */ | |
1241 | is_write = 1; | |
1242 | } | |
1243 | break; | |
1244 | } | |
f54b3f92 | 1245 | |
f54b3f92 | 1246 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
f57040be | 1247 | is_write, &uc->uc_sigmask, puc); |
f54b3f92 AJ |
1248 | } |
1249 | ||
9de5e440 | 1250 | #else |
2b413144 | 1251 | |
3fb2ded1 | 1252 | #error host CPU specific signal handler needed |
2b413144 | 1253 | |
9de5e440 | 1254 | #endif |
67b915a5 FB |
1255 | |
1256 | #endif /* !defined(CONFIG_SOFTMMU) */ |