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7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
93ac68bc 43#if defined(TARGET_ARM) || defined(TARGET_SPARC)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
50
fbf9eeb3
FB		 51/* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
53 */
54void cpu_resume_from_signal(CPUState *env1, void *puc)
55{
56#if !defined(CONFIG_SOFTMMU)
57 struct ucontext *uc = puc;
58#endif
59
60 env = env1;
61
62 /* XXX: restore cpu registers saved in host registers */
63
64#if !defined(CONFIG_SOFTMMU)
65 if (puc) {
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
68 }
69#endif
70 longjmp(env->jmp_env, 1);
71}
72
7d13299d
FB		 73/* main execution loop */
74
e4533c7a 75int cpu_exec(CPUState *env1)
7d13299d 76{
e4533c7a
FB		 77 int saved_T0, saved_T1, saved_T2;
78 CPUState *saved_env;
04369ff2
FB		 79#ifdef reg_EAX
80 int saved_EAX;
81#endif
82#ifdef reg_ECX
83 int saved_ECX;
84#endif
85#ifdef reg_EDX
86 int saved_EDX;
87#endif
88#ifdef reg_EBX
89 int saved_EBX;
90#endif
91#ifdef reg_ESP
92 int saved_ESP;
93#endif
94#ifdef reg_EBP
95 int saved_EBP;
96#endif
97#ifdef reg_ESI
98 int saved_ESI;
99#endif
100#ifdef reg_EDI
101 int saved_EDI;
8c6939c0
FB		 102#endif
103#ifdef __sparc__
104 int saved_i7, tmp_T0;
04369ff2 105#endif
68a79315 106 int code_gen_size, ret, interrupt_request;
7d13299d 107 void (*gen_func)(void);
9de5e440 108 TranslationBlock *tb, **ptb;
dab2ed99 109 uint8_t *tc_ptr, *cs_base, *pc;
6dbad63e 110 unsigned int flags;
8c6939c0 111
7d13299d
FB		 112 /* first we save global registers */
113 saved_T0 = T0;
114 saved_T1 = T1;
e4533c7a 115 saved_T2 = T2;
7d13299d
FB		 116 saved_env = env;
117 env = env1;
e4533c7a
FB		 118#ifdef __sparc__
119 /* we also save i7 because longjmp may not restore it */
120 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
121#endif
122
123#if defined(TARGET_I386)
04369ff2
FB		 124#ifdef reg_EAX
125 saved_EAX = EAX;
04369ff2
FB		 126#endif
127#ifdef reg_ECX
128 saved_ECX = ECX;
04369ff2
FB		 129#endif
130#ifdef reg_EDX
131 saved_EDX = EDX;
04369ff2
FB		 132#endif
133#ifdef reg_EBX
134 saved_EBX = EBX;
04369ff2
FB		 135#endif
136#ifdef reg_ESP
137 saved_ESP = ESP;
04369ff2
FB		 138#endif
139#ifdef reg_EBP
140 saved_EBP = EBP;
04369ff2
FB		 141#endif
142#ifdef reg_ESI
143 saved_ESI = ESI;
04369ff2
FB		 144#endif
145#ifdef reg_EDI
146 saved_EDI = EDI;
04369ff2 147#endif
0d1a29f9
FB		 148
149 env_to_regs();
9de5e440 150 /* put eflags in CPU temporary format */
fc2b4c48
FB		 151 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
152 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 153 CC_OP = CC_OP_EFLAGS;
fc2b4c48 154 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a
FB		 155#elif defined(TARGET_ARM)
156 {
157 unsigned int psr;
158 psr = env->cpsr;
159 env->CF = (psr >> 29) & 1;
160 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
161 env->VF = (psr << 3) & 0x80000000;
162 env->cpsr = psr & ~0xf0000000;
163 }
93ac68bc 164#elif defined(TARGET_SPARC)
67867308 165#elif defined(TARGET_PPC)
e4533c7a
FB		 166#else
167#error unsupported target CPU
168#endif
3fb2ded1 169 env->exception_index = -1;
9d27abd9 170
7d13299d 171 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 172 for(;;) {
173 if (setjmp(env->jmp_env) == 0) {
ee8b7021 174 env->current_tb = NULL;
3fb2ded1
FB		 175 /* if an exception is pending, we execute it here */
176 if (env->exception_index >= 0) {
177 if (env->exception_index >= EXCP_INTERRUPT) {
178 /* exit request from the cpu execution loop */
179 ret = env->exception_index;
180 break;
181 } else if (env->user_mode_only) {
182 /* if user mode only, we simulate a fake exception
183 which will be hanlded outside the cpu execution
184 loop */
83479e77 185#if defined(TARGET_I386)
3fb2ded1
FB		 186 do_interrupt_user(env->exception_index,
187 env->exception_is_int,
188 env->error_code,
189 env->exception_next_eip);
83479e77 190#endif
3fb2ded1
FB		 191 ret = env->exception_index;
192 break;
193 } else {
83479e77 194#if defined(TARGET_I386)
3fb2ded1
FB		 195 /* simulate a real cpu exception. On i386, it can
196 trigger new exceptions, but we do not handle
197 double or triple faults yet. */
198 do_interrupt(env->exception_index,
199 env->exception_is_int,
200 env->error_code,
d05e66d2 201 env->exception_next_eip, 0);
ce09776b
FB		 202#elif defined(TARGET_PPC)
203 do_interrupt(env);
e95c8d51
FB		 204#elif defined(TARGET_SPARC)
205 do_interrupt(env->exception_index,
206 0,
207 env->error_code,
208 env->exception_next_pc, 0);
83479e77 209#endif
3fb2ded1
FB		 210 }
211 env->exception_index = -1;
212 }
3fb2ded1
FB		 213 T0 = 0; /* force lookup of first TB */
214 for(;;) {
8c6939c0 215#ifdef __sparc__
3fb2ded1
FB		 216 /* g1 can be modified by some libc? functions */
217 tmp_T0 = T0;
8c6939c0 218#endif
68a79315 219 interrupt_request = env->interrupt_request;
2e255c6b 220 if (__builtin_expect(interrupt_request, 0)) {
68a79315
FB		 221#if defined(TARGET_I386)
222 /* if hardware interrupt pending, we execute it */
223 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 224 (env->eflags & IF_MASK) &&
225 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 226 int intno;
fbf9eeb3 227 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 228 intno = cpu_get_pic_interrupt(env);
f193c797 229 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 230 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
231 }
d05e66d2 232 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 233 /* ensure that no TB jump will be modified as
234 the program flow was changed */
235#ifdef __sparc__
236 tmp_T0 = 0;
237#else
238 T0 = 0;
239#endif
68a79315 240 }
ce09776b 241#elif defined(TARGET_PPC)
9fddaa0c
FB		 242#if 0
243 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
244 cpu_ppc_reset(env);
245 }
246#endif
247 if (msr_ee != 0) {
ce09776b 248 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
9fddaa0c
FB		 249 /* Raise it */
250 env->exception_index = EXCP_EXTERNAL;
251 env->error_code = 0;
ce09776b
FB		 252 do_interrupt(env);
253 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
9fddaa0c
FB		 254 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
255 /* Raise it */
256 env->exception_index = EXCP_DECR;
257 env->error_code = 0;
258 do_interrupt(env);
259 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
260 }
ce09776b 261 }
e95c8d51
FB		 262#elif defined(TARGET_SPARC)
263 if (interrupt_request & CPU_INTERRUPT_HARD) {
264 do_interrupt(0, 0, 0, 0, 0);
265 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
266 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
267 //do_interrupt(0, 0, 0, 0, 0);
268 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
269 }
68a79315 270#endif
bf3e8bf1
FB		 271 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
272 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
273 /* ensure that no TB jump will be modified as
274 the program flow was changed */
275#ifdef __sparc__
276 tmp_T0 = 0;
277#else
278 T0 = 0;
279#endif
280 }
68a79315
FB		 281 if (interrupt_request & CPU_INTERRUPT_EXIT) {
282 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
283 env->exception_index = EXCP_INTERRUPT;
284 cpu_loop_exit();
285 }
3fb2ded1 286 }
7d13299d 287#ifdef DEBUG_EXEC
f193c797 288 if (loglevel & CPU_LOG_EXEC) {
e4533c7a 289#if defined(TARGET_I386)
3fb2ded1
FB		 290 /* restore flags in standard format */
291 env->regs[R_EAX] = EAX;
292 env->regs[R_EBX] = EBX;
293 env->regs[R_ECX] = ECX;
294 env->regs[R_EDX] = EDX;
295 env->regs[R_ESI] = ESI;
296 env->regs[R_EDI] = EDI;
297 env->regs[R_EBP] = EBP;
298 env->regs[R_ESP] = ESP;
299 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 300 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 301 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 302#elif defined(TARGET_ARM)
1b21b62a 303 env->cpsr = compute_cpsr();
7fe48483 304 cpu_dump_state(env, logfile, fprintf, 0);
1b21b62a 305 env->cpsr &= ~0xf0000000;
93ac68bc 306#elif defined(TARGET_SPARC)
7fe48483 307 cpu_dump_state (env, logfile, fprintf, 0);
67867308 308#elif defined(TARGET_PPC)
7fe48483 309 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 310#else
311#error unsupported target CPU
312#endif
3fb2ded1 313 }
7d13299d 314#endif
3f337316
FB		 315 /* we record a subset of the CPU state. It will
316 always be the same before a given translated block
317 is executed. */
e4533c7a 318#if defined(TARGET_I386)
2e255c6b 319 flags = env->hflags;
3f337316 320 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
3fb2ded1
FB		 321 cs_base = env->segs[R_CS].base;
322 pc = cs_base + env->eip;
e4533c7a 323#elif defined(TARGET_ARM)
3fb2ded1
FB		 324 flags = 0;
325 cs_base = 0;
326 pc = (uint8_t *)env->regs[15];
93ac68bc 327#elif defined(TARGET_SPARC)
67867308 328 flags = 0;
ce09776b 329 cs_base = (uint8_t *)env->npc;
67867308
FB		 330 pc = (uint8_t *) env->pc;
331#elif defined(TARGET_PPC)
332 flags = 0;
333 cs_base = 0;
334 pc = (uint8_t *)env->nip;
e4533c7a
FB		 335#else
336#error unsupported CPU
337#endif
3fb2ded1
FB		 338 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
339 flags);
d4e8164f 340 if (!tb) {
1376847f
FB		 341 TranslationBlock **ptb1;
342 unsigned int h;
343 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
344
345
3fb2ded1 346 spin_lock(&tb_lock);
1376847f
FB		 347
348 tb_invalidated_flag = 0;
0d1a29f9
FB		 349
350 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
1376847f
FB		 351
352 /* find translated block using physical mappings */
353 phys_pc = get_phys_addr_code(env, (unsigned long)pc);
354 phys_page1 = phys_pc & TARGET_PAGE_MASK;
355 phys_page2 = -1;
356 h = tb_phys_hash_func(phys_pc);
357 ptb1 = &tb_phys_hash[h];
358 for(;;) {
359 tb = *ptb1;
360 if (!tb)
361 goto not_found;
362 if (tb->pc == (unsigned long)pc &&
363 tb->page_addr[0] == phys_page1 &&
364 tb->cs_base == (unsigned long)cs_base &&
365 tb->flags == flags) {
366 /* check next page if needed */
b516f85c
FB		 367 if (tb->page_addr[1] != -1) {
368 virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
369 TARGET_PAGE_SIZE;
1376847f
FB		 370 phys_page2 = get_phys_addr_code(env, virt_page2);
371 if (tb->page_addr[1] == phys_page2)
372 goto found;
373 } else {
374 goto found;
375 }
376 }
377 ptb1 = &tb->phys_hash_next;
378 }
379 not_found:
3fb2ded1 380 /* if no translated code available, then translate it now */
d4e8164f 381 tb = tb_alloc((unsigned long)pc);
3fb2ded1
FB		 382 if (!tb) {
383 /* flush must be done */
b453b70b 384 tb_flush(env);
3fb2ded1
FB		 385 /* cannot fail at this point */
386 tb = tb_alloc((unsigned long)pc);
387 /* don't forget to invalidate previous TB info */
388 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
389 T0 = 0;
390 }
391 tc_ptr = code_gen_ptr;
392 tb->tc_ptr = tc_ptr;
393 tb->cs_base = (unsigned long)cs_base;
394 tb->flags = flags;
facc68be 395 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
1376847f
FB		 396 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
397
398 /* check next page if needed */
399 virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
400 phys_page2 = -1;
401 if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
402 phys_page2 = get_phys_addr_code(env, virt_page2);
403 }
404 tb_link_phys(tb, phys_pc, phys_page2);
405
406 found:
36bdbe54
FB		 407 if (tb_invalidated_flag) {
408 /* as some TB could have been invalidated because
409 of memory exceptions while generating the code, we
410 must recompute the hash index here */
411 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
412 while (*ptb != NULL)
413 ptb = &(*ptb)->hash_next;
414 T0 = 0;
415 }
1376847f 416 /* we add the TB in the virtual pc hash table */
3fb2ded1
FB		 417 *ptb = tb;
418 tb->hash_next = NULL;
419 tb_link(tb);
25eb4484 420 spin_unlock(&tb_lock);
9de5e440 421 }
9d27abd9 422#ifdef DEBUG_EXEC
f193c797 423 if (loglevel & CPU_LOG_EXEC) {
3fb2ded1
FB		 424 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
425 (long)tb->tc_ptr, (long)tb->pc,
426 lookup_symbol((void *)tb->pc));
427 }
9d27abd9 428#endif
8c6939c0 429#ifdef __sparc__
3fb2ded1 430 T0 = tmp_T0;
8c6939c0 431#endif
facc68be 432 /* see if we can patch the calling TB. */
bf3e8bf1
FB		 433 if (T0 != 0
434#if defined(TARGET_I386) && defined(USE_CODE_COPY)
435 && (tb->cflags & CF_CODE_COPY) ==
436 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
437#endif
438 ) {
3fb2ded1
FB		 439 spin_lock(&tb_lock);
440 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 441#if defined(USE_CODE_COPY)
442 /* propagates the FP use info */
443 ((TranslationBlock *)(T0 & ~3))->cflags |=
444 (tb->cflags & CF_FP_USED);
445#endif
3fb2ded1
FB		 446 spin_unlock(&tb_lock);
447 }
3fb2ded1 448 tc_ptr = tb->tc_ptr;
83479e77 449 env->current_tb = tb;
3fb2ded1
FB		 450 /* execute the generated code */
451 gen_func = (void *)tc_ptr;
8c6939c0 452#if defined(__sparc__)
3fb2ded1
FB		 453 __asm__ __volatile__("call %0\n\t"
454 "mov %%o7,%%i0"
455 : /* no outputs */
456 : "r" (gen_func)
457 : "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0 458#elif defined(__arm__)
3fb2ded1
FB		 459 asm volatile ("mov pc, %0\n\t"
460 ".global exec_loop\n\t"
461 "exec_loop:\n\t"
462 : /* no outputs */
463 : "r" (gen_func)
464 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 465#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
466{
467 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 468 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
469 save_native_fp_state(env);
470 }
bf3e8bf1
FB		 471 gen_func();
472 } else {
97eb5b14
FB		 473 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
474 restore_native_fp_state(env);
475 }
bf3e8bf1
FB		 476 /* we work with native eflags */
477 CC_SRC = cc_table[CC_OP].compute_all();
478 CC_OP = CC_OP_EFLAGS;
479 asm(".globl exec_loop\n"
480 "\n"
481 "debug1:\n"
482 " pushl %%ebp\n"
483 " fs movl %10, %9\n"
484 " fs movl %11, %%eax\n"
485 " andl $0x400, %%eax\n"
486 " fs orl %8, %%eax\n"
487 " pushl %%eax\n"
488 " popf\n"
489 " fs movl %%esp, %12\n"
490 " fs movl %0, %%eax\n"
491 " fs movl %1, %%ecx\n"
492 " fs movl %2, %%edx\n"
493 " fs movl %3, %%ebx\n"
494 " fs movl %4, %%esp\n"
495 " fs movl %5, %%ebp\n"
496 " fs movl %6, %%esi\n"
497 " fs movl %7, %%edi\n"
498 " fs jmp *%9\n"
499 "exec_loop:\n"
500 " fs movl %%esp, %4\n"
501 " fs movl %12, %%esp\n"
502 " fs movl %%eax, %0\n"
503 " fs movl %%ecx, %1\n"
504 " fs movl %%edx, %2\n"
505 " fs movl %%ebx, %3\n"
506 " fs movl %%ebp, %5\n"
507 " fs movl %%esi, %6\n"
508 " fs movl %%edi, %7\n"
509 " pushf\n"
510 " popl %%eax\n"
511 " movl %%eax, %%ecx\n"
512 " andl $0x400, %%ecx\n"
513 " shrl $9, %%ecx\n"
514 " andl $0x8d5, %%eax\n"
515 " fs movl %%eax, %8\n"
516 " movl $1, %%eax\n"
517 " subl %%ecx, %%eax\n"
518 " fs movl %%eax, %11\n"
519 " fs movl %9, %%ebx\n" /* get T0 value */
520 " popl %%ebp\n"
521 :
522 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
523 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
524 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
525 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
526 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
527 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
528 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
529 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
530 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
531 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
532 "a" (gen_func),
533 "m" (*(uint8_t *)offsetof(CPUState, df)),
534 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
535 : "%ecx", "%edx"
536 );
537 }
538}
ae228531 539#else
3fb2ded1 540 gen_func();
ae228531 541#endif
83479e77 542 env->current_tb = NULL;
4cbf74b6
FB		 543 /* reset soft MMU for next block (it can currently
544 only be set by a memory fault) */
545#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 546 if (env->hflags & HF_SOFTMMU_MASK) {
547 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 548 /* do not allow linking to another block */
549 T0 = 0;
550 }
551#endif
3fb2ded1
FB		 552 }
553 } else {
0d1a29f9 554 env_to_regs();
7d13299d 555 }
3fb2ded1
FB		 556 } /* for(;;) */
557
7d13299d 558
e4533c7a 559#if defined(TARGET_I386)
97eb5b14
FB		 560#if defined(USE_CODE_COPY)
561 if (env->native_fp_regs) {
562 save_native_fp_state(env);
563 }
564#endif
9de5e440 565 /* restore flags in standard format */
fc2b4c48 566 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 567
7d13299d 568 /* restore global registers */
04369ff2
FB		 569#ifdef reg_EAX
570 EAX = saved_EAX;
571#endif
572#ifdef reg_ECX
573 ECX = saved_ECX;
574#endif
575#ifdef reg_EDX
576 EDX = saved_EDX;
577#endif
578#ifdef reg_EBX
579 EBX = saved_EBX;
580#endif
581#ifdef reg_ESP
582 ESP = saved_ESP;
583#endif
584#ifdef reg_EBP
585 EBP = saved_EBP;
586#endif
587#ifdef reg_ESI
588 ESI = saved_ESI;
589#endif
590#ifdef reg_EDI
591 EDI = saved_EDI;
8c6939c0 592#endif
e4533c7a 593#elif defined(TARGET_ARM)
1b21b62a 594 env->cpsr = compute_cpsr();
93ac68bc 595#elif defined(TARGET_SPARC)
67867308 596#elif defined(TARGET_PPC)
e4533c7a
FB		 597#else
598#error unsupported target CPU
599#endif
8c6939c0
FB		 600#ifdef __sparc__
601 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 602#endif
7d13299d
FB		 603 T0 = saved_T0;
604 T1 = saved_T1;
e4533c7a 605 T2 = saved_T2;
7d13299d
FB		 606 env = saved_env;
607 return ret;
608}
6dbad63e 609
fbf9eeb3
FB		 610/* must only be called from the generated code as an exception can be
611 generated */
612void tb_invalidate_page_range(target_ulong start, target_ulong end)
613{
dc5d0b3d
FB		 614 /* XXX: cannot enable it yet because it yields to MMU exception
615 where NIP != read address on PowerPC */
616#if 0
fbf9eeb3
FB		 617 target_ulong phys_addr;
618 phys_addr = get_phys_addr_code(env, start);
619 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 620#endif
fbf9eeb3
FB		 621}
622
1a18c71b 623#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 624
6dbad63e
FB		 625void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
626{
627 CPUX86State *saved_env;
628
629 saved_env = env;
630 env = s;
a412ac57 631 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 632 selector &= 0xffff;
2e255c6b
FB		 633 cpu_x86_load_seg_cache(env, seg_reg, selector,
634 (uint8_t *)(selector << 4), 0xffff, 0);
a513fe19 635 } else {
b453b70b 636 load_seg(seg_reg, selector);
a513fe19 637 }
6dbad63e
FB		 638 env = saved_env;
639}
9de5e440 640
d0a1ffc9
FB		 641void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
642{
643 CPUX86State *saved_env;
644
645 saved_env = env;
646 env = s;
647
648 helper_fsave(ptr, data32);
649
650 env = saved_env;
651}
652
653void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
654{
655 CPUX86State *saved_env;
656
657 saved_env = env;
658 env = s;
659
660 helper_frstor(ptr, data32);
661
662 env = saved_env;
663}
664
e4533c7a
FB		 665#endif /* TARGET_I386 */
666
67b915a5
FB		 667#if !defined(CONFIG_SOFTMMU)
668
3fb2ded1
FB		 669#if defined(TARGET_I386)
670
b56dad1c 671/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 672 the effective address of the memory exception. 'is_write' is 1 if a
673 write caused the exception and otherwise 0'. 'old_set' is the
674 signal set which should be restored */
2b413144 675static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 676 int is_write, sigset_t *old_set,
677 void *puc)
9de5e440 678{
a513fe19
FB		 679 TranslationBlock *tb;
680 int ret;
68a79315 681
83479e77
FB		 682 if (cpu_single_env)
683 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 684#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 685 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
686 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 687#endif
25eb4484 688 /* XXX: locking issue */
fbf9eeb3 689 if (is_write && page_unprotect(address, pc, puc)) {
fd6ce8f6
FB		 690 return 1;
691 }
fbf9eeb3 692
3fb2ded1 693 /* see if it is an MMU fault */
93a40ea9
FB		 694 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
695 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 696 if (ret < 0)
697 return 0; /* not an MMU fault */
698 if (ret == 0)
699 return 1; /* the MMU fault was handled without causing real CPU fault */
700 /* now we have a real cpu fault */
a513fe19
FB		 701 tb = tb_find_pc(pc);
702 if (tb) {
9de5e440
FB		 703 /* the PC is inside the translated code. It means that we have
704 a virtual CPU fault */
bf3e8bf1 705 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 706 }
4cbf74b6 707 if (ret == 1) {
3fb2ded1 708#if 0
4cbf74b6
FB		 709 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
710 env->eip, env->cr[2], env->error_code);
3fb2ded1 711#endif
4cbf74b6
FB		 712 /* we restore the process signal mask as the sigreturn should
713 do it (XXX: use sigsetjmp) */
714 sigprocmask(SIG_SETMASK, old_set, NULL);
715 raise_exception_err(EXCP0E_PAGE, env->error_code);
716 } else {
717 /* activate soft MMU for this block */
3f337316 718 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 719 cpu_resume_from_signal(env, puc);
4cbf74b6 720 }
3fb2ded1
FB		 721 /* never comes here */
722 return 1;
723}
724
e4533c7a 725#elif defined(TARGET_ARM)
3fb2ded1 726static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 727 int is_write, sigset_t *old_set,
728 void *puc)
3fb2ded1
FB		 729{
730 /* XXX: do more */
731 return 0;
732}
93ac68bc
FB		 733#elif defined(TARGET_SPARC)
734static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 735 int is_write, sigset_t *old_set,
736 void *puc)
93ac68bc 737{
b453b70b 738 /* XXX: locking issue */
fbf9eeb3 739 if (is_write && page_unprotect(address, pc, puc)) {
b453b70b
FB		 740 return 1;
741 }
742 return 0;
93ac68bc 743}
67867308
FB		 744#elif defined (TARGET_PPC)
745static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 746 int is_write, sigset_t *old_set,
747 void *puc)
67867308
FB		 748{
749 TranslationBlock *tb;
ce09776b 750 int ret;
67867308 751
ce09776b 752#if 1
67867308
FB		 753 if (cpu_single_env)
754 env = cpu_single_env; /* XXX: find a correct solution for multithread */
755#endif
756#if defined(DEBUG_SIGNAL)
757 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
758 pc, address, is_write, *(unsigned long *)old_set);
759#endif
760 /* XXX: locking issue */
fbf9eeb3 761 if (is_write && page_unprotect(address, pc, puc)) {
67867308
FB		 762 return 1;
763 }
764
ce09776b 765 /* see if it is an MMU fault */
7f957d28 766 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 767 if (ret < 0)
768 return 0; /* not an MMU fault */
769 if (ret == 0)
770 return 1; /* the MMU fault was handled without causing real CPU fault */
771
67867308
FB		 772 /* now we have a real cpu fault */
773 tb = tb_find_pc(pc);
774 if (tb) {
775 /* the PC is inside the translated code. It means that we have
776 a virtual CPU fault */
bf3e8bf1 777 cpu_restore_state(tb, env, pc, puc);
67867308 778 }
ce09776b 779 if (ret == 1) {
67867308 780#if 0
ce09776b
FB		 781 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
782 env->nip, env->error_code, tb);
67867308
FB		 783#endif
784 /* we restore the process signal mask as the sigreturn should
785 do it (XXX: use sigsetjmp) */
bf3e8bf1 786 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 787 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 788 } else {
789 /* activate soft MMU for this block */
fbf9eeb3 790 cpu_resume_from_signal(env, puc);
ce09776b 791 }
67867308
FB		 792 /* never comes here */
793 return 1;
794}
e4533c7a
FB		 795#else
796#error unsupported target CPU
797#endif
9de5e440 798
2b413144
FB		 799#if defined(__i386__)
800
bf3e8bf1
FB		 801#if defined(USE_CODE_COPY)
802static void cpu_send_trap(unsigned long pc, int trap,
803 struct ucontext *uc)
804{
805 TranslationBlock *tb;
806
807 if (cpu_single_env)
808 env = cpu_single_env; /* XXX: find a correct solution for multithread */
809 /* now we have a real cpu fault */
810 tb = tb_find_pc(pc);
811 if (tb) {
812 /* the PC is inside the translated code. It means that we have
813 a virtual CPU fault */
814 cpu_restore_state(tb, env, pc, uc);
815 }
816 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
817 raise_exception_err(trap, env->error_code);
818}
819#endif
820
e4533c7a
FB		 821int cpu_signal_handler(int host_signum, struct siginfo *info,
822 void *puc)
9de5e440 823{
9de5e440
FB		 824 struct ucontext *uc = puc;
825 unsigned long pc;
bf3e8bf1 826 int trapno;
97eb5b14 827
d691f669
FB		 828#ifndef REG_EIP
829/* for glibc 2.1 */
fd6ce8f6
FB		 830#define REG_EIP EIP
831#define REG_ERR ERR
832#define REG_TRAPNO TRAPNO
d691f669 833#endif
fc2b4c48 834 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB		 835 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
836#if defined(TARGET_I386) && defined(USE_CODE_COPY)
837 if (trapno == 0x00 || trapno == 0x05) {
838 /* send division by zero or bound exception */
839 cpu_send_trap(pc, trapno, uc);
840 return 1;
841 } else
842#endif
843 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
844 trapno == 0xe ?
845 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
846 &uc->uc_sigmask, puc);
2b413144
FB		 847}
848
bc51c5c9
FB		 849#elif defined(__x86_64__)
850
851int cpu_signal_handler(int host_signum, struct siginfo *info,
852 void *puc)
853{
854 struct ucontext *uc = puc;
855 unsigned long pc;
856
857 pc = uc->uc_mcontext.gregs[REG_RIP];
858 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
859 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
860 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
861 &uc->uc_sigmask, puc);
862}
863
83fb7adf 864#elif defined(__powerpc__)
2b413144 865
83fb7adf
FB		 866/***********************************************************************
867 * signal context platform-specific definitions
868 * From Wine
869 */
870#ifdef linux
871/* All Registers access - only for local access */
872# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
873/* Gpr Registers access */
874# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
875# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
876# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
877# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
878# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
879# define LR_sig(context) REG_sig(link, context) /* Link register */
880# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
881/* Float Registers access */
882# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
883# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
884/* Exception Registers access */
885# define DAR_sig(context) REG_sig(dar, context)
886# define DSISR_sig(context) REG_sig(dsisr, context)
887# define TRAP_sig(context) REG_sig(trap, context)
888#endif /* linux */
889
890#ifdef __APPLE__
891# include <sys/ucontext.h>
892typedef struct ucontext SIGCONTEXT;
893/* All Registers access - only for local access */
894# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
895# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
896# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
897# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
898/* Gpr Registers access */
899# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
900# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
901# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
902# define CTR_sig(context) REG_sig(ctr, context)
903# define XER_sig(context) REG_sig(xer, context) /* Link register */
904# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
905# define CR_sig(context) REG_sig(cr, context) /* Condition register */
906/* Float Registers access */
907# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
908# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
909/* Exception Registers access */
910# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
911# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
912# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
913#endif /* __APPLE__ */
914
d1d9f421 915int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a 916 void *puc)
2b413144 917{
25eb4484 918 struct ucontext *uc = puc;
25eb4484 919 unsigned long pc;
25eb4484
FB		 920 int is_write;
921
83fb7adf 922 pc = IAR_sig(uc);
25eb4484
FB		 923 is_write = 0;
924#if 0
925 /* ppc 4xx case */
83fb7adf 926 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 927 is_write = 1;
928#else
83fb7adf 929 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 930 is_write = 1;
931#endif
932 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 933 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 934}
935
2f87c607
FB		 936#elif defined(__alpha__)
937
e4533c7a 938int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB		 939 void *puc)
940{
941 struct ucontext *uc = puc;
942 uint32_t *pc = uc->uc_mcontext.sc_pc;
943 uint32_t insn = *pc;
944 int is_write = 0;
945
8c6939c0 946 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 947 switch (insn >> 26) {
948 case 0x0d: // stw
949 case 0x0e: // stb
950 case 0x0f: // stq_u
951 case 0x24: // stf
952 case 0x25: // stg
953 case 0x26: // sts
954 case 0x27: // stt
955 case 0x2c: // stl
956 case 0x2d: // stq
957 case 0x2e: // stl_c
958 case 0x2f: // stq_c
959 is_write = 1;
960 }
961
962 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 963 is_write, &uc->uc_sigmask, puc);
2f87c607 964}
8c6939c0
FB		 965#elif defined(__sparc__)
966
e4533c7a
FB		 967int cpu_signal_handler(int host_signum, struct siginfo *info,
968 void *puc)
8c6939c0
FB		 969{
970 uint32_t *regs = (uint32_t *)(info + 1);
971 void *sigmask = (regs + 20);
972 unsigned long pc;
973 int is_write;
974 uint32_t insn;
975
976 /* XXX: is there a standard glibc define ? */
977 pc = regs[1];
978 /* XXX: need kernel patch to get write flag faster */
979 is_write = 0;
980 insn = *(uint32_t *)pc;
981 if ((insn >> 30) == 3) {
982 switch((insn >> 19) & 0x3f) {
983 case 0x05: // stb
984 case 0x06: // sth
985 case 0x04: // st
986 case 0x07: // std
987 case 0x24: // stf
988 case 0x27: // stdf
989 case 0x25: // stfsr
990 is_write = 1;
991 break;
992 }
993 }
994 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 995 is_write, sigmask, NULL);
8c6939c0
FB		 996}
997
998#elif defined(__arm__)
999
e4533c7a
FB		 1000int cpu_signal_handler(int host_signum, struct siginfo *info,
1001 void *puc)
8c6939c0
FB		 1002{
1003 struct ucontext *uc = puc;
1004 unsigned long pc;
1005 int is_write;
1006
1007 pc = uc->uc_mcontext.gregs[R15];
1008 /* XXX: compute is_write */
1009 is_write = 0;
1010 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1011 is_write,
1012 &uc->uc_sigmask);
1013}
1014
38e584a0
FB		 1015#elif defined(__mc68000)
1016
1017int cpu_signal_handler(int host_signum, struct siginfo *info,
1018 void *puc)
1019{
1020 struct ucontext *uc = puc;
1021 unsigned long pc;
1022 int is_write;
1023
1024 pc = uc->uc_mcontext.gregs[16];
1025 /* XXX: compute is_write */
1026 is_write = 0;
1027 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1028 is_write,
bf3e8bf1 1029 &uc->uc_sigmask, puc);
38e584a0
FB		 1030}
1031
9de5e440 1032#else
2b413144 1033
3fb2ded1 1034#error host CPU specific signal handler needed
2b413144 1035
9de5e440 1036#endif
67b915a5
FB		 1037
1038#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing