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use mask in C0_status (Ralf Baechle)
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
93ac68bc 43#if defined(TARGET_ARM) || defined(TARGET_SPARC)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
3475187d
FB		 50#ifndef TARGET_SPARC
51#define reg_T2
52#endif
e4533c7a 53
fbf9eeb3
FB		 54/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
7d13299d
FB		 76/* main execution loop */
77
e4533c7a 78int cpu_exec(CPUState *env1)
7d13299d 79{
3475187d
FB		 80 int saved_T0, saved_T1;
81#if defined(reg_T2)
82 int saved_T2;
83#endif
e4533c7a 84 CPUState *saved_env;
3475187d 85#if defined(TARGET_I386)
04369ff2
FB		 86#ifdef reg_EAX
87 int saved_EAX;
88#endif
89#ifdef reg_ECX
90 int saved_ECX;
91#endif
92#ifdef reg_EDX
93 int saved_EDX;
94#endif
95#ifdef reg_EBX
96 int saved_EBX;
97#endif
98#ifdef reg_ESP
99 int saved_ESP;
100#endif
101#ifdef reg_EBP
102 int saved_EBP;
103#endif
104#ifdef reg_ESI
105 int saved_ESI;
106#endif
107#ifdef reg_EDI
108 int saved_EDI;
8c6939c0 109#endif
3475187d
FB		 110#elif defined(TARGET_SPARC)
111#if defined(reg_REGWPTR)
112 uint32_t *saved_regwptr;
113#endif
114#endif
8c6939c0
FB		 115#ifdef __sparc__
116 int saved_i7, tmp_T0;
04369ff2 117#endif
68a79315 118 int code_gen_size, ret, interrupt_request;
7d13299d 119 void (*gen_func)(void);
9de5e440 120 TranslationBlock *tb, **ptb;
c27004ec
FB		 121 target_ulong cs_base, pc;
122 uint8_t *tc_ptr;
6dbad63e 123 unsigned int flags;
8c6939c0 124
7d13299d 125 /* first we save global registers */
c27004ec
FB		 126 saved_env = env;
127 env = env1;
7d13299d
FB		 128 saved_T0 = T0;
129 saved_T1 = T1;
3475187d 130#if defined(reg_T2)
e4533c7a 131 saved_T2 = T2;
3475187d 132#endif
e4533c7a
FB		 133#ifdef __sparc__
134 /* we also save i7 because longjmp may not restore it */
135 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
136#endif
137
138#if defined(TARGET_I386)
04369ff2
FB		 139#ifdef reg_EAX
140 saved_EAX = EAX;
04369ff2
FB		 141#endif
142#ifdef reg_ECX
143 saved_ECX = ECX;
04369ff2
FB		 144#endif
145#ifdef reg_EDX
146 saved_EDX = EDX;
04369ff2
FB		 147#endif
148#ifdef reg_EBX
149 saved_EBX = EBX;
04369ff2
FB		 150#endif
151#ifdef reg_ESP
152 saved_ESP = ESP;
04369ff2
FB		 153#endif
154#ifdef reg_EBP
155 saved_EBP = EBP;
04369ff2
FB		 156#endif
157#ifdef reg_ESI
158 saved_ESI = ESI;
04369ff2
FB		 159#endif
160#ifdef reg_EDI
161 saved_EDI = EDI;
04369ff2 162#endif
0d1a29f9
FB		 163
164 env_to_regs();
9de5e440 165 /* put eflags in CPU temporary format */
fc2b4c48
FB		 166 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
167 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 168 CC_OP = CC_OP_EFLAGS;
fc2b4c48 169 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a
FB		 170#elif defined(TARGET_ARM)
171 {
172 unsigned int psr;
173 psr = env->cpsr;
174 env->CF = (psr >> 29) & 1;
175 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
176 env->VF = (psr << 3) & 0x80000000;
99c475ab
FB		 177 env->QF = (psr >> 27) & 1;
178 env->cpsr = psr & ~CACHED_CPSR_BITS;
e4533c7a 179 }
93ac68bc 180#elif defined(TARGET_SPARC)
3475187d
FB		 181#if defined(reg_REGWPTR)
182 saved_regwptr = REGWPTR;
183#endif
67867308 184#elif defined(TARGET_PPC)
6af0bf9c 185#elif defined(TARGET_MIPS)
e4533c7a
FB		 186#else
187#error unsupported target CPU
188#endif
3fb2ded1 189 env->exception_index = -1;
9d27abd9 190
7d13299d 191 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 192 for(;;) {
193 if (setjmp(env->jmp_env) == 0) {
ee8b7021 194 env->current_tb = NULL;
3fb2ded1
FB		 195 /* if an exception is pending, we execute it here */
196 if (env->exception_index >= 0) {
197 if (env->exception_index >= EXCP_INTERRUPT) {
198 /* exit request from the cpu execution loop */
199 ret = env->exception_index;
200 break;
201 } else if (env->user_mode_only) {
202 /* if user mode only, we simulate a fake exception
203 which will be hanlded outside the cpu execution
204 loop */
83479e77 205#if defined(TARGET_I386)
3fb2ded1
FB		 206 do_interrupt_user(env->exception_index,
207 env->exception_is_int,
208 env->error_code,
209 env->exception_next_eip);
83479e77 210#endif
3fb2ded1
FB		 211 ret = env->exception_index;
212 break;
213 } else {
83479e77 214#if defined(TARGET_I386)
3fb2ded1
FB		 215 /* simulate a real cpu exception. On i386, it can
216 trigger new exceptions, but we do not handle
217 double or triple faults yet. */
218 do_interrupt(env->exception_index,
219 env->exception_is_int,
220 env->error_code,
d05e66d2 221 env->exception_next_eip, 0);
ce09776b
FB		 222#elif defined(TARGET_PPC)
223 do_interrupt(env);
6af0bf9c
FB		 224#elif defined(TARGET_MIPS)
225 do_interrupt(env);
e95c8d51 226#elif defined(TARGET_SPARC)
1a0c3292 227 do_interrupt(env->exception_index);
83479e77 228#endif
3fb2ded1
FB		 229 }
230 env->exception_index = -1;
9df217a3
FB		 231 }
232#ifdef USE_KQEMU
233 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
234 int ret;
235 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
236 ret = kqemu_cpu_exec(env);
237 /* put eflags in CPU temporary format */
238 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
239 DF = 1 - (2 * ((env->eflags >> 10) & 1));
240 CC_OP = CC_OP_EFLAGS;
241 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
242 if (ret == 1) {
243 /* exception */
244 longjmp(env->jmp_env, 1);
245 } else if (ret == 2) {
246 /* softmmu execution needed */
247 } else {
248 if (env->interrupt_request != 0) {
249 /* hardware interrupt will be executed just after */
250 } else {
251 /* otherwise, we restart */
252 longjmp(env->jmp_env, 1);
253 }
254 }
3fb2ded1 255 }
9df217a3
FB		 256#endif
257
3fb2ded1
FB		 258 T0 = 0; /* force lookup of first TB */
259 for(;;) {
8c6939c0 260#ifdef __sparc__
3fb2ded1
FB		 261 /* g1 can be modified by some libc? functions */
262 tmp_T0 = T0;
8c6939c0 263#endif
68a79315 264 interrupt_request = env->interrupt_request;
2e255c6b 265 if (__builtin_expect(interrupt_request, 0)) {
68a79315
FB		 266#if defined(TARGET_I386)
267 /* if hardware interrupt pending, we execute it */
268 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 269 (env->eflags & IF_MASK) &&
270 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 271 int intno;
fbf9eeb3 272 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 273 intno = cpu_get_pic_interrupt(env);
f193c797 274 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 275 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
276 }
d05e66d2 277 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 278 /* ensure that no TB jump will be modified as
279 the program flow was changed */
280#ifdef __sparc__
281 tmp_T0 = 0;
282#else
283 T0 = 0;
284#endif
68a79315 285 }
ce09776b 286#elif defined(TARGET_PPC)
9fddaa0c
FB		 287#if 0
288 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
289 cpu_ppc_reset(env);
290 }
291#endif
292 if (msr_ee != 0) {
ce09776b 293 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
9fddaa0c
FB		 294 /* Raise it */
295 env->exception_index = EXCP_EXTERNAL;
296 env->error_code = 0;
ce09776b
FB		 297 do_interrupt(env);
298 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
9fddaa0c
FB		 299 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
300 /* Raise it */
301 env->exception_index = EXCP_DECR;
302 env->error_code = 0;
303 do_interrupt(env);
304 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
305 }
ce09776b 306 }
6af0bf9c
FB		 307#elif defined(TARGET_MIPS)
308 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
309 (env->CP0_Status & (1 << CP0St_IE)) &&
ae022501 310 (env->CP0_Cause & 0x0000FF00) &&
6af0bf9c
FB		 311 !(env->hflags & MIPS_HFLAG_EXL) &&
312 !(env->hflags & MIPS_HFLAG_ERL) &&
313 !(env->hflags & MIPS_HFLAG_DM)) {
314 /* Raise it */
315 env->exception_index = EXCP_EXT_INTERRUPT;
316 env->error_code = 0;
317 do_interrupt(env);
318 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
319 }
e95c8d51 320#elif defined(TARGET_SPARC)
66321a11
FB		 321 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
322 (env->psret != 0)) {
323 int pil = env->interrupt_index & 15;
324 int type = env->interrupt_index & 0xf0;
325
326 if (((type == TT_EXTINT) &&
327 (pil == 15 || pil > env->psrpil)) ||
328 type != TT_EXTINT) {
329 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
330 do_interrupt(env->interrupt_index);
331 env->interrupt_index = 0;
332 }
e95c8d51
FB		 333 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
334 //do_interrupt(0, 0, 0, 0, 0);
335 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
336 }
68a79315 337#endif
bf3e8bf1
FB		 338 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
339 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
340 /* ensure that no TB jump will be modified as
341 the program flow was changed */
342#ifdef __sparc__
343 tmp_T0 = 0;
344#else
345 T0 = 0;
346#endif
347 }
68a79315
FB		 348 if (interrupt_request & CPU_INTERRUPT_EXIT) {
349 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
350 env->exception_index = EXCP_INTERRUPT;
351 cpu_loop_exit();
352 }
3fb2ded1 353 }
7d13299d 354#ifdef DEBUG_EXEC
c27004ec 355 if ((loglevel & CPU_LOG_EXEC)) {
e4533c7a 356#if defined(TARGET_I386)
3fb2ded1 357 /* restore flags in standard format */
fc9f715d 358#ifdef reg_EAX
3fb2ded1 359 env->regs[R_EAX] = EAX;
fc9f715d
FB		 360#endif
361#ifdef reg_EBX
3fb2ded1 362 env->regs[R_EBX] = EBX;
fc9f715d
FB		 363#endif
364#ifdef reg_ECX
3fb2ded1 365 env->regs[R_ECX] = ECX;
fc9f715d
FB		 366#endif
367#ifdef reg_EDX
3fb2ded1 368 env->regs[R_EDX] = EDX;
fc9f715d
FB		 369#endif
370#ifdef reg_ESI
3fb2ded1 371 env->regs[R_ESI] = ESI;
fc9f715d
FB		 372#endif
373#ifdef reg_EDI
3fb2ded1 374 env->regs[R_EDI] = EDI;
fc9f715d
FB		 375#endif
376#ifdef reg_EBP
3fb2ded1 377 env->regs[R_EBP] = EBP;
fc9f715d
FB		 378#endif
379#ifdef reg_ESP
3fb2ded1 380 env->regs[R_ESP] = ESP;
fc9f715d 381#endif
3fb2ded1 382 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 383 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 384 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 385#elif defined(TARGET_ARM)
1b21b62a 386 env->cpsr = compute_cpsr();
7fe48483 387 cpu_dump_state(env, logfile, fprintf, 0);
99c475ab 388 env->cpsr &= ~CACHED_CPSR_BITS;
93ac68bc 389#elif defined(TARGET_SPARC)
3475187d
FB		 390 REGWPTR = env->regbase + (env->cwp * 16);
391 env->regwptr = REGWPTR;
392 cpu_dump_state(env, logfile, fprintf, 0);
67867308 393#elif defined(TARGET_PPC)
7fe48483 394 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 395#elif defined(TARGET_MIPS)
396 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 397#else
398#error unsupported target CPU
399#endif
3fb2ded1 400 }
7d13299d 401#endif
3f337316
FB		 402 /* we record a subset of the CPU state. It will
403 always be the same before a given translated block
404 is executed. */
e4533c7a 405#if defined(TARGET_I386)
2e255c6b 406 flags = env->hflags;
3f337316 407 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
3fb2ded1
FB		 408 cs_base = env->segs[R_CS].base;
409 pc = cs_base + env->eip;
e4533c7a 410#elif defined(TARGET_ARM)
b7bcbe95
FB		 411 flags = env->thumb | (env->vfp.vec_len << 1)
412 | (env->vfp.vec_stride << 4);
3fb2ded1 413 cs_base = 0;
c27004ec 414 pc = env->regs[15];
93ac68bc 415#elif defined(TARGET_SPARC)
3475187d
FB		 416#ifdef TARGET_SPARC64
417 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
418#else
419 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
420#endif
c27004ec
FB		 421 cs_base = env->npc;
422 pc = env->pc;
67867308 423#elif defined(TARGET_PPC)
111bfab3
FB		 424 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
425 (msr_se << MSR_SE) | (msr_le << MSR_LE);
67867308 426 cs_base = 0;
c27004ec 427 pc = env->nip;
6af0bf9c
FB		 428#elif defined(TARGET_MIPS)
429 flags = env->hflags & MIPS_HFLAGS_TMASK;
430 cs_base = NULL;
431 pc = env->PC;
e4533c7a
FB		 432#else
433#error unsupported CPU
434#endif
c27004ec 435 tb = tb_find(&ptb, pc, cs_base,
3fb2ded1 436 flags);
d4e8164f 437 if (!tb) {
1376847f
FB		 438 TranslationBlock **ptb1;
439 unsigned int h;
440 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
441
442
3fb2ded1 443 spin_lock(&tb_lock);
1376847f
FB		 444
445 tb_invalidated_flag = 0;
0d1a29f9
FB		 446
447 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
1376847f
FB		 448
449 /* find translated block using physical mappings */
c27004ec 450 phys_pc = get_phys_addr_code(env, pc);
1376847f
FB		 451 phys_page1 = phys_pc & TARGET_PAGE_MASK;
452 phys_page2 = -1;
453 h = tb_phys_hash_func(phys_pc);
454 ptb1 = &tb_phys_hash[h];
455 for(;;) {
456 tb = *ptb1;
457 if (!tb)
458 goto not_found;
c27004ec 459 if (tb->pc == pc &&
1376847f 460 tb->page_addr[0] == phys_page1 &&
c27004ec 461 tb->cs_base == cs_base &&
1376847f
FB		 462 tb->flags == flags) {
463 /* check next page if needed */
b516f85c 464 if (tb->page_addr[1] != -1) {
c27004ec 465 virt_page2 = (pc & TARGET_PAGE_MASK) +
b516f85c 466 TARGET_PAGE_SIZE;
1376847f
FB		 467 phys_page2 = get_phys_addr_code(env, virt_page2);
468 if (tb->page_addr[1] == phys_page2)
469 goto found;
470 } else {
471 goto found;
472 }
473 }
474 ptb1 = &tb->phys_hash_next;
475 }
476 not_found:
3fb2ded1 477 /* if no translated code available, then translate it now */
c27004ec 478 tb = tb_alloc(pc);
3fb2ded1
FB		 479 if (!tb) {
480 /* flush must be done */
b453b70b 481 tb_flush(env);
3fb2ded1 482 /* cannot fail at this point */
c27004ec 483 tb = tb_alloc(pc);
3fb2ded1 484 /* don't forget to invalidate previous TB info */
c27004ec 485 ptb = &tb_hash[tb_hash_func(pc)];
3fb2ded1
FB		 486 T0 = 0;
487 }
488 tc_ptr = code_gen_ptr;
489 tb->tc_ptr = tc_ptr;
c27004ec 490 tb->cs_base = cs_base;
3fb2ded1 491 tb->flags = flags;
facc68be 492 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
1376847f
FB		 493 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
494
495 /* check next page if needed */
c27004ec 496 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
1376847f 497 phys_page2 = -1;
c27004ec 498 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
1376847f
FB		 499 phys_page2 = get_phys_addr_code(env, virt_page2);
500 }
501 tb_link_phys(tb, phys_pc, phys_page2);
502
503 found:
36bdbe54
FB		 504 if (tb_invalidated_flag) {
505 /* as some TB could have been invalidated because
506 of memory exceptions while generating the code, we
507 must recompute the hash index here */
c27004ec 508 ptb = &tb_hash[tb_hash_func(pc)];
36bdbe54
FB		 509 while (*ptb != NULL)
510 ptb = &(*ptb)->hash_next;
511 T0 = 0;
512 }
1376847f 513 /* we add the TB in the virtual pc hash table */
3fb2ded1
FB		 514 *ptb = tb;
515 tb->hash_next = NULL;
516 tb_link(tb);
25eb4484 517 spin_unlock(&tb_lock);
9de5e440 518 }
9d27abd9 519#ifdef DEBUG_EXEC
c1135f61 520 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 521 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
522 (long)tb->tc_ptr, tb->pc,
523 lookup_symbol(tb->pc));
3fb2ded1 524 }
9d27abd9 525#endif
8c6939c0 526#ifdef __sparc__
3fb2ded1 527 T0 = tmp_T0;
8c6939c0 528#endif
facc68be 529 /* see if we can patch the calling TB. */
c27004ec
FB		 530 {
531 if (T0 != 0
bf3e8bf1
FB		 532#if defined(TARGET_I386) && defined(USE_CODE_COPY)
533 && (tb->cflags & CF_CODE_COPY) ==
534 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
535#endif
536 ) {
3fb2ded1 537 spin_lock(&tb_lock);
c27004ec 538 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 539#if defined(USE_CODE_COPY)
540 /* propagates the FP use info */
541 ((TranslationBlock *)(T0 & ~3))->cflags |=
542 (tb->cflags & CF_FP_USED);
543#endif
3fb2ded1
FB		 544 spin_unlock(&tb_lock);
545 }
c27004ec 546 }
3fb2ded1 547 tc_ptr = tb->tc_ptr;
83479e77 548 env->current_tb = tb;
3fb2ded1
FB		 549 /* execute the generated code */
550 gen_func = (void *)tc_ptr;
8c6939c0 551#if defined(__sparc__)
3fb2ded1
FB		 552 __asm__ __volatile__("call %0\n\t"
553 "mov %%o7,%%i0"
554 : /* no outputs */
555 : "r" (gen_func)
556 : "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0 557#elif defined(__arm__)
3fb2ded1
FB		 558 asm volatile ("mov pc, %0\n\t"
559 ".global exec_loop\n\t"
560 "exec_loop:\n\t"
561 : /* no outputs */
562 : "r" (gen_func)
563 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 564#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
565{
566 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 567 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
568 save_native_fp_state(env);
569 }
bf3e8bf1
FB		 570 gen_func();
571 } else {
97eb5b14
FB		 572 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
573 restore_native_fp_state(env);
574 }
bf3e8bf1
FB		 575 /* we work with native eflags */
576 CC_SRC = cc_table[CC_OP].compute_all();
577 CC_OP = CC_OP_EFLAGS;
578 asm(".globl exec_loop\n"
579 "\n"
580 "debug1:\n"
581 " pushl %%ebp\n"
582 " fs movl %10, %9\n"
583 " fs movl %11, %%eax\n"
584 " andl $0x400, %%eax\n"
585 " fs orl %8, %%eax\n"
586 " pushl %%eax\n"
587 " popf\n"
588 " fs movl %%esp, %12\n"
589 " fs movl %0, %%eax\n"
590 " fs movl %1, %%ecx\n"
591 " fs movl %2, %%edx\n"
592 " fs movl %3, %%ebx\n"
593 " fs movl %4, %%esp\n"
594 " fs movl %5, %%ebp\n"
595 " fs movl %6, %%esi\n"
596 " fs movl %7, %%edi\n"
597 " fs jmp *%9\n"
598 "exec_loop:\n"
599 " fs movl %%esp, %4\n"
600 " fs movl %12, %%esp\n"
601 " fs movl %%eax, %0\n"
602 " fs movl %%ecx, %1\n"
603 " fs movl %%edx, %2\n"
604 " fs movl %%ebx, %3\n"
605 " fs movl %%ebp, %5\n"
606 " fs movl %%esi, %6\n"
607 " fs movl %%edi, %7\n"
608 " pushf\n"
609 " popl %%eax\n"
610 " movl %%eax, %%ecx\n"
611 " andl $0x400, %%ecx\n"
612 " shrl $9, %%ecx\n"
613 " andl $0x8d5, %%eax\n"
614 " fs movl %%eax, %8\n"
615 " movl $1, %%eax\n"
616 " subl %%ecx, %%eax\n"
617 " fs movl %%eax, %11\n"
618 " fs movl %9, %%ebx\n" /* get T0 value */
619 " popl %%ebp\n"
620 :
621 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
622 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
623 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
624 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
625 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
626 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
627 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
628 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
629 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
630 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
631 "a" (gen_func),
632 "m" (*(uint8_t *)offsetof(CPUState, df)),
633 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
634 : "%ecx", "%edx"
635 );
636 }
637}
b8076a74
FB		 638#elif defined(__ia64)
639 struct fptr {
640 void *ip;
641 void *gp;
642 } fp;
643
644 fp.ip = tc_ptr;
645 fp.gp = code_gen_buffer + 2 * (1 << 20);
646 (*(void (*)(void)) &fp)();
ae228531 647#else
3fb2ded1 648 gen_func();
ae228531 649#endif
83479e77 650 env->current_tb = NULL;
4cbf74b6
FB		 651 /* reset soft MMU for next block (it can currently
652 only be set by a memory fault) */
653#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 654 if (env->hflags & HF_SOFTMMU_MASK) {
655 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 656 /* do not allow linking to another block */
657 T0 = 0;
658 }
659#endif
3fb2ded1
FB		 660 }
661 } else {
0d1a29f9 662 env_to_regs();
7d13299d 663 }
3fb2ded1
FB		 664 } /* for(;;) */
665
7d13299d 666
e4533c7a 667#if defined(TARGET_I386)
97eb5b14
FB		 668#if defined(USE_CODE_COPY)
669 if (env->native_fp_regs) {
670 save_native_fp_state(env);
671 }
672#endif
9de5e440 673 /* restore flags in standard format */
fc2b4c48 674 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 675
7d13299d 676 /* restore global registers */
04369ff2
FB		 677#ifdef reg_EAX
678 EAX = saved_EAX;
679#endif
680#ifdef reg_ECX
681 ECX = saved_ECX;
682#endif
683#ifdef reg_EDX
684 EDX = saved_EDX;
685#endif
686#ifdef reg_EBX
687 EBX = saved_EBX;
688#endif
689#ifdef reg_ESP
690 ESP = saved_ESP;
691#endif
692#ifdef reg_EBP
693 EBP = saved_EBP;
694#endif
695#ifdef reg_ESI
696 ESI = saved_ESI;
697#endif
698#ifdef reg_EDI
699 EDI = saved_EDI;
8c6939c0 700#endif
e4533c7a 701#elif defined(TARGET_ARM)
1b21b62a 702 env->cpsr = compute_cpsr();
b7bcbe95 703 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 704#elif defined(TARGET_SPARC)
3475187d
FB		 705#if defined(reg_REGWPTR)
706 REGWPTR = saved_regwptr;
707#endif
67867308 708#elif defined(TARGET_PPC)
6af0bf9c 709#elif defined(TARGET_MIPS)
e4533c7a
FB		 710#else
711#error unsupported target CPU
712#endif
8c6939c0
FB		 713#ifdef __sparc__
714 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 715#endif
7d13299d
FB		 716 T0 = saved_T0;
717 T1 = saved_T1;
3475187d 718#if defined(reg_T2)
e4533c7a 719 T2 = saved_T2;
3475187d 720#endif
7d13299d
FB		 721 env = saved_env;
722 return ret;
723}
6dbad63e 724
fbf9eeb3
FB		 725/* must only be called from the generated code as an exception can be
726 generated */
727void tb_invalidate_page_range(target_ulong start, target_ulong end)
728{
dc5d0b3d
FB		 729 /* XXX: cannot enable it yet because it yields to MMU exception
730 where NIP != read address on PowerPC */
731#if 0
fbf9eeb3
FB		 732 target_ulong phys_addr;
733 phys_addr = get_phys_addr_code(env, start);
734 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 735#endif
fbf9eeb3
FB		 736}
737
1a18c71b 738#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 739
6dbad63e
FB		 740void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
741{
742 CPUX86State *saved_env;
743
744 saved_env = env;
745 env = s;
a412ac57 746 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 747 selector &= 0xffff;
2e255c6b 748 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 749 (selector << 4), 0xffff, 0);
a513fe19 750 } else {
b453b70b 751 load_seg(seg_reg, selector);
a513fe19 752 }
6dbad63e
FB		 753 env = saved_env;
754}
9de5e440 755
d0a1ffc9
FB		 756void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
757{
758 CPUX86State *saved_env;
759
760 saved_env = env;
761 env = s;
762
c27004ec 763 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 764
765 env = saved_env;
766}
767
768void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
769{
770 CPUX86State *saved_env;
771
772 saved_env = env;
773 env = s;
774
c27004ec 775 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 776
777 env = saved_env;
778}
779
e4533c7a
FB		 780#endif /* TARGET_I386 */
781
67b915a5
FB		 782#if !defined(CONFIG_SOFTMMU)
783
3fb2ded1
FB		 784#if defined(TARGET_I386)
785
b56dad1c 786/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 787 the effective address of the memory exception. 'is_write' is 1 if a
788 write caused the exception and otherwise 0'. 'old_set' is the
789 signal set which should be restored */
2b413144 790static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 791 int is_write, sigset_t *old_set,
792 void *puc)
9de5e440 793{
a513fe19
FB		 794 TranslationBlock *tb;
795 int ret;
68a79315 796
83479e77
FB		 797 if (cpu_single_env)
798 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 799#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 800 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
801 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 802#endif
25eb4484 803 /* XXX: locking issue */
fbf9eeb3 804 if (is_write && page_unprotect(address, pc, puc)) {
fd6ce8f6
FB		 805 return 1;
806 }
fbf9eeb3 807
3fb2ded1 808 /* see if it is an MMU fault */
93a40ea9
FB		 809 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
810 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 811 if (ret < 0)
812 return 0; /* not an MMU fault */
813 if (ret == 0)
814 return 1; /* the MMU fault was handled without causing real CPU fault */
815 /* now we have a real cpu fault */
a513fe19
FB		 816 tb = tb_find_pc(pc);
817 if (tb) {
9de5e440
FB		 818 /* the PC is inside the translated code. It means that we have
819 a virtual CPU fault */
bf3e8bf1 820 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 821 }
4cbf74b6 822 if (ret == 1) {
3fb2ded1 823#if 0
4cbf74b6
FB		 824 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
825 env->eip, env->cr[2], env->error_code);
3fb2ded1 826#endif
4cbf74b6
FB		 827 /* we restore the process signal mask as the sigreturn should
828 do it (XXX: use sigsetjmp) */
829 sigprocmask(SIG_SETMASK, old_set, NULL);
830 raise_exception_err(EXCP0E_PAGE, env->error_code);
831 } else {
832 /* activate soft MMU for this block */
3f337316 833 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 834 cpu_resume_from_signal(env, puc);
4cbf74b6 835 }
3fb2ded1
FB		 836 /* never comes here */
837 return 1;
838}
839
e4533c7a 840#elif defined(TARGET_ARM)
3fb2ded1 841static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 842 int is_write, sigset_t *old_set,
843 void *puc)
3fb2ded1 844{
68016c62
FB		 845 TranslationBlock *tb;
846 int ret;
847
848 if (cpu_single_env)
849 env = cpu_single_env; /* XXX: find a correct solution for multithread */
850#if defined(DEBUG_SIGNAL)
851 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
852 pc, address, is_write, *(unsigned long *)old_set);
853#endif
9f0777ed
FB		 854 /* XXX: locking issue */
855 if (is_write && page_unprotect(address, pc, puc)) {
856 return 1;
857 }
68016c62
FB		 858 /* see if it is an MMU fault */
859 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
860 if (ret < 0)
861 return 0; /* not an MMU fault */
862 if (ret == 0)
863 return 1; /* the MMU fault was handled without causing real CPU fault */
864 /* now we have a real cpu fault */
865 tb = tb_find_pc(pc);
866 if (tb) {
867 /* the PC is inside the translated code. It means that we have
868 a virtual CPU fault */
869 cpu_restore_state(tb, env, pc, puc);
870 }
871 /* we restore the process signal mask as the sigreturn should
872 do it (XXX: use sigsetjmp) */
873 sigprocmask(SIG_SETMASK, old_set, NULL);
874 cpu_loop_exit();
3fb2ded1 875}
93ac68bc
FB		 876#elif defined(TARGET_SPARC)
877static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 878 int is_write, sigset_t *old_set,
879 void *puc)
93ac68bc 880{
68016c62
FB		 881 TranslationBlock *tb;
882 int ret;
883
884 if (cpu_single_env)
885 env = cpu_single_env; /* XXX: find a correct solution for multithread */
886#if defined(DEBUG_SIGNAL)
887 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
888 pc, address, is_write, *(unsigned long *)old_set);
889#endif
b453b70b 890 /* XXX: locking issue */
fbf9eeb3 891 if (is_write && page_unprotect(address, pc, puc)) {
b453b70b
FB		 892 return 1;
893 }
68016c62
FB		 894 /* see if it is an MMU fault */
895 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
896 if (ret < 0)
897 return 0; /* not an MMU fault */
898 if (ret == 0)
899 return 1; /* the MMU fault was handled without causing real CPU fault */
900 /* now we have a real cpu fault */
901 tb = tb_find_pc(pc);
902 if (tb) {
903 /* the PC is inside the translated code. It means that we have
904 a virtual CPU fault */
905 cpu_restore_state(tb, env, pc, puc);
906 }
907 /* we restore the process signal mask as the sigreturn should
908 do it (XXX: use sigsetjmp) */
909 sigprocmask(SIG_SETMASK, old_set, NULL);
910 cpu_loop_exit();
93ac68bc 911}
67867308
FB		 912#elif defined (TARGET_PPC)
913static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 914 int is_write, sigset_t *old_set,
915 void *puc)
67867308
FB		 916{
917 TranslationBlock *tb;
ce09776b 918 int ret;
67867308 919
67867308
FB		 920 if (cpu_single_env)
921 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 922#if defined(DEBUG_SIGNAL)
923 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
924 pc, address, is_write, *(unsigned long *)old_set);
925#endif
926 /* XXX: locking issue */
fbf9eeb3 927 if (is_write && page_unprotect(address, pc, puc)) {
67867308
FB		 928 return 1;
929 }
930
ce09776b 931 /* see if it is an MMU fault */
7f957d28 932 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 933 if (ret < 0)
934 return 0; /* not an MMU fault */
935 if (ret == 0)
936 return 1; /* the MMU fault was handled without causing real CPU fault */
937
67867308
FB		 938 /* now we have a real cpu fault */
939 tb = tb_find_pc(pc);
940 if (tb) {
941 /* the PC is inside the translated code. It means that we have
942 a virtual CPU fault */
bf3e8bf1 943 cpu_restore_state(tb, env, pc, puc);
67867308 944 }
ce09776b 945 if (ret == 1) {
67867308 946#if 0
ce09776b
FB		 947 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
948 env->nip, env->error_code, tb);
67867308
FB		 949#endif
950 /* we restore the process signal mask as the sigreturn should
951 do it (XXX: use sigsetjmp) */
bf3e8bf1 952 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 953 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 954 } else {
955 /* activate soft MMU for this block */
fbf9eeb3 956 cpu_resume_from_signal(env, puc);
ce09776b 957 }
67867308
FB		 958 /* never comes here */
959 return 1;
960}
6af0bf9c
FB		 961
962#elif defined (TARGET_MIPS)
963static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
964 int is_write, sigset_t *old_set,
965 void *puc)
966{
967 TranslationBlock *tb;
968 int ret;
969
970 if (cpu_single_env)
971 env = cpu_single_env; /* XXX: find a correct solution for multithread */
972#if defined(DEBUG_SIGNAL)
973 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
974 pc, address, is_write, *(unsigned long *)old_set);
975#endif
976 /* XXX: locking issue */
977 if (is_write && page_unprotect(address, pc, puc)) {
978 return 1;
979 }
980
981 /* see if it is an MMU fault */
982 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
983 if (ret < 0)
984 return 0; /* not an MMU fault */
985 if (ret == 0)
986 return 1; /* the MMU fault was handled without causing real CPU fault */
987
988 /* now we have a real cpu fault */
989 tb = tb_find_pc(pc);
990 if (tb) {
991 /* the PC is inside the translated code. It means that we have
992 a virtual CPU fault */
993 cpu_restore_state(tb, env, pc, puc);
994 }
995 if (ret == 1) {
996#if 0
997 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
998 env->nip, env->error_code, tb);
999#endif
1000 /* we restore the process signal mask as the sigreturn should
1001 do it (XXX: use sigsetjmp) */
1002 sigprocmask(SIG_SETMASK, old_set, NULL);
1003 do_raise_exception_err(env->exception_index, env->error_code);
1004 } else {
1005 /* activate soft MMU for this block */
1006 cpu_resume_from_signal(env, puc);
1007 }
1008 /* never comes here */
1009 return 1;
1010}
1011
e4533c7a
FB		 1012#else
1013#error unsupported target CPU
1014#endif
9de5e440 1015
2b413144
FB		 1016#if defined(__i386__)
1017
bf3e8bf1
FB		 1018#if defined(USE_CODE_COPY)
1019static void cpu_send_trap(unsigned long pc, int trap,
1020 struct ucontext *uc)
1021{
1022 TranslationBlock *tb;
1023
1024 if (cpu_single_env)
1025 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1026 /* now we have a real cpu fault */
1027 tb = tb_find_pc(pc);
1028 if (tb) {
1029 /* the PC is inside the translated code. It means that we have
1030 a virtual CPU fault */
1031 cpu_restore_state(tb, env, pc, uc);
1032 }
1033 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1034 raise_exception_err(trap, env->error_code);
1035}
1036#endif
1037
e4533c7a
FB		 1038int cpu_signal_handler(int host_signum, struct siginfo *info,
1039 void *puc)
9de5e440 1040{
9de5e440
FB		 1041 struct ucontext *uc = puc;
1042 unsigned long pc;
bf3e8bf1 1043 int trapno;
97eb5b14 1044
d691f669
FB		 1045#ifndef REG_EIP
1046/* for glibc 2.1 */
fd6ce8f6
FB		 1047#define REG_EIP EIP
1048#define REG_ERR ERR
1049#define REG_TRAPNO TRAPNO
d691f669 1050#endif
fc2b4c48 1051 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB		 1052 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1053#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1054 if (trapno == 0x00 || trapno == 0x05) {
1055 /* send division by zero or bound exception */
1056 cpu_send_trap(pc, trapno, uc);
1057 return 1;
1058 } else
1059#endif
1060 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1061 trapno == 0xe ?
1062 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1063 &uc->uc_sigmask, puc);
2b413144
FB		 1064}
1065
bc51c5c9
FB		 1066#elif defined(__x86_64__)
1067
1068int cpu_signal_handler(int host_signum, struct siginfo *info,
1069 void *puc)
1070{
1071 struct ucontext *uc = puc;
1072 unsigned long pc;
1073
1074 pc = uc->uc_mcontext.gregs[REG_RIP];
1075 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1076 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1077 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1078 &uc->uc_sigmask, puc);
1079}
1080
83fb7adf 1081#elif defined(__powerpc__)
2b413144 1082
83fb7adf
FB		 1083/***********************************************************************
1084 * signal context platform-specific definitions
1085 * From Wine
1086 */
1087#ifdef linux
1088/* All Registers access - only for local access */
1089# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1090/* Gpr Registers access */
1091# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1092# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1093# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1094# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1095# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1096# define LR_sig(context) REG_sig(link, context) /* Link register */
1097# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1098/* Float Registers access */
1099# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1100# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1101/* Exception Registers access */
1102# define DAR_sig(context) REG_sig(dar, context)
1103# define DSISR_sig(context) REG_sig(dsisr, context)
1104# define TRAP_sig(context) REG_sig(trap, context)
1105#endif /* linux */
1106
1107#ifdef __APPLE__
1108# include <sys/ucontext.h>
1109typedef struct ucontext SIGCONTEXT;
1110/* All Registers access - only for local access */
1111# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1112# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1113# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1114# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1115/* Gpr Registers access */
1116# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1117# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1118# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1119# define CTR_sig(context) REG_sig(ctr, context)
1120# define XER_sig(context) REG_sig(xer, context) /* Link register */
1121# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1122# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1123/* Float Registers access */
1124# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1125# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1126/* Exception Registers access */
1127# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1128# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1129# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1130#endif /* __APPLE__ */
1131
d1d9f421 1132int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a 1133 void *puc)
2b413144 1134{
25eb4484 1135 struct ucontext *uc = puc;
25eb4484 1136 unsigned long pc;
25eb4484
FB		 1137 int is_write;
1138
83fb7adf 1139 pc = IAR_sig(uc);
25eb4484
FB		 1140 is_write = 0;
1141#if 0
1142 /* ppc 4xx case */
83fb7adf 1143 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1144 is_write = 1;
1145#else
83fb7adf 1146 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1147 is_write = 1;
1148#endif
1149 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1150 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1151}
1152
2f87c607
FB		 1153#elif defined(__alpha__)
1154
e4533c7a 1155int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB		 1156 void *puc)
1157{
1158 struct ucontext *uc = puc;
1159 uint32_t *pc = uc->uc_mcontext.sc_pc;
1160 uint32_t insn = *pc;
1161 int is_write = 0;
1162
8c6939c0 1163 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1164 switch (insn >> 26) {
1165 case 0x0d: // stw
1166 case 0x0e: // stb
1167 case 0x0f: // stq_u
1168 case 0x24: // stf
1169 case 0x25: // stg
1170 case 0x26: // sts
1171 case 0x27: // stt
1172 case 0x2c: // stl
1173 case 0x2d: // stq
1174 case 0x2e: // stl_c
1175 case 0x2f: // stq_c
1176 is_write = 1;
1177 }
1178
1179 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1180 is_write, &uc->uc_sigmask, puc);
2f87c607 1181}
8c6939c0
FB		 1182#elif defined(__sparc__)
1183
e4533c7a
FB		 1184int cpu_signal_handler(int host_signum, struct siginfo *info,
1185 void *puc)
8c6939c0
FB		 1186{
1187 uint32_t *regs = (uint32_t *)(info + 1);
1188 void *sigmask = (regs + 20);
1189 unsigned long pc;
1190 int is_write;
1191 uint32_t insn;
1192
1193 /* XXX: is there a standard glibc define ? */
1194 pc = regs[1];
1195 /* XXX: need kernel patch to get write flag faster */
1196 is_write = 0;
1197 insn = *(uint32_t *)pc;
1198 if ((insn >> 30) == 3) {
1199 switch((insn >> 19) & 0x3f) {
1200 case 0x05: // stb
1201 case 0x06: // sth
1202 case 0x04: // st
1203 case 0x07: // std
1204 case 0x24: // stf
1205 case 0x27: // stdf
1206 case 0x25: // stfsr
1207 is_write = 1;
1208 break;
1209 }
1210 }
1211 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1212 is_write, sigmask, NULL);
8c6939c0
FB		 1213}
1214
1215#elif defined(__arm__)
1216
e4533c7a
FB		 1217int cpu_signal_handler(int host_signum, struct siginfo *info,
1218 void *puc)
8c6939c0
FB		 1219{
1220 struct ucontext *uc = puc;
1221 unsigned long pc;
1222 int is_write;
1223
1224 pc = uc->uc_mcontext.gregs[R15];
1225 /* XXX: compute is_write */
1226 is_write = 0;
1227 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1228 is_write,
1229 &uc->uc_sigmask);
1230}
1231
38e584a0
FB		 1232#elif defined(__mc68000)
1233
1234int cpu_signal_handler(int host_signum, struct siginfo *info,
1235 void *puc)
1236{
1237 struct ucontext *uc = puc;
1238 unsigned long pc;
1239 int is_write;
1240
1241 pc = uc->uc_mcontext.gregs[16];
1242 /* XXX: compute is_write */
1243 is_write = 0;
1244 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1245 is_write,
bf3e8bf1 1246 &uc->uc_sigmask, puc);
38e584a0
FB		 1247}
1248
b8076a74
FB		 1249#elif defined(__ia64)
1250
1251#ifndef __ISR_VALID
1252 /* This ought to be in <bits/siginfo.h>... */
1253# define __ISR_VALID 1
1254# define si_flags _sifields._sigfault._si_pad0
1255#endif
1256
1257int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1258{
1259 struct ucontext *uc = puc;
1260 unsigned long ip;
1261 int is_write = 0;
1262
1263 ip = uc->uc_mcontext.sc_ip;
1264 switch (host_signum) {
1265 case SIGILL:
1266 case SIGFPE:
1267 case SIGSEGV:
1268 case SIGBUS:
1269 case SIGTRAP:
1270 if (info->si_code && (info->si_flags & __ISR_VALID))
1271 /* ISR.W (write-access) is bit 33: */
1272 is_write = (info->si_isr >> 33) & 1;
1273 break;
1274
1275 default:
1276 break;
1277 }
1278 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1279 is_write,
1280 &uc->uc_sigmask, puc);
1281}
1282
9de5e440 1283#else
2b413144 1284
3fb2ded1 1285#error host CPU specific signal handler needed
2b413144 1286
9de5e440 1287#endif
67b915a5
FB		 1288
1289#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing