[qemu.git] / cpu-exec.c

/*
 *  i386 emulator main execution loop
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "config.h"
#ifdef TARGET_I386
#include "exec-i386.h"
#endif
#ifdef TARGET_ARM
#include "exec-arm.h"
#endif

#include "disas.h"

//#define DEBUG_EXEC
//#define DEBUG_SIGNAL

#if defined(TARGET_ARM)
/* XXX: unify with i386 target */
void cpu_loop_exit(void)
{
    longjmp(env->jmp_env, 1);
}
#endif

/* main execution loop */

int cpu_exec(CPUState *env1)
{
    int saved_T0, saved_T1, saved_T2;
    CPUState *saved_env;
#ifdef reg_EAX
    int saved_EAX;
#endif
#ifdef reg_ECX
    int saved_ECX;
#endif
#ifdef reg_EDX
    int saved_EDX;
#endif
#ifdef reg_EBX
    int saved_EBX;
#endif
#ifdef reg_ESP
    int saved_ESP;
#endif
#ifdef reg_EBP
    int saved_EBP;
#endif
#ifdef reg_ESI
    int saved_ESI;
#endif
#ifdef reg_EDI
    int saved_EDI;
#endif
#ifdef __sparc__
    int saved_i7, tmp_T0;
#endif
    int code_gen_size, ret, interrupt_request;
    void (*gen_func)(void);
    TranslationBlock *tb, **ptb;
    uint8_t *tc_ptr, *cs_base, *pc;
    unsigned int flags;

    /* first we save global registers */
    saved_T0 = T0;
    saved_T1 = T1;
    saved_T2 = T2;
    saved_env = env;
    env = env1;
#ifdef __sparc__
    /* we also save i7 because longjmp may not restore it */
    asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
#endif

#if defined(TARGET_I386)
#ifdef reg_EAX
    saved_EAX = EAX;
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    saved_ECX = ECX;
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    saved_EDX = EDX;
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    saved_EBX = EBX;
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    saved_ESP = ESP;
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    saved_EBP = EBP;
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    saved_ESI = ESI;
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    saved_EDI = EDI;
    EDI = env->regs[R_EDI];
#endif
    
    /* put eflags in CPU temporary format */
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
    CC_OP = CC_OP_EFLAGS;
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
    {
        unsigned int psr;
        psr = env->cpsr;
        env->CF = (psr >> 29) & 1;
        env->NZF = (psr & 0xc0000000) ^ 0x40000000;
        env->VF = (psr << 3) & 0x80000000;
        env->cpsr = psr & ~0xf0000000;
    }
#else
#error unsupported target CPU
#endif
    env->exception_index = -1;

    /* prepare setjmp context for exception handling */
    for(;;) {
        if (setjmp(env->jmp_env) == 0) {
            /* if an exception is pending, we execute it here */
            if (env->exception_index >= 0) {
                if (env->exception_index >= EXCP_INTERRUPT) {
                    /* exit request from the cpu execution loop */
                    ret = env->exception_index;
                    break;
                } else if (env->user_mode_only) {
                    /* if user mode only, we simulate a fake exception
                       which will be hanlded outside the cpu execution
                       loop */
#if defined(TARGET_I386)
                    do_interrupt_user(env->exception_index, 
                                      env->exception_is_int, 
                                      env->error_code, 
                                      env->exception_next_eip);
#endif
                    ret = env->exception_index;
                    break;
                } else {
#if defined(TARGET_I386)
                    /* simulate a real cpu exception. On i386, it can
                       trigger new exceptions, but we do not handle
                       double or triple faults yet. */
                    do_interrupt(env->exception_index, 
                                 env->exception_is_int, 
                                 env->error_code, 
                                 env->exception_next_eip);
#endif
                }
                env->exception_index = -1;
            }
            T0 = 0; /* force lookup of first TB */
            for(;;) {
#ifdef __sparc__
                /* g1 can be modified by some libc? functions */ 
                tmp_T0 = T0;
#endif	    
                interrupt_request = env->interrupt_request;
                if (interrupt_request) {
#if defined(TARGET_I386)
                    /* if hardware interrupt pending, we execute it */
                    if ((interrupt_request & CPU_INTERRUPT_HARD) &&
                        (env->eflags & IF_MASK)) {
                        int intno;
                        intno = cpu_x86_get_pic_interrupt(env);
                        if (loglevel) {
                            fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
                        }
                        do_interrupt(intno, 0, 0, 0);
                        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
                        /* ensure that no TB jump will be modified as
                           the program flow was changed */
#ifdef __sparc__
                        tmp_T0 = 0;
#else
                        T0 = 0;
#endif
                    }
#endif
                    if (interrupt_request & CPU_INTERRUPT_EXIT) {
                        env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
                        env->exception_index = EXCP_INTERRUPT;
                        cpu_loop_exit();
                    }
                }
#ifdef DEBUG_EXEC
                if (loglevel) {
#if defined(TARGET_I386)
                    /* restore flags in standard format */
                    env->regs[R_EAX] = EAX;
                    env->regs[R_EBX] = EBX;
                    env->regs[R_ECX] = ECX;
                    env->regs[R_EDX] = EDX;
                    env->regs[R_ESI] = ESI;
                    env->regs[R_EDI] = EDI;
                    env->regs[R_EBP] = EBP;
                    env->regs[R_ESP] = ESP;
                    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
                    cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
                    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
                    env->cpsr = compute_cpsr();
                    cpu_arm_dump_state(env, logfile, 0);
                    env->cpsr &= ~0xf0000000;
#else
#error unsupported target CPU 
#endif
                }
#endif
                /* we compute the CPU state. We assume it will not
                   change during the whole generated block. */
#if defined(TARGET_I386)
                flags = (env->segs[R_CS].flags & DESC_B_MASK)
                    >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
                flags |= (env->segs[R_SS].flags & DESC_B_MASK)
                    >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
                flags |= (((unsigned long)env->segs[R_DS].base | 
                           (unsigned long)env->segs[R_ES].base |
                           (unsigned long)env->segs[R_SS].base) != 0) << 
                    GEN_FLAG_ADDSEG_SHIFT;
                flags |= env->cpl << GEN_FLAG_CPL_SHIFT;
                flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT);
                flags |= (env->eflags & (IOPL_MASK | TF_MASK));
                cs_base = env->segs[R_CS].base;
                pc = cs_base + env->eip;
#elif defined(TARGET_ARM)
                flags = 0;
                cs_base = 0;
                pc = (uint8_t *)env->regs[15];
#else
#error unsupported CPU
#endif
                tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, 
                             flags);
                if (!tb) {
                    spin_lock(&tb_lock);
                    /* if no translated code available, then translate it now */
                    tb = tb_alloc((unsigned long)pc);
                    if (!tb) {
                        /* flush must be done */
                        tb_flush();
                        /* cannot fail at this point */
                        tb = tb_alloc((unsigned long)pc);
                        /* don't forget to invalidate previous TB info */
                        ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
                        T0 = 0;
                    }
                    tc_ptr = code_gen_ptr;
                    tb->tc_ptr = tc_ptr;
                    tb->cs_base = (unsigned long)cs_base;
                    tb->flags = flags;
                    ret = cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
#if defined(TARGET_I386)
                    /* XXX: suppress that, this is incorrect */
                    /* if invalid instruction, signal it */
                    if (ret != 0) {
                        /* NOTE: the tb is allocated but not linked, so we
                           can leave it */
                        spin_unlock(&tb_lock);
                        raise_exception(EXCP06_ILLOP);
                    }
#endif
                    *ptb = tb;
                    tb->hash_next = NULL;
                    tb_link(tb);
                    code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
                    spin_unlock(&tb_lock);
                }
#ifdef DEBUG_EXEC
                if (loglevel) {
                    fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
                            (long)tb->tc_ptr, (long)tb->pc,
                            lookup_symbol((void *)tb->pc));
                }
#endif
#ifdef __sparc__
                T0 = tmp_T0;
#endif	    
                /* see if we can patch the calling TB. XXX: remove TF test */
                if (T0 != 0
#if defined(TARGET_I386)
                    && !(env->eflags & TF_MASK)
#endif
                    ) {
                    spin_lock(&tb_lock);
                    tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
                    spin_unlock(&tb_lock);
                }
                tc_ptr = tb->tc_ptr;
                env->current_tb = tb;
                /* execute the generated code */
                gen_func = (void *)tc_ptr;
#if defined(__sparc__)
                __asm__ __volatile__("call	%0\n\t"
                                     "mov	%%o7,%%i0"
                                     : /* no outputs */
                                     : "r" (gen_func) 
                                     : "i0", "i1", "i2", "i3", "i4", "i5");
#elif defined(__arm__)
                asm volatile ("mov pc, %0\n\t"
                              ".global exec_loop\n\t"
                              "exec_loop:\n\t"
                              : /* no outputs */
                              : "r" (gen_func)
                              : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
#else
                gen_func();
#endif
                env->current_tb = NULL;
            }
        } else {
        }
    } /* for(;;) */


#if defined(TARGET_I386)
    /* restore flags in standard format */
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);

    /* restore global registers */
#ifdef reg_EAX
    EAX = saved_EAX;
#endif
#ifdef reg_ECX
    ECX = saved_ECX;
#endif
#ifdef reg_EDX
    EDX = saved_EDX;
#endif
#ifdef reg_EBX
    EBX = saved_EBX;
#endif
#ifdef reg_ESP
    ESP = saved_ESP;
#endif
#ifdef reg_EBP
    EBP = saved_EBP;
#endif
#ifdef reg_ESI
    ESI = saved_ESI;
#endif
#ifdef reg_EDI
    EDI = saved_EDI;
#endif
#elif defined(TARGET_ARM)
    env->cpsr = compute_cpsr();
#else
#error unsupported target CPU
#endif
#ifdef __sparc__
    asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
#endif
    T0 = saved_T0;
    T1 = saved_T1;
    T2 = saved_T2;
    env = saved_env;
    return ret;
}

#if defined(TARGET_I386)

void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
        SegmentCache *sc;
        selector &= 0xffff;
        sc = &env->segs[seg_reg];
        sc->base = (void *)(selector << 4);
        sc->limit = 0xffff;
        sc->flags = 0;
        sc->selector = selector;
    } else {
        load_seg(seg_reg, selector, 0);
    }
    env = saved_env;
}

void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_fsave(ptr, data32);

    env = saved_env;
}

void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_frstor(ptr, data32);

    env = saved_env;
}

#endif /* TARGET_I386 */

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#include <sys/ucontext.h>

#if defined(TARGET_I386)

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    TranslationBlock *tb;
    int ret;

    if (cpu_single_env)
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
#if defined(DEBUG_SIGNAL)
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
           pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && page_unprotect(address)) {
        return 1;
    }
    /* see if it is an MMU fault */
    ret = cpu_x86_handle_mmu_fault(env, address, is_write);
    if (ret < 0)
        return 0; /* not an MMU fault */
    if (ret == 0)
        return 1; /* the MMU fault was handled without causing real CPU fault */
    /* now we have a real cpu fault */
    tb = tb_find_pc(pc);
    if (tb) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        cpu_restore_state(tb, env, pc);
    }
#if 0
    printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", 
           env->eip, env->cr[2], env->error_code);
#endif
    /* we restore the process signal mask as the sigreturn should
       do it (XXX: use sigsetjmp) */
    sigprocmask(SIG_SETMASK, old_set, NULL);
    raise_exception_err(EXCP0E_PAGE, env->error_code);
    /* never comes here */
    return 1;
}

#elif defined(TARGET_ARM)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    /* XXX: do more */
    return 0;
}
#else
#error unsupported target CPU
#endif

#if defined(__i386__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = uc->uc_mcontext.gregs[REG_EIP];
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? 
                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                             &uc->uc_sigmask);
}

#elif defined(__powerpc)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    struct pt_regs *regs = uc->uc_mcontext.regs;
    unsigned long pc;
    int is_write;

    pc = regs->nip;
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (regs->dsisr & 0x00800000)
        is_write = 1;
#else
    if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
        is_write = 1;
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}

#elif defined(__alpha__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    uint32_t *pc = uc->uc_mcontext.sc_pc;
    uint32_t insn = *pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster */
    switch (insn >> 26) {
    case 0x0d: // stw
    case 0x0e: // stb
    case 0x0f: // stq_u
    case 0x24: // stf
    case 0x25: // stg
    case 0x26: // sts
    case 0x27: // stt
    case 0x2c: // stl
    case 0x2d: // stq
    case 0x2e: // stl_c
    case 0x2f: // stq_c
	is_write = 1;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}
#elif defined(__sparc__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    uint32_t *regs = (uint32_t *)(info + 1);
    void *sigmask = (regs + 20);
    unsigned long pc;
    int is_write;
    uint32_t insn;
    
    /* XXX: is there a standard glibc define ? */
    pc = regs[1];
    /* XXX: need kernel patch to get write flag faster */
    is_write = 0;
    insn = *(uint32_t *)pc;
    if ((insn >> 30) == 3) {
      switch((insn >> 19) & 0x3f) {
      case 0x05: // stb
      case 0x06: // sth
      case 0x04: // st
      case 0x07: // std
      case 0x24: // stf
      case 0x27: // stdf
      case 0x25: // stfsr
	is_write = 1;
	break;
      }
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, sigmask);
}

#elif defined(__arm__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;
    
    pc = uc->uc_mcontext.gregs[R15];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write,
                             &uc->uc_sigmask);
}

#else

#error host CPU specific signal handler needed

#endif
Commit	Line	Data
7d13299d FB	1	/*
	2	* i386 emulator main execution loop
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
3ef693a0 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
7d13299d	10	*
3ef693a0 FB	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
7d13299d	15	*
3ef693a0 FB	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d	19	*/
e4533c7a FB	20	#include "config.h"
e4533c7a FB	21	#ifdef TARGET_I386
7d13299d	22	#include "exec-i386.h"
e4533c7a FB	23	#endif
	24	#ifdef TARGET_ARM
	25	#include "exec-arm.h"
	26	#endif
	27
956034d7	28	#include "disas.h"
7d13299d	29
dc99065b	30	//#define DEBUG_EXEC
9de5e440	31	//#define DEBUG_SIGNAL
7d13299d	32
e4533c7a FB	33	#if defined(TARGET_ARM)
	34	/* XXX: unify with i386 target */
	35	void cpu_loop_exit(void)
	36	{
	37	longjmp(env->jmp_env, 1);
	38	}
	39	#endif
	40
7d13299d FB	41	/* main execution loop */
7d13299d FB	42
e4533c7a	43	int cpu_exec(CPUState *env1)
7d13299d	44	{
e4533c7a FB	45	int saved_T0, saved_T1, saved_T2;
e4533c7a FB	46	CPUState *saved_env;
04369ff2 FB	47	#ifdef reg_EAX
	48	int saved_EAX;
	49	#endif
	50	#ifdef reg_ECX
	51	int saved_ECX;
	52	#endif
	53	#ifdef reg_EDX
	54	int saved_EDX;
	55	#endif
	56	#ifdef reg_EBX
	57	int saved_EBX;
	58	#endif
	59	#ifdef reg_ESP
	60	int saved_ESP;
	61	#endif
	62	#ifdef reg_EBP
	63	int saved_EBP;
	64	#endif
	65	#ifdef reg_ESI
	66	int saved_ESI;
	67	#endif
	68	#ifdef reg_EDI
	69	int saved_EDI;
8c6939c0 FB	70	#endif
	71	#ifdef __sparc__
	72	int saved_i7, tmp_T0;
04369ff2	73	#endif
68a79315	74	int code_gen_size, ret, interrupt_request;
7d13299d	75	void (*gen_func)(void);
9de5e440	76	TranslationBlock tb, *ptb;
dab2ed99	77	uint8_t tc_ptr, cs_base, *pc;
6dbad63e	78	unsigned int flags;
8c6939c0	79
7d13299d FB	80	/* first we save global registers */
	81	saved_T0 = T0;
	82	saved_T1 = T1;
e4533c7a	83	saved_T2 = T2;
7d13299d FB	84	saved_env = env;
7d13299d FB	85	env = env1;
e4533c7a FB	86	#ifdef __sparc__
	87	/* we also save i7 because longjmp may not restore it */
	88	asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
	89	#endif
	90
	91	#if defined(TARGET_I386)
04369ff2 FB	92	#ifdef reg_EAX
	93	saved_EAX = EAX;
	94	EAX = env->regs[R_EAX];
	95	#endif
	96	#ifdef reg_ECX
	97	saved_ECX = ECX;
	98	ECX = env->regs[R_ECX];
	99	#endif
	100	#ifdef reg_EDX
	101	saved_EDX = EDX;
	102	EDX = env->regs[R_EDX];
	103	#endif
	104	#ifdef reg_EBX
	105	saved_EBX = EBX;
	106	EBX = env->regs[R_EBX];
	107	#endif
	108	#ifdef reg_ESP
	109	saved_ESP = ESP;
	110	ESP = env->regs[R_ESP];
	111	#endif
	112	#ifdef reg_EBP
	113	saved_EBP = EBP;
	114	EBP = env->regs[R_EBP];
	115	#endif
	116	#ifdef reg_ESI
	117	saved_ESI = ESI;
	118	ESI = env->regs[R_ESI];
	119	#endif
	120	#ifdef reg_EDI
	121	saved_EDI = EDI;
	122	EDI = env->regs[R_EDI];
	123	#endif
7d13299d	124
9de5e440	125	/* put eflags in CPU temporary format */
fc2b4c48 FB	126	CC_SRC = env->eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
fc2b4c48 FB	127	DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440	128	CC_OP = CC_OP_EFLAGS;
fc2b4c48	129	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a FB	130	#elif defined(TARGET_ARM)
	131	{
	132	unsigned int psr;
	133	psr = env->cpsr;
	134	env->CF = (psr >> 29) & 1;
	135	env->NZF = (psr & 0xc0000000) ^ 0x40000000;
	136	env->VF = (psr << 3) & 0x80000000;
	137	env->cpsr = psr & ~0xf0000000;
	138	}
	139	#else
	140	#error unsupported target CPU
	141	#endif
3fb2ded1	142	env->exception_index = -1;
9d27abd9	143
7d13299d	144	/* prepare setjmp context for exception handling */
3fb2ded1 FB	145	for(;;) {
	146	if (setjmp(env->jmp_env) == 0) {
	147	/* if an exception is pending, we execute it here */
	148	if (env->exception_index >= 0) {
	149	if (env->exception_index >= EXCP_INTERRUPT) {
	150	/* exit request from the cpu execution loop */
	151	ret = env->exception_index;
	152	break;
	153	} else if (env->user_mode_only) {
	154	/* if user mode only, we simulate a fake exception
	155	which will be hanlded outside the cpu execution
	156	loop */
83479e77	157	#if defined(TARGET_I386)
3fb2ded1 FB	158	do_interrupt_user(env->exception_index,
	159	env->exception_is_int,
	160	env->error_code,
	161	env->exception_next_eip);
83479e77	162	#endif
3fb2ded1 FB	163	ret = env->exception_index;
	164	break;
	165	} else {
83479e77	166	#if defined(TARGET_I386)
3fb2ded1 FB	167	/* simulate a real cpu exception. On i386, it can
	168	trigger new exceptions, but we do not handle
	169	double or triple faults yet. */
	170	do_interrupt(env->exception_index,
	171	env->exception_is_int,
	172	env->error_code,
	173	env->exception_next_eip);
83479e77	174	#endif
3fb2ded1 FB	175	}
	176	env->exception_index = -1;
	177	}
3fb2ded1 FB	178	T0 = 0; /* force lookup of first TB */
3fb2ded1 FB	179	for(;;) {
8c6939c0	180	#ifdef __sparc__
3fb2ded1 FB	181	/* g1 can be modified by some libc? functions */
3fb2ded1 FB	182	tmp_T0 = T0;
8c6939c0	183	#endif
68a79315 FB	184	interrupt_request = env->interrupt_request;
	185	if (interrupt_request) {
	186	#if defined(TARGET_I386)
	187	/* if hardware interrupt pending, we execute it */
	188	if ((interrupt_request & CPU_INTERRUPT_HARD) &&
	189	(env->eflags & IF_MASK)) {
	190	int intno;
	191	intno = cpu_x86_get_pic_interrupt(env);
	192	if (loglevel) {
	193	fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
	194	}
	195	do_interrupt(intno, 0, 0, 0);
	196	env->interrupt_request &= ~CPU_INTERRUPT_HARD;
907a5b26 FB	197	/* ensure that no TB jump will be modified as
	198	the program flow was changed */
	199	#ifdef __sparc__
	200	tmp_T0 = 0;
	201	#else
	202	T0 = 0;
	203	#endif
68a79315 FB	204	}
	205	#endif
	206	if (interrupt_request & CPU_INTERRUPT_EXIT) {
	207	env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
	208	env->exception_index = EXCP_INTERRUPT;
	209	cpu_loop_exit();
	210	}
3fb2ded1	211	}
7d13299d	212	#ifdef DEBUG_EXEC
3fb2ded1	213	if (loglevel) {
e4533c7a	214	#if defined(TARGET_I386)
3fb2ded1 FB	215	/* restore flags in standard format */
	216	env->regs[R_EAX] = EAX;
	217	env->regs[R_EBX] = EBX;
	218	env->regs[R_ECX] = ECX;
	219	env->regs[R_EDX] = EDX;
	220	env->regs[R_ESI] = ESI;
	221	env->regs[R_EDI] = EDI;
	222	env->regs[R_EBP] = EBP;
	223	env->regs[R_ESP] = ESP;
	224	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
68a79315	225	cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
3fb2ded1	226	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a	227	#elif defined(TARGET_ARM)
1b21b62a	228	env->cpsr = compute_cpsr();
3fb2ded1	229	cpu_arm_dump_state(env, logfile, 0);
1b21b62a	230	env->cpsr &= ~0xf0000000;
e4533c7a FB	231	#else
	232	#error unsupported target CPU
	233	#endif
3fb2ded1	234	}
7d13299d	235	#endif
3fb2ded1 FB	236	/* we compute the CPU state. We assume it will not
3fb2ded1 FB	237	change during the whole generated block. */
e4533c7a	238	#if defined(TARGET_I386)
3fb2ded1 FB	239	flags = (env->segs[R_CS].flags & DESC_B_MASK)
	240	>> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
	241	flags \|= (env->segs[R_SS].flags & DESC_B_MASK)
	242	>> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
	243	flags \|= (((unsigned long)env->segs[R_DS].base \|
	244	(unsigned long)env->segs[R_ES].base \|
	245	(unsigned long)env->segs[R_SS].base) != 0) <<
	246	GEN_FLAG_ADDSEG_SHIFT;
b6d78bfa FB	247	flags \|= env->cpl << GEN_FLAG_CPL_SHIFT;
b6d78bfa FB	248	flags \|= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT);
3fb2ded1 FB	249	flags \|= (env->eflags & (IOPL_MASK \| TF_MASK));
	250	cs_base = env->segs[R_CS].base;
	251	pc = cs_base + env->eip;
e4533c7a	252	#elif defined(TARGET_ARM)
3fb2ded1 FB	253	flags = 0;
	254	cs_base = 0;
	255	pc = (uint8_t *)env->regs[15];
e4533c7a FB	256	#else
	257	#error unsupported CPU
	258	#endif
3fb2ded1 FB	259	tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
3fb2ded1 FB	260	flags);
d4e8164f	261	if (!tb) {
3fb2ded1 FB	262	spin_lock(&tb_lock);
3fb2ded1 FB	263	/* if no translated code available, then translate it now */
d4e8164f	264	tb = tb_alloc((unsigned long)pc);
3fb2ded1 FB	265	if (!tb) {
	266	/* flush must be done */
	267	tb_flush();
	268	/* cannot fail at this point */
	269	tb = tb_alloc((unsigned long)pc);
	270	/* don't forget to invalidate previous TB info */
	271	ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
	272	T0 = 0;
	273	}
	274	tc_ptr = code_gen_ptr;
	275	tb->tc_ptr = tc_ptr;
	276	tb->cs_base = (unsigned long)cs_base;
	277	tb->flags = flags;
4c3a88a2	278	ret = cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
e4533c7a	279	#if defined(TARGET_I386)
3fb2ded1 FB	280	/* XXX: suppress that, this is incorrect */
	281	/* if invalid instruction, signal it */
	282	if (ret != 0) {
	283	/* NOTE: the tb is allocated but not linked, so we
	284	can leave it */
	285	spin_unlock(&tb_lock);
	286	raise_exception(EXCP06_ILLOP);
	287	}
	288	#endif
	289	*ptb = tb;
	290	tb->hash_next = NULL;
	291	tb_link(tb);
	292	code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
25eb4484	293	spin_unlock(&tb_lock);
9de5e440	294	}
9d27abd9	295	#ifdef DEBUG_EXEC
3fb2ded1 FB	296	if (loglevel) {
	297	fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
	298	(long)tb->tc_ptr, (long)tb->pc,
	299	lookup_symbol((void *)tb->pc));
	300	}
9d27abd9	301	#endif
8c6939c0	302	#ifdef __sparc__
3fb2ded1	303	T0 = tmp_T0;
8c6939c0	304	#endif
3fb2ded1	305	/* see if we can patch the calling TB. XXX: remove TF test */
1b21b62a	306	if (T0 != 0
e4533c7a	307	#if defined(TARGET_I386)
3fb2ded1	308	&& !(env->eflags & TF_MASK)
e4533c7a	309	#endif
3fb2ded1 FB	310	) {
	311	spin_lock(&tb_lock);
	312	tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
	313	spin_unlock(&tb_lock);
	314	}
3fb2ded1	315	tc_ptr = tb->tc_ptr;
83479e77	316	env->current_tb = tb;
3fb2ded1 FB	317	/* execute the generated code */
3fb2ded1 FB	318	gen_func = (void *)tc_ptr;
8c6939c0	319	#if defined(__sparc__)
3fb2ded1 FB	320	__asm__ __volatile__("call %0\n\t"
	321	"mov %%o7,%%i0"
	322	: /* no outputs */
	323	: "r" (gen_func)
	324	: "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0	325	#elif defined(__arm__)
3fb2ded1 FB	326	asm volatile ("mov pc, %0\n\t"
	327	".global exec_loop\n\t"
	328	"exec_loop:\n\t"
	329	: /* no outputs */
	330	: "r" (gen_func)
	331	: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
ae228531	332	#else
3fb2ded1	333	gen_func();
ae228531	334	#endif
83479e77	335	env->current_tb = NULL;
3fb2ded1 FB	336	}
3fb2ded1 FB	337	} else {
7d13299d	338	}
3fb2ded1 FB	339	} /* for(;;) */
3fb2ded1 FB	340
7d13299d	341
e4533c7a	342	#if defined(TARGET_I386)
9de5e440	343	/* restore flags in standard format */
fc2b4c48	344	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
9de5e440	345
7d13299d	346	/* restore global registers */
04369ff2 FB	347	#ifdef reg_EAX
	348	EAX = saved_EAX;
	349	#endif
	350	#ifdef reg_ECX
	351	ECX = saved_ECX;
	352	#endif
	353	#ifdef reg_EDX
	354	EDX = saved_EDX;
	355	#endif
	356	#ifdef reg_EBX
	357	EBX = saved_EBX;
	358	#endif
	359	#ifdef reg_ESP
	360	ESP = saved_ESP;
	361	#endif
	362	#ifdef reg_EBP
	363	EBP = saved_EBP;
	364	#endif
	365	#ifdef reg_ESI
	366	ESI = saved_ESI;
	367	#endif
	368	#ifdef reg_EDI
	369	EDI = saved_EDI;
8c6939c0	370	#endif
e4533c7a	371	#elif defined(TARGET_ARM)
1b21b62a	372	env->cpsr = compute_cpsr();
e4533c7a FB	373	#else
	374	#error unsupported target CPU
	375	#endif
8c6939c0 FB	376	#ifdef __sparc__
8c6939c0 FB	377	asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2	378	#endif
7d13299d FB	379	T0 = saved_T0;
7d13299d FB	380	T1 = saved_T1;
e4533c7a	381	T2 = saved_T2;
7d13299d FB	382	env = saved_env;
	383	return ret;
	384	}
6dbad63e	385
e4533c7a FB	386	#if defined(TARGET_I386)
e4533c7a FB	387
6dbad63e FB	388	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
	389	{
	390	CPUX86State *saved_env;
	391
	392	saved_env = env;
	393	env = s;
a412ac57	394	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
a513fe19 FB	395	SegmentCache *sc;
a513fe19 FB	396	selector &= 0xffff;
970a87a6	397	sc = &env->segs[seg_reg];
a513fe19 FB	398	sc->base = (void *)(selector << 4);
a513fe19 FB	399	sc->limit = 0xffff;
3fb2ded1	400	sc->flags = 0;
970a87a6	401	sc->selector = selector;
a513fe19 FB	402	} else {
	403	load_seg(seg_reg, selector, 0);
	404	}
6dbad63e FB	405	env = saved_env;
6dbad63e FB	406	}
9de5e440	407
d0a1ffc9 FB	408	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32)
	409	{
	410	CPUX86State *saved_env;
	411
	412	saved_env = env;
	413	env = s;
	414
	415	helper_fsave(ptr, data32);
	416
	417	env = saved_env;
	418	}
	419
	420	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32)
	421	{
	422	CPUX86State *saved_env;
	423
	424	saved_env = env;
	425	env = s;
	426
	427	helper_frstor(ptr, data32);
	428
	429	env = saved_env;
	430	}
	431
e4533c7a FB	432	#endif /* TARGET_I386 */
e4533c7a FB	433
9de5e440 FB	434	#undef EAX
	435	#undef ECX
	436	#undef EDX
	437	#undef EBX
	438	#undef ESP
	439	#undef EBP
	440	#undef ESI
	441	#undef EDI
	442	#undef EIP
	443	#include <signal.h>
	444	#include <sys/ucontext.h>
	445
3fb2ded1 FB	446	#if defined(TARGET_I386)
3fb2ded1 FB	447
b56dad1c	448	/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6 FB	449	the effective address of the memory exception. 'is_write' is 1 if a
	450	write caused the exception and otherwise 0'. 'old_set' is the
	451	signal set which should be restored */
2b413144 FB	452	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
2b413144 FB	453	int is_write, sigset_t *old_set)
9de5e440	454	{
a513fe19 FB	455	TranslationBlock *tb;
a513fe19 FB	456	int ret;
68a79315	457
83479e77 FB	458	if (cpu_single_env)
83479e77 FB	459	env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6	460	#if defined(DEBUG_SIGNAL)
3fb2ded1	461	printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
fd6ce8f6	462	pc, address, is_write, (unsigned long )old_set);
9de5e440	463	#endif
25eb4484	464	/* XXX: locking issue */
fd6ce8f6	465	if (is_write && page_unprotect(address)) {
fd6ce8f6 FB	466	return 1;
fd6ce8f6 FB	467	}
3fb2ded1 FB	468	/* see if it is an MMU fault */
	469	ret = cpu_x86_handle_mmu_fault(env, address, is_write);
	470	if (ret < 0)
	471	return 0; /* not an MMU fault */
	472	if (ret == 0)
	473	return 1; /* the MMU fault was handled without causing real CPU fault */
	474	/* now we have a real cpu fault */
a513fe19 FB	475	tb = tb_find_pc(pc);
a513fe19 FB	476	if (tb) {
9de5e440 FB	477	/* the PC is inside the translated code. It means that we have
9de5e440 FB	478	a virtual CPU fault */
3fb2ded1 FB	479	cpu_restore_state(tb, env, pc);
	480	}
	481	#if 0
	482	printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
	483	env->eip, env->cr[2], env->error_code);
	484	#endif
	485	/* we restore the process signal mask as the sigreturn should
	486	do it (XXX: use sigsetjmp) */
	487	sigprocmask(SIG_SETMASK, old_set, NULL);
	488	raise_exception_err(EXCP0E_PAGE, env->error_code);
	489	/* never comes here */
	490	return 1;
	491	}
	492
e4533c7a	493	#elif defined(TARGET_ARM)
3fb2ded1 FB	494	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
	495	int is_write, sigset_t *old_set)
	496	{
	497	/* XXX: do more */
	498	return 0;
	499	}
e4533c7a FB	500	#else
	501	#error unsupported target CPU
	502	#endif
9de5e440	503
2b413144 FB	504	#if defined(__i386__)
2b413144 FB	505
e4533c7a FB	506	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	507	void *puc)
9de5e440	508	{
9de5e440 FB	509	struct ucontext *uc = puc;
9de5e440 FB	510	unsigned long pc;
9de5e440	511
d691f669 FB	512	#ifndef REG_EIP
d691f669 FB	513	/* for glibc 2.1 */
fd6ce8f6 FB	514	#define REG_EIP EIP
	515	#define REG_ERR ERR
	516	#define REG_TRAPNO TRAPNO
d691f669	517	#endif
fc2b4c48	518	pc = uc->uc_mcontext.gregs[REG_EIP];
fd6ce8f6 FB	519	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	520	uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
	521	(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
2b413144 FB	522	&uc->uc_sigmask);
	523	}
	524
25eb4484	525	#elif defined(__powerpc)
2b413144	526
e4533c7a FB	527	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	528	void *puc)
2b413144	529	{
25eb4484 FB	530	struct ucontext *uc = puc;
	531	struct pt_regs *regs = uc->uc_mcontext.regs;
	532	unsigned long pc;
25eb4484 FB	533	int is_write;
	534
	535	pc = regs->nip;
25eb4484 FB	536	is_write = 0;
	537	#if 0
	538	/* ppc 4xx case */
	539	if (regs->dsisr & 0x00800000)
	540	is_write = 1;
	541	#else
	542	if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
	543	is_write = 1;
	544	#endif
	545	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
2b413144 FB	546	is_write, &uc->uc_sigmask);
	547	}
	548
2f87c607 FB	549	#elif defined(__alpha__)
2f87c607 FB	550
e4533c7a	551	int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607 FB	552	void *puc)
	553	{
	554	struct ucontext *uc = puc;
	555	uint32_t *pc = uc->uc_mcontext.sc_pc;
	556	uint32_t insn = *pc;
	557	int is_write = 0;
	558
8c6939c0	559	/* XXX: need kernel patch to get write flag faster */
2f87c607 FB	560	switch (insn >> 26) {
	561	case 0x0d: // stw
	562	case 0x0e: // stb
	563	case 0x0f: // stq_u
	564	case 0x24: // stf
	565	case 0x25: // stg
	566	case 0x26: // sts
	567	case 0x27: // stt
	568	case 0x2c: // stl
	569	case 0x2d: // stq
	570	case 0x2e: // stl_c
	571	case 0x2f: // stq_c
	572	is_write = 1;
	573	}
	574
	575	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	576	is_write, &uc->uc_sigmask);
	577	}
8c6939c0 FB	578	#elif defined(__sparc__)
8c6939c0 FB	579
e4533c7a FB	580	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	581	void *puc)
8c6939c0 FB	582	{
	583	uint32_t regs = (uint32_t )(info + 1);
	584	void *sigmask = (regs + 20);
	585	unsigned long pc;
	586	int is_write;
	587	uint32_t insn;
	588
	589	/* XXX: is there a standard glibc define ? */
	590	pc = regs[1];
	591	/* XXX: need kernel patch to get write flag faster */
	592	is_write = 0;
	593	insn = (uint32_t )pc;
	594	if ((insn >> 30) == 3) {
	595	switch((insn >> 19) & 0x3f) {
	596	case 0x05: // stb
	597	case 0x06: // sth
	598	case 0x04: // st
	599	case 0x07: // std
	600	case 0x24: // stf
	601	case 0x27: // stdf
	602	case 0x25: // stfsr
	603	is_write = 1;
	604	break;
	605	}
	606	}
	607	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	608	is_write, sigmask);
	609	}
	610
	611	#elif defined(__arm__)
	612
e4533c7a FB	613	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	614	void *puc)
8c6939c0 FB	615	{
	616	struct ucontext *uc = puc;
	617	unsigned long pc;
	618	int is_write;
	619
	620	pc = uc->uc_mcontext.gregs[R15];
	621	/* XXX: compute is_write */
	622	is_write = 0;
	623	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	624	is_write,
	625	&uc->uc_sigmask);
	626	}
	627
9de5e440	628	#else
2b413144	629
3fb2ded1	630	#error host CPU specific signal handler needed
2b413144	631
9de5e440	632	#endif