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mips-dis: Add missing static attributes
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
7d13299d 24
fbf9eeb3
FB		 25#if !defined(CONFIG_SOFTMMU)
26#undef EAX
27#undef ECX
28#undef EDX
29#undef EBX
30#undef ESP
31#undef EBP
32#undef ESI
33#undef EDI
34#undef EIP
35#include <signal.h>
84778508 36#ifdef __linux__
fbf9eeb3
FB		 37#include <sys/ucontext.h>
38#endif
84778508 39#endif
fbf9eeb3 40
dfe5fff3 41#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 42// Work around ugly bugs in glibc that mangle global register contents
43#undef env
44#define env cpu_single_env
45#endif
46
36bdbe54
FB		 47int tb_invalidated_flag;
48
f0667e66 49//#define CONFIG_DEBUG_EXEC
9de5e440 50//#define DEBUG_SIGNAL
7d13299d 51
6a4955a8
AL		 52int qemu_cpu_has_work(CPUState *env)
53{
54 return cpu_has_work(env);
55}
56
e4533c7a
FB		 57void cpu_loop_exit(void)
58{
1c3569fe 59 env->current_tb = NULL;
e4533c7a
FB		 60 longjmp(env->jmp_env, 1);
61}
bfed01fc 62
fbf9eeb3
FB		 63/* exit the current TB from a signal handler. The host registers are
64 restored in a state compatible with the CPU emulator
65 */
5fafdf24 66void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 67{
68#if !defined(CONFIG_SOFTMMU)
84778508 69#ifdef __linux__
fbf9eeb3 70 struct ucontext *uc = puc;
84778508
BS		 71#elif defined(__OpenBSD__)
72 struct sigcontext *uc = puc;
73#endif
fbf9eeb3
FB		 74#endif
75
76 env = env1;
77
78 /* XXX: restore cpu registers saved in host registers */
79
80#if !defined(CONFIG_SOFTMMU)
81 if (puc) {
82 /* XXX: use siglongjmp ? */
84778508 83#ifdef __linux__
60e99246
AJ		 84#ifdef __ia64
85 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
86#else
fbf9eeb3 87 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
60e99246 88#endif
84778508
BS		 89#elif defined(__OpenBSD__)
90 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
91#endif
fbf9eeb3
FB		 92 }
93#endif
9a3ea654 94 env->exception_index = -1;
fbf9eeb3
FB		 95 longjmp(env->jmp_env, 1);
96}
97
2e70f6ef
PB		 98/* Execute the code without caching the generated code. An interpreter
99 could be used if available. */
100static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
101{
102 unsigned long next_tb;
103 TranslationBlock *tb;
104
105 /* Should never happen.
106 We only end up here when an existing TB is too long. */
107 if (max_cycles > CF_COUNT_MASK)
108 max_cycles = CF_COUNT_MASK;
109
110 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
111 max_cycles);
112 env->current_tb = tb;
113 /* execute the generated code */
114 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
1c3569fe 115 env->current_tb = NULL;
2e70f6ef
PB		 116
117 if ((next_tb & 3) == 2) {
118 /* Restore PC. This may happen if async event occurs before
119 the TB starts executing. */
622ed360 120 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 121 }
122 tb_phys_invalidate(tb, -1);
123 tb_free(tb);
124}
125
8a40a180
FB		 126static TranslationBlock *tb_find_slow(target_ulong pc,
127 target_ulong cs_base,
c068688b 128 uint64_t flags)
8a40a180
FB		 129{
130 TranslationBlock *tb, **ptb1;
8a40a180 131 unsigned int h;
41c1b1c9
PB		 132 tb_page_addr_t phys_pc, phys_page1, phys_page2;
133 target_ulong virt_page2;
3b46e624 134
8a40a180 135 tb_invalidated_flag = 0;
3b46e624 136
8a40a180 137 /* find translated block using physical mappings */
41c1b1c9 138 phys_pc = get_page_addr_code(env, pc);
8a40a180
FB		 139 phys_page1 = phys_pc & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 h = tb_phys_hash_func(phys_pc);
142 ptb1 = &tb_phys_hash[h];
143 for(;;) {
144 tb = *ptb1;
145 if (!tb)
146 goto not_found;
5fafdf24 147 if (tb->pc == pc &&
8a40a180 148 tb->page_addr[0] == phys_page1 &&
5fafdf24 149 tb->cs_base == cs_base &&
8a40a180
FB		 150 tb->flags == flags) {
151 /* check next page if needed */
152 if (tb->page_addr[1] != -1) {
5fafdf24 153 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 154 TARGET_PAGE_SIZE;
41c1b1c9 155 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 156 if (tb->page_addr[1] == phys_page2)
157 goto found;
158 } else {
159 goto found;
160 }
161 }
162 ptb1 = &tb->phys_hash_next;
163 }
164 not_found:
2e70f6ef
PB		 165 /* if no translated code available, then translate it now */
166 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 167
8a40a180 168 found:
8a40a180
FB		 169 /* we add the TB in the virtual pc hash table */
170 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 171 return tb;
172}
173
174static inline TranslationBlock *tb_find_fast(void)
175{
176 TranslationBlock *tb;
177 target_ulong cs_base, pc;
6b917547 178 int flags;
8a40a180
FB		 179
180 /* we record a subset of the CPU state. It will
181 always be the same before a given translated block
182 is executed. */
6b917547 183 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 184 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 185 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
186 tb->flags != flags)) {
8a40a180
FB		 187 tb = tb_find_slow(pc, cs_base, flags);
188 }
189 return tb;
190}
191
dde2367e
AL		 192static CPUDebugExcpHandler *debug_excp_handler;
193
194CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
195{
196 CPUDebugExcpHandler *old_handler = debug_excp_handler;
197
198 debug_excp_handler = handler;
199 return old_handler;
200}
201
6e140f28
AL		 202static void cpu_handle_debug_exception(CPUState *env)
203{
204 CPUWatchpoint *wp;
205
206 if (!env->watchpoint_hit)
72cf2d4f 207 QTAILQ_FOREACH(wp, &env->watchpoints, entry)
6e140f28 208 wp->flags &= ~BP_WATCHPOINT_HIT;
dde2367e
AL		 209
210 if (debug_excp_handler)
211 debug_excp_handler(env);
6e140f28
AL		 212}
213
7d13299d
FB		 214/* main execution loop */
215
e4533c7a 216int cpu_exec(CPUState *env1)
7d13299d 217{
1d9000e8 218 volatile host_reg_t saved_env_reg;
8a40a180 219 int ret, interrupt_request;
8a40a180 220 TranslationBlock *tb;
c27004ec 221 uint8_t *tc_ptr;
d5975363 222 unsigned long next_tb;
8c6939c0 223
bfed01fc
TS		 224 if (cpu_halted(env1) == EXCP_HALTED)
225 return EXCP_HALTED;
5a1e3cfc 226
5fafdf24 227 cpu_single_env = env1;
6a00d601 228
24ebf5f3
PB		 229 /* the access to env below is actually saving the global register's
230 value, so that files not including target-xyz/exec.h are free to
231 use it. */
232 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
233 saved_env_reg = (host_reg_t) env;
234 asm("");
c27004ec 235 env = env1;
e4533c7a 236
ecb644f4 237#if defined(TARGET_I386)
14dcc3e2
JK		 238 if (!kvm_enabled()) {
239 /* put eflags in CPU temporary format */
240 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
241 DF = 1 - (2 * ((env->eflags >> 10) & 1));
242 CC_OP = CC_OP_EFLAGS;
243 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
244 }
93ac68bc 245#elif defined(TARGET_SPARC)
e6e5906b
PB		 246#elif defined(TARGET_M68K)
247 env->cc_op = CC_OP_FLAGS;
248 env->cc_dest = env->sr & 0xf;
249 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 250#elif defined(TARGET_ALPHA)
251#elif defined(TARGET_ARM)
252#elif defined(TARGET_PPC)
b779e29e 253#elif defined(TARGET_MICROBLAZE)
6af0bf9c 254#elif defined(TARGET_MIPS)
fdf9b3e8 255#elif defined(TARGET_SH4)
f1ccf904 256#elif defined(TARGET_CRIS)
10ec5117 257#elif defined(TARGET_S390X)
fdf9b3e8 258 /* XXXXX */
e4533c7a
FB		 259#else
260#error unsupported target CPU
261#endif
3fb2ded1 262 env->exception_index = -1;
9d27abd9 263
7d13299d 264 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 265 for(;;) {
266 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 267#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 268#undef env
269 env = cpu_single_env;
270#define env cpu_single_env
271#endif
3fb2ded1
FB		 272 /* if an exception is pending, we execute it here */
273 if (env->exception_index >= 0) {
274 if (env->exception_index >= EXCP_INTERRUPT) {
275 /* exit request from the cpu execution loop */
276 ret = env->exception_index;
6e140f28
AL		 277 if (ret == EXCP_DEBUG)
278 cpu_handle_debug_exception(env);
3fb2ded1 279 break;
72d239ed
AJ		 280 } else {
281#if defined(CONFIG_USER_ONLY)
3fb2ded1 282 /* if user mode only, we simulate a fake exception
9f083493 283 which will be handled outside the cpu execution
3fb2ded1 284 loop */
83479e77 285#if defined(TARGET_I386)
5fafdf24
TS		 286 do_interrupt_user(env->exception_index,
287 env->exception_is_int,
288 env->error_code,
3fb2ded1 289 env->exception_next_eip);
eba01623
FB		 290 /* successfully delivered */
291 env->old_exception = -1;
83479e77 292#endif
3fb2ded1
FB		 293 ret = env->exception_index;
294 break;
72d239ed 295#else
83479e77 296#if defined(TARGET_I386)
3fb2ded1
FB		 297 /* simulate a real cpu exception. On i386, it can
298 trigger new exceptions, but we do not handle
299 double or triple faults yet. */
5fafdf24
TS		 300 do_interrupt(env->exception_index,
301 env->exception_is_int,
302 env->error_code,
d05e66d2 303 env->exception_next_eip, 0);
678dde13
TS		 304 /* successfully delivered */
305 env->old_exception = -1;
ce09776b
FB		 306#elif defined(TARGET_PPC)
307 do_interrupt(env);
b779e29e
EI		 308#elif defined(TARGET_MICROBLAZE)
309 do_interrupt(env);
6af0bf9c
FB		 310#elif defined(TARGET_MIPS)
311 do_interrupt(env);
e95c8d51 312#elif defined(TARGET_SPARC)
f2bc7e7f 313 do_interrupt(env);
b5ff1b31
FB		 314#elif defined(TARGET_ARM)
315 do_interrupt(env);
fdf9b3e8
FB		 316#elif defined(TARGET_SH4)
317 do_interrupt(env);
eddf68a6
JM		 318#elif defined(TARGET_ALPHA)
319 do_interrupt(env);
f1ccf904
TS		 320#elif defined(TARGET_CRIS)
321 do_interrupt(env);
0633879f
PB		 322#elif defined(TARGET_M68K)
323 do_interrupt(0);
72d239ed 324#endif
301d2908 325 env->exception_index = -1;
83479e77 326#endif
3fb2ded1 327 }
5fafdf24 328 }
9df217a3 329
7ba1e619 330 if (kvm_enabled()) {
becfc390
AL		 331 kvm_cpu_exec(env);
332 longjmp(env->jmp_env, 1);
7ba1e619
AL		 333 }
334
b5fc09ae 335 next_tb = 0; /* force lookup of first TB */
3fb2ded1 336 for(;;) {
68a79315 337 interrupt_request = env->interrupt_request;
e1638bd8 338 if (unlikely(interrupt_request)) {
339 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
340 /* Mask out external interrupts for this step. */
341 interrupt_request &= ~(CPU_INTERRUPT_HARD |
342 CPU_INTERRUPT_FIQ |
343 CPU_INTERRUPT_SMI |
344 CPU_INTERRUPT_NMI);
345 }
6658ffb8
PB		 346 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
347 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
348 env->exception_index = EXCP_DEBUG;
349 cpu_loop_exit();
350 }
a90b7318 351#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e
EI		 352 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
353 defined(TARGET_MICROBLAZE)
a90b7318
AZ		 354 if (interrupt_request & CPU_INTERRUPT_HALT) {
355 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
356 env->halted = 1;
357 env->exception_index = EXCP_HLT;
358 cpu_loop_exit();
359 }
360#endif
68a79315 361#if defined(TARGET_I386)
b09ea7d5
GN		 362 if (interrupt_request & CPU_INTERRUPT_INIT) {
363 svm_check_intercept(SVM_EXIT_INIT);
364 do_cpu_init(env);
365 env->exception_index = EXCP_HALTED;
366 cpu_loop_exit();
367 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
368 do_cpu_sipi(env);
369 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 370 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
371 !(env->hflags & HF_SMM_MASK)) {
372 svm_check_intercept(SVM_EXIT_SMI);
373 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
374 do_smm_enter();
375 next_tb = 0;
376 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
377 !(env->hflags2 & HF2_NMI_MASK)) {
378 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
379 env->hflags2 |= HF2_NMI_MASK;
380 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
381 next_tb = 0;
79c4f6b0
HY		 382 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
383 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
384 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
385 next_tb = 0;
db620f46
FB		 386 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
387 (((env->hflags2 & HF2_VINTR_MASK) &&
388 (env->hflags2 & HF2_HIF_MASK)) ||
389 (!(env->hflags2 & HF2_VINTR_MASK) &&
390 (env->eflags & IF_MASK &&
391 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
392 int intno;
393 svm_check_intercept(SVM_EXIT_INTR);
394 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
395 intno = cpu_get_pic_interrupt(env);
93fcfe39 396 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 397#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 398#undef env
399 env = cpu_single_env;
400#define env cpu_single_env
401#endif
db620f46
FB		 402 do_interrupt(intno, 0, 0, 0, 1);
403 /* ensure that no TB jump will be modified as
404 the program flow was changed */
405 next_tb = 0;
0573fbfc 406#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 407 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
408 (env->eflags & IF_MASK) &&
409 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
410 int intno;
411 /* FIXME: this should respect TPR */
412 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 413 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 414 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 415 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 416 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 417 next_tb = 0;
907a5b26 418#endif
db620f46 419 }
68a79315 420 }
ce09776b 421#elif defined(TARGET_PPC)
9fddaa0c
FB		 422#if 0
423 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 424 cpu_reset(env);
9fddaa0c
FB		 425 }
426#endif
47103572 427 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 428 ppc_hw_interrupt(env);
429 if (env->pending_interrupts == 0)
430 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 431 next_tb = 0;
ce09776b 432 }
b779e29e
EI		 433#elif defined(TARGET_MICROBLAZE)
434 if ((interrupt_request & CPU_INTERRUPT_HARD)
435 && (env->sregs[SR_MSR] & MSR_IE)
436 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
437 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
438 env->exception_index = EXCP_IRQ;
439 do_interrupt(env);
440 next_tb = 0;
441 }
6af0bf9c
FB		 442#elif defined(TARGET_MIPS)
443 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 444 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 445 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 446 !(env->CP0_Status & (1 << CP0St_EXL)) &&
447 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 448 !(env->hflags & MIPS_HFLAG_DM)) {
449 /* Raise it */
450 env->exception_index = EXCP_EXT_INTERRUPT;
451 env->error_code = 0;
452 do_interrupt(env);
b5fc09ae 453 next_tb = 0;
6af0bf9c 454 }
e95c8d51 455#elif defined(TARGET_SPARC)
d532b26c
IK		 456 if (interrupt_request & CPU_INTERRUPT_HARD) {
457 if (cpu_interrupts_enabled(env) &&
458 env->interrupt_index > 0) {
459 int pil = env->interrupt_index & 0xf;
460 int type = env->interrupt_index & 0xf0;
461
462 if (((type == TT_EXTINT) &&
463 cpu_pil_allowed(env, pil)) ||
464 type != TT_EXTINT) {
465 env->exception_index = env->interrupt_index;
466 do_interrupt(env);
467 next_tb = 0;
468 }
469 }
e95c8d51
FB		 470 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
471 //do_interrupt(0, 0, 0, 0, 0);
472 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 473 }
b5ff1b31
FB		 474#elif defined(TARGET_ARM)
475 if (interrupt_request & CPU_INTERRUPT_FIQ
476 && !(env->uncached_cpsr & CPSR_F)) {
477 env->exception_index = EXCP_FIQ;
478 do_interrupt(env);
b5fc09ae 479 next_tb = 0;
b5ff1b31 480 }
9ee6e8bb
PB		 481 /* ARMv7-M interrupt return works by loading a magic value
482 into the PC. On real hardware the load causes the
483 return to occur. The qemu implementation performs the
484 jump normally, then does the exception return when the
485 CPU tries to execute code at the magic address.
486 This will cause the magic PC value to be pushed to
487 the stack if an interrupt occured at the wrong time.
488 We avoid this by disabling interrupts when
489 pc contains a magic address. */
b5ff1b31 490 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 491 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
492 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 493 env->exception_index = EXCP_IRQ;
494 do_interrupt(env);
b5fc09ae 495 next_tb = 0;
b5ff1b31 496 }
fdf9b3e8 497#elif defined(TARGET_SH4)
e96e2044
TS		 498 if (interrupt_request & CPU_INTERRUPT_HARD) {
499 do_interrupt(env);
b5fc09ae 500 next_tb = 0;
e96e2044 501 }
eddf68a6
JM		 502#elif defined(TARGET_ALPHA)
503 if (interrupt_request & CPU_INTERRUPT_HARD) {
504 do_interrupt(env);
b5fc09ae 505 next_tb = 0;
eddf68a6 506 }
f1ccf904 507#elif defined(TARGET_CRIS)
1b1a38b0 508 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 509 && (env->pregs[PR_CCS] & I_FLAG)
510 && !env->locked_irq) {
1b1a38b0
EI		 511 env->exception_index = EXCP_IRQ;
512 do_interrupt(env);
513 next_tb = 0;
514 }
515 if (interrupt_request & CPU_INTERRUPT_NMI
516 && (env->pregs[PR_CCS] & M_FLAG)) {
517 env->exception_index = EXCP_NMI;
f1ccf904 518 do_interrupt(env);
b5fc09ae 519 next_tb = 0;
f1ccf904 520 }
0633879f
PB		 521#elif defined(TARGET_M68K)
522 if (interrupt_request & CPU_INTERRUPT_HARD
523 && ((env->sr & SR_I) >> SR_I_SHIFT)
524 < env->pending_level) {
525 /* Real hardware gets the interrupt vector via an
526 IACK cycle at this point. Current emulated
527 hardware doesn't rely on this, so we
528 provide/save the vector when the interrupt is
529 first signalled. */
530 env->exception_index = env->pending_vector;
531 do_interrupt(1);
b5fc09ae 532 next_tb = 0;
0633879f 533 }
68a79315 534#endif
9d05095e
FB		 535 /* Don't use the cached interupt_request value,
536 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 537 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 538 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
539 /* ensure that no TB jump will be modified as
540 the program flow was changed */
b5fc09ae 541 next_tb = 0;
bf3e8bf1 542 }
be214e6c
AJ		 543 }
544 if (unlikely(env->exit_request)) {
545 env->exit_request = 0;
546 env->exception_index = EXCP_INTERRUPT;
547 cpu_loop_exit();
3fb2ded1 548 }
a73b1fd9 549#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 550 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 551 /* restore flags in standard format */
ecb644f4 552#if defined(TARGET_I386)
a7812ae4 553 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 554 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 555 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 556#elif defined(TARGET_M68K)
557 cpu_m68k_flush_flags(env, env->cc_op);
558 env->cc_op = CC_OP_FLAGS;
559 env->sr = (env->sr & 0xffe0)
560 | env->cc_dest | (env->cc_x << 4);
93fcfe39 561 log_cpu_state(env, 0);
e4533c7a 562#else
a73b1fd9 563 log_cpu_state(env, 0);
e4533c7a 564#endif
3fb2ded1 565 }
a73b1fd9 566#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
d5975363 567 spin_lock(&tb_lock);
8a40a180 568 tb = tb_find_fast();
d5975363
PB		 569 /* Note: we do it here to avoid a gcc bug on Mac OS X when
570 doing it in tb_find_slow */
571 if (tb_invalidated_flag) {
572 /* as some TB could have been invalidated because
573 of memory exceptions while generating the code, we
574 must recompute the hash index here */
575 next_tb = 0;
2e70f6ef 576 tb_invalidated_flag = 0;
d5975363 577 }
f0667e66 578#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 579 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
580 (long)tb->tc_ptr, tb->pc,
581 lookup_symbol(tb->pc));
9d27abd9 582#endif
8a40a180
FB		 583 /* see if we can patch the calling TB. When the TB
584 spans two pages, we cannot safely do a direct
585 jump. */
040f2fb2 586 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 587 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 588 }
d5975363 589 spin_unlock(&tb_lock);
55e8b85e 590
591 /* cpu_interrupt might be called while translating the
592 TB, but before it is linked into a potentially
593 infinite loop and becomes env->current_tb. Avoid
594 starting execution if there is a pending interrupt. */
6113d6d3
PB		 595 if (!unlikely (env->exit_request)) {
596 env->current_tb = tb;
2e70f6ef 597 tc_ptr = tb->tc_ptr;
3fb2ded1 598 /* execute the generated code */
dfe5fff3 599#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 600#undef env
2e70f6ef 601 env = cpu_single_env;
572a9d4a
BS		 602#define env cpu_single_env
603#endif
2e70f6ef
PB		 604 next_tb = tcg_qemu_tb_exec(tc_ptr);
605 env->current_tb = NULL;
606 if ((next_tb & 3) == 2) {
bf20dc07 607 /* Instruction counter expired. */
2e70f6ef
PB		 608 int insns_left;
609 tb = (TranslationBlock *)(long)(next_tb & ~3);
610 /* Restore PC. */
622ed360 611 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 612 insns_left = env->icount_decr.u32;
613 if (env->icount_extra && insns_left >= 0) {
614 /* Refill decrementer and continue execution. */
615 env->icount_extra += insns_left;
616 if (env->icount_extra > 0xffff) {
617 insns_left = 0xffff;
618 } else {
619 insns_left = env->icount_extra;
620 }
621 env->icount_extra -= insns_left;
622 env->icount_decr.u16.low = insns_left;
623 } else {
624 if (insns_left > 0) {
625 /* Execute remaining instructions. */
626 cpu_exec_nocache(insns_left, tb);
627 }
628 env->exception_index = EXCP_INTERRUPT;
629 next_tb = 0;
630 cpu_loop_exit();
631 }
632 }
633 }
4cbf74b6
FB		 634 /* reset soft MMU for next block (it can currently
635 only be set by a memory fault) */
50a518e3 636 } /* for(;;) */
7d13299d 637 }
3fb2ded1
FB		 638 } /* for(;;) */
639
7d13299d 640
e4533c7a 641#if defined(TARGET_I386)
9de5e440 642 /* restore flags in standard format */
a7812ae4 643 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 644#elif defined(TARGET_ARM)
b7bcbe95 645 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 646#elif defined(TARGET_SPARC)
67867308 647#elif defined(TARGET_PPC)
e6e5906b
PB		 648#elif defined(TARGET_M68K)
649 cpu_m68k_flush_flags(env, env->cc_op);
650 env->cc_op = CC_OP_FLAGS;
651 env->sr = (env->sr & 0xffe0)
652 | env->cc_dest | (env->cc_x << 4);
b779e29e 653#elif defined(TARGET_MICROBLAZE)
6af0bf9c 654#elif defined(TARGET_MIPS)
fdf9b3e8 655#elif defined(TARGET_SH4)
eddf68a6 656#elif defined(TARGET_ALPHA)
f1ccf904 657#elif defined(TARGET_CRIS)
10ec5117 658#elif defined(TARGET_S390X)
fdf9b3e8 659 /* XXXXX */
e4533c7a
FB		 660#else
661#error unsupported target CPU
662#endif
1057eaa7
PB		 663
664 /* restore global registers */
24ebf5f3
PB		 665 asm("");
666 env = (void *) saved_env_reg;
1057eaa7 667
6a00d601 668 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 669 cpu_single_env = NULL;
7d13299d
FB		 670 return ret;
671}
6dbad63e 672
fbf9eeb3
FB		 673/* must only be called from the generated code as an exception can be
674 generated */
675void tb_invalidate_page_range(target_ulong start, target_ulong end)
676{
dc5d0b3d
FB		 677 /* XXX: cannot enable it yet because it yields to MMU exception
678 where NIP != read address on PowerPC */
679#if 0
fbf9eeb3
FB		 680 target_ulong phys_addr;
681 phys_addr = get_phys_addr_code(env, start);
682 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 683#endif
fbf9eeb3
FB		 684}
685
1a18c71b 686#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 687
6dbad63e
FB		 688void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
689{
690 CPUX86State *saved_env;
691
692 saved_env = env;
693 env = s;
a412ac57 694 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 695 selector &= 0xffff;
5fafdf24 696 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 697 (selector << 4), 0xffff, 0);
a513fe19 698 } else {
5d97559d 699 helper_load_seg(seg_reg, selector);
a513fe19 700 }
6dbad63e
FB		 701 env = saved_env;
702}
9de5e440 703
6f12a2a6 704void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 705{
706 CPUX86State *saved_env;
707
708 saved_env = env;
709 env = s;
3b46e624 710
6f12a2a6 711 helper_fsave(ptr, data32);
d0a1ffc9
FB		 712
713 env = saved_env;
714}
715
6f12a2a6 716void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 717{
718 CPUX86State *saved_env;
719
720 saved_env = env;
721 env = s;
3b46e624 722
6f12a2a6 723 helper_frstor(ptr, data32);
d0a1ffc9
FB		 724
725 env = saved_env;
726}
727
e4533c7a
FB		 728#endif /* TARGET_I386 */
729
67b915a5
FB		 730#if !defined(CONFIG_SOFTMMU)
731
3fb2ded1 732#if defined(TARGET_I386)
0b5c1ce8
NF		 733#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
734#else
735#define EXCEPTION_ACTION cpu_loop_exit()
736#endif
3fb2ded1 737
b56dad1c 738/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 739 the effective address of the memory exception. 'is_write' is 1 if a
740 write caused the exception and otherwise 0'. 'old_set' is the
741 signal set which should be restored */
2b413144 742static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 743 int is_write, sigset_t *old_set,
bf3e8bf1 744 void *puc)
9de5e440 745{
a513fe19
FB		 746 TranslationBlock *tb;
747 int ret;
68a79315 748
83479e77
FB		 749 if (cpu_single_env)
750 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 751#if defined(DEBUG_SIGNAL)
5fafdf24 752 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 753 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 754#endif
25eb4484 755 /* XXX: locking issue */
53a5960a 756 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 757 return 1;
758 }
fbf9eeb3 759
3fb2ded1 760 /* see if it is an MMU fault */
0b5c1ce8 761 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 762 if (ret < 0)
763 return 0; /* not an MMU fault */
764 if (ret == 0)
765 return 1; /* the MMU fault was handled without causing real CPU fault */
766 /* now we have a real cpu fault */
767 tb = tb_find_pc(pc);
768 if (tb) {
769 /* the PC is inside the translated code. It means that we have
770 a virtual CPU fault */
771 cpu_restore_state(tb, env, pc, puc);
772 }
68016c62 773
68016c62
FB		 774 /* we restore the process signal mask as the sigreturn should
775 do it (XXX: use sigsetjmp) */
776 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 777 EXCEPTION_ACTION;
e6e5906b 778
e6e5906b 779 /* never comes here */
67867308
FB		 780 return 1;
781}
6af0bf9c 782
2b413144
FB		 783#if defined(__i386__)
784
d8ecc0b9
FB		 785#if defined(__APPLE__)
786# include <sys/ucontext.h>
787
788# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
789# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
790# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 791# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 792#elif defined (__NetBSD__)
793# include <ucontext.h>
794
795# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
796# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
797# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
798# define MASK_sig(context) ((context)->uc_sigmask)
799#elif defined (__FreeBSD__) || defined(__DragonFly__)
800# include <ucontext.h>
801
802# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
803# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
804# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
805# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 806#elif defined(__OpenBSD__)
807# define EIP_sig(context) ((context)->sc_eip)
808# define TRAP_sig(context) ((context)->sc_trapno)
809# define ERROR_sig(context) ((context)->sc_err)
810# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 811#else
812# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
813# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
814# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 815# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 816#endif
817
5fafdf24 818int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 819 void *puc)
9de5e440 820{
5a7b542b 821 siginfo_t *info = pinfo;
78cfb07f
JL		 822#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
823 ucontext_t *uc = puc;
824#elif defined(__OpenBSD__)
d39bb24a
BS		 825 struct sigcontext *uc = puc;
826#else
9de5e440 827 struct ucontext *uc = puc;
d39bb24a 828#endif
9de5e440 829 unsigned long pc;
bf3e8bf1 830 int trapno;
97eb5b14 831
d691f669
FB		 832#ifndef REG_EIP
833/* for glibc 2.1 */
fd6ce8f6
FB		 834#define REG_EIP EIP
835#define REG_ERR ERR
836#define REG_TRAPNO TRAPNO
d691f669 837#endif
d8ecc0b9
FB		 838 pc = EIP_sig(uc);
839 trapno = TRAP_sig(uc);
ec6338ba
FB		 840 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
841 trapno == 0xe ?
842 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 843 &MASK_sig(uc), puc);
2b413144
FB		 844}
845
bc51c5c9
FB		 846#elif defined(__x86_64__)
847
b3efe5c8 848#ifdef __NetBSD__
d397abbd
BS		 849#define PC_sig(context) _UC_MACHINE_PC(context)
850#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
851#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
852#define MASK_sig(context) ((context)->uc_sigmask)
853#elif defined(__OpenBSD__)
854#define PC_sig(context) ((context)->sc_rip)
855#define TRAP_sig(context) ((context)->sc_trapno)
856#define ERROR_sig(context) ((context)->sc_err)
857#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 858#elif defined (__FreeBSD__) || defined(__DragonFly__)
859#include <ucontext.h>
860
861#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
862#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
863#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
864#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 865#else
d397abbd
BS		 866#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
867#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
868#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
869#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 870#endif
871
5a7b542b 872int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 873 void *puc)
874{
5a7b542b 875 siginfo_t *info = pinfo;
bc51c5c9 876 unsigned long pc;
78cfb07f 877#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 878 ucontext_t *uc = puc;
d397abbd
BS		 879#elif defined(__OpenBSD__)
880 struct sigcontext *uc = puc;
b3efe5c8
BS		 881#else
882 struct ucontext *uc = puc;
883#endif
bc51c5c9 884
d397abbd 885 pc = PC_sig(uc);
5fafdf24 886 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 887 TRAP_sig(uc) == 0xe ?
888 (ERROR_sig(uc) >> 1) & 1 : 0,
889 &MASK_sig(uc), puc);
bc51c5c9
FB		 890}
891
e58ffeb3 892#elif defined(_ARCH_PPC)
2b413144 893
83fb7adf
FB		 894/***********************************************************************
895 * signal context platform-specific definitions
896 * From Wine
897 */
898#ifdef linux
899/* All Registers access - only for local access */
900# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
901/* Gpr Registers access */
902# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
903# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
904# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
905# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
906# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
907# define LR_sig(context) REG_sig(link, context) /* Link register */
908# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
909/* Float Registers access */
910# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
911# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
912/* Exception Registers access */
913# define DAR_sig(context) REG_sig(dar, context)
914# define DSISR_sig(context) REG_sig(dsisr, context)
915# define TRAP_sig(context) REG_sig(trap, context)
916#endif /* linux */
917
58d9b1e0
JL		 918#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
919#include <ucontext.h>
920# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
921# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
922# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
923# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
924# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
925# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
926/* Exception Registers access */
927# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
928# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
929# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
930#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
931
83fb7adf
FB		 932#ifdef __APPLE__
933# include <sys/ucontext.h>
934typedef struct ucontext SIGCONTEXT;
935/* All Registers access - only for local access */
936# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
937# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
938# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
939# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
940/* Gpr Registers access */
941# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
942# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
943# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
944# define CTR_sig(context) REG_sig(ctr, context)
945# define XER_sig(context) REG_sig(xer, context) /* Link register */
946# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
947# define CR_sig(context) REG_sig(cr, context) /* Condition register */
948/* Float Registers access */
949# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
950# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
951/* Exception Registers access */
952# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
953# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
954# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
955#endif /* __APPLE__ */
956
5fafdf24 957int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 958 void *puc)
2b413144 959{
5a7b542b 960 siginfo_t *info = pinfo;
58d9b1e0
JL		 961#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
962 ucontext_t *uc = puc;
963#else
25eb4484 964 struct ucontext *uc = puc;
58d9b1e0 965#endif
25eb4484 966 unsigned long pc;
25eb4484
FB		 967 int is_write;
968
83fb7adf 969 pc = IAR_sig(uc);
25eb4484
FB		 970 is_write = 0;
971#if 0
972 /* ppc 4xx case */
83fb7adf 973 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 974 is_write = 1;
975#else
83fb7adf 976 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 977 is_write = 1;
978#endif
5fafdf24 979 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 980 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 981}
982
2f87c607
FB		 983#elif defined(__alpha__)
984
5fafdf24 985int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 986 void *puc)
987{
5a7b542b 988 siginfo_t *info = pinfo;
2f87c607
FB		 989 struct ucontext *uc = puc;
990 uint32_t *pc = uc->uc_mcontext.sc_pc;
991 uint32_t insn = *pc;
992 int is_write = 0;
993
8c6939c0 994 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 995 switch (insn >> 26) {
996 case 0x0d: // stw
997 case 0x0e: // stb
998 case 0x0f: // stq_u
999 case 0x24: // stf
1000 case 0x25: // stg
1001 case 0x26: // sts
1002 case 0x27: // stt
1003 case 0x2c: // stl
1004 case 0x2d: // stq
1005 case 0x2e: // stl_c
1006 case 0x2f: // stq_c
1007 is_write = 1;
1008 }
1009
5fafdf24 1010 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1011 is_write, &uc->uc_sigmask, puc);
2f87c607 1012}
8c6939c0
FB		 1013#elif defined(__sparc__)
1014
5fafdf24 1015int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1016 void *puc)
8c6939c0 1017{
5a7b542b 1018 siginfo_t *info = pinfo;
8c6939c0
FB		 1019 int is_write;
1020 uint32_t insn;
dfe5fff3 1021#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1022 uint32_t *regs = (uint32_t *)(info + 1);
1023 void *sigmask = (regs + 20);
8c6939c0 1024 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1025 unsigned long pc = regs[1];
1026#else
84778508 1027#ifdef __linux__
c9e1e2b0
BS		 1028 struct sigcontext *sc = puc;
1029 unsigned long pc = sc->sigc_regs.tpc;
1030 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1031#elif defined(__OpenBSD__)
1032 struct sigcontext *uc = puc;
1033 unsigned long pc = uc->sc_pc;
1034 void *sigmask = (void *)(long)uc->sc_mask;
1035#endif
c9e1e2b0
BS		 1036#endif
1037
8c6939c0
FB		 1038 /* XXX: need kernel patch to get write flag faster */
1039 is_write = 0;
1040 insn = *(uint32_t *)pc;
1041 if ((insn >> 30) == 3) {
1042 switch((insn >> 19) & 0x3f) {
1043 case 0x05: // stb
d877fa5a 1044 case 0x15: // stba
8c6939c0 1045 case 0x06: // sth
d877fa5a 1046 case 0x16: // stha
8c6939c0 1047 case 0x04: // st
d877fa5a 1048 case 0x14: // sta
8c6939c0 1049 case 0x07: // std
d877fa5a
BS		 1050 case 0x17: // stda
1051 case 0x0e: // stx
1052 case 0x1e: // stxa
8c6939c0 1053 case 0x24: // stf
d877fa5a 1054 case 0x34: // stfa
8c6939c0 1055 case 0x27: // stdf
d877fa5a
BS		 1056 case 0x37: // stdfa
1057 case 0x26: // stqf
1058 case 0x36: // stqfa
8c6939c0 1059 case 0x25: // stfsr
d877fa5a
BS		 1060 case 0x3c: // casa
1061 case 0x3e: // casxa
8c6939c0
FB		 1062 is_write = 1;
1063 break;
1064 }
1065 }
5fafdf24 1066 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1067 is_write, sigmask, NULL);
8c6939c0
FB		 1068}
1069
1070#elif defined(__arm__)
1071
5fafdf24 1072int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1073 void *puc)
8c6939c0 1074{
5a7b542b 1075 siginfo_t *info = pinfo;
8c6939c0
FB		 1076 struct ucontext *uc = puc;
1077 unsigned long pc;
1078 int is_write;
3b46e624 1079
48bbf11b 1080#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1081 pc = uc->uc_mcontext.gregs[R15];
1082#else
4eee57f5 1083 pc = uc->uc_mcontext.arm_pc;
5c49b363 1084#endif
8c6939c0
FB		 1085 /* XXX: compute is_write */
1086 is_write = 0;
5fafdf24 1087 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1088 is_write,
f3a9676a 1089 &uc->uc_sigmask, puc);
8c6939c0
FB		 1090}
1091
38e584a0
FB		 1092#elif defined(__mc68000)
1093
5fafdf24 1094int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1095 void *puc)
1096{
5a7b542b 1097 siginfo_t *info = pinfo;
38e584a0
FB		 1098 struct ucontext *uc = puc;
1099 unsigned long pc;
1100 int is_write;
3b46e624 1101
38e584a0
FB		 1102 pc = uc->uc_mcontext.gregs[16];
1103 /* XXX: compute is_write */
1104 is_write = 0;
5fafdf24 1105 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1106 is_write,
bf3e8bf1 1107 &uc->uc_sigmask, puc);
38e584a0
FB		 1108}
1109
b8076a74
FB		 1110#elif defined(__ia64)
1111
1112#ifndef __ISR_VALID
1113 /* This ought to be in <bits/siginfo.h>... */
1114# define __ISR_VALID 1
b8076a74
FB		 1115#endif
1116
5a7b542b 1117int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1118{
5a7b542b 1119 siginfo_t *info = pinfo;
b8076a74
FB		 1120 struct ucontext *uc = puc;
1121 unsigned long ip;
1122 int is_write = 0;
1123
1124 ip = uc->uc_mcontext.sc_ip;
1125 switch (host_signum) {
1126 case SIGILL:
1127 case SIGFPE:
1128 case SIGSEGV:
1129 case SIGBUS:
1130 case SIGTRAP:
fd4a43e4 1131 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1132 /* ISR.W (write-access) is bit 33: */
1133 is_write = (info->si_isr >> 33) & 1;
1134 break;
1135
1136 default:
1137 break;
1138 }
1139 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1140 is_write,
60e99246 1141 (sigset_t *)&uc->uc_sigmask, puc);
b8076a74
FB		 1142}
1143
90cb9493
FB		 1144#elif defined(__s390__)
1145
5fafdf24 1146int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1147 void *puc)
1148{
5a7b542b 1149 siginfo_t *info = pinfo;
90cb9493
FB		 1150 struct ucontext *uc = puc;
1151 unsigned long pc;
1152 int is_write;
3b46e624 1153
90cb9493
FB		 1154 pc = uc->uc_mcontext.psw.addr;
1155 /* XXX: compute is_write */
1156 is_write = 0;
5fafdf24 1157 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1158 is_write, &uc->uc_sigmask, puc);
1159}
1160
1161#elif defined(__mips__)
1162
5fafdf24 1163int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1164 void *puc)
1165{
9617efe8 1166 siginfo_t *info = pinfo;
c4b89d18
TS		 1167 struct ucontext *uc = puc;
1168 greg_t pc = uc->uc_mcontext.pc;
1169 int is_write;
3b46e624 1170
c4b89d18
TS		 1171 /* XXX: compute is_write */
1172 is_write = 0;
5fafdf24 1173 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1174 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1175}
1176
f54b3f92
AJ		 1177#elif defined(__hppa__)
1178
1179int cpu_signal_handler(int host_signum, void *pinfo,
1180 void *puc)
1181{
1182 struct siginfo *info = pinfo;
1183 struct ucontext *uc = puc;
f57040be
RH		 1184 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
1185 uint32_t insn = *(uint32_t *)pc;
1186 int is_write = 0;
1187
1188 /* XXX: need kernel patch to get write flag faster. */
1189 switch (insn >> 26) {
1190 case 0x1a: /* STW */
1191 case 0x19: /* STH */
1192 case 0x18: /* STB */
1193 case 0x1b: /* STWM */
1194 is_write = 1;
1195 break;
1196
1197 case 0x09: /* CSTWX, FSTWX, FSTWS */
1198 case 0x0b: /* CSTDX, FSTDX, FSTDS */
1199 /* Distinguish from coprocessor load ... */
1200 is_write = (insn >> 9) & 1;
1201 break;
1202
1203 case 0x03:
1204 switch ((insn >> 6) & 15) {
1205 case 0xa: /* STWS */
1206 case 0x9: /* STHS */
1207 case 0x8: /* STBS */
1208 case 0xe: /* STWAS */
1209 case 0xc: /* STBYS */
1210 is_write = 1;
1211 }
1212 break;
1213 }
f54b3f92 1214
f54b3f92 1215 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
f57040be 1216 is_write, &uc->uc_sigmask, puc);
f54b3f92
AJ		 1217}
1218
9de5e440 1219#else
2b413144 1220
3fb2ded1 1221#error host CPU specific signal handler needed
2b413144 1222
9de5e440 1223#endif
67b915a5
FB		 1224
1225#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing