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7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
7d13299d 24
fbf9eeb3
FB		 25#if !defined(CONFIG_SOFTMMU)
26#undef EAX
27#undef ECX
28#undef EDX
29#undef EBX
30#undef ESP
31#undef EBP
32#undef ESI
33#undef EDI
34#undef EIP
35#include <signal.h>
84778508 36#ifdef __linux__
fbf9eeb3
FB		 37#include <sys/ucontext.h>
38#endif
84778508 39#endif
fbf9eeb3 40
dfe5fff3 41#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 42// Work around ugly bugs in glibc that mangle global register contents
43#undef env
44#define env cpu_single_env
45#endif
46
36bdbe54
FB		 47int tb_invalidated_flag;
48
f0667e66 49//#define CONFIG_DEBUG_EXEC
9de5e440 50//#define DEBUG_SIGNAL
7d13299d 51
6a4955a8
AL		 52int qemu_cpu_has_work(CPUState *env)
53{
54 return cpu_has_work(env);
55}
56
e4533c7a
FB		 57void cpu_loop_exit(void)
58{
59 longjmp(env->jmp_env, 1);
60}
bfed01fc 61
fbf9eeb3
FB		 62/* exit the current TB from a signal handler. The host registers are
63 restored in a state compatible with the CPU emulator
64 */
5fafdf24 65void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 66{
67#if !defined(CONFIG_SOFTMMU)
84778508 68#ifdef __linux__
fbf9eeb3 69 struct ucontext *uc = puc;
84778508
BS		 70#elif defined(__OpenBSD__)
71 struct sigcontext *uc = puc;
72#endif
fbf9eeb3
FB		 73#endif
74
75 env = env1;
76
77 /* XXX: restore cpu registers saved in host registers */
78
79#if !defined(CONFIG_SOFTMMU)
80 if (puc) {
81 /* XXX: use siglongjmp ? */
84778508 82#ifdef __linux__
fbf9eeb3 83 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
84778508
BS		 84#elif defined(__OpenBSD__)
85 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
86#endif
fbf9eeb3
FB		 87 }
88#endif
9a3ea654 89 env->exception_index = -1;
fbf9eeb3
FB		 90 longjmp(env->jmp_env, 1);
91}
92
2e70f6ef
PB		 93/* Execute the code without caching the generated code. An interpreter
94 could be used if available. */
95static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
96{
97 unsigned long next_tb;
98 TranslationBlock *tb;
99
100 /* Should never happen.
101 We only end up here when an existing TB is too long. */
102 if (max_cycles > CF_COUNT_MASK)
103 max_cycles = CF_COUNT_MASK;
104
105 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
106 max_cycles);
107 env->current_tb = tb;
108 /* execute the generated code */
109 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
110
111 if ((next_tb & 3) == 2) {
112 /* Restore PC. This may happen if async event occurs before
113 the TB starts executing. */
622ed360 114 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 115 }
116 tb_phys_invalidate(tb, -1);
117 tb_free(tb);
118}
119
8a40a180
FB		 120static TranslationBlock *tb_find_slow(target_ulong pc,
121 target_ulong cs_base,
c068688b 122 uint64_t flags)
8a40a180
FB		 123{
124 TranslationBlock *tb, **ptb1;
8a40a180
FB		 125 unsigned int h;
126 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
3b46e624 127
8a40a180 128 tb_invalidated_flag = 0;
3b46e624 129
8a40a180
FB		 130 /* find translated block using physical mappings */
131 phys_pc = get_phys_addr_code(env, pc);
132 phys_page1 = phys_pc & TARGET_PAGE_MASK;
133 phys_page2 = -1;
134 h = tb_phys_hash_func(phys_pc);
135 ptb1 = &tb_phys_hash[h];
136 for(;;) {
137 tb = *ptb1;
138 if (!tb)
139 goto not_found;
5fafdf24 140 if (tb->pc == pc &&
8a40a180 141 tb->page_addr[0] == phys_page1 &&
5fafdf24 142 tb->cs_base == cs_base &&
8a40a180
FB		 143 tb->flags == flags) {
144 /* check next page if needed */
145 if (tb->page_addr[1] != -1) {
5fafdf24 146 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180
FB		 147 TARGET_PAGE_SIZE;
148 phys_page2 = get_phys_addr_code(env, virt_page2);
149 if (tb->page_addr[1] == phys_page2)
150 goto found;
151 } else {
152 goto found;
153 }
154 }
155 ptb1 = &tb->phys_hash_next;
156 }
157 not_found:
2e70f6ef
PB		 158 /* if no translated code available, then translate it now */
159 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 160
8a40a180 161 found:
8a40a180
FB		 162 /* we add the TB in the virtual pc hash table */
163 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 164 return tb;
165}
166
167static inline TranslationBlock *tb_find_fast(void)
168{
169 TranslationBlock *tb;
170 target_ulong cs_base, pc;
6b917547 171 int flags;
8a40a180
FB		 172
173 /* we record a subset of the CPU state. It will
174 always be the same before a given translated block
175 is executed. */
6b917547 176 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 177 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 178 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
179 tb->flags != flags)) {
8a40a180
FB		 180 tb = tb_find_slow(pc, cs_base, flags);
181 }
182 return tb;
183}
184
dde2367e
AL		 185static CPUDebugExcpHandler *debug_excp_handler;
186
187CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
188{
189 CPUDebugExcpHandler *old_handler = debug_excp_handler;
190
191 debug_excp_handler = handler;
192 return old_handler;
193}
194
6e140f28
AL		 195static void cpu_handle_debug_exception(CPUState *env)
196{
197 CPUWatchpoint *wp;
198
199 if (!env->watchpoint_hit)
72cf2d4f 200 QTAILQ_FOREACH(wp, &env->watchpoints, entry)
6e140f28 201 wp->flags &= ~BP_WATCHPOINT_HIT;
dde2367e
AL		 202
203 if (debug_excp_handler)
204 debug_excp_handler(env);
6e140f28
AL		 205}
206
7d13299d
FB		 207/* main execution loop */
208
e4533c7a 209int cpu_exec(CPUState *env1)
7d13299d 210{
1057eaa7
PB		 211#define DECLARE_HOST_REGS 1
212#include "hostregs_helper.h"
8a40a180 213 int ret, interrupt_request;
8a40a180 214 TranslationBlock *tb;
c27004ec 215 uint8_t *tc_ptr;
d5975363 216 unsigned long next_tb;
8c6939c0 217
bfed01fc
TS		 218 if (cpu_halted(env1) == EXCP_HALTED)
219 return EXCP_HALTED;
5a1e3cfc 220
5fafdf24 221 cpu_single_env = env1;
6a00d601 222
7d13299d 223 /* first we save global registers */
1057eaa7
PB		 224#define SAVE_HOST_REGS 1
225#include "hostregs_helper.h"
c27004ec 226 env = env1;
e4533c7a 227
ecb644f4 228#if defined(TARGET_I386)
9de5e440 229 /* put eflags in CPU temporary format */
fc2b4c48
FB		 230 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
231 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 232 CC_OP = CC_OP_EFLAGS;
fc2b4c48 233 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 234#elif defined(TARGET_SPARC)
e6e5906b
PB		 235#elif defined(TARGET_M68K)
236 env->cc_op = CC_OP_FLAGS;
237 env->cc_dest = env->sr & 0xf;
238 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 239#elif defined(TARGET_ALPHA)
240#elif defined(TARGET_ARM)
241#elif defined(TARGET_PPC)
b779e29e 242#elif defined(TARGET_MICROBLAZE)
6af0bf9c 243#elif defined(TARGET_MIPS)
fdf9b3e8 244#elif defined(TARGET_SH4)
f1ccf904 245#elif defined(TARGET_CRIS)
10ec5117 246#elif defined(TARGET_S390X)
fdf9b3e8 247 /* XXXXX */
e4533c7a
FB		 248#else
249#error unsupported target CPU
250#endif
3fb2ded1 251 env->exception_index = -1;
9d27abd9 252
7d13299d 253 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 254 for(;;) {
255 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 256#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 257#undef env
258 env = cpu_single_env;
259#define env cpu_single_env
260#endif
ee8b7021 261 env->current_tb = NULL;
3fb2ded1
FB		 262 /* if an exception is pending, we execute it here */
263 if (env->exception_index >= 0) {
264 if (env->exception_index >= EXCP_INTERRUPT) {
265 /* exit request from the cpu execution loop */
266 ret = env->exception_index;
6e140f28
AL		 267 if (ret == EXCP_DEBUG)
268 cpu_handle_debug_exception(env);
3fb2ded1 269 break;
72d239ed
AJ		 270 } else {
271#if defined(CONFIG_USER_ONLY)
3fb2ded1 272 /* if user mode only, we simulate a fake exception
9f083493 273 which will be handled outside the cpu execution
3fb2ded1 274 loop */
83479e77 275#if defined(TARGET_I386)
5fafdf24
TS		 276 do_interrupt_user(env->exception_index,
277 env->exception_is_int,
278 env->error_code,
3fb2ded1 279 env->exception_next_eip);
eba01623
FB		 280 /* successfully delivered */
281 env->old_exception = -1;
83479e77 282#endif
3fb2ded1
FB		 283 ret = env->exception_index;
284 break;
72d239ed 285#else
83479e77 286#if defined(TARGET_I386)
3fb2ded1
FB		 287 /* simulate a real cpu exception. On i386, it can
288 trigger new exceptions, but we do not handle
289 double or triple faults yet. */
5fafdf24
TS		 290 do_interrupt(env->exception_index,
291 env->exception_is_int,
292 env->error_code,
d05e66d2 293 env->exception_next_eip, 0);
678dde13
TS		 294 /* successfully delivered */
295 env->old_exception = -1;
ce09776b
FB		 296#elif defined(TARGET_PPC)
297 do_interrupt(env);
b779e29e
EI		 298#elif defined(TARGET_MICROBLAZE)
299 do_interrupt(env);
6af0bf9c
FB		 300#elif defined(TARGET_MIPS)
301 do_interrupt(env);
e95c8d51 302#elif defined(TARGET_SPARC)
f2bc7e7f 303 do_interrupt(env);
b5ff1b31
FB		 304#elif defined(TARGET_ARM)
305 do_interrupt(env);
fdf9b3e8
FB		 306#elif defined(TARGET_SH4)
307 do_interrupt(env);
eddf68a6
JM		 308#elif defined(TARGET_ALPHA)
309 do_interrupt(env);
f1ccf904
TS		 310#elif defined(TARGET_CRIS)
311 do_interrupt(env);
0633879f
PB		 312#elif defined(TARGET_M68K)
313 do_interrupt(0);
72d239ed 314#endif
83479e77 315#endif
3fb2ded1
FB		 316 }
317 env->exception_index = -1;
5fafdf24 318 }
9df217a3 319
7ba1e619 320 if (kvm_enabled()) {
becfc390
AL		 321 kvm_cpu_exec(env);
322 longjmp(env->jmp_env, 1);
7ba1e619
AL		 323 }
324
b5fc09ae 325 next_tb = 0; /* force lookup of first TB */
3fb2ded1 326 for(;;) {
68a79315 327 interrupt_request = env->interrupt_request;
e1638bd8 328 if (unlikely(interrupt_request)) {
329 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
330 /* Mask out external interrupts for this step. */
331 interrupt_request &= ~(CPU_INTERRUPT_HARD |
332 CPU_INTERRUPT_FIQ |
333 CPU_INTERRUPT_SMI |
334 CPU_INTERRUPT_NMI);
335 }
6658ffb8
PB		 336 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
337 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
338 env->exception_index = EXCP_DEBUG;
339 cpu_loop_exit();
340 }
a90b7318 341#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e
EI		 342 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
343 defined(TARGET_MICROBLAZE)
a90b7318
AZ		 344 if (interrupt_request & CPU_INTERRUPT_HALT) {
345 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
346 env->halted = 1;
347 env->exception_index = EXCP_HLT;
348 cpu_loop_exit();
349 }
350#endif
68a79315 351#if defined(TARGET_I386)
b09ea7d5
GN		 352 if (interrupt_request & CPU_INTERRUPT_INIT) {
353 svm_check_intercept(SVM_EXIT_INIT);
354 do_cpu_init(env);
355 env->exception_index = EXCP_HALTED;
356 cpu_loop_exit();
357 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
358 do_cpu_sipi(env);
359 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 360 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
361 !(env->hflags & HF_SMM_MASK)) {
362 svm_check_intercept(SVM_EXIT_SMI);
363 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
364 do_smm_enter();
365 next_tb = 0;
366 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
367 !(env->hflags2 & HF2_NMI_MASK)) {
368 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
369 env->hflags2 |= HF2_NMI_MASK;
370 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
371 next_tb = 0;
79c4f6b0
HY		 372 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
373 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
374 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
375 next_tb = 0;
db620f46
FB		 376 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
377 (((env->hflags2 & HF2_VINTR_MASK) &&
378 (env->hflags2 & HF2_HIF_MASK)) ||
379 (!(env->hflags2 & HF2_VINTR_MASK) &&
380 (env->eflags & IF_MASK &&
381 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
382 int intno;
383 svm_check_intercept(SVM_EXIT_INTR);
384 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
385 intno = cpu_get_pic_interrupt(env);
93fcfe39 386 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 387#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 388#undef env
389 env = cpu_single_env;
390#define env cpu_single_env
391#endif
db620f46
FB		 392 do_interrupt(intno, 0, 0, 0, 1);
393 /* ensure that no TB jump will be modified as
394 the program flow was changed */
395 next_tb = 0;
0573fbfc 396#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 397 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
398 (env->eflags & IF_MASK) &&
399 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
400 int intno;
401 /* FIXME: this should respect TPR */
402 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 403 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 404 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 405 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 406 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 407 next_tb = 0;
907a5b26 408#endif
db620f46 409 }
68a79315 410 }
ce09776b 411#elif defined(TARGET_PPC)
9fddaa0c
FB		 412#if 0
413 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 414 cpu_reset(env);
9fddaa0c
FB		 415 }
416#endif
47103572 417 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 418 ppc_hw_interrupt(env);
419 if (env->pending_interrupts == 0)
420 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 421 next_tb = 0;
ce09776b 422 }
b779e29e
EI		 423#elif defined(TARGET_MICROBLAZE)
424 if ((interrupt_request & CPU_INTERRUPT_HARD)
425 && (env->sregs[SR_MSR] & MSR_IE)
426 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
427 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
428 env->exception_index = EXCP_IRQ;
429 do_interrupt(env);
430 next_tb = 0;
431 }
6af0bf9c
FB		 432#elif defined(TARGET_MIPS)
433 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 434 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 435 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 436 !(env->CP0_Status & (1 << CP0St_EXL)) &&
437 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 438 !(env->hflags & MIPS_HFLAG_DM)) {
439 /* Raise it */
440 env->exception_index = EXCP_EXT_INTERRUPT;
441 env->error_code = 0;
442 do_interrupt(env);
b5fc09ae 443 next_tb = 0;
6af0bf9c 444 }
e95c8d51 445#elif defined(TARGET_SPARC)
d532b26c
IK		 446 if (interrupt_request & CPU_INTERRUPT_HARD) {
447 if (cpu_interrupts_enabled(env) &&
448 env->interrupt_index > 0) {
449 int pil = env->interrupt_index & 0xf;
450 int type = env->interrupt_index & 0xf0;
451
452 if (((type == TT_EXTINT) &&
453 cpu_pil_allowed(env, pil)) ||
454 type != TT_EXTINT) {
455 env->exception_index = env->interrupt_index;
456 do_interrupt(env);
457 next_tb = 0;
458 }
459 }
e95c8d51
FB		 460 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
461 //do_interrupt(0, 0, 0, 0, 0);
462 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 463 }
b5ff1b31
FB		 464#elif defined(TARGET_ARM)
465 if (interrupt_request & CPU_INTERRUPT_FIQ
466 && !(env->uncached_cpsr & CPSR_F)) {
467 env->exception_index = EXCP_FIQ;
468 do_interrupt(env);
b5fc09ae 469 next_tb = 0;
b5ff1b31 470 }
9ee6e8bb
PB		 471 /* ARMv7-M interrupt return works by loading a magic value
472 into the PC. On real hardware the load causes the
473 return to occur. The qemu implementation performs the
474 jump normally, then does the exception return when the
475 CPU tries to execute code at the magic address.
476 This will cause the magic PC value to be pushed to
477 the stack if an interrupt occured at the wrong time.
478 We avoid this by disabling interrupts when
479 pc contains a magic address. */
b5ff1b31 480 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 481 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
482 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 483 env->exception_index = EXCP_IRQ;
484 do_interrupt(env);
b5fc09ae 485 next_tb = 0;
b5ff1b31 486 }
fdf9b3e8 487#elif defined(TARGET_SH4)
e96e2044
TS		 488 if (interrupt_request & CPU_INTERRUPT_HARD) {
489 do_interrupt(env);
b5fc09ae 490 next_tb = 0;
e96e2044 491 }
eddf68a6
JM		 492#elif defined(TARGET_ALPHA)
493 if (interrupt_request & CPU_INTERRUPT_HARD) {
494 do_interrupt(env);
b5fc09ae 495 next_tb = 0;
eddf68a6 496 }
f1ccf904 497#elif defined(TARGET_CRIS)
1b1a38b0
EI		 498 if (interrupt_request & CPU_INTERRUPT_HARD
499 && (env->pregs[PR_CCS] & I_FLAG)) {
500 env->exception_index = EXCP_IRQ;
501 do_interrupt(env);
502 next_tb = 0;
503 }
504 if (interrupt_request & CPU_INTERRUPT_NMI
505 && (env->pregs[PR_CCS] & M_FLAG)) {
506 env->exception_index = EXCP_NMI;
f1ccf904 507 do_interrupt(env);
b5fc09ae 508 next_tb = 0;
f1ccf904 509 }
0633879f
PB		 510#elif defined(TARGET_M68K)
511 if (interrupt_request & CPU_INTERRUPT_HARD
512 && ((env->sr & SR_I) >> SR_I_SHIFT)
513 < env->pending_level) {
514 /* Real hardware gets the interrupt vector via an
515 IACK cycle at this point. Current emulated
516 hardware doesn't rely on this, so we
517 provide/save the vector when the interrupt is
518 first signalled. */
519 env->exception_index = env->pending_vector;
520 do_interrupt(1);
b5fc09ae 521 next_tb = 0;
0633879f 522 }
68a79315 523#endif
9d05095e
FB		 524 /* Don't use the cached interupt_request value,
525 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 526 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 527 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
528 /* ensure that no TB jump will be modified as
529 the program flow was changed */
b5fc09ae 530 next_tb = 0;
bf3e8bf1 531 }
be214e6c
AJ		 532 }
533 if (unlikely(env->exit_request)) {
534 env->exit_request = 0;
535 env->exception_index = EXCP_INTERRUPT;
536 cpu_loop_exit();
3fb2ded1 537 }
f0667e66 538#ifdef CONFIG_DEBUG_EXEC
8fec2b8c 539 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 540 /* restore flags in standard format */
ecb644f4 541#if defined(TARGET_I386)
a7812ae4 542 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 543 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 544 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 545#elif defined(TARGET_ARM)
93fcfe39 546 log_cpu_state(env, 0);
93ac68bc 547#elif defined(TARGET_SPARC)
93fcfe39 548 log_cpu_state(env, 0);
67867308 549#elif defined(TARGET_PPC)
93fcfe39 550 log_cpu_state(env, 0);
e6e5906b
PB		 551#elif defined(TARGET_M68K)
552 cpu_m68k_flush_flags(env, env->cc_op);
553 env->cc_op = CC_OP_FLAGS;
554 env->sr = (env->sr & 0xffe0)
555 | env->cc_dest | (env->cc_x << 4);
93fcfe39 556 log_cpu_state(env, 0);
b779e29e
EI		 557#elif defined(TARGET_MICROBLAZE)
558 log_cpu_state(env, 0);
6af0bf9c 559#elif defined(TARGET_MIPS)
93fcfe39 560 log_cpu_state(env, 0);
fdf9b3e8 561#elif defined(TARGET_SH4)
93fcfe39 562 log_cpu_state(env, 0);
eddf68a6 563#elif defined(TARGET_ALPHA)
93fcfe39 564 log_cpu_state(env, 0);
f1ccf904 565#elif defined(TARGET_CRIS)
93fcfe39 566 log_cpu_state(env, 0);
e4533c7a 567#else
5fafdf24 568#error unsupported target CPU
e4533c7a 569#endif
3fb2ded1 570 }
7d13299d 571#endif
d5975363 572 spin_lock(&tb_lock);
8a40a180 573 tb = tb_find_fast();
d5975363
PB		 574 /* Note: we do it here to avoid a gcc bug on Mac OS X when
575 doing it in tb_find_slow */
576 if (tb_invalidated_flag) {
577 /* as some TB could have been invalidated because
578 of memory exceptions while generating the code, we
579 must recompute the hash index here */
580 next_tb = 0;
2e70f6ef 581 tb_invalidated_flag = 0;
d5975363 582 }
f0667e66 583#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 584 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
585 (long)tb->tc_ptr, tb->pc,
586 lookup_symbol(tb->pc));
9d27abd9 587#endif
8a40a180
FB		 588 /* see if we can patch the calling TB. When the TB
589 spans two pages, we cannot safely do a direct
590 jump. */
040f2fb2 591 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 592 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 593 }
d5975363 594 spin_unlock(&tb_lock);
83479e77 595 env->current_tb = tb;
55e8b85e 596
597 /* cpu_interrupt might be called while translating the
598 TB, but before it is linked into a potentially
599 infinite loop and becomes env->current_tb. Avoid
600 starting execution if there is a pending interrupt. */
be214e6c 601 if (unlikely (env->exit_request))
55e8b85e 602 env->current_tb = NULL;
603
2e70f6ef
PB		 604 while (env->current_tb) {
605 tc_ptr = tb->tc_ptr;
3fb2ded1 606 /* execute the generated code */
dfe5fff3 607#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 608#undef env
2e70f6ef 609 env = cpu_single_env;
572a9d4a
BS		 610#define env cpu_single_env
611#endif
2e70f6ef
PB		 612 next_tb = tcg_qemu_tb_exec(tc_ptr);
613 env->current_tb = NULL;
614 if ((next_tb & 3) == 2) {
bf20dc07 615 /* Instruction counter expired. */
2e70f6ef
PB		 616 int insns_left;
617 tb = (TranslationBlock *)(long)(next_tb & ~3);
618 /* Restore PC. */
622ed360 619 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 620 insns_left = env->icount_decr.u32;
621 if (env->icount_extra && insns_left >= 0) {
622 /* Refill decrementer and continue execution. */
623 env->icount_extra += insns_left;
624 if (env->icount_extra > 0xffff) {
625 insns_left = 0xffff;
626 } else {
627 insns_left = env->icount_extra;
628 }
629 env->icount_extra -= insns_left;
630 env->icount_decr.u16.low = insns_left;
631 } else {
632 if (insns_left > 0) {
633 /* Execute remaining instructions. */
634 cpu_exec_nocache(insns_left, tb);
635 }
636 env->exception_index = EXCP_INTERRUPT;
637 next_tb = 0;
638 cpu_loop_exit();
639 }
640 }
641 }
4cbf74b6
FB		 642 /* reset soft MMU for next block (it can currently
643 only be set by a memory fault) */
50a518e3 644 } /* for(;;) */
7d13299d 645 }
3fb2ded1
FB		 646 } /* for(;;) */
647
7d13299d 648
e4533c7a 649#if defined(TARGET_I386)
9de5e440 650 /* restore flags in standard format */
a7812ae4 651 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 652#elif defined(TARGET_ARM)
b7bcbe95 653 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 654#elif defined(TARGET_SPARC)
67867308 655#elif defined(TARGET_PPC)
e6e5906b
PB		 656#elif defined(TARGET_M68K)
657 cpu_m68k_flush_flags(env, env->cc_op);
658 env->cc_op = CC_OP_FLAGS;
659 env->sr = (env->sr & 0xffe0)
660 | env->cc_dest | (env->cc_x << 4);
b779e29e 661#elif defined(TARGET_MICROBLAZE)
6af0bf9c 662#elif defined(TARGET_MIPS)
fdf9b3e8 663#elif defined(TARGET_SH4)
eddf68a6 664#elif defined(TARGET_ALPHA)
f1ccf904 665#elif defined(TARGET_CRIS)
10ec5117 666#elif defined(TARGET_S390X)
fdf9b3e8 667 /* XXXXX */
e4533c7a
FB		 668#else
669#error unsupported target CPU
670#endif
1057eaa7
PB		 671
672 /* restore global registers */
1057eaa7
PB		 673#include "hostregs_helper.h"
674
6a00d601 675 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 676 cpu_single_env = NULL;
7d13299d
FB		 677 return ret;
678}
6dbad63e 679
fbf9eeb3
FB		 680/* must only be called from the generated code as an exception can be
681 generated */
682void tb_invalidate_page_range(target_ulong start, target_ulong end)
683{
dc5d0b3d
FB		 684 /* XXX: cannot enable it yet because it yields to MMU exception
685 where NIP != read address on PowerPC */
686#if 0
fbf9eeb3
FB		 687 target_ulong phys_addr;
688 phys_addr = get_phys_addr_code(env, start);
689 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 690#endif
fbf9eeb3
FB		 691}
692
1a18c71b 693#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 694
6dbad63e
FB		 695void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
696{
697 CPUX86State *saved_env;
698
699 saved_env = env;
700 env = s;
a412ac57 701 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 702 selector &= 0xffff;
5fafdf24 703 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 704 (selector << 4), 0xffff, 0);
a513fe19 705 } else {
5d97559d 706 helper_load_seg(seg_reg, selector);
a513fe19 707 }
6dbad63e
FB		 708 env = saved_env;
709}
9de5e440 710
6f12a2a6 711void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 712{
713 CPUX86State *saved_env;
714
715 saved_env = env;
716 env = s;
3b46e624 717
6f12a2a6 718 helper_fsave(ptr, data32);
d0a1ffc9
FB		 719
720 env = saved_env;
721}
722
6f12a2a6 723void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 724{
725 CPUX86State *saved_env;
726
727 saved_env = env;
728 env = s;
3b46e624 729
6f12a2a6 730 helper_frstor(ptr, data32);
d0a1ffc9
FB		 731
732 env = saved_env;
733}
734
e4533c7a
FB		 735#endif /* TARGET_I386 */
736
67b915a5
FB		 737#if !defined(CONFIG_SOFTMMU)
738
3fb2ded1 739#if defined(TARGET_I386)
0b5c1ce8
NF		 740#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
741#else
742#define EXCEPTION_ACTION cpu_loop_exit()
743#endif
3fb2ded1 744
b56dad1c 745/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 746 the effective address of the memory exception. 'is_write' is 1 if a
747 write caused the exception and otherwise 0'. 'old_set' is the
748 signal set which should be restored */
2b413144 749static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 750 int is_write, sigset_t *old_set,
bf3e8bf1 751 void *puc)
9de5e440 752{
a513fe19
FB		 753 TranslationBlock *tb;
754 int ret;
68a79315 755
83479e77
FB		 756 if (cpu_single_env)
757 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 758#if defined(DEBUG_SIGNAL)
5fafdf24 759 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 760 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 761#endif
25eb4484 762 /* XXX: locking issue */
53a5960a 763 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 764 return 1;
765 }
fbf9eeb3 766
3fb2ded1 767 /* see if it is an MMU fault */
0b5c1ce8 768 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 769 if (ret < 0)
770 return 0; /* not an MMU fault */
771 if (ret == 0)
772 return 1; /* the MMU fault was handled without causing real CPU fault */
773 /* now we have a real cpu fault */
774 tb = tb_find_pc(pc);
775 if (tb) {
776 /* the PC is inside the translated code. It means that we have
777 a virtual CPU fault */
778 cpu_restore_state(tb, env, pc, puc);
779 }
68016c62 780
68016c62
FB		 781 /* we restore the process signal mask as the sigreturn should
782 do it (XXX: use sigsetjmp) */
783 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 784 EXCEPTION_ACTION;
e6e5906b 785
e6e5906b 786 /* never comes here */
67867308
FB		 787 return 1;
788}
6af0bf9c 789
2b413144
FB		 790#if defined(__i386__)
791
d8ecc0b9
FB		 792#if defined(__APPLE__)
793# include <sys/ucontext.h>
794
795# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
796# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
797# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 798# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 799#elif defined (__NetBSD__)
800# include <ucontext.h>
801
802# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
803# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
804# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
805# define MASK_sig(context) ((context)->uc_sigmask)
806#elif defined (__FreeBSD__) || defined(__DragonFly__)
807# include <ucontext.h>
808
809# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
810# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
811# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
812# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 813#elif defined(__OpenBSD__)
814# define EIP_sig(context) ((context)->sc_eip)
815# define TRAP_sig(context) ((context)->sc_trapno)
816# define ERROR_sig(context) ((context)->sc_err)
817# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 818#else
819# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
820# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
821# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 822# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 823#endif
824
5fafdf24 825int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 826 void *puc)
9de5e440 827{
5a7b542b 828 siginfo_t *info = pinfo;
78cfb07f
JL		 829#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
830 ucontext_t *uc = puc;
831#elif defined(__OpenBSD__)
d39bb24a
BS		 832 struct sigcontext *uc = puc;
833#else
9de5e440 834 struct ucontext *uc = puc;
d39bb24a 835#endif
9de5e440 836 unsigned long pc;
bf3e8bf1 837 int trapno;
97eb5b14 838
d691f669
FB		 839#ifndef REG_EIP
840/* for glibc 2.1 */
fd6ce8f6
FB		 841#define REG_EIP EIP
842#define REG_ERR ERR
843#define REG_TRAPNO TRAPNO
d691f669 844#endif
d8ecc0b9
FB		 845 pc = EIP_sig(uc);
846 trapno = TRAP_sig(uc);
ec6338ba
FB		 847 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
848 trapno == 0xe ?
849 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 850 &MASK_sig(uc), puc);
2b413144
FB		 851}
852
bc51c5c9
FB		 853#elif defined(__x86_64__)
854
b3efe5c8 855#ifdef __NetBSD__
d397abbd
BS		 856#define PC_sig(context) _UC_MACHINE_PC(context)
857#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
858#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
859#define MASK_sig(context) ((context)->uc_sigmask)
860#elif defined(__OpenBSD__)
861#define PC_sig(context) ((context)->sc_rip)
862#define TRAP_sig(context) ((context)->sc_trapno)
863#define ERROR_sig(context) ((context)->sc_err)
864#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 865#elif defined (__FreeBSD__) || defined(__DragonFly__)
866#include <ucontext.h>
867
868#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
869#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
870#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
871#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 872#else
d397abbd
BS		 873#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
874#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
875#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
876#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 877#endif
878
5a7b542b 879int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 880 void *puc)
881{
5a7b542b 882 siginfo_t *info = pinfo;
bc51c5c9 883 unsigned long pc;
78cfb07f 884#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 885 ucontext_t *uc = puc;
d397abbd
BS		 886#elif defined(__OpenBSD__)
887 struct sigcontext *uc = puc;
b3efe5c8
BS		 888#else
889 struct ucontext *uc = puc;
890#endif
bc51c5c9 891
d397abbd 892 pc = PC_sig(uc);
5fafdf24 893 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 894 TRAP_sig(uc) == 0xe ?
895 (ERROR_sig(uc) >> 1) & 1 : 0,
896 &MASK_sig(uc), puc);
bc51c5c9
FB		 897}
898
e58ffeb3 899#elif defined(_ARCH_PPC)
2b413144 900
83fb7adf
FB		 901/***********************************************************************
902 * signal context platform-specific definitions
903 * From Wine
904 */
905#ifdef linux
906/* All Registers access - only for local access */
907# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
908/* Gpr Registers access */
909# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
910# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
911# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
912# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
913# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
914# define LR_sig(context) REG_sig(link, context) /* Link register */
915# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
916/* Float Registers access */
917# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
918# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
919/* Exception Registers access */
920# define DAR_sig(context) REG_sig(dar, context)
921# define DSISR_sig(context) REG_sig(dsisr, context)
922# define TRAP_sig(context) REG_sig(trap, context)
923#endif /* linux */
924
925#ifdef __APPLE__
926# include <sys/ucontext.h>
927typedef struct ucontext SIGCONTEXT;
928/* All Registers access - only for local access */
929# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
930# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
931# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
932# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
933/* Gpr Registers access */
934# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
935# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
936# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
937# define CTR_sig(context) REG_sig(ctr, context)
938# define XER_sig(context) REG_sig(xer, context) /* Link register */
939# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
940# define CR_sig(context) REG_sig(cr, context) /* Condition register */
941/* Float Registers access */
942# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
943# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
944/* Exception Registers access */
945# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
946# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
947# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
948#endif /* __APPLE__ */
949
5fafdf24 950int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 951 void *puc)
2b413144 952{
5a7b542b 953 siginfo_t *info = pinfo;
25eb4484 954 struct ucontext *uc = puc;
25eb4484 955 unsigned long pc;
25eb4484
FB		 956 int is_write;
957
83fb7adf 958 pc = IAR_sig(uc);
25eb4484
FB		 959 is_write = 0;
960#if 0
961 /* ppc 4xx case */
83fb7adf 962 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 963 is_write = 1;
964#else
83fb7adf 965 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 966 is_write = 1;
967#endif
5fafdf24 968 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 969 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 970}
971
2f87c607
FB		 972#elif defined(__alpha__)
973
5fafdf24 974int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 975 void *puc)
976{
5a7b542b 977 siginfo_t *info = pinfo;
2f87c607
FB		 978 struct ucontext *uc = puc;
979 uint32_t *pc = uc->uc_mcontext.sc_pc;
980 uint32_t insn = *pc;
981 int is_write = 0;
982
8c6939c0 983 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 984 switch (insn >> 26) {
985 case 0x0d: // stw
986 case 0x0e: // stb
987 case 0x0f: // stq_u
988 case 0x24: // stf
989 case 0x25: // stg
990 case 0x26: // sts
991 case 0x27: // stt
992 case 0x2c: // stl
993 case 0x2d: // stq
994 case 0x2e: // stl_c
995 case 0x2f: // stq_c
996 is_write = 1;
997 }
998
5fafdf24 999 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1000 is_write, &uc->uc_sigmask, puc);
2f87c607 1001}
8c6939c0
FB		 1002#elif defined(__sparc__)
1003
5fafdf24 1004int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1005 void *puc)
8c6939c0 1006{
5a7b542b 1007 siginfo_t *info = pinfo;
8c6939c0
FB		 1008 int is_write;
1009 uint32_t insn;
dfe5fff3 1010#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1011 uint32_t *regs = (uint32_t *)(info + 1);
1012 void *sigmask = (regs + 20);
8c6939c0 1013 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1014 unsigned long pc = regs[1];
1015#else
84778508 1016#ifdef __linux__
c9e1e2b0
BS		 1017 struct sigcontext *sc = puc;
1018 unsigned long pc = sc->sigc_regs.tpc;
1019 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1020#elif defined(__OpenBSD__)
1021 struct sigcontext *uc = puc;
1022 unsigned long pc = uc->sc_pc;
1023 void *sigmask = (void *)(long)uc->sc_mask;
1024#endif
c9e1e2b0
BS		 1025#endif
1026
8c6939c0
FB		 1027 /* XXX: need kernel patch to get write flag faster */
1028 is_write = 0;
1029 insn = *(uint32_t *)pc;
1030 if ((insn >> 30) == 3) {
1031 switch((insn >> 19) & 0x3f) {
1032 case 0x05: // stb
d877fa5a 1033 case 0x15: // stba
8c6939c0 1034 case 0x06: // sth
d877fa5a 1035 case 0x16: // stha
8c6939c0 1036 case 0x04: // st
d877fa5a 1037 case 0x14: // sta
8c6939c0 1038 case 0x07: // std
d877fa5a
BS		 1039 case 0x17: // stda
1040 case 0x0e: // stx
1041 case 0x1e: // stxa
8c6939c0 1042 case 0x24: // stf
d877fa5a 1043 case 0x34: // stfa
8c6939c0 1044 case 0x27: // stdf
d877fa5a
BS		 1045 case 0x37: // stdfa
1046 case 0x26: // stqf
1047 case 0x36: // stqfa
8c6939c0 1048 case 0x25: // stfsr
d877fa5a
BS		 1049 case 0x3c: // casa
1050 case 0x3e: // casxa
8c6939c0
FB		 1051 is_write = 1;
1052 break;
1053 }
1054 }
5fafdf24 1055 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1056 is_write, sigmask, NULL);
8c6939c0
FB		 1057}
1058
1059#elif defined(__arm__)
1060
5fafdf24 1061int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1062 void *puc)
8c6939c0 1063{
5a7b542b 1064 siginfo_t *info = pinfo;
8c6939c0
FB		 1065 struct ucontext *uc = puc;
1066 unsigned long pc;
1067 int is_write;
3b46e624 1068
48bbf11b 1069#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1070 pc = uc->uc_mcontext.gregs[R15];
1071#else
4eee57f5 1072 pc = uc->uc_mcontext.arm_pc;
5c49b363 1073#endif
8c6939c0
FB		 1074 /* XXX: compute is_write */
1075 is_write = 0;
5fafdf24 1076 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1077 is_write,
f3a9676a 1078 &uc->uc_sigmask, puc);
8c6939c0
FB		 1079}
1080
38e584a0
FB		 1081#elif defined(__mc68000)
1082
5fafdf24 1083int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1084 void *puc)
1085{
5a7b542b 1086 siginfo_t *info = pinfo;
38e584a0
FB		 1087 struct ucontext *uc = puc;
1088 unsigned long pc;
1089 int is_write;
3b46e624 1090
38e584a0
FB		 1091 pc = uc->uc_mcontext.gregs[16];
1092 /* XXX: compute is_write */
1093 is_write = 0;
5fafdf24 1094 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1095 is_write,
bf3e8bf1 1096 &uc->uc_sigmask, puc);
38e584a0
FB		 1097}
1098
b8076a74
FB		 1099#elif defined(__ia64)
1100
1101#ifndef __ISR_VALID
1102 /* This ought to be in <bits/siginfo.h>... */
1103# define __ISR_VALID 1
b8076a74
FB		 1104#endif
1105
5a7b542b 1106int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1107{
5a7b542b 1108 siginfo_t *info = pinfo;
b8076a74
FB		 1109 struct ucontext *uc = puc;
1110 unsigned long ip;
1111 int is_write = 0;
1112
1113 ip = uc->uc_mcontext.sc_ip;
1114 switch (host_signum) {
1115 case SIGILL:
1116 case SIGFPE:
1117 case SIGSEGV:
1118 case SIGBUS:
1119 case SIGTRAP:
fd4a43e4 1120 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1121 /* ISR.W (write-access) is bit 33: */
1122 is_write = (info->si_isr >> 33) & 1;
1123 break;
1124
1125 default:
1126 break;
1127 }
1128 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1129 is_write,
1130 &uc->uc_sigmask, puc);
1131}
1132
90cb9493
FB		 1133#elif defined(__s390__)
1134
5fafdf24 1135int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1136 void *puc)
1137{
5a7b542b 1138 siginfo_t *info = pinfo;
90cb9493
FB		 1139 struct ucontext *uc = puc;
1140 unsigned long pc;
1141 int is_write;
3b46e624 1142
90cb9493
FB		 1143 pc = uc->uc_mcontext.psw.addr;
1144 /* XXX: compute is_write */
1145 is_write = 0;
5fafdf24 1146 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1147 is_write, &uc->uc_sigmask, puc);
1148}
1149
1150#elif defined(__mips__)
1151
5fafdf24 1152int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1153 void *puc)
1154{
9617efe8 1155 siginfo_t *info = pinfo;
c4b89d18
TS		 1156 struct ucontext *uc = puc;
1157 greg_t pc = uc->uc_mcontext.pc;
1158 int is_write;
3b46e624 1159
c4b89d18
TS		 1160 /* XXX: compute is_write */
1161 is_write = 0;
5fafdf24 1162 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1163 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1164}
1165
f54b3f92
AJ		 1166#elif defined(__hppa__)
1167
1168int cpu_signal_handler(int host_signum, void *pinfo,
1169 void *puc)
1170{
1171 struct siginfo *info = pinfo;
1172 struct ucontext *uc = puc;
1173 unsigned long pc;
1174 int is_write;
1175
1176 pc = uc->uc_mcontext.sc_iaoq[0];
1177 /* FIXME: compute is_write */
1178 is_write = 0;
1179 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1180 is_write,
1181 &uc->uc_sigmask, puc);
1182}
1183
9de5e440 1184#else
2b413144 1185
3fb2ded1 1186#error host CPU specific signal handler needed
2b413144 1187
9de5e440 1188#endif
67b915a5
FB		 1189
1190#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing