]> git.proxmox.com Git - qemu.git/blame - cpu-exec.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Avoid compiler warning.
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
eddf68a6
JM		 43#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \
44 defined(TARGET_ALPHA)
e4533c7a
FB		 45/* XXX: unify with i386 target */
46void cpu_loop_exit(void)
47{
48 longjmp(env->jmp_env, 1);
49}
50#endif
e6e5906b 51#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
3475187d
FB		 52#define reg_T2
53#endif
e4533c7a 54
fbf9eeb3
FB		 55/* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
58void cpu_resume_from_signal(CPUState *env1, void *puc)
59{
60#if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62#endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68#if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73#endif
74 longjmp(env->jmp_env, 1);
75}
76
8a40a180
FB		 77
78static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
80 unsigned int flags)
81{
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
87
88 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
91
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93
94 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
104 if (tb->pc == pc &&
105 tb->page_addr[0] == phys_page1 &&
106 tb->cs_base == cs_base &&
107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
110 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
15388002 130 tb_invalidated_flag = 1;
8a40a180
FB		 131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138
139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
146
147 found:
8a40a180
FB		 148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152}
153
154static inline TranslationBlock *tb_find_fast(void)
155{
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
158 unsigned int flags;
159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163#if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166 cs_base = env->segs[R_CS].base;
167 pc = cs_base + env->eip;
168#elif defined(TARGET_ARM)
169 flags = env->thumb | (env->vfp.vec_len << 1)
b5ff1b31
FB		 170 | (env->vfp.vec_stride << 4);
171 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
172 flags |= (1 << 6);
40f137e1
PB		 173 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
174 flags |= (1 << 7);
8a40a180
FB		 175 cs_base = 0;
176 pc = env->regs[15];
177#elif defined(TARGET_SPARC)
178#ifdef TARGET_SPARC64
a80dde08
FB		 179 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
180 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
181 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
8a40a180 182#else
a80dde08
FB		 183 // FPU enable . MMU enabled . MMU no-fault . Supervisor
184 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
185 | env->psrs;
8a40a180
FB		 186#endif
187 cs_base = env->npc;
188 pc = env->pc;
189#elif defined(TARGET_PPC)
190 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
191 (msr_se << MSR_SE) | (msr_le << MSR_LE);
192 cs_base = 0;
193 pc = env->nip;
194#elif defined(TARGET_MIPS)
56b19403 195 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cc9442b9 196 cs_base = 0;
8a40a180 197 pc = env->PC;
e6e5906b 198#elif defined(TARGET_M68K)
acf930aa
PB		 199 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
200 | (env->sr & SR_S) /* Bit 13 */
201 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
e6e5906b
PB		 202 cs_base = 0;
203 pc = env->pc;
fdf9b3e8
FB		 204#elif defined(TARGET_SH4)
205 flags = env->sr & (SR_MD | SR_RB);
206 cs_base = 0; /* XXXXX */
207 pc = env->pc;
eddf68a6
JM		 208#elif defined(TARGET_ALPHA)
209 flags = env->ps;
210 cs_base = 0;
211 pc = env->pc;
8a40a180
FB		 212#else
213#error unsupported CPU
214#endif
215 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
216 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
217 tb->flags != flags, 0)) {
218 tb = tb_find_slow(pc, cs_base, flags);
15388002
FB		 219 /* Note: we do it here to avoid a gcc bug on Mac OS X when
220 doing it in tb_find_slow */
221 if (tb_invalidated_flag) {
222 /* as some TB could have been invalidated because
223 of memory exceptions while generating the code, we
224 must recompute the hash index here */
225 T0 = 0;
226 }
8a40a180
FB		 227 }
228 return tb;
229}
230
231
7d13299d
FB		 232/* main execution loop */
233
e4533c7a 234int cpu_exec(CPUState *env1)
7d13299d 235{
1057eaa7
PB		 236#define DECLARE_HOST_REGS 1
237#include "hostregs_helper.h"
238#if defined(TARGET_SPARC)
3475187d
FB		 239#if defined(reg_REGWPTR)
240 uint32_t *saved_regwptr;
241#endif
242#endif
fdbb4691 243#if defined(__sparc__) && !defined(HOST_SOLARIS)
b49d07ba
TS		 244 int saved_i7;
245 target_ulong tmp_T0;
04369ff2 246#endif
8a40a180 247 int ret, interrupt_request;
7d13299d 248 void (*gen_func)(void);
8a40a180 249 TranslationBlock *tb;
c27004ec 250 uint8_t *tc_ptr;
8c6939c0 251
5a1e3cfc
FB		 252#if defined(TARGET_I386)
253 /* handle exit of HALTED state */
254 if (env1->hflags & HF_HALTED_MASK) {
255 /* disable halt condition */
256 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
257 (env1->eflags & IF_MASK)) {
258 env1->hflags &= ~HF_HALTED_MASK;
259 } else {
260 return EXCP_HALTED;
e80e1cc4
FB		 261 }
262 }
263#elif defined(TARGET_PPC)
50443c98 264 if (env1->halted) {
e80e1cc4 265 if (env1->msr[MSR_EE] &&
47103572 266 (env1->interrupt_request & CPU_INTERRUPT_HARD)) {
50443c98 267 env1->halted = 0;
e80e1cc4
FB		 268 } else {
269 return EXCP_HALTED;
5a1e3cfc
FB		 270 }
271 }
ba3c64fb
FB		 272#elif defined(TARGET_SPARC)
273 if (env1->halted) {
274 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
275 (env1->psret != 0)) {
276 env1->halted = 0;
277 } else {
278 return EXCP_HALTED;
279 }
280 }
9332f9da
FB		 281#elif defined(TARGET_ARM)
282 if (env1->halted) {
283 /* An interrupt wakes the CPU even if the I and F CPSR bits are
a90b7318
AZ		 284 set. We use EXITTB to silently wake CPU without causing an
285 actual interrupt. */
286 if (env1->interrupt_request &
287 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) {
9332f9da
FB		 288 env1->halted = 0;
289 } else {
290 return EXCP_HALTED;
291 }
292 }
6810e154
FB		 293#elif defined(TARGET_MIPS)
294 if (env1->halted) {
295 if (env1->interrupt_request &
296 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
297 env1->halted = 0;
298 } else {
299 return EXCP_HALTED;
300 }
301 }
0633879f 302#elif defined(TARGET_ALPHA) || defined(TARGET_M68K)
eddf68a6
JM		 303 if (env1->halted) {
304 if (env1->interrupt_request & CPU_INTERRUPT_HARD) {
305 env1->halted = 0;
306 } else {
307 return EXCP_HALTED;
308 }
309 }
5a1e3cfc
FB		 310#endif
311
6a00d601
FB		 312 cpu_single_env = env1;
313
7d13299d 314 /* first we save global registers */
1057eaa7
PB		 315#define SAVE_HOST_REGS 1
316#include "hostregs_helper.h"
c27004ec 317 env = env1;
fdbb4691 318#if defined(__sparc__) && !defined(HOST_SOLARIS)
e4533c7a
FB		 319 /* we also save i7 because longjmp may not restore it */
320 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
321#endif
322
323#if defined(TARGET_I386)
0d1a29f9 324 env_to_regs();
9de5e440 325 /* put eflags in CPU temporary format */
fc2b4c48
FB		 326 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
327 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 328 CC_OP = CC_OP_EFLAGS;
fc2b4c48 329 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 330#elif defined(TARGET_ARM)
93ac68bc 331#elif defined(TARGET_SPARC)
3475187d
FB		 332#if defined(reg_REGWPTR)
333 saved_regwptr = REGWPTR;
334#endif
67867308 335#elif defined(TARGET_PPC)
e6e5906b
PB		 336#elif defined(TARGET_M68K)
337 env->cc_op = CC_OP_FLAGS;
338 env->cc_dest = env->sr & 0xf;
339 env->cc_x = (env->sr >> 4) & 1;
6af0bf9c 340#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 341#elif defined(TARGET_SH4)
342 /* XXXXX */
eddf68a6
JM		 343#elif defined(TARGET_ALPHA)
344 env_to_regs();
e4533c7a
FB		 345#else
346#error unsupported target CPU
347#endif
3fb2ded1 348 env->exception_index = -1;
9d27abd9 349
7d13299d 350 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 351 for(;;) {
352 if (setjmp(env->jmp_env) == 0) {
ee8b7021 353 env->current_tb = NULL;
3fb2ded1
FB		 354 /* if an exception is pending, we execute it here */
355 if (env->exception_index >= 0) {
356 if (env->exception_index >= EXCP_INTERRUPT) {
357 /* exit request from the cpu execution loop */
358 ret = env->exception_index;
359 break;
360 } else if (env->user_mode_only) {
361 /* if user mode only, we simulate a fake exception
9f083493 362 which will be handled outside the cpu execution
3fb2ded1 363 loop */
83479e77 364#if defined(TARGET_I386)
3fb2ded1
FB		 365 do_interrupt_user(env->exception_index,
366 env->exception_is_int,
367 env->error_code,
368 env->exception_next_eip);
83479e77 369#endif
3fb2ded1
FB		 370 ret = env->exception_index;
371 break;
372 } else {
83479e77 373#if defined(TARGET_I386)
3fb2ded1
FB		 374 /* simulate a real cpu exception. On i386, it can
375 trigger new exceptions, but we do not handle
376 double or triple faults yet. */
377 do_interrupt(env->exception_index,
378 env->exception_is_int,
379 env->error_code,
d05e66d2 380 env->exception_next_eip, 0);
678dde13
TS		 381 /* successfully delivered */
382 env->old_exception = -1;
ce09776b
FB		 383#elif defined(TARGET_PPC)
384 do_interrupt(env);
6af0bf9c
FB		 385#elif defined(TARGET_MIPS)
386 do_interrupt(env);
e95c8d51 387#elif defined(TARGET_SPARC)
1a0c3292 388 do_interrupt(env->exception_index);
b5ff1b31
FB		 389#elif defined(TARGET_ARM)
390 do_interrupt(env);
fdf9b3e8
FB		 391#elif defined(TARGET_SH4)
392 do_interrupt(env);
eddf68a6
JM		 393#elif defined(TARGET_ALPHA)
394 do_interrupt(env);
0633879f
PB		 395#elif defined(TARGET_M68K)
396 do_interrupt(0);
83479e77 397#endif
3fb2ded1
FB		 398 }
399 env->exception_index = -1;
9df217a3
FB		 400 }
401#ifdef USE_KQEMU
402 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
403 int ret;
404 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
405 ret = kqemu_cpu_exec(env);
406 /* put eflags in CPU temporary format */
407 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
408 DF = 1 - (2 * ((env->eflags >> 10) & 1));
409 CC_OP = CC_OP_EFLAGS;
410 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
411 if (ret == 1) {
412 /* exception */
413 longjmp(env->jmp_env, 1);
414 } else if (ret == 2) {
415 /* softmmu execution needed */
416 } else {
417 if (env->interrupt_request != 0) {
418 /* hardware interrupt will be executed just after */
419 } else {
420 /* otherwise, we restart */
421 longjmp(env->jmp_env, 1);
422 }
423 }
3fb2ded1 424 }
9df217a3
FB		 425#endif
426
3fb2ded1
FB		 427 T0 = 0; /* force lookup of first TB */
428 for(;;) {
fdbb4691 429#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1
FB		 430 /* g1 can be modified by some libc? functions */
431 tmp_T0 = T0;
8c6939c0 432#endif
68a79315 433 interrupt_request = env->interrupt_request;
2e255c6b 434 if (__builtin_expect(interrupt_request, 0)) {
6658ffb8
PB		 435 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
436 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
437 env->exception_index = EXCP_DEBUG;
438 cpu_loop_exit();
439 }
a90b7318
AZ		 440#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
441 defined(TARGET_PPC) || defined(TARGET_ALPHA)
442 if (interrupt_request & CPU_INTERRUPT_HALT) {
443 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
444 env->halted = 1;
445 env->exception_index = EXCP_HLT;
446 cpu_loop_exit();
447 }
448#endif
68a79315 449#if defined(TARGET_I386)
3b21e03e
FB		 450 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
451 !(env->hflags & HF_SMM_MASK)) {
452 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
453 do_smm_enter();
454#if defined(__sparc__) && !defined(HOST_SOLARIS)
455 tmp_T0 = 0;
456#else
457 T0 = 0;
458#endif
459 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 460 (env->eflags & IF_MASK) &&
461 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 462 int intno;
fbf9eeb3 463 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 464 intno = cpu_get_pic_interrupt(env);
f193c797 465 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 466 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
467 }
d05e66d2 468 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 469 /* ensure that no TB jump will be modified as
470 the program flow was changed */
fdbb4691 471#if defined(__sparc__) && !defined(HOST_SOLARIS)
907a5b26
FB		 472 tmp_T0 = 0;
473#else
474 T0 = 0;
475#endif
68a79315 476 }
ce09776b 477#elif defined(TARGET_PPC)
9fddaa0c
FB		 478#if 0
479 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
480 cpu_ppc_reset(env);
481 }
482#endif
47103572 483 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 484 ppc_hw_interrupt(env);
485 if (env->pending_interrupts == 0)
486 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
fdbb4691 487#if defined(__sparc__) && !defined(HOST_SOLARIS)
e9df014c 488 tmp_T0 = 0;
8a40a180 489#else
e9df014c 490 T0 = 0;
8a40a180 491#endif
ce09776b 492 }
6af0bf9c
FB		 493#elif defined(TARGET_MIPS)
494 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 495 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 496 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 497 !(env->CP0_Status & (1 << CP0St_EXL)) &&
498 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 499 !(env->hflags & MIPS_HFLAG_DM)) {
500 /* Raise it */
501 env->exception_index = EXCP_EXT_INTERRUPT;
502 env->error_code = 0;
503 do_interrupt(env);
fdbb4691 504#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 505 tmp_T0 = 0;
506#else
507 T0 = 0;
508#endif
6af0bf9c 509 }
e95c8d51 510#elif defined(TARGET_SPARC)
66321a11
FB		 511 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
512 (env->psret != 0)) {
513 int pil = env->interrupt_index & 15;
514 int type = env->interrupt_index & 0xf0;
515
516 if (((type == TT_EXTINT) &&
517 (pil == 15 || pil > env->psrpil)) ||
518 type != TT_EXTINT) {
519 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
520 do_interrupt(env->interrupt_index);
521 env->interrupt_index = 0;
fdbb4691 522#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 523 tmp_T0 = 0;
524#else
525 T0 = 0;
526#endif
66321a11 527 }
e95c8d51
FB		 528 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
529 //do_interrupt(0, 0, 0, 0, 0);
530 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 531 }
b5ff1b31
FB		 532#elif defined(TARGET_ARM)
533 if (interrupt_request & CPU_INTERRUPT_FIQ
534 && !(env->uncached_cpsr & CPSR_F)) {
535 env->exception_index = EXCP_FIQ;
536 do_interrupt(env);
537 }
538 if (interrupt_request & CPU_INTERRUPT_HARD
539 && !(env->uncached_cpsr & CPSR_I)) {
540 env->exception_index = EXCP_IRQ;
541 do_interrupt(env);
542 }
fdf9b3e8
FB		 543#elif defined(TARGET_SH4)
544 /* XXXXX */
eddf68a6
JM		 545#elif defined(TARGET_ALPHA)
546 if (interrupt_request & CPU_INTERRUPT_HARD) {
547 do_interrupt(env);
548 }
0633879f
PB		 549#elif defined(TARGET_M68K)
550 if (interrupt_request & CPU_INTERRUPT_HARD
551 && ((env->sr & SR_I) >> SR_I_SHIFT)
552 < env->pending_level) {
553 /* Real hardware gets the interrupt vector via an
554 IACK cycle at this point. Current emulated
555 hardware doesn't rely on this, so we
556 provide/save the vector when the interrupt is
557 first signalled. */
558 env->exception_index = env->pending_vector;
559 do_interrupt(1);
560 }
68a79315 561#endif
9d05095e
FB		 562 /* Don't use the cached interupt_request value,
563 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 564 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 565 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
566 /* ensure that no TB jump will be modified as
567 the program flow was changed */
fdbb4691 568#if defined(__sparc__) && !defined(HOST_SOLARIS)
bf3e8bf1
FB		 569 tmp_T0 = 0;
570#else
571 T0 = 0;
572#endif
573 }
68a79315
FB		 574 if (interrupt_request & CPU_INTERRUPT_EXIT) {
575 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
576 env->exception_index = EXCP_INTERRUPT;
577 cpu_loop_exit();
578 }
3fb2ded1 579 }
7d13299d 580#ifdef DEBUG_EXEC
b5ff1b31 581 if ((loglevel & CPU_LOG_TB_CPU)) {
e4533c7a 582#if defined(TARGET_I386)
3fb2ded1 583 /* restore flags in standard format */
fc9f715d 584#ifdef reg_EAX
3fb2ded1 585 env->regs[R_EAX] = EAX;
fc9f715d
FB		 586#endif
587#ifdef reg_EBX
3fb2ded1 588 env->regs[R_EBX] = EBX;
fc9f715d
FB		 589#endif
590#ifdef reg_ECX
3fb2ded1 591 env->regs[R_ECX] = ECX;
fc9f715d
FB		 592#endif
593#ifdef reg_EDX
3fb2ded1 594 env->regs[R_EDX] = EDX;
fc9f715d
FB		 595#endif
596#ifdef reg_ESI
3fb2ded1 597 env->regs[R_ESI] = ESI;
fc9f715d
FB		 598#endif
599#ifdef reg_EDI
3fb2ded1 600 env->regs[R_EDI] = EDI;
fc9f715d
FB		 601#endif
602#ifdef reg_EBP
3fb2ded1 603 env->regs[R_EBP] = EBP;
fc9f715d
FB		 604#endif
605#ifdef reg_ESP
3fb2ded1 606 env->regs[R_ESP] = ESP;
fc9f715d 607#endif
3fb2ded1 608 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 609 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 610 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 611#elif defined(TARGET_ARM)
7fe48483 612 cpu_dump_state(env, logfile, fprintf, 0);
93ac68bc 613#elif defined(TARGET_SPARC)
3475187d
FB		 614 REGWPTR = env->regbase + (env->cwp * 16);
615 env->regwptr = REGWPTR;
616 cpu_dump_state(env, logfile, fprintf, 0);
67867308 617#elif defined(TARGET_PPC)
7fe48483 618 cpu_dump_state(env, logfile, fprintf, 0);
e6e5906b
PB		 619#elif defined(TARGET_M68K)
620 cpu_m68k_flush_flags(env, env->cc_op);
621 env->cc_op = CC_OP_FLAGS;
622 env->sr = (env->sr & 0xffe0)
623 | env->cc_dest | (env->cc_x << 4);
624 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 625#elif defined(TARGET_MIPS)
626 cpu_dump_state(env, logfile, fprintf, 0);
fdf9b3e8
FB		 627#elif defined(TARGET_SH4)
628 cpu_dump_state(env, logfile, fprintf, 0);
eddf68a6
JM		 629#elif defined(TARGET_ALPHA)
630 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 631#else
632#error unsupported target CPU
633#endif
3fb2ded1 634 }
7d13299d 635#endif
8a40a180 636 tb = tb_find_fast();
9d27abd9 637#ifdef DEBUG_EXEC
c1135f61 638 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 639 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
640 (long)tb->tc_ptr, tb->pc,
641 lookup_symbol(tb->pc));
3fb2ded1 642 }
9d27abd9 643#endif
fdbb4691 644#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1 645 T0 = tmp_T0;
8c6939c0 646#endif
8a40a180
FB		 647 /* see if we can patch the calling TB. When the TB
648 spans two pages, we cannot safely do a direct
649 jump. */
c27004ec 650 {
8a40a180 651 if (T0 != 0 &&
f32fc648
FB		 652#if USE_KQEMU
653 (env->kqemu_enabled != 2) &&
654#endif
8a40a180 655 tb->page_addr[1] == -1
bf3e8bf1
FB		 656#if defined(TARGET_I386) && defined(USE_CODE_COPY)
657 && (tb->cflags & CF_CODE_COPY) ==
658 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
659#endif
660 ) {
3fb2ded1 661 spin_lock(&tb_lock);
c27004ec 662 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 663#if defined(USE_CODE_COPY)
664 /* propagates the FP use info */
665 ((TranslationBlock *)(T0 & ~3))->cflags |=
666 (tb->cflags & CF_FP_USED);
667#endif
3fb2ded1
FB		 668 spin_unlock(&tb_lock);
669 }
c27004ec 670 }
3fb2ded1 671 tc_ptr = tb->tc_ptr;
83479e77 672 env->current_tb = tb;
3fb2ded1
FB		 673 /* execute the generated code */
674 gen_func = (void *)tc_ptr;
8c6939c0 675#if defined(__sparc__)
3fb2ded1
FB		 676 __asm__ __volatile__("call %0\n\t"
677 "mov %%o7,%%i0"
678 : /* no outputs */
679 : "r" (gen_func)
fdbb4691 680 : "i0", "i1", "i2", "i3", "i4", "i5",
faab7592 681 "o0", "o1", "o2", "o3", "o4", "o5",
fdbb4691
FB		 682 "l0", "l1", "l2", "l3", "l4", "l5",
683 "l6", "l7");
8c6939c0 684#elif defined(__arm__)
3fb2ded1
FB		 685 asm volatile ("mov pc, %0\n\t"
686 ".global exec_loop\n\t"
687 "exec_loop:\n\t"
688 : /* no outputs */
689 : "r" (gen_func)
690 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 691#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
692{
693 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 694 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
695 save_native_fp_state(env);
696 }
bf3e8bf1
FB		 697 gen_func();
698 } else {
97eb5b14
FB		 699 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
700 restore_native_fp_state(env);
701 }
bf3e8bf1
FB		 702 /* we work with native eflags */
703 CC_SRC = cc_table[CC_OP].compute_all();
704 CC_OP = CC_OP_EFLAGS;
705 asm(".globl exec_loop\n"
706 "\n"
707 "debug1:\n"
708 " pushl %%ebp\n"
709 " fs movl %10, %9\n"
710 " fs movl %11, %%eax\n"
711 " andl $0x400, %%eax\n"
712 " fs orl %8, %%eax\n"
713 " pushl %%eax\n"
714 " popf\n"
715 " fs movl %%esp, %12\n"
716 " fs movl %0, %%eax\n"
717 " fs movl %1, %%ecx\n"
718 " fs movl %2, %%edx\n"
719 " fs movl %3, %%ebx\n"
720 " fs movl %4, %%esp\n"
721 " fs movl %5, %%ebp\n"
722 " fs movl %6, %%esi\n"
723 " fs movl %7, %%edi\n"
724 " fs jmp *%9\n"
725 "exec_loop:\n"
726 " fs movl %%esp, %4\n"
727 " fs movl %12, %%esp\n"
728 " fs movl %%eax, %0\n"
729 " fs movl %%ecx, %1\n"
730 " fs movl %%edx, %2\n"
731 " fs movl %%ebx, %3\n"
732 " fs movl %%ebp, %5\n"
733 " fs movl %%esi, %6\n"
734 " fs movl %%edi, %7\n"
735 " pushf\n"
736 " popl %%eax\n"
737 " movl %%eax, %%ecx\n"
738 " andl $0x400, %%ecx\n"
739 " shrl $9, %%ecx\n"
740 " andl $0x8d5, %%eax\n"
741 " fs movl %%eax, %8\n"
742 " movl $1, %%eax\n"
743 " subl %%ecx, %%eax\n"
744 " fs movl %%eax, %11\n"
745 " fs movl %9, %%ebx\n" /* get T0 value */
746 " popl %%ebp\n"
747 :
748 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
749 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
750 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
751 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
752 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
753 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
754 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
755 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
756 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
757 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
758 "a" (gen_func),
759 "m" (*(uint8_t *)offsetof(CPUState, df)),
760 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
761 : "%ecx", "%edx"
762 );
763 }
764}
b8076a74
FB		 765#elif defined(__ia64)
766 struct fptr {
767 void *ip;
768 void *gp;
769 } fp;
770
771 fp.ip = tc_ptr;
772 fp.gp = code_gen_buffer + 2 * (1 << 20);
773 (*(void (*)(void)) &fp)();
ae228531 774#else
3fb2ded1 775 gen_func();
ae228531 776#endif
83479e77 777 env->current_tb = NULL;
4cbf74b6
FB		 778 /* reset soft MMU for next block (it can currently
779 only be set by a memory fault) */
780#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 781 if (env->hflags & HF_SOFTMMU_MASK) {
782 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 783 /* do not allow linking to another block */
784 T0 = 0;
785 }
f32fc648
FB		 786#endif
787#if defined(USE_KQEMU)
788#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
789 if (kqemu_is_ok(env) &&
790 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
791 cpu_loop_exit();
792 }
4cbf74b6 793#endif
3fb2ded1
FB		 794 }
795 } else {
0d1a29f9 796 env_to_regs();
7d13299d 797 }
3fb2ded1
FB		 798 } /* for(;;) */
799
7d13299d 800
e4533c7a 801#if defined(TARGET_I386)
97eb5b14
FB		 802#if defined(USE_CODE_COPY)
803 if (env->native_fp_regs) {
804 save_native_fp_state(env);
805 }
806#endif
9de5e440 807 /* restore flags in standard format */
fc2b4c48 808 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
e4533c7a 809#elif defined(TARGET_ARM)
b7bcbe95 810 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 811#elif defined(TARGET_SPARC)
3475187d
FB		 812#if defined(reg_REGWPTR)
813 REGWPTR = saved_regwptr;
814#endif
67867308 815#elif defined(TARGET_PPC)
e6e5906b
PB		 816#elif defined(TARGET_M68K)
817 cpu_m68k_flush_flags(env, env->cc_op);
818 env->cc_op = CC_OP_FLAGS;
819 env->sr = (env->sr & 0xffe0)
820 | env->cc_dest | (env->cc_x << 4);
6af0bf9c 821#elif defined(TARGET_MIPS)
fdf9b3e8 822#elif defined(TARGET_SH4)
eddf68a6 823#elif defined(TARGET_ALPHA)
fdf9b3e8 824 /* XXXXX */
e4533c7a
FB		 825#else
826#error unsupported target CPU
827#endif
1057eaa7
PB		 828
829 /* restore global registers */
fdbb4691 830#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 831 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 832#endif
1057eaa7
PB		 833#include "hostregs_helper.h"
834
6a00d601
FB		 835 /* fail safe : never use cpu_single_env outside cpu_exec() */
836 cpu_single_env = NULL;
7d13299d
FB		 837 return ret;
838}
6dbad63e 839
fbf9eeb3
FB		 840/* must only be called from the generated code as an exception can be
841 generated */
842void tb_invalidate_page_range(target_ulong start, target_ulong end)
843{
dc5d0b3d
FB		 844 /* XXX: cannot enable it yet because it yields to MMU exception
845 where NIP != read address on PowerPC */
846#if 0
fbf9eeb3
FB		 847 target_ulong phys_addr;
848 phys_addr = get_phys_addr_code(env, start);
849 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 850#endif
fbf9eeb3
FB		 851}
852
1a18c71b 853#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 854
6dbad63e
FB		 855void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
856{
857 CPUX86State *saved_env;
858
859 saved_env = env;
860 env = s;
a412ac57 861 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 862 selector &= 0xffff;
2e255c6b 863 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 864 (selector << 4), 0xffff, 0);
a513fe19 865 } else {
b453b70b 866 load_seg(seg_reg, selector);
a513fe19 867 }
6dbad63e
FB		 868 env = saved_env;
869}
9de5e440 870
d0a1ffc9
FB		 871void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
872{
873 CPUX86State *saved_env;
874
875 saved_env = env;
876 env = s;
877
c27004ec 878 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 879
880 env = saved_env;
881}
882
883void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
884{
885 CPUX86State *saved_env;
886
887 saved_env = env;
888 env = s;
889
c27004ec 890 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 891
892 env = saved_env;
893}
894
e4533c7a
FB		 895#endif /* TARGET_I386 */
896
67b915a5
FB		 897#if !defined(CONFIG_SOFTMMU)
898
3fb2ded1
FB		 899#if defined(TARGET_I386)
900
b56dad1c 901/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 902 the effective address of the memory exception. 'is_write' is 1 if a
903 write caused the exception and otherwise 0'. 'old_set' is the
904 signal set which should be restored */
2b413144 905static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 906 int is_write, sigset_t *old_set,
907 void *puc)
9de5e440 908{
a513fe19
FB		 909 TranslationBlock *tb;
910 int ret;
68a79315 911
83479e77
FB		 912 if (cpu_single_env)
913 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 914#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 915 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
916 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 917#endif
25eb4484 918 /* XXX: locking issue */
53a5960a 919 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 920 return 1;
921 }
fbf9eeb3 922
3fb2ded1 923 /* see if it is an MMU fault */
93a40ea9
FB		 924 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
925 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 926 if (ret < 0)
927 return 0; /* not an MMU fault */
928 if (ret == 0)
929 return 1; /* the MMU fault was handled without causing real CPU fault */
930 /* now we have a real cpu fault */
a513fe19
FB		 931 tb = tb_find_pc(pc);
932 if (tb) {
9de5e440
FB		 933 /* the PC is inside the translated code. It means that we have
934 a virtual CPU fault */
bf3e8bf1 935 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 936 }
4cbf74b6 937 if (ret == 1) {
3fb2ded1 938#if 0
4cbf74b6
FB		 939 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
940 env->eip, env->cr[2], env->error_code);
3fb2ded1 941#endif
4cbf74b6
FB		 942 /* we restore the process signal mask as the sigreturn should
943 do it (XXX: use sigsetjmp) */
944 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 945 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 946 } else {
947 /* activate soft MMU for this block */
3f337316 948 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 949 cpu_resume_from_signal(env, puc);
4cbf74b6 950 }
3fb2ded1
FB		 951 /* never comes here */
952 return 1;
953}
954
e4533c7a 955#elif defined(TARGET_ARM)
3fb2ded1 956static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 957 int is_write, sigset_t *old_set,
958 void *puc)
3fb2ded1 959{
68016c62
FB		 960 TranslationBlock *tb;
961 int ret;
962
963 if (cpu_single_env)
964 env = cpu_single_env; /* XXX: find a correct solution for multithread */
965#if defined(DEBUG_SIGNAL)
966 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
967 pc, address, is_write, *(unsigned long *)old_set);
968#endif
9f0777ed 969 /* XXX: locking issue */
53a5960a 970 if (is_write && page_unprotect(h2g(address), pc, puc)) {
9f0777ed
FB		 971 return 1;
972 }
68016c62
FB		 973 /* see if it is an MMU fault */
974 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
975 if (ret < 0)
976 return 0; /* not an MMU fault */
977 if (ret == 0)
978 return 1; /* the MMU fault was handled without causing real CPU fault */
979 /* now we have a real cpu fault */
980 tb = tb_find_pc(pc);
981 if (tb) {
982 /* the PC is inside the translated code. It means that we have
983 a virtual CPU fault */
984 cpu_restore_state(tb, env, pc, puc);
985 }
986 /* we restore the process signal mask as the sigreturn should
987 do it (XXX: use sigsetjmp) */
988 sigprocmask(SIG_SETMASK, old_set, NULL);
989 cpu_loop_exit();
3fb2ded1 990}
93ac68bc
FB		 991#elif defined(TARGET_SPARC)
992static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 993 int is_write, sigset_t *old_set,
994 void *puc)
93ac68bc 995{
68016c62
FB		 996 TranslationBlock *tb;
997 int ret;
998
999 if (cpu_single_env)
1000 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1001#if defined(DEBUG_SIGNAL)
1002 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1003 pc, address, is_write, *(unsigned long *)old_set);
1004#endif
b453b70b 1005 /* XXX: locking issue */
53a5960a 1006 if (is_write && page_unprotect(h2g(address), pc, puc)) {
b453b70b
FB		 1007 return 1;
1008 }
68016c62
FB		 1009 /* see if it is an MMU fault */
1010 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1011 if (ret < 0)
1012 return 0; /* not an MMU fault */
1013 if (ret == 0)
1014 return 1; /* the MMU fault was handled without causing real CPU fault */
1015 /* now we have a real cpu fault */
1016 tb = tb_find_pc(pc);
1017 if (tb) {
1018 /* the PC is inside the translated code. It means that we have
1019 a virtual CPU fault */
1020 cpu_restore_state(tb, env, pc, puc);
1021 }
1022 /* we restore the process signal mask as the sigreturn should
1023 do it (XXX: use sigsetjmp) */
1024 sigprocmask(SIG_SETMASK, old_set, NULL);
1025 cpu_loop_exit();
93ac68bc 1026}
67867308
FB		 1027#elif defined (TARGET_PPC)
1028static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1029 int is_write, sigset_t *old_set,
1030 void *puc)
67867308
FB		 1031{
1032 TranslationBlock *tb;
ce09776b 1033 int ret;
67867308 1034
67867308
FB		 1035 if (cpu_single_env)
1036 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 1037#if defined(DEBUG_SIGNAL)
1038 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1039 pc, address, is_write, *(unsigned long *)old_set);
1040#endif
1041 /* XXX: locking issue */
53a5960a 1042 if (is_write && page_unprotect(h2g(address), pc, puc)) {
67867308
FB		 1043 return 1;
1044 }
1045
ce09776b 1046 /* see if it is an MMU fault */
7f957d28 1047 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 1048 if (ret < 0)
1049 return 0; /* not an MMU fault */
1050 if (ret == 0)
1051 return 1; /* the MMU fault was handled without causing real CPU fault */
1052
67867308
FB		 1053 /* now we have a real cpu fault */
1054 tb = tb_find_pc(pc);
1055 if (tb) {
1056 /* the PC is inside the translated code. It means that we have
1057 a virtual CPU fault */
bf3e8bf1 1058 cpu_restore_state(tb, env, pc, puc);
67867308 1059 }
ce09776b 1060 if (ret == 1) {
67867308 1061#if 0
ce09776b
FB		 1062 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1063 env->nip, env->error_code, tb);
67867308
FB		 1064#endif
1065 /* we restore the process signal mask as the sigreturn should
1066 do it (XXX: use sigsetjmp) */
bf3e8bf1 1067 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 1068 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 1069 } else {
1070 /* activate soft MMU for this block */
fbf9eeb3 1071 cpu_resume_from_signal(env, puc);
ce09776b 1072 }
67867308 1073 /* never comes here */
e6e5906b
PB		 1074 return 1;
1075}
1076
1077#elif defined(TARGET_M68K)
1078static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1079 int is_write, sigset_t *old_set,
1080 void *puc)
1081{
1082 TranslationBlock *tb;
1083 int ret;
1084
1085 if (cpu_single_env)
1086 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1087#if defined(DEBUG_SIGNAL)
1088 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1089 pc, address, is_write, *(unsigned long *)old_set);
1090#endif
1091 /* XXX: locking issue */
1092 if (is_write && page_unprotect(address, pc, puc)) {
1093 return 1;
1094 }
1095 /* see if it is an MMU fault */
1096 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1097 if (ret < 0)
1098 return 0; /* not an MMU fault */
1099 if (ret == 0)
1100 return 1; /* the MMU fault was handled without causing real CPU fault */
1101 /* now we have a real cpu fault */
1102 tb = tb_find_pc(pc);
1103 if (tb) {
1104 /* the PC is inside the translated code. It means that we have
1105 a virtual CPU fault */
1106 cpu_restore_state(tb, env, pc, puc);
1107 }
1108 /* we restore the process signal mask as the sigreturn should
1109 do it (XXX: use sigsetjmp) */
1110 sigprocmask(SIG_SETMASK, old_set, NULL);
1111 cpu_loop_exit();
1112 /* never comes here */
67867308
FB		 1113 return 1;
1114}
6af0bf9c
FB		 1115
1116#elif defined (TARGET_MIPS)
1117static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1118 int is_write, sigset_t *old_set,
1119 void *puc)
1120{
1121 TranslationBlock *tb;
1122 int ret;
1123
1124 if (cpu_single_env)
1125 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1126#if defined(DEBUG_SIGNAL)
1127 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1128 pc, address, is_write, *(unsigned long *)old_set);
1129#endif
1130 /* XXX: locking issue */
53a5960a 1131 if (is_write && page_unprotect(h2g(address), pc, puc)) {
6af0bf9c
FB		 1132 return 1;
1133 }
1134
1135 /* see if it is an MMU fault */
cc9442b9 1136 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
6af0bf9c
FB		 1137 if (ret < 0)
1138 return 0; /* not an MMU fault */
1139 if (ret == 0)
1140 return 1; /* the MMU fault was handled without causing real CPU fault */
1141
1142 /* now we have a real cpu fault */
1143 tb = tb_find_pc(pc);
1144 if (tb) {
1145 /* the PC is inside the translated code. It means that we have
1146 a virtual CPU fault */
1147 cpu_restore_state(tb, env, pc, puc);
1148 }
1149 if (ret == 1) {
1150#if 0
1eb5207b
TS		 1151 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1152 env->PC, env->error_code, tb);
6af0bf9c
FB		 1153#endif
1154 /* we restore the process signal mask as the sigreturn should
1155 do it (XXX: use sigsetjmp) */
1156 sigprocmask(SIG_SETMASK, old_set, NULL);
1157 do_raise_exception_err(env->exception_index, env->error_code);
1158 } else {
1159 /* activate soft MMU for this block */
1160 cpu_resume_from_signal(env, puc);
1161 }
1162 /* never comes here */
1163 return 1;
1164}
1165
fdf9b3e8
FB		 1166#elif defined (TARGET_SH4)
1167static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1168 int is_write, sigset_t *old_set,
1169 void *puc)
1170{
1171 TranslationBlock *tb;
1172 int ret;
1173
1174 if (cpu_single_env)
1175 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1176#if defined(DEBUG_SIGNAL)
1177 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1178 pc, address, is_write, *(unsigned long *)old_set);
1179#endif
1180 /* XXX: locking issue */
1181 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1182 return 1;
1183 }
1184
1185 /* see if it is an MMU fault */
1186 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1187 if (ret < 0)
1188 return 0; /* not an MMU fault */
1189 if (ret == 0)
1190 return 1; /* the MMU fault was handled without causing real CPU fault */
1191
1192 /* now we have a real cpu fault */
eddf68a6
JM		 1193 tb = tb_find_pc(pc);
1194 if (tb) {
1195 /* the PC is inside the translated code. It means that we have
1196 a virtual CPU fault */
1197 cpu_restore_state(tb, env, pc, puc);
1198 }
1199#if 0
1200 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1201 env->nip, env->error_code, tb);
1202#endif
1203 /* we restore the process signal mask as the sigreturn should
1204 do it (XXX: use sigsetjmp) */
1205 sigprocmask(SIG_SETMASK, old_set, NULL);
1206 cpu_loop_exit();
1207 /* never comes here */
1208 return 1;
1209}
1210
1211#elif defined (TARGET_ALPHA)
1212static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1213 int is_write, sigset_t *old_set,
1214 void *puc)
1215{
1216 TranslationBlock *tb;
1217 int ret;
1218
1219 if (cpu_single_env)
1220 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1221#if defined(DEBUG_SIGNAL)
1222 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1223 pc, address, is_write, *(unsigned long *)old_set);
1224#endif
1225 /* XXX: locking issue */
1226 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1227 return 1;
1228 }
1229
1230 /* see if it is an MMU fault */
1231 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1232 if (ret < 0)
1233 return 0; /* not an MMU fault */
1234 if (ret == 0)
1235 return 1; /* the MMU fault was handled without causing real CPU fault */
1236
1237 /* now we have a real cpu fault */
fdf9b3e8
FB		 1238 tb = tb_find_pc(pc);
1239 if (tb) {
1240 /* the PC is inside the translated code. It means that we have
1241 a virtual CPU fault */
1242 cpu_restore_state(tb, env, pc, puc);
1243 }
fdf9b3e8
FB		 1244#if 0
1245 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1246 env->nip, env->error_code, tb);
1247#endif
1248 /* we restore the process signal mask as the sigreturn should
1249 do it (XXX: use sigsetjmp) */
355fb23d
PB		 1250 sigprocmask(SIG_SETMASK, old_set, NULL);
1251 cpu_loop_exit();
fdf9b3e8
FB		 1252 /* never comes here */
1253 return 1;
1254}
e4533c7a
FB		 1255#else
1256#error unsupported target CPU
1257#endif
9de5e440 1258
2b413144
FB		 1259#if defined(__i386__)
1260
d8ecc0b9
FB		 1261#if defined(__APPLE__)
1262# include <sys/ucontext.h>
1263
1264# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1265# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1266# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1267#else
1268# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1269# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1270# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1271#endif
1272
bf3e8bf1
FB		 1273#if defined(USE_CODE_COPY)
1274static void cpu_send_trap(unsigned long pc, int trap,
1275 struct ucontext *uc)
1276{
1277 TranslationBlock *tb;
1278
1279 if (cpu_single_env)
1280 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1281 /* now we have a real cpu fault */
1282 tb = tb_find_pc(pc);
1283 if (tb) {
1284 /* the PC is inside the translated code. It means that we have
1285 a virtual CPU fault */
1286 cpu_restore_state(tb, env, pc, uc);
1287 }
1288 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1289 raise_exception_err(trap, env->error_code);
1290}
1291#endif
1292
5a7b542b 1293int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1294 void *puc)
9de5e440 1295{
5a7b542b 1296 siginfo_t *info = pinfo;
9de5e440
FB		 1297 struct ucontext *uc = puc;
1298 unsigned long pc;
bf3e8bf1 1299 int trapno;
97eb5b14 1300
d691f669
FB		 1301#ifndef REG_EIP
1302/* for glibc 2.1 */
fd6ce8f6
FB		 1303#define REG_EIP EIP
1304#define REG_ERR ERR
1305#define REG_TRAPNO TRAPNO
d691f669 1306#endif
d8ecc0b9
FB		 1307 pc = EIP_sig(uc);
1308 trapno = TRAP_sig(uc);
bf3e8bf1
FB		 1309#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1310 if (trapno == 0x00 || trapno == 0x05) {
1311 /* send division by zero or bound exception */
1312 cpu_send_trap(pc, trapno, uc);
1313 return 1;
1314 } else
1315#endif
1316 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1317 trapno == 0xe ?
d8ecc0b9 1318 (ERROR_sig(uc) >> 1) & 1 : 0,
bf3e8bf1 1319 &uc->uc_sigmask, puc);
2b413144
FB		 1320}
1321
bc51c5c9
FB		 1322#elif defined(__x86_64__)
1323
5a7b542b 1324int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 1325 void *puc)
1326{
5a7b542b 1327 siginfo_t *info = pinfo;
bc51c5c9
FB		 1328 struct ucontext *uc = puc;
1329 unsigned long pc;
1330
1331 pc = uc->uc_mcontext.gregs[REG_RIP];
1332 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1333 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1334 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1335 &uc->uc_sigmask, puc);
1336}
1337
83fb7adf 1338#elif defined(__powerpc__)
2b413144 1339
83fb7adf
FB		 1340/***********************************************************************
1341 * signal context platform-specific definitions
1342 * From Wine
1343 */
1344#ifdef linux
1345/* All Registers access - only for local access */
1346# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1347/* Gpr Registers access */
1348# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1349# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1350# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1351# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1352# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1353# define LR_sig(context) REG_sig(link, context) /* Link register */
1354# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1355/* Float Registers access */
1356# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1357# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1358/* Exception Registers access */
1359# define DAR_sig(context) REG_sig(dar, context)
1360# define DSISR_sig(context) REG_sig(dsisr, context)
1361# define TRAP_sig(context) REG_sig(trap, context)
1362#endif /* linux */
1363
1364#ifdef __APPLE__
1365# include <sys/ucontext.h>
1366typedef struct ucontext SIGCONTEXT;
1367/* All Registers access - only for local access */
1368# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1369# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1370# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1371# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1372/* Gpr Registers access */
1373# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1374# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1375# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1376# define CTR_sig(context) REG_sig(ctr, context)
1377# define XER_sig(context) REG_sig(xer, context) /* Link register */
1378# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1379# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1380/* Float Registers access */
1381# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1382# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1383/* Exception Registers access */
1384# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1385# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1386# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1387#endif /* __APPLE__ */
1388
5a7b542b 1389int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1390 void *puc)
2b413144 1391{
5a7b542b 1392 siginfo_t *info = pinfo;
25eb4484 1393 struct ucontext *uc = puc;
25eb4484 1394 unsigned long pc;
25eb4484
FB		 1395 int is_write;
1396
83fb7adf 1397 pc = IAR_sig(uc);
25eb4484
FB		 1398 is_write = 0;
1399#if 0
1400 /* ppc 4xx case */
83fb7adf 1401 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1402 is_write = 1;
1403#else
83fb7adf 1404 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1405 is_write = 1;
1406#endif
1407 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1408 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1409}
1410
2f87c607
FB		 1411#elif defined(__alpha__)
1412
5a7b542b 1413int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1414 void *puc)
1415{
5a7b542b 1416 siginfo_t *info = pinfo;
2f87c607
FB		 1417 struct ucontext *uc = puc;
1418 uint32_t *pc = uc->uc_mcontext.sc_pc;
1419 uint32_t insn = *pc;
1420 int is_write = 0;
1421
8c6939c0 1422 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1423 switch (insn >> 26) {
1424 case 0x0d: // stw
1425 case 0x0e: // stb
1426 case 0x0f: // stq_u
1427 case 0x24: // stf
1428 case 0x25: // stg
1429 case 0x26: // sts
1430 case 0x27: // stt
1431 case 0x2c: // stl
1432 case 0x2d: // stq
1433 case 0x2e: // stl_c
1434 case 0x2f: // stq_c
1435 is_write = 1;
1436 }
1437
1438 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1439 is_write, &uc->uc_sigmask, puc);
2f87c607 1440}
8c6939c0
FB		 1441#elif defined(__sparc__)
1442
5a7b542b 1443int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1444 void *puc)
8c6939c0 1445{
5a7b542b 1446 siginfo_t *info = pinfo;
8c6939c0
FB		 1447 uint32_t *regs = (uint32_t *)(info + 1);
1448 void *sigmask = (regs + 20);
1449 unsigned long pc;
1450 int is_write;
1451 uint32_t insn;
1452
1453 /* XXX: is there a standard glibc define ? */
1454 pc = regs[1];
1455 /* XXX: need kernel patch to get write flag faster */
1456 is_write = 0;
1457 insn = *(uint32_t *)pc;
1458 if ((insn >> 30) == 3) {
1459 switch((insn >> 19) & 0x3f) {
1460 case 0x05: // stb
1461 case 0x06: // sth
1462 case 0x04: // st
1463 case 0x07: // std
1464 case 0x24: // stf
1465 case 0x27: // stdf
1466 case 0x25: // stfsr
1467 is_write = 1;
1468 break;
1469 }
1470 }
1471 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1472 is_write, sigmask, NULL);
8c6939c0
FB		 1473}
1474
1475#elif defined(__arm__)
1476
5a7b542b 1477int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1478 void *puc)
8c6939c0 1479{
5a7b542b 1480 siginfo_t *info = pinfo;
8c6939c0
FB		 1481 struct ucontext *uc = puc;
1482 unsigned long pc;
1483 int is_write;
1484
1485 pc = uc->uc_mcontext.gregs[R15];
1486 /* XXX: compute is_write */
1487 is_write = 0;
1488 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1489 is_write,
f3a9676a 1490 &uc->uc_sigmask, puc);
8c6939c0
FB		 1491}
1492
38e584a0
FB		 1493#elif defined(__mc68000)
1494
5a7b542b 1495int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1496 void *puc)
1497{
5a7b542b 1498 siginfo_t *info = pinfo;
38e584a0
FB		 1499 struct ucontext *uc = puc;
1500 unsigned long pc;
1501 int is_write;
1502
1503 pc = uc->uc_mcontext.gregs[16];
1504 /* XXX: compute is_write */
1505 is_write = 0;
1506 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1507 is_write,
bf3e8bf1 1508 &uc->uc_sigmask, puc);
38e584a0
FB		 1509}
1510
b8076a74
FB		 1511#elif defined(__ia64)
1512
1513#ifndef __ISR_VALID
1514 /* This ought to be in <bits/siginfo.h>... */
1515# define __ISR_VALID 1
b8076a74
FB		 1516#endif
1517
5a7b542b 1518int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1519{
5a7b542b 1520 siginfo_t *info = pinfo;
b8076a74
FB		 1521 struct ucontext *uc = puc;
1522 unsigned long ip;
1523 int is_write = 0;
1524
1525 ip = uc->uc_mcontext.sc_ip;
1526 switch (host_signum) {
1527 case SIGILL:
1528 case SIGFPE:
1529 case SIGSEGV:
1530 case SIGBUS:
1531 case SIGTRAP:
fd4a43e4 1532 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1533 /* ISR.W (write-access) is bit 33: */
1534 is_write = (info->si_isr >> 33) & 1;
1535 break;
1536
1537 default:
1538 break;
1539 }
1540 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1541 is_write,
1542 &uc->uc_sigmask, puc);
1543}
1544
90cb9493
FB		 1545#elif defined(__s390__)
1546
5a7b542b 1547int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1548 void *puc)
1549{
5a7b542b 1550 siginfo_t *info = pinfo;
90cb9493
FB		 1551 struct ucontext *uc = puc;
1552 unsigned long pc;
1553 int is_write;
1554
1555 pc = uc->uc_mcontext.psw.addr;
1556 /* XXX: compute is_write */
1557 is_write = 0;
1558 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1559 is_write, &uc->uc_sigmask, puc);
1560}
1561
1562#elif defined(__mips__)
1563
9617efe8 1564int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1565 void *puc)
1566{
9617efe8 1567 siginfo_t *info = pinfo;
c4b89d18
TS		 1568 struct ucontext *uc = puc;
1569 greg_t pc = uc->uc_mcontext.pc;
1570 int is_write;
1571
1572 /* XXX: compute is_write */
1573 is_write = 0;
1574 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1575 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1576}
1577
9de5e440 1578#else
2b413144 1579
3fb2ded1 1580#error host CPU specific signal handler needed
2b413144 1581
9de5e440 1582#endif
67b915a5
FB		 1583
1584#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing