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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d | 19 | */ |
e4533c7a | 20 | #include "config.h" |
93ac68bc | 21 | #include "exec.h" |
956034d7 | 22 | #include "disas.h" |
7d13299d | 23 | |
36bdbe54 FB |
24 | int tb_invalidated_flag; |
25 | ||
dc99065b | 26 | //#define DEBUG_EXEC |
9de5e440 | 27 | //#define DEBUG_SIGNAL |
7d13299d | 28 | |
93ac68bc | 29 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) |
e4533c7a FB |
30 | /* XXX: unify with i386 target */ |
31 | void cpu_loop_exit(void) | |
32 | { | |
33 | longjmp(env->jmp_env, 1); | |
34 | } | |
35 | #endif | |
36 | ||
7d13299d FB |
37 | /* main execution loop */ |
38 | ||
e4533c7a | 39 | int cpu_exec(CPUState *env1) |
7d13299d | 40 | { |
e4533c7a FB |
41 | int saved_T0, saved_T1, saved_T2; |
42 | CPUState *saved_env; | |
04369ff2 FB |
43 | #ifdef reg_EAX |
44 | int saved_EAX; | |
45 | #endif | |
46 | #ifdef reg_ECX | |
47 | int saved_ECX; | |
48 | #endif | |
49 | #ifdef reg_EDX | |
50 | int saved_EDX; | |
51 | #endif | |
52 | #ifdef reg_EBX | |
53 | int saved_EBX; | |
54 | #endif | |
55 | #ifdef reg_ESP | |
56 | int saved_ESP; | |
57 | #endif | |
58 | #ifdef reg_EBP | |
59 | int saved_EBP; | |
60 | #endif | |
61 | #ifdef reg_ESI | |
62 | int saved_ESI; | |
63 | #endif | |
64 | #ifdef reg_EDI | |
65 | int saved_EDI; | |
8c6939c0 FB |
66 | #endif |
67 | #ifdef __sparc__ | |
68 | int saved_i7, tmp_T0; | |
04369ff2 | 69 | #endif |
68a79315 | 70 | int code_gen_size, ret, interrupt_request; |
7d13299d | 71 | void (*gen_func)(void); |
9de5e440 | 72 | TranslationBlock *tb, **ptb; |
dab2ed99 | 73 | uint8_t *tc_ptr, *cs_base, *pc; |
6dbad63e | 74 | unsigned int flags; |
8c6939c0 | 75 | |
7d13299d FB |
76 | /* first we save global registers */ |
77 | saved_T0 = T0; | |
78 | saved_T1 = T1; | |
e4533c7a | 79 | saved_T2 = T2; |
7d13299d FB |
80 | saved_env = env; |
81 | env = env1; | |
e4533c7a FB |
82 | #ifdef __sparc__ |
83 | /* we also save i7 because longjmp may not restore it */ | |
84 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); | |
85 | #endif | |
86 | ||
87 | #if defined(TARGET_I386) | |
04369ff2 FB |
88 | #ifdef reg_EAX |
89 | saved_EAX = EAX; | |
90 | EAX = env->regs[R_EAX]; | |
91 | #endif | |
92 | #ifdef reg_ECX | |
93 | saved_ECX = ECX; | |
94 | ECX = env->regs[R_ECX]; | |
95 | #endif | |
96 | #ifdef reg_EDX | |
97 | saved_EDX = EDX; | |
98 | EDX = env->regs[R_EDX]; | |
99 | #endif | |
100 | #ifdef reg_EBX | |
101 | saved_EBX = EBX; | |
102 | EBX = env->regs[R_EBX]; | |
103 | #endif | |
104 | #ifdef reg_ESP | |
105 | saved_ESP = ESP; | |
106 | ESP = env->regs[R_ESP]; | |
107 | #endif | |
108 | #ifdef reg_EBP | |
109 | saved_EBP = EBP; | |
110 | EBP = env->regs[R_EBP]; | |
111 | #endif | |
112 | #ifdef reg_ESI | |
113 | saved_ESI = ESI; | |
114 | ESI = env->regs[R_ESI]; | |
115 | #endif | |
116 | #ifdef reg_EDI | |
117 | saved_EDI = EDI; | |
118 | EDI = env->regs[R_EDI]; | |
119 | #endif | |
7d13299d | 120 | |
9de5e440 | 121 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
122 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
123 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 124 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 125 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a FB |
126 | #elif defined(TARGET_ARM) |
127 | { | |
128 | unsigned int psr; | |
129 | psr = env->cpsr; | |
130 | env->CF = (psr >> 29) & 1; | |
131 | env->NZF = (psr & 0xc0000000) ^ 0x40000000; | |
132 | env->VF = (psr << 3) & 0x80000000; | |
133 | env->cpsr = psr & ~0xf0000000; | |
134 | } | |
93ac68bc | 135 | #elif defined(TARGET_SPARC) |
67867308 | 136 | #elif defined(TARGET_PPC) |
e4533c7a FB |
137 | #else |
138 | #error unsupported target CPU | |
139 | #endif | |
3fb2ded1 | 140 | env->exception_index = -1; |
9d27abd9 | 141 | |
7d13299d | 142 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
143 | for(;;) { |
144 | if (setjmp(env->jmp_env) == 0) { | |
145 | /* if an exception is pending, we execute it here */ | |
146 | if (env->exception_index >= 0) { | |
147 | if (env->exception_index >= EXCP_INTERRUPT) { | |
148 | /* exit request from the cpu execution loop */ | |
149 | ret = env->exception_index; | |
150 | break; | |
151 | } else if (env->user_mode_only) { | |
152 | /* if user mode only, we simulate a fake exception | |
153 | which will be hanlded outside the cpu execution | |
154 | loop */ | |
83479e77 | 155 | #if defined(TARGET_I386) |
3fb2ded1 FB |
156 | do_interrupt_user(env->exception_index, |
157 | env->exception_is_int, | |
158 | env->error_code, | |
159 | env->exception_next_eip); | |
83479e77 | 160 | #endif |
3fb2ded1 FB |
161 | ret = env->exception_index; |
162 | break; | |
163 | } else { | |
83479e77 | 164 | #if defined(TARGET_I386) |
3fb2ded1 FB |
165 | /* simulate a real cpu exception. On i386, it can |
166 | trigger new exceptions, but we do not handle | |
167 | double or triple faults yet. */ | |
168 | do_interrupt(env->exception_index, | |
169 | env->exception_is_int, | |
170 | env->error_code, | |
d05e66d2 | 171 | env->exception_next_eip, 0); |
83479e77 | 172 | #endif |
3fb2ded1 FB |
173 | } |
174 | env->exception_index = -1; | |
175 | } | |
3fb2ded1 FB |
176 | T0 = 0; /* force lookup of first TB */ |
177 | for(;;) { | |
8c6939c0 | 178 | #ifdef __sparc__ |
3fb2ded1 FB |
179 | /* g1 can be modified by some libc? functions */ |
180 | tmp_T0 = T0; | |
8c6939c0 | 181 | #endif |
68a79315 | 182 | interrupt_request = env->interrupt_request; |
2e255c6b | 183 | if (__builtin_expect(interrupt_request, 0)) { |
68a79315 FB |
184 | #if defined(TARGET_I386) |
185 | /* if hardware interrupt pending, we execute it */ | |
186 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
3f337316 FB |
187 | (env->eflags & IF_MASK) && |
188 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
68a79315 FB |
189 | int intno; |
190 | intno = cpu_x86_get_pic_interrupt(env); | |
191 | if (loglevel) { | |
192 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); | |
193 | } | |
d05e66d2 | 194 | do_interrupt(intno, 0, 0, 0, 1); |
68a79315 | 195 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
907a5b26 FB |
196 | /* ensure that no TB jump will be modified as |
197 | the program flow was changed */ | |
198 | #ifdef __sparc__ | |
199 | tmp_T0 = 0; | |
200 | #else | |
201 | T0 = 0; | |
202 | #endif | |
68a79315 FB |
203 | } |
204 | #endif | |
205 | if (interrupt_request & CPU_INTERRUPT_EXIT) { | |
206 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; | |
207 | env->exception_index = EXCP_INTERRUPT; | |
208 | cpu_loop_exit(); | |
209 | } | |
3fb2ded1 | 210 | } |
7d13299d | 211 | #ifdef DEBUG_EXEC |
3fb2ded1 | 212 | if (loglevel) { |
e4533c7a | 213 | #if defined(TARGET_I386) |
3fb2ded1 FB |
214 | /* restore flags in standard format */ |
215 | env->regs[R_EAX] = EAX; | |
216 | env->regs[R_EBX] = EBX; | |
217 | env->regs[R_ECX] = ECX; | |
218 | env->regs[R_EDX] = EDX; | |
219 | env->regs[R_ESI] = ESI; | |
220 | env->regs[R_EDI] = EDI; | |
221 | env->regs[R_EBP] = EBP; | |
222 | env->regs[R_ESP] = ESP; | |
223 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
68a79315 | 224 | cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
3fb2ded1 | 225 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 226 | #elif defined(TARGET_ARM) |
1b21b62a | 227 | env->cpsr = compute_cpsr(); |
3fb2ded1 | 228 | cpu_arm_dump_state(env, logfile, 0); |
1b21b62a | 229 | env->cpsr &= ~0xf0000000; |
93ac68bc | 230 | #elif defined(TARGET_SPARC) |
93a40ea9 | 231 | cpu_sparc_dump_state (env, logfile, 0); |
67867308 FB |
232 | #elif defined(TARGET_PPC) |
233 | cpu_ppc_dump_state(env, logfile, 0); | |
e4533c7a FB |
234 | #else |
235 | #error unsupported target CPU | |
236 | #endif | |
3fb2ded1 | 237 | } |
7d13299d | 238 | #endif |
3f337316 FB |
239 | /* we record a subset of the CPU state. It will |
240 | always be the same before a given translated block | |
241 | is executed. */ | |
e4533c7a | 242 | #if defined(TARGET_I386) |
2e255c6b | 243 | flags = env->hflags; |
3f337316 | 244 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
3fb2ded1 FB |
245 | cs_base = env->segs[R_CS].base; |
246 | pc = cs_base + env->eip; | |
e4533c7a | 247 | #elif defined(TARGET_ARM) |
3fb2ded1 FB |
248 | flags = 0; |
249 | cs_base = 0; | |
250 | pc = (uint8_t *)env->regs[15]; | |
93ac68bc | 251 | #elif defined(TARGET_SPARC) |
67867308 FB |
252 | flags = 0; |
253 | cs_base = 0; | |
254 | if (env->npc) { | |
255 | env->pc = env->npc; | |
256 | env->npc = 0; | |
257 | } | |
258 | pc = (uint8_t *) env->pc; | |
259 | #elif defined(TARGET_PPC) | |
260 | flags = 0; | |
261 | cs_base = 0; | |
262 | pc = (uint8_t *)env->nip; | |
e4533c7a FB |
263 | #else |
264 | #error unsupported CPU | |
265 | #endif | |
3fb2ded1 FB |
266 | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
267 | flags); | |
d4e8164f | 268 | if (!tb) { |
3fb2ded1 FB |
269 | spin_lock(&tb_lock); |
270 | /* if no translated code available, then translate it now */ | |
d4e8164f | 271 | tb = tb_alloc((unsigned long)pc); |
3fb2ded1 FB |
272 | if (!tb) { |
273 | /* flush must be done */ | |
274 | tb_flush(); | |
275 | /* cannot fail at this point */ | |
276 | tb = tb_alloc((unsigned long)pc); | |
277 | /* don't forget to invalidate previous TB info */ | |
278 | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; | |
279 | T0 = 0; | |
280 | } | |
281 | tc_ptr = code_gen_ptr; | |
282 | tb->tc_ptr = tc_ptr; | |
283 | tb->cs_base = (unsigned long)cs_base; | |
284 | tb->flags = flags; | |
36bdbe54 | 285 | tb_invalidated_flag = 0; |
facc68be | 286 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
36bdbe54 FB |
287 | if (tb_invalidated_flag) { |
288 | /* as some TB could have been invalidated because | |
289 | of memory exceptions while generating the code, we | |
290 | must recompute the hash index here */ | |
291 | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; | |
292 | while (*ptb != NULL) | |
293 | ptb = &(*ptb)->hash_next; | |
294 | T0 = 0; | |
295 | } | |
3fb2ded1 FB |
296 | *ptb = tb; |
297 | tb->hash_next = NULL; | |
298 | tb_link(tb); | |
299 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); | |
25eb4484 | 300 | spin_unlock(&tb_lock); |
9de5e440 | 301 | } |
9d27abd9 | 302 | #ifdef DEBUG_EXEC |
3fb2ded1 FB |
303 | if (loglevel) { |
304 | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n", | |
305 | (long)tb->tc_ptr, (long)tb->pc, | |
306 | lookup_symbol((void *)tb->pc)); | |
307 | } | |
9d27abd9 | 308 | #endif |
8c6939c0 | 309 | #ifdef __sparc__ |
3fb2ded1 | 310 | T0 = tmp_T0; |
8c6939c0 | 311 | #endif |
facc68be FB |
312 | /* see if we can patch the calling TB. */ |
313 | if (T0 != 0) { | |
3fb2ded1 FB |
314 | spin_lock(&tb_lock); |
315 | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); | |
316 | spin_unlock(&tb_lock); | |
317 | } | |
3fb2ded1 | 318 | tc_ptr = tb->tc_ptr; |
83479e77 | 319 | env->current_tb = tb; |
3fb2ded1 FB |
320 | /* execute the generated code */ |
321 | gen_func = (void *)tc_ptr; | |
8c6939c0 | 322 | #if defined(__sparc__) |
3fb2ded1 FB |
323 | __asm__ __volatile__("call %0\n\t" |
324 | "mov %%o7,%%i0" | |
325 | : /* no outputs */ | |
326 | : "r" (gen_func) | |
327 | : "i0", "i1", "i2", "i3", "i4", "i5"); | |
8c6939c0 | 328 | #elif defined(__arm__) |
3fb2ded1 FB |
329 | asm volatile ("mov pc, %0\n\t" |
330 | ".global exec_loop\n\t" | |
331 | "exec_loop:\n\t" | |
332 | : /* no outputs */ | |
333 | : "r" (gen_func) | |
334 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); | |
ae228531 | 335 | #else |
3fb2ded1 | 336 | gen_func(); |
ae228531 | 337 | #endif |
83479e77 | 338 | env->current_tb = NULL; |
4cbf74b6 FB |
339 | /* reset soft MMU for next block (it can currently |
340 | only be set by a memory fault) */ | |
341 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) | |
3f337316 FB |
342 | if (env->hflags & HF_SOFTMMU_MASK) { |
343 | env->hflags &= ~HF_SOFTMMU_MASK; | |
4cbf74b6 FB |
344 | /* do not allow linking to another block */ |
345 | T0 = 0; | |
346 | } | |
347 | #endif | |
3fb2ded1 FB |
348 | } |
349 | } else { | |
7d13299d | 350 | } |
3fb2ded1 FB |
351 | } /* for(;;) */ |
352 | ||
7d13299d | 353 | |
e4533c7a | 354 | #if defined(TARGET_I386) |
9de5e440 | 355 | /* restore flags in standard format */ |
fc2b4c48 | 356 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
9de5e440 | 357 | |
7d13299d | 358 | /* restore global registers */ |
04369ff2 FB |
359 | #ifdef reg_EAX |
360 | EAX = saved_EAX; | |
361 | #endif | |
362 | #ifdef reg_ECX | |
363 | ECX = saved_ECX; | |
364 | #endif | |
365 | #ifdef reg_EDX | |
366 | EDX = saved_EDX; | |
367 | #endif | |
368 | #ifdef reg_EBX | |
369 | EBX = saved_EBX; | |
370 | #endif | |
371 | #ifdef reg_ESP | |
372 | ESP = saved_ESP; | |
373 | #endif | |
374 | #ifdef reg_EBP | |
375 | EBP = saved_EBP; | |
376 | #endif | |
377 | #ifdef reg_ESI | |
378 | ESI = saved_ESI; | |
379 | #endif | |
380 | #ifdef reg_EDI | |
381 | EDI = saved_EDI; | |
8c6939c0 | 382 | #endif |
e4533c7a | 383 | #elif defined(TARGET_ARM) |
1b21b62a | 384 | env->cpsr = compute_cpsr(); |
93ac68bc | 385 | #elif defined(TARGET_SPARC) |
67867308 | 386 | #elif defined(TARGET_PPC) |
e4533c7a FB |
387 | #else |
388 | #error unsupported target CPU | |
389 | #endif | |
8c6939c0 FB |
390 | #ifdef __sparc__ |
391 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); | |
04369ff2 | 392 | #endif |
7d13299d FB |
393 | T0 = saved_T0; |
394 | T1 = saved_T1; | |
e4533c7a | 395 | T2 = saved_T2; |
7d13299d FB |
396 | env = saved_env; |
397 | return ret; | |
398 | } | |
6dbad63e | 399 | |
1a18c71b | 400 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 401 | |
6dbad63e FB |
402 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
403 | { | |
404 | CPUX86State *saved_env; | |
405 | ||
406 | saved_env = env; | |
407 | env = s; | |
a412ac57 | 408 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 409 | selector &= 0xffff; |
2e255c6b FB |
410 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
411 | (uint8_t *)(selector << 4), 0xffff, 0); | |
a513fe19 FB |
412 | } else { |
413 | load_seg(seg_reg, selector, 0); | |
414 | } | |
6dbad63e FB |
415 | env = saved_env; |
416 | } | |
9de5e440 | 417 | |
d0a1ffc9 FB |
418 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
419 | { | |
420 | CPUX86State *saved_env; | |
421 | ||
422 | saved_env = env; | |
423 | env = s; | |
424 | ||
425 | helper_fsave(ptr, data32); | |
426 | ||
427 | env = saved_env; | |
428 | } | |
429 | ||
430 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) | |
431 | { | |
432 | CPUX86State *saved_env; | |
433 | ||
434 | saved_env = env; | |
435 | env = s; | |
436 | ||
437 | helper_frstor(ptr, data32); | |
438 | ||
439 | env = saved_env; | |
440 | } | |
441 | ||
e4533c7a FB |
442 | #endif /* TARGET_I386 */ |
443 | ||
9de5e440 FB |
444 | #undef EAX |
445 | #undef ECX | |
446 | #undef EDX | |
447 | #undef EBX | |
448 | #undef ESP | |
449 | #undef EBP | |
450 | #undef ESI | |
451 | #undef EDI | |
452 | #undef EIP | |
453 | #include <signal.h> | |
454 | #include <sys/ucontext.h> | |
455 | ||
3fb2ded1 FB |
456 | #if defined(TARGET_I386) |
457 | ||
b56dad1c | 458 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
459 | the effective address of the memory exception. 'is_write' is 1 if a |
460 | write caused the exception and otherwise 0'. 'old_set' is the | |
461 | signal set which should be restored */ | |
2b413144 FB |
462 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
463 | int is_write, sigset_t *old_set) | |
9de5e440 | 464 | { |
a513fe19 FB |
465 | TranslationBlock *tb; |
466 | int ret; | |
68a79315 | 467 | |
83479e77 FB |
468 | if (cpu_single_env) |
469 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 470 | #if defined(DEBUG_SIGNAL) |
3fb2ded1 | 471 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
fd6ce8f6 | 472 | pc, address, is_write, *(unsigned long *)old_set); |
9de5e440 | 473 | #endif |
25eb4484 | 474 | /* XXX: locking issue */ |
fd6ce8f6 | 475 | if (is_write && page_unprotect(address)) { |
fd6ce8f6 FB |
476 | return 1; |
477 | } | |
3fb2ded1 | 478 | /* see if it is an MMU fault */ |
93a40ea9 FB |
479 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
480 | ((env->hflags & HF_CPL_MASK) == 3), 0); | |
3fb2ded1 FB |
481 | if (ret < 0) |
482 | return 0; /* not an MMU fault */ | |
483 | if (ret == 0) | |
484 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
485 | /* now we have a real cpu fault */ | |
a513fe19 FB |
486 | tb = tb_find_pc(pc); |
487 | if (tb) { | |
9de5e440 FB |
488 | /* the PC is inside the translated code. It means that we have |
489 | a virtual CPU fault */ | |
3fb2ded1 FB |
490 | cpu_restore_state(tb, env, pc); |
491 | } | |
4cbf74b6 | 492 | if (ret == 1) { |
3fb2ded1 | 493 | #if 0 |
4cbf74b6 FB |
494 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
495 | env->eip, env->cr[2], env->error_code); | |
3fb2ded1 | 496 | #endif |
4cbf74b6 FB |
497 | /* we restore the process signal mask as the sigreturn should |
498 | do it (XXX: use sigsetjmp) */ | |
499 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
500 | raise_exception_err(EXCP0E_PAGE, env->error_code); | |
501 | } else { | |
502 | /* activate soft MMU for this block */ | |
3f337316 | 503 | env->hflags |= HF_SOFTMMU_MASK; |
4cbf74b6 FB |
504 | sigprocmask(SIG_SETMASK, old_set, NULL); |
505 | cpu_loop_exit(); | |
506 | } | |
3fb2ded1 FB |
507 | /* never comes here */ |
508 | return 1; | |
509 | } | |
510 | ||
e4533c7a | 511 | #elif defined(TARGET_ARM) |
3fb2ded1 FB |
512 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
513 | int is_write, sigset_t *old_set) | |
514 | { | |
515 | /* XXX: do more */ | |
516 | return 0; | |
517 | } | |
93ac68bc FB |
518 | #elif defined(TARGET_SPARC) |
519 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
520 | int is_write, sigset_t *old_set) | |
521 | { | |
522 | return 0; | |
523 | } | |
67867308 FB |
524 | #elif defined (TARGET_PPC) |
525 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
526 | int is_write, sigset_t *old_set) | |
527 | { | |
528 | TranslationBlock *tb; | |
529 | ||
530 | #if 0 | |
531 | if (cpu_single_env) | |
532 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
533 | #endif | |
534 | #if defined(DEBUG_SIGNAL) | |
535 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
536 | pc, address, is_write, *(unsigned long *)old_set); | |
537 | #endif | |
538 | /* XXX: locking issue */ | |
539 | if (is_write && page_unprotect(address)) { | |
540 | return 1; | |
541 | } | |
542 | ||
543 | /* now we have a real cpu fault */ | |
544 | tb = tb_find_pc(pc); | |
545 | if (tb) { | |
546 | /* the PC is inside the translated code. It means that we have | |
547 | a virtual CPU fault */ | |
548 | cpu_restore_state(tb, env, pc); | |
549 | } | |
550 | #if 0 | |
551 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", | |
552 | env->eip, env->cr[2], env->error_code); | |
553 | #endif | |
554 | /* we restore the process signal mask as the sigreturn should | |
555 | do it (XXX: use sigsetjmp) */ | |
556 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
557 | raise_exception_err(EXCP_PROGRAM, env->error_code); | |
558 | /* never comes here */ | |
559 | return 1; | |
560 | } | |
e4533c7a FB |
561 | #else |
562 | #error unsupported target CPU | |
563 | #endif | |
9de5e440 | 564 | |
2b413144 FB |
565 | #if defined(__i386__) |
566 | ||
e4533c7a FB |
567 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
568 | void *puc) | |
9de5e440 | 569 | { |
9de5e440 FB |
570 | struct ucontext *uc = puc; |
571 | unsigned long pc; | |
9de5e440 | 572 | |
d691f669 FB |
573 | #ifndef REG_EIP |
574 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
575 | #define REG_EIP EIP |
576 | #define REG_ERR ERR | |
577 | #define REG_TRAPNO TRAPNO | |
d691f669 | 578 | #endif |
fc2b4c48 | 579 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
fd6ce8f6 FB |
580 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
581 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
582 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
2b413144 FB |
583 | &uc->uc_sigmask); |
584 | } | |
585 | ||
25eb4484 | 586 | #elif defined(__powerpc) |
2b413144 | 587 | |
e4533c7a FB |
588 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
589 | void *puc) | |
2b413144 | 590 | { |
25eb4484 FB |
591 | struct ucontext *uc = puc; |
592 | struct pt_regs *regs = uc->uc_mcontext.regs; | |
593 | unsigned long pc; | |
25eb4484 FB |
594 | int is_write; |
595 | ||
596 | pc = regs->nip; | |
25eb4484 FB |
597 | is_write = 0; |
598 | #if 0 | |
599 | /* ppc 4xx case */ | |
600 | if (regs->dsisr & 0x00800000) | |
601 | is_write = 1; | |
602 | #else | |
603 | if (regs->trap != 0x400 && (regs->dsisr & 0x02000000)) | |
604 | is_write = 1; | |
605 | #endif | |
606 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
2b413144 FB |
607 | is_write, &uc->uc_sigmask); |
608 | } | |
609 | ||
2f87c607 FB |
610 | #elif defined(__alpha__) |
611 | ||
e4533c7a | 612 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
2f87c607 FB |
613 | void *puc) |
614 | { | |
615 | struct ucontext *uc = puc; | |
616 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
617 | uint32_t insn = *pc; | |
618 | int is_write = 0; | |
619 | ||
8c6939c0 | 620 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
621 | switch (insn >> 26) { |
622 | case 0x0d: // stw | |
623 | case 0x0e: // stb | |
624 | case 0x0f: // stq_u | |
625 | case 0x24: // stf | |
626 | case 0x25: // stg | |
627 | case 0x26: // sts | |
628 | case 0x27: // stt | |
629 | case 0x2c: // stl | |
630 | case 0x2d: // stq | |
631 | case 0x2e: // stl_c | |
632 | case 0x2f: // stq_c | |
633 | is_write = 1; | |
634 | } | |
635 | ||
636 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
637 | is_write, &uc->uc_sigmask); | |
638 | } | |
8c6939c0 FB |
639 | #elif defined(__sparc__) |
640 | ||
e4533c7a FB |
641 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
642 | void *puc) | |
8c6939c0 FB |
643 | { |
644 | uint32_t *regs = (uint32_t *)(info + 1); | |
645 | void *sigmask = (regs + 20); | |
646 | unsigned long pc; | |
647 | int is_write; | |
648 | uint32_t insn; | |
649 | ||
650 | /* XXX: is there a standard glibc define ? */ | |
651 | pc = regs[1]; | |
652 | /* XXX: need kernel patch to get write flag faster */ | |
653 | is_write = 0; | |
654 | insn = *(uint32_t *)pc; | |
655 | if ((insn >> 30) == 3) { | |
656 | switch((insn >> 19) & 0x3f) { | |
657 | case 0x05: // stb | |
658 | case 0x06: // sth | |
659 | case 0x04: // st | |
660 | case 0x07: // std | |
661 | case 0x24: // stf | |
662 | case 0x27: // stdf | |
663 | case 0x25: // stfsr | |
664 | is_write = 1; | |
665 | break; | |
666 | } | |
667 | } | |
668 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
669 | is_write, sigmask); | |
670 | } | |
671 | ||
672 | #elif defined(__arm__) | |
673 | ||
e4533c7a FB |
674 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
675 | void *puc) | |
8c6939c0 FB |
676 | { |
677 | struct ucontext *uc = puc; | |
678 | unsigned long pc; | |
679 | int is_write; | |
680 | ||
681 | pc = uc->uc_mcontext.gregs[R15]; | |
682 | /* XXX: compute is_write */ | |
683 | is_write = 0; | |
684 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
685 | is_write, | |
686 | &uc->uc_sigmask); | |
687 | } | |
688 | ||
38e584a0 FB |
689 | #elif defined(__mc68000) |
690 | ||
691 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
692 | void *puc) | |
693 | { | |
694 | struct ucontext *uc = puc; | |
695 | unsigned long pc; | |
696 | int is_write; | |
697 | ||
698 | pc = uc->uc_mcontext.gregs[16]; | |
699 | /* XXX: compute is_write */ | |
700 | is_write = 0; | |
701 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
702 | is_write, | |
703 | &uc->uc_sigmask); | |
704 | } | |
705 | ||
9de5e440 | 706 | #else |
2b413144 | 707 | |
3fb2ded1 | 708 | #error host CPU specific signal handler needed |
2b413144 | 709 | |
9de5e440 | 710 | #endif |