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Sanitize mips exception handling.
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
e6e5906b 43#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
e6e5906b 50#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
3475187d
FB		 51#define reg_T2
52#endif
e4533c7a 53
fbf9eeb3
FB		 54/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
8a40a180
FB		 76
77static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80{
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
15388002 129 tb_invalidated_flag = 1;
8a40a180
FB		 130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
8a40a180
FB		 147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151}
152
153static inline TranslationBlock *tb_find_fast(void)
154{
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162#if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167#elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
b5ff1b31
FB		 169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
40f137e1
PB		 172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
8a40a180
FB		 174 cs_base = 0;
175 pc = env->regs[15];
176#elif defined(TARGET_SPARC)
177#ifdef TARGET_SPARC64
a80dde08
FB		 178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
8a40a180 181#else
a80dde08
FB		 182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
8a40a180
FB		 185#endif
186 cs_base = env->npc;
187 pc = env->pc;
188#elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193#elif defined(TARGET_MIPS)
56b19403 194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cc9442b9 195 cs_base = 0;
8a40a180 196 pc = env->PC;
e6e5906b
PB		 197#elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
199 cs_base = 0;
200 pc = env->pc;
fdf9b3e8
FB		 201#elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
204 pc = env->pc;
8a40a180
FB		 205#else
206#error unsupported CPU
207#endif
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
15388002
FB		 212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
218 T0 = 0;
219 }
8a40a180
FB		 220 }
221 return tb;
222}
223
224
7d13299d
FB		 225/* main execution loop */
226
e4533c7a 227int cpu_exec(CPUState *env1)
7d13299d 228{
1057eaa7
PB		 229#define DECLARE_HOST_REGS 1
230#include "hostregs_helper.h"
231#if defined(TARGET_SPARC)
3475187d
FB		 232#if defined(reg_REGWPTR)
233 uint32_t *saved_regwptr;
234#endif
235#endif
fdbb4691 236#if defined(__sparc__) && !defined(HOST_SOLARIS)
b49d07ba
TS		 237 int saved_i7;
238 target_ulong tmp_T0;
04369ff2 239#endif
8a40a180 240 int ret, interrupt_request;
7d13299d 241 void (*gen_func)(void);
8a40a180 242 TranslationBlock *tb;
c27004ec 243 uint8_t *tc_ptr;
8c6939c0 244
5a1e3cfc
FB		 245#if defined(TARGET_I386)
246 /* handle exit of HALTED state */
247 if (env1->hflags & HF_HALTED_MASK) {
248 /* disable halt condition */
249 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
250 (env1->eflags & IF_MASK)) {
251 env1->hflags &= ~HF_HALTED_MASK;
252 } else {
253 return EXCP_HALTED;
e80e1cc4
FB		 254 }
255 }
256#elif defined(TARGET_PPC)
50443c98 257 if (env1->halted) {
e80e1cc4 258 if (env1->msr[MSR_EE] &&
47103572 259 (env1->interrupt_request & CPU_INTERRUPT_HARD)) {
50443c98 260 env1->halted = 0;
e80e1cc4
FB		 261 } else {
262 return EXCP_HALTED;
5a1e3cfc
FB		 263 }
264 }
ba3c64fb
FB		 265#elif defined(TARGET_SPARC)
266 if (env1->halted) {
267 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
268 (env1->psret != 0)) {
269 env1->halted = 0;
270 } else {
271 return EXCP_HALTED;
272 }
273 }
9332f9da
FB		 274#elif defined(TARGET_ARM)
275 if (env1->halted) {
276 /* An interrupt wakes the CPU even if the I and F CPSR bits are
277 set. */
278 if (env1->interrupt_request
279 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
280 env1->halted = 0;
281 } else {
282 return EXCP_HALTED;
283 }
284 }
6810e154
FB		 285#elif defined(TARGET_MIPS)
286 if (env1->halted) {
287 if (env1->interrupt_request &
288 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
289 env1->halted = 0;
290 } else {
291 return EXCP_HALTED;
292 }
293 }
5a1e3cfc
FB		 294#endif
295
6a00d601
FB		 296 cpu_single_env = env1;
297
7d13299d 298 /* first we save global registers */
1057eaa7
PB		 299#define SAVE_HOST_REGS 1
300#include "hostregs_helper.h"
c27004ec 301 env = env1;
fdbb4691 302#if defined(__sparc__) && !defined(HOST_SOLARIS)
e4533c7a
FB		 303 /* we also save i7 because longjmp may not restore it */
304 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
305#endif
306
307#if defined(TARGET_I386)
0d1a29f9 308 env_to_regs();
9de5e440 309 /* put eflags in CPU temporary format */
fc2b4c48
FB		 310 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
311 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 312 CC_OP = CC_OP_EFLAGS;
fc2b4c48 313 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 314#elif defined(TARGET_ARM)
93ac68bc 315#elif defined(TARGET_SPARC)
3475187d
FB		 316#if defined(reg_REGWPTR)
317 saved_regwptr = REGWPTR;
318#endif
67867308 319#elif defined(TARGET_PPC)
e6e5906b
PB		 320#elif defined(TARGET_M68K)
321 env->cc_op = CC_OP_FLAGS;
322 env->cc_dest = env->sr & 0xf;
323 env->cc_x = (env->sr >> 4) & 1;
6af0bf9c 324#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 325#elif defined(TARGET_SH4)
326 /* XXXXX */
e4533c7a
FB		 327#else
328#error unsupported target CPU
329#endif
3fb2ded1 330 env->exception_index = -1;
9d27abd9 331
7d13299d 332 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 333 for(;;) {
334 if (setjmp(env->jmp_env) == 0) {
ee8b7021 335 env->current_tb = NULL;
3fb2ded1
FB		 336 /* if an exception is pending, we execute it here */
337 if (env->exception_index >= 0) {
338 if (env->exception_index >= EXCP_INTERRUPT) {
339 /* exit request from the cpu execution loop */
340 ret = env->exception_index;
341 break;
342 } else if (env->user_mode_only) {
343 /* if user mode only, we simulate a fake exception
9f083493 344 which will be handled outside the cpu execution
3fb2ded1 345 loop */
83479e77 346#if defined(TARGET_I386)
3fb2ded1
FB		 347 do_interrupt_user(env->exception_index,
348 env->exception_is_int,
349 env->error_code,
350 env->exception_next_eip);
83479e77 351#endif
3fb2ded1
FB		 352 ret = env->exception_index;
353 break;
354 } else {
83479e77 355#if defined(TARGET_I386)
3fb2ded1
FB		 356 /* simulate a real cpu exception. On i386, it can
357 trigger new exceptions, but we do not handle
358 double or triple faults yet. */
359 do_interrupt(env->exception_index,
360 env->exception_is_int,
361 env->error_code,
d05e66d2 362 env->exception_next_eip, 0);
ce09776b
FB		 363#elif defined(TARGET_PPC)
364 do_interrupt(env);
6af0bf9c
FB		 365#elif defined(TARGET_MIPS)
366 do_interrupt(env);
e95c8d51 367#elif defined(TARGET_SPARC)
1a0c3292 368 do_interrupt(env->exception_index);
b5ff1b31
FB		 369#elif defined(TARGET_ARM)
370 do_interrupt(env);
fdf9b3e8
FB		 371#elif defined(TARGET_SH4)
372 do_interrupt(env);
83479e77 373#endif
3fb2ded1
FB		 374 }
375 env->exception_index = -1;
9df217a3
FB		 376 }
377#ifdef USE_KQEMU
378 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
379 int ret;
380 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
381 ret = kqemu_cpu_exec(env);
382 /* put eflags in CPU temporary format */
383 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
384 DF = 1 - (2 * ((env->eflags >> 10) & 1));
385 CC_OP = CC_OP_EFLAGS;
386 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
387 if (ret == 1) {
388 /* exception */
389 longjmp(env->jmp_env, 1);
390 } else if (ret == 2) {
391 /* softmmu execution needed */
392 } else {
393 if (env->interrupt_request != 0) {
394 /* hardware interrupt will be executed just after */
395 } else {
396 /* otherwise, we restart */
397 longjmp(env->jmp_env, 1);
398 }
399 }
3fb2ded1 400 }
9df217a3
FB		 401#endif
402
3fb2ded1
FB		 403 T0 = 0; /* force lookup of first TB */
404 for(;;) {
fdbb4691 405#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1
FB		 406 /* g1 can be modified by some libc? functions */
407 tmp_T0 = T0;
8c6939c0 408#endif
68a79315 409 interrupt_request = env->interrupt_request;
2e255c6b 410 if (__builtin_expect(interrupt_request, 0)) {
6658ffb8
PB		 411 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
412 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
413 env->exception_index = EXCP_DEBUG;
414 cpu_loop_exit();
415 }
68a79315 416#if defined(TARGET_I386)
3b21e03e
FB		 417 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
418 !(env->hflags & HF_SMM_MASK)) {
419 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
420 do_smm_enter();
421#if defined(__sparc__) && !defined(HOST_SOLARIS)
422 tmp_T0 = 0;
423#else
424 T0 = 0;
425#endif
426 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 427 (env->eflags & IF_MASK) &&
428 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 429 int intno;
fbf9eeb3 430 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 431 intno = cpu_get_pic_interrupt(env);
f193c797 432 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 433 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
434 }
d05e66d2 435 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 436 /* ensure that no TB jump will be modified as
437 the program flow was changed */
fdbb4691 438#if defined(__sparc__) && !defined(HOST_SOLARIS)
907a5b26
FB		 439 tmp_T0 = 0;
440#else
441 T0 = 0;
442#endif
68a79315 443 }
ce09776b 444#elif defined(TARGET_PPC)
9fddaa0c
FB		 445#if 0
446 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
447 cpu_ppc_reset(env);
448 }
449#endif
47103572
JM		 450 if (interrupt_request & CPU_INTERRUPT_HARD) {
451 if (ppc_hw_interrupt(env) == 1) {
452 /* Some exception was raised */
453 if (env->pending_interrupts == 0)
454 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
fdbb4691 455#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 456 tmp_T0 = 0;
457#else
458 T0 = 0;
459#endif
460 }
ce09776b 461 }
6af0bf9c
FB		 462#elif defined(TARGET_MIPS)
463 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 464 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 465 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 466 !(env->CP0_Status & (1 << CP0St_EXL)) &&
467 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 468 !(env->hflags & MIPS_HFLAG_DM)) {
469 /* Raise it */
470 env->exception_index = EXCP_EXT_INTERRUPT;
471 env->error_code = 0;
472 do_interrupt(env);
fdbb4691 473#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 474 tmp_T0 = 0;
475#else
476 T0 = 0;
477#endif
6af0bf9c 478 }
e95c8d51 479#elif defined(TARGET_SPARC)
66321a11
FB		 480 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
481 (env->psret != 0)) {
482 int pil = env->interrupt_index & 15;
483 int type = env->interrupt_index & 0xf0;
484
485 if (((type == TT_EXTINT) &&
486 (pil == 15 || pil > env->psrpil)) ||
487 type != TT_EXTINT) {
488 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
489 do_interrupt(env->interrupt_index);
490 env->interrupt_index = 0;
fdbb4691 491#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 492 tmp_T0 = 0;
493#else
494 T0 = 0;
495#endif
66321a11 496 }
e95c8d51
FB		 497 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
498 //do_interrupt(0, 0, 0, 0, 0);
499 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
ba3c64fb 500 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
df52b000
FB		 501 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
502 env->halted = 1;
503 env->exception_index = EXCP_HLT;
504 cpu_loop_exit();
ba3c64fb 505 }
b5ff1b31
FB		 506#elif defined(TARGET_ARM)
507 if (interrupt_request & CPU_INTERRUPT_FIQ
508 && !(env->uncached_cpsr & CPSR_F)) {
509 env->exception_index = EXCP_FIQ;
510 do_interrupt(env);
511 }
512 if (interrupt_request & CPU_INTERRUPT_HARD
513 && !(env->uncached_cpsr & CPSR_I)) {
514 env->exception_index = EXCP_IRQ;
515 do_interrupt(env);
516 }
fdf9b3e8
FB		 517#elif defined(TARGET_SH4)
518 /* XXXXX */
68a79315 519#endif
9d05095e
FB		 520 /* Don't use the cached interupt_request value,
521 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 522 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 523 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
524 /* ensure that no TB jump will be modified as
525 the program flow was changed */
fdbb4691 526#if defined(__sparc__) && !defined(HOST_SOLARIS)
bf3e8bf1
FB		 527 tmp_T0 = 0;
528#else
529 T0 = 0;
530#endif
531 }
68a79315
FB		 532 if (interrupt_request & CPU_INTERRUPT_EXIT) {
533 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
534 env->exception_index = EXCP_INTERRUPT;
535 cpu_loop_exit();
536 }
3fb2ded1 537 }
7d13299d 538#ifdef DEBUG_EXEC
b5ff1b31 539 if ((loglevel & CPU_LOG_TB_CPU)) {
e4533c7a 540#if defined(TARGET_I386)
3fb2ded1 541 /* restore flags in standard format */
fc9f715d 542#ifdef reg_EAX
3fb2ded1 543 env->regs[R_EAX] = EAX;
fc9f715d
FB		 544#endif
545#ifdef reg_EBX
3fb2ded1 546 env->regs[R_EBX] = EBX;
fc9f715d
FB		 547#endif
548#ifdef reg_ECX
3fb2ded1 549 env->regs[R_ECX] = ECX;
fc9f715d
FB		 550#endif
551#ifdef reg_EDX
3fb2ded1 552 env->regs[R_EDX] = EDX;
fc9f715d
FB		 553#endif
554#ifdef reg_ESI
3fb2ded1 555 env->regs[R_ESI] = ESI;
fc9f715d
FB		 556#endif
557#ifdef reg_EDI
3fb2ded1 558 env->regs[R_EDI] = EDI;
fc9f715d
FB		 559#endif
560#ifdef reg_EBP
3fb2ded1 561 env->regs[R_EBP] = EBP;
fc9f715d
FB		 562#endif
563#ifdef reg_ESP
3fb2ded1 564 env->regs[R_ESP] = ESP;
fc9f715d 565#endif
3fb2ded1 566 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 567 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 568 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 569#elif defined(TARGET_ARM)
7fe48483 570 cpu_dump_state(env, logfile, fprintf, 0);
93ac68bc 571#elif defined(TARGET_SPARC)
3475187d
FB		 572 REGWPTR = env->regbase + (env->cwp * 16);
573 env->regwptr = REGWPTR;
574 cpu_dump_state(env, logfile, fprintf, 0);
67867308 575#elif defined(TARGET_PPC)
7fe48483 576 cpu_dump_state(env, logfile, fprintf, 0);
e6e5906b
PB		 577#elif defined(TARGET_M68K)
578 cpu_m68k_flush_flags(env, env->cc_op);
579 env->cc_op = CC_OP_FLAGS;
580 env->sr = (env->sr & 0xffe0)
581 | env->cc_dest | (env->cc_x << 4);
582 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 583#elif defined(TARGET_MIPS)
584 cpu_dump_state(env, logfile, fprintf, 0);
fdf9b3e8
FB		 585#elif defined(TARGET_SH4)
586 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 587#else
588#error unsupported target CPU
589#endif
3fb2ded1 590 }
7d13299d 591#endif
8a40a180 592 tb = tb_find_fast();
9d27abd9 593#ifdef DEBUG_EXEC
c1135f61 594 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 595 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
596 (long)tb->tc_ptr, tb->pc,
597 lookup_symbol(tb->pc));
3fb2ded1 598 }
9d27abd9 599#endif
fdbb4691 600#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1 601 T0 = tmp_T0;
8c6939c0 602#endif
8a40a180
FB		 603 /* see if we can patch the calling TB. When the TB
604 spans two pages, we cannot safely do a direct
605 jump. */
c27004ec 606 {
8a40a180 607 if (T0 != 0 &&
f32fc648
FB		 608#if USE_KQEMU
609 (env->kqemu_enabled != 2) &&
610#endif
8a40a180 611 tb->page_addr[1] == -1
bf3e8bf1
FB		 612#if defined(TARGET_I386) && defined(USE_CODE_COPY)
613 && (tb->cflags & CF_CODE_COPY) ==
614 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
615#endif
616 ) {
3fb2ded1 617 spin_lock(&tb_lock);
c27004ec 618 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 619#if defined(USE_CODE_COPY)
620 /* propagates the FP use info */
621 ((TranslationBlock *)(T0 & ~3))->cflags |=
622 (tb->cflags & CF_FP_USED);
623#endif
3fb2ded1
FB		 624 spin_unlock(&tb_lock);
625 }
c27004ec 626 }
3fb2ded1 627 tc_ptr = tb->tc_ptr;
83479e77 628 env->current_tb = tb;
3fb2ded1
FB		 629 /* execute the generated code */
630 gen_func = (void *)tc_ptr;
8c6939c0 631#if defined(__sparc__)
3fb2ded1
FB		 632 __asm__ __volatile__("call %0\n\t"
633 "mov %%o7,%%i0"
634 : /* no outputs */
635 : "r" (gen_func)
fdbb4691 636 : "i0", "i1", "i2", "i3", "i4", "i5",
faab7592 637 "o0", "o1", "o2", "o3", "o4", "o5",
fdbb4691
FB		 638 "l0", "l1", "l2", "l3", "l4", "l5",
639 "l6", "l7");
8c6939c0 640#elif defined(__arm__)
3fb2ded1
FB		 641 asm volatile ("mov pc, %0\n\t"
642 ".global exec_loop\n\t"
643 "exec_loop:\n\t"
644 : /* no outputs */
645 : "r" (gen_func)
646 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 647#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
648{
649 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 650 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
651 save_native_fp_state(env);
652 }
bf3e8bf1
FB		 653 gen_func();
654 } else {
97eb5b14
FB		 655 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
656 restore_native_fp_state(env);
657 }
bf3e8bf1
FB		 658 /* we work with native eflags */
659 CC_SRC = cc_table[CC_OP].compute_all();
660 CC_OP = CC_OP_EFLAGS;
661 asm(".globl exec_loop\n"
662 "\n"
663 "debug1:\n"
664 " pushl %%ebp\n"
665 " fs movl %10, %9\n"
666 " fs movl %11, %%eax\n"
667 " andl $0x400, %%eax\n"
668 " fs orl %8, %%eax\n"
669 " pushl %%eax\n"
670 " popf\n"
671 " fs movl %%esp, %12\n"
672 " fs movl %0, %%eax\n"
673 " fs movl %1, %%ecx\n"
674 " fs movl %2, %%edx\n"
675 " fs movl %3, %%ebx\n"
676 " fs movl %4, %%esp\n"
677 " fs movl %5, %%ebp\n"
678 " fs movl %6, %%esi\n"
679 " fs movl %7, %%edi\n"
680 " fs jmp *%9\n"
681 "exec_loop:\n"
682 " fs movl %%esp, %4\n"
683 " fs movl %12, %%esp\n"
684 " fs movl %%eax, %0\n"
685 " fs movl %%ecx, %1\n"
686 " fs movl %%edx, %2\n"
687 " fs movl %%ebx, %3\n"
688 " fs movl %%ebp, %5\n"
689 " fs movl %%esi, %6\n"
690 " fs movl %%edi, %7\n"
691 " pushf\n"
692 " popl %%eax\n"
693 " movl %%eax, %%ecx\n"
694 " andl $0x400, %%ecx\n"
695 " shrl $9, %%ecx\n"
696 " andl $0x8d5, %%eax\n"
697 " fs movl %%eax, %8\n"
698 " movl $1, %%eax\n"
699 " subl %%ecx, %%eax\n"
700 " fs movl %%eax, %11\n"
701 " fs movl %9, %%ebx\n" /* get T0 value */
702 " popl %%ebp\n"
703 :
704 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
705 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
706 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
707 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
708 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
709 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
710 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
711 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
712 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
713 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
714 "a" (gen_func),
715 "m" (*(uint8_t *)offsetof(CPUState, df)),
716 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
717 : "%ecx", "%edx"
718 );
719 }
720}
b8076a74
FB		 721#elif defined(__ia64)
722 struct fptr {
723 void *ip;
724 void *gp;
725 } fp;
726
727 fp.ip = tc_ptr;
728 fp.gp = code_gen_buffer + 2 * (1 << 20);
729 (*(void (*)(void)) &fp)();
ae228531 730#else
3fb2ded1 731 gen_func();
ae228531 732#endif
83479e77 733 env->current_tb = NULL;
4cbf74b6
FB		 734 /* reset soft MMU for next block (it can currently
735 only be set by a memory fault) */
736#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 737 if (env->hflags & HF_SOFTMMU_MASK) {
738 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 739 /* do not allow linking to another block */
740 T0 = 0;
741 }
f32fc648
FB		 742#endif
743#if defined(USE_KQEMU)
744#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
745 if (kqemu_is_ok(env) &&
746 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
747 cpu_loop_exit();
748 }
4cbf74b6 749#endif
3fb2ded1
FB		 750 }
751 } else {
0d1a29f9 752 env_to_regs();
7d13299d 753 }
3fb2ded1
FB		 754 } /* for(;;) */
755
7d13299d 756
e4533c7a 757#if defined(TARGET_I386)
97eb5b14
FB		 758#if defined(USE_CODE_COPY)
759 if (env->native_fp_regs) {
760 save_native_fp_state(env);
761 }
762#endif
9de5e440 763 /* restore flags in standard format */
fc2b4c48 764 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
e4533c7a 765#elif defined(TARGET_ARM)
b7bcbe95 766 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 767#elif defined(TARGET_SPARC)
3475187d
FB		 768#if defined(reg_REGWPTR)
769 REGWPTR = saved_regwptr;
770#endif
67867308 771#elif defined(TARGET_PPC)
e6e5906b
PB		 772#elif defined(TARGET_M68K)
773 cpu_m68k_flush_flags(env, env->cc_op);
774 env->cc_op = CC_OP_FLAGS;
775 env->sr = (env->sr & 0xffe0)
776 | env->cc_dest | (env->cc_x << 4);
6af0bf9c 777#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 778#elif defined(TARGET_SH4)
779 /* XXXXX */
e4533c7a
FB		 780#else
781#error unsupported target CPU
782#endif
1057eaa7
PB		 783
784 /* restore global registers */
fdbb4691 785#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 786 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 787#endif
1057eaa7
PB		 788#include "hostregs_helper.h"
789
6a00d601
FB		 790 /* fail safe : never use cpu_single_env outside cpu_exec() */
791 cpu_single_env = NULL;
7d13299d
FB		 792 return ret;
793}
6dbad63e 794
fbf9eeb3
FB		 795/* must only be called from the generated code as an exception can be
796 generated */
797void tb_invalidate_page_range(target_ulong start, target_ulong end)
798{
dc5d0b3d
FB		 799 /* XXX: cannot enable it yet because it yields to MMU exception
800 where NIP != read address on PowerPC */
801#if 0
fbf9eeb3
FB		 802 target_ulong phys_addr;
803 phys_addr = get_phys_addr_code(env, start);
804 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 805#endif
fbf9eeb3
FB		 806}
807
1a18c71b 808#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 809
6dbad63e
FB		 810void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
811{
812 CPUX86State *saved_env;
813
814 saved_env = env;
815 env = s;
a412ac57 816 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 817 selector &= 0xffff;
2e255c6b 818 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 819 (selector << 4), 0xffff, 0);
a513fe19 820 } else {
b453b70b 821 load_seg(seg_reg, selector);
a513fe19 822 }
6dbad63e
FB		 823 env = saved_env;
824}
9de5e440 825
d0a1ffc9
FB		 826void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
827{
828 CPUX86State *saved_env;
829
830 saved_env = env;
831 env = s;
832
c27004ec 833 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 834
835 env = saved_env;
836}
837
838void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
839{
840 CPUX86State *saved_env;
841
842 saved_env = env;
843 env = s;
844
c27004ec 845 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 846
847 env = saved_env;
848}
849
e4533c7a
FB		 850#endif /* TARGET_I386 */
851
67b915a5
FB		 852#if !defined(CONFIG_SOFTMMU)
853
3fb2ded1
FB		 854#if defined(TARGET_I386)
855
b56dad1c 856/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 857 the effective address of the memory exception. 'is_write' is 1 if a
858 write caused the exception and otherwise 0'. 'old_set' is the
859 signal set which should be restored */
2b413144 860static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 861 int is_write, sigset_t *old_set,
862 void *puc)
9de5e440 863{
a513fe19
FB		 864 TranslationBlock *tb;
865 int ret;
68a79315 866
83479e77
FB		 867 if (cpu_single_env)
868 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 869#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 870 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
871 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 872#endif
25eb4484 873 /* XXX: locking issue */
53a5960a 874 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 875 return 1;
876 }
fbf9eeb3 877
3fb2ded1 878 /* see if it is an MMU fault */
93a40ea9
FB		 879 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
880 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 881 if (ret < 0)
882 return 0; /* not an MMU fault */
883 if (ret == 0)
884 return 1; /* the MMU fault was handled without causing real CPU fault */
885 /* now we have a real cpu fault */
a513fe19
FB		 886 tb = tb_find_pc(pc);
887 if (tb) {
9de5e440
FB		 888 /* the PC is inside the translated code. It means that we have
889 a virtual CPU fault */
bf3e8bf1 890 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 891 }
4cbf74b6 892 if (ret == 1) {
3fb2ded1 893#if 0
4cbf74b6
FB		 894 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
895 env->eip, env->cr[2], env->error_code);
3fb2ded1 896#endif
4cbf74b6
FB		 897 /* we restore the process signal mask as the sigreturn should
898 do it (XXX: use sigsetjmp) */
899 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 900 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 901 } else {
902 /* activate soft MMU for this block */
3f337316 903 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 904 cpu_resume_from_signal(env, puc);
4cbf74b6 905 }
3fb2ded1
FB		 906 /* never comes here */
907 return 1;
908}
909
e4533c7a 910#elif defined(TARGET_ARM)
3fb2ded1 911static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 912 int is_write, sigset_t *old_set,
913 void *puc)
3fb2ded1 914{
68016c62
FB		 915 TranslationBlock *tb;
916 int ret;
917
918 if (cpu_single_env)
919 env = cpu_single_env; /* XXX: find a correct solution for multithread */
920#if defined(DEBUG_SIGNAL)
921 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
922 pc, address, is_write, *(unsigned long *)old_set);
923#endif
9f0777ed 924 /* XXX: locking issue */
53a5960a 925 if (is_write && page_unprotect(h2g(address), pc, puc)) {
9f0777ed
FB		 926 return 1;
927 }
68016c62
FB		 928 /* see if it is an MMU fault */
929 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
930 if (ret < 0)
931 return 0; /* not an MMU fault */
932 if (ret == 0)
933 return 1; /* the MMU fault was handled without causing real CPU fault */
934 /* now we have a real cpu fault */
935 tb = tb_find_pc(pc);
936 if (tb) {
937 /* the PC is inside the translated code. It means that we have
938 a virtual CPU fault */
939 cpu_restore_state(tb, env, pc, puc);
940 }
941 /* we restore the process signal mask as the sigreturn should
942 do it (XXX: use sigsetjmp) */
943 sigprocmask(SIG_SETMASK, old_set, NULL);
944 cpu_loop_exit();
3fb2ded1 945}
93ac68bc
FB		 946#elif defined(TARGET_SPARC)
947static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 948 int is_write, sigset_t *old_set,
949 void *puc)
93ac68bc 950{
68016c62
FB		 951 TranslationBlock *tb;
952 int ret;
953
954 if (cpu_single_env)
955 env = cpu_single_env; /* XXX: find a correct solution for multithread */
956#if defined(DEBUG_SIGNAL)
957 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
958 pc, address, is_write, *(unsigned long *)old_set);
959#endif
b453b70b 960 /* XXX: locking issue */
53a5960a 961 if (is_write && page_unprotect(h2g(address), pc, puc)) {
b453b70b
FB		 962 return 1;
963 }
68016c62
FB		 964 /* see if it is an MMU fault */
965 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
966 if (ret < 0)
967 return 0; /* not an MMU fault */
968 if (ret == 0)
969 return 1; /* the MMU fault was handled without causing real CPU fault */
970 /* now we have a real cpu fault */
971 tb = tb_find_pc(pc);
972 if (tb) {
973 /* the PC is inside the translated code. It means that we have
974 a virtual CPU fault */
975 cpu_restore_state(tb, env, pc, puc);
976 }
977 /* we restore the process signal mask as the sigreturn should
978 do it (XXX: use sigsetjmp) */
979 sigprocmask(SIG_SETMASK, old_set, NULL);
980 cpu_loop_exit();
93ac68bc 981}
67867308
FB		 982#elif defined (TARGET_PPC)
983static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 984 int is_write, sigset_t *old_set,
985 void *puc)
67867308
FB		 986{
987 TranslationBlock *tb;
ce09776b 988 int ret;
67867308 989
67867308
FB		 990 if (cpu_single_env)
991 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 992#if defined(DEBUG_SIGNAL)
993 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
994 pc, address, is_write, *(unsigned long *)old_set);
995#endif
996 /* XXX: locking issue */
53a5960a 997 if (is_write && page_unprotect(h2g(address), pc, puc)) {
67867308
FB		 998 return 1;
999 }
1000
ce09776b 1001 /* see if it is an MMU fault */
7f957d28 1002 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 1003 if (ret < 0)
1004 return 0; /* not an MMU fault */
1005 if (ret == 0)
1006 return 1; /* the MMU fault was handled without causing real CPU fault */
1007
67867308
FB		 1008 /* now we have a real cpu fault */
1009 tb = tb_find_pc(pc);
1010 if (tb) {
1011 /* the PC is inside the translated code. It means that we have
1012 a virtual CPU fault */
bf3e8bf1 1013 cpu_restore_state(tb, env, pc, puc);
67867308 1014 }
ce09776b 1015 if (ret == 1) {
67867308 1016#if 0
ce09776b
FB		 1017 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1018 env->nip, env->error_code, tb);
67867308
FB		 1019#endif
1020 /* we restore the process signal mask as the sigreturn should
1021 do it (XXX: use sigsetjmp) */
bf3e8bf1 1022 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 1023 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 1024 } else {
1025 /* activate soft MMU for this block */
fbf9eeb3 1026 cpu_resume_from_signal(env, puc);
ce09776b 1027 }
67867308 1028 /* never comes here */
e6e5906b
PB		 1029 return 1;
1030}
1031
1032#elif defined(TARGET_M68K)
1033static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1034 int is_write, sigset_t *old_set,
1035 void *puc)
1036{
1037 TranslationBlock *tb;
1038 int ret;
1039
1040 if (cpu_single_env)
1041 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1042#if defined(DEBUG_SIGNAL)
1043 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1044 pc, address, is_write, *(unsigned long *)old_set);
1045#endif
1046 /* XXX: locking issue */
1047 if (is_write && page_unprotect(address, pc, puc)) {
1048 return 1;
1049 }
1050 /* see if it is an MMU fault */
1051 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1052 if (ret < 0)
1053 return 0; /* not an MMU fault */
1054 if (ret == 0)
1055 return 1; /* the MMU fault was handled without causing real CPU fault */
1056 /* now we have a real cpu fault */
1057 tb = tb_find_pc(pc);
1058 if (tb) {
1059 /* the PC is inside the translated code. It means that we have
1060 a virtual CPU fault */
1061 cpu_restore_state(tb, env, pc, puc);
1062 }
1063 /* we restore the process signal mask as the sigreturn should
1064 do it (XXX: use sigsetjmp) */
1065 sigprocmask(SIG_SETMASK, old_set, NULL);
1066 cpu_loop_exit();
1067 /* never comes here */
67867308
FB		 1068 return 1;
1069}
6af0bf9c
FB		 1070
1071#elif defined (TARGET_MIPS)
1072static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1073 int is_write, sigset_t *old_set,
1074 void *puc)
1075{
1076 TranslationBlock *tb;
1077 int ret;
1078
1079 if (cpu_single_env)
1080 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1081#if defined(DEBUG_SIGNAL)
1082 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1083 pc, address, is_write, *(unsigned long *)old_set);
1084#endif
1085 /* XXX: locking issue */
53a5960a 1086 if (is_write && page_unprotect(h2g(address), pc, puc)) {
6af0bf9c
FB		 1087 return 1;
1088 }
1089
1090 /* see if it is an MMU fault */
cc9442b9 1091 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
6af0bf9c
FB		 1092 if (ret < 0)
1093 return 0; /* not an MMU fault */
1094 if (ret == 0)
1095 return 1; /* the MMU fault was handled without causing real CPU fault */
1096
1097 /* now we have a real cpu fault */
1098 tb = tb_find_pc(pc);
1099 if (tb) {
1100 /* the PC is inside the translated code. It means that we have
1101 a virtual CPU fault */
1102 cpu_restore_state(tb, env, pc, puc);
1103 }
1104 if (ret == 1) {
1105#if 0
1106 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1107 env->nip, env->error_code, tb);
1108#endif
1109 /* we restore the process signal mask as the sigreturn should
1110 do it (XXX: use sigsetjmp) */
1111 sigprocmask(SIG_SETMASK, old_set, NULL);
1112 do_raise_exception_err(env->exception_index, env->error_code);
1113 } else {
1114 /* activate soft MMU for this block */
1115 cpu_resume_from_signal(env, puc);
1116 }
1117 /* never comes here */
1118 return 1;
1119}
1120
fdf9b3e8
FB		 1121#elif defined (TARGET_SH4)
1122static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1123 int is_write, sigset_t *old_set,
1124 void *puc)
1125{
1126 TranslationBlock *tb;
1127 int ret;
1128
1129 if (cpu_single_env)
1130 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1131#if defined(DEBUG_SIGNAL)
1132 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1133 pc, address, is_write, *(unsigned long *)old_set);
1134#endif
1135 /* XXX: locking issue */
1136 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1137 return 1;
1138 }
1139
1140 /* see if it is an MMU fault */
1141 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1142 if (ret < 0)
1143 return 0; /* not an MMU fault */
1144 if (ret == 0)
1145 return 1; /* the MMU fault was handled without causing real CPU fault */
1146
1147 /* now we have a real cpu fault */
1148 tb = tb_find_pc(pc);
1149 if (tb) {
1150 /* the PC is inside the translated code. It means that we have
1151 a virtual CPU fault */
1152 cpu_restore_state(tb, env, pc, puc);
1153 }
fdf9b3e8
FB		 1154#if 0
1155 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1156 env->nip, env->error_code, tb);
1157#endif
1158 /* we restore the process signal mask as the sigreturn should
1159 do it (XXX: use sigsetjmp) */
355fb23d
PB		 1160 sigprocmask(SIG_SETMASK, old_set, NULL);
1161 cpu_loop_exit();
fdf9b3e8
FB		 1162 /* never comes here */
1163 return 1;
1164}
e4533c7a
FB		 1165#else
1166#error unsupported target CPU
1167#endif
9de5e440 1168
2b413144
FB		 1169#if defined(__i386__)
1170
d8ecc0b9
FB		 1171#if defined(__APPLE__)
1172# include <sys/ucontext.h>
1173
1174# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1175# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1176# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1177#else
1178# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1179# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1180# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1181#endif
1182
bf3e8bf1
FB		 1183#if defined(USE_CODE_COPY)
1184static void cpu_send_trap(unsigned long pc, int trap,
1185 struct ucontext *uc)
1186{
1187 TranslationBlock *tb;
1188
1189 if (cpu_single_env)
1190 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1191 /* now we have a real cpu fault */
1192 tb = tb_find_pc(pc);
1193 if (tb) {
1194 /* the PC is inside the translated code. It means that we have
1195 a virtual CPU fault */
1196 cpu_restore_state(tb, env, pc, uc);
1197 }
1198 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1199 raise_exception_err(trap, env->error_code);
1200}
1201#endif
1202
5a7b542b 1203int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1204 void *puc)
9de5e440 1205{
5a7b542b 1206 siginfo_t *info = pinfo;
9de5e440
FB		 1207 struct ucontext *uc = puc;
1208 unsigned long pc;
bf3e8bf1 1209 int trapno;
97eb5b14 1210
d691f669
FB		 1211#ifndef REG_EIP
1212/* for glibc 2.1 */
fd6ce8f6
FB		 1213#define REG_EIP EIP
1214#define REG_ERR ERR
1215#define REG_TRAPNO TRAPNO
d691f669 1216#endif
d8ecc0b9
FB		 1217 pc = EIP_sig(uc);
1218 trapno = TRAP_sig(uc);
bf3e8bf1
FB		 1219#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1220 if (trapno == 0x00 || trapno == 0x05) {
1221 /* send division by zero or bound exception */
1222 cpu_send_trap(pc, trapno, uc);
1223 return 1;
1224 } else
1225#endif
1226 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1227 trapno == 0xe ?
d8ecc0b9 1228 (ERROR_sig(uc) >> 1) & 1 : 0,
bf3e8bf1 1229 &uc->uc_sigmask, puc);
2b413144
FB		 1230}
1231
bc51c5c9
FB		 1232#elif defined(__x86_64__)
1233
5a7b542b 1234int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 1235 void *puc)
1236{
5a7b542b 1237 siginfo_t *info = pinfo;
bc51c5c9
FB		 1238 struct ucontext *uc = puc;
1239 unsigned long pc;
1240
1241 pc = uc->uc_mcontext.gregs[REG_RIP];
1242 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1243 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1244 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1245 &uc->uc_sigmask, puc);
1246}
1247
83fb7adf 1248#elif defined(__powerpc__)
2b413144 1249
83fb7adf
FB		 1250/***********************************************************************
1251 * signal context platform-specific definitions
1252 * From Wine
1253 */
1254#ifdef linux
1255/* All Registers access - only for local access */
1256# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1257/* Gpr Registers access */
1258# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1259# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1260# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1261# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1262# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1263# define LR_sig(context) REG_sig(link, context) /* Link register */
1264# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1265/* Float Registers access */
1266# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1267# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1268/* Exception Registers access */
1269# define DAR_sig(context) REG_sig(dar, context)
1270# define DSISR_sig(context) REG_sig(dsisr, context)
1271# define TRAP_sig(context) REG_sig(trap, context)
1272#endif /* linux */
1273
1274#ifdef __APPLE__
1275# include <sys/ucontext.h>
1276typedef struct ucontext SIGCONTEXT;
1277/* All Registers access - only for local access */
1278# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1279# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1280# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1281# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1282/* Gpr Registers access */
1283# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1284# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1285# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1286# define CTR_sig(context) REG_sig(ctr, context)
1287# define XER_sig(context) REG_sig(xer, context) /* Link register */
1288# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1289# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1290/* Float Registers access */
1291# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1292# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1293/* Exception Registers access */
1294# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1295# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1296# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1297#endif /* __APPLE__ */
1298
5a7b542b 1299int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1300 void *puc)
2b413144 1301{
5a7b542b 1302 siginfo_t *info = pinfo;
25eb4484 1303 struct ucontext *uc = puc;
25eb4484 1304 unsigned long pc;
25eb4484
FB		 1305 int is_write;
1306
83fb7adf 1307 pc = IAR_sig(uc);
25eb4484
FB		 1308 is_write = 0;
1309#if 0
1310 /* ppc 4xx case */
83fb7adf 1311 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1312 is_write = 1;
1313#else
83fb7adf 1314 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1315 is_write = 1;
1316#endif
1317 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1318 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1319}
1320
2f87c607
FB		 1321#elif defined(__alpha__)
1322
5a7b542b 1323int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1324 void *puc)
1325{
5a7b542b 1326 siginfo_t *info = pinfo;
2f87c607
FB		 1327 struct ucontext *uc = puc;
1328 uint32_t *pc = uc->uc_mcontext.sc_pc;
1329 uint32_t insn = *pc;
1330 int is_write = 0;
1331
8c6939c0 1332 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1333 switch (insn >> 26) {
1334 case 0x0d: // stw
1335 case 0x0e: // stb
1336 case 0x0f: // stq_u
1337 case 0x24: // stf
1338 case 0x25: // stg
1339 case 0x26: // sts
1340 case 0x27: // stt
1341 case 0x2c: // stl
1342 case 0x2d: // stq
1343 case 0x2e: // stl_c
1344 case 0x2f: // stq_c
1345 is_write = 1;
1346 }
1347
1348 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1349 is_write, &uc->uc_sigmask, puc);
2f87c607 1350}
8c6939c0
FB		 1351#elif defined(__sparc__)
1352
5a7b542b 1353int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1354 void *puc)
8c6939c0 1355{
5a7b542b 1356 siginfo_t *info = pinfo;
8c6939c0
FB		 1357 uint32_t *regs = (uint32_t *)(info + 1);
1358 void *sigmask = (regs + 20);
1359 unsigned long pc;
1360 int is_write;
1361 uint32_t insn;
1362
1363 /* XXX: is there a standard glibc define ? */
1364 pc = regs[1];
1365 /* XXX: need kernel patch to get write flag faster */
1366 is_write = 0;
1367 insn = *(uint32_t *)pc;
1368 if ((insn >> 30) == 3) {
1369 switch((insn >> 19) & 0x3f) {
1370 case 0x05: // stb
1371 case 0x06: // sth
1372 case 0x04: // st
1373 case 0x07: // std
1374 case 0x24: // stf
1375 case 0x27: // stdf
1376 case 0x25: // stfsr
1377 is_write = 1;
1378 break;
1379 }
1380 }
1381 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1382 is_write, sigmask, NULL);
8c6939c0
FB		 1383}
1384
1385#elif defined(__arm__)
1386
5a7b542b 1387int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1388 void *puc)
8c6939c0 1389{
5a7b542b 1390 siginfo_t *info = pinfo;
8c6939c0
FB		 1391 struct ucontext *uc = puc;
1392 unsigned long pc;
1393 int is_write;
1394
1395 pc = uc->uc_mcontext.gregs[R15];
1396 /* XXX: compute is_write */
1397 is_write = 0;
1398 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1399 is_write,
f3a9676a 1400 &uc->uc_sigmask, puc);
8c6939c0
FB		 1401}
1402
38e584a0
FB		 1403#elif defined(__mc68000)
1404
5a7b542b 1405int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1406 void *puc)
1407{
5a7b542b 1408 siginfo_t *info = pinfo;
38e584a0
FB		 1409 struct ucontext *uc = puc;
1410 unsigned long pc;
1411 int is_write;
1412
1413 pc = uc->uc_mcontext.gregs[16];
1414 /* XXX: compute is_write */
1415 is_write = 0;
1416 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1417 is_write,
bf3e8bf1 1418 &uc->uc_sigmask, puc);
38e584a0
FB		 1419}
1420
b8076a74
FB		 1421#elif defined(__ia64)
1422
1423#ifndef __ISR_VALID
1424 /* This ought to be in <bits/siginfo.h>... */
1425# define __ISR_VALID 1
b8076a74
FB		 1426#endif
1427
5a7b542b 1428int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1429{
5a7b542b 1430 siginfo_t *info = pinfo;
b8076a74
FB		 1431 struct ucontext *uc = puc;
1432 unsigned long ip;
1433 int is_write = 0;
1434
1435 ip = uc->uc_mcontext.sc_ip;
1436 switch (host_signum) {
1437 case SIGILL:
1438 case SIGFPE:
1439 case SIGSEGV:
1440 case SIGBUS:
1441 case SIGTRAP:
fd4a43e4 1442 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1443 /* ISR.W (write-access) is bit 33: */
1444 is_write = (info->si_isr >> 33) & 1;
1445 break;
1446
1447 default:
1448 break;
1449 }
1450 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1451 is_write,
1452 &uc->uc_sigmask, puc);
1453}
1454
90cb9493
FB		 1455#elif defined(__s390__)
1456
5a7b542b 1457int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1458 void *puc)
1459{
5a7b542b 1460 siginfo_t *info = pinfo;
90cb9493
FB		 1461 struct ucontext *uc = puc;
1462 unsigned long pc;
1463 int is_write;
1464
1465 pc = uc->uc_mcontext.psw.addr;
1466 /* XXX: compute is_write */
1467 is_write = 0;
1468 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1469 is_write,
1470 &uc->uc_sigmask, puc);
1471}
1472
9de5e440 1473#else
2b413144 1474
3fb2ded1 1475#error host CPU specific signal handler needed
2b413144 1476
9de5e440 1477#endif
67b915a5
FB		 1478
1479#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing