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Fix last page errors in page_check_range and page_set_flags.
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
7d13299d 24
fbf9eeb3
FB		 25#if !defined(CONFIG_SOFTMMU)
26#undef EAX
27#undef ECX
28#undef EDX
29#undef EBX
30#undef ESP
31#undef EBP
32#undef ESI
33#undef EDI
34#undef EIP
35#include <signal.h>
84778508 36#ifdef __linux__
fbf9eeb3
FB		 37#include <sys/ucontext.h>
38#endif
84778508 39#endif
fbf9eeb3 40
dfe5fff3 41#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 42// Work around ugly bugs in glibc that mangle global register contents
43#undef env
44#define env cpu_single_env
45#endif
46
36bdbe54
FB		 47int tb_invalidated_flag;
48
f0667e66 49//#define CONFIG_DEBUG_EXEC
9de5e440 50//#define DEBUG_SIGNAL
7d13299d 51
6a4955a8
AL		 52int qemu_cpu_has_work(CPUState *env)
53{
54 return cpu_has_work(env);
55}
56
e4533c7a
FB		 57void cpu_loop_exit(void)
58{
1c3569fe 59 env->current_tb = NULL;
e4533c7a
FB		 60 longjmp(env->jmp_env, 1);
61}
bfed01fc 62
fbf9eeb3
FB		 63/* exit the current TB from a signal handler. The host registers are
64 restored in a state compatible with the CPU emulator
65 */
5fafdf24 66void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 67{
68#if !defined(CONFIG_SOFTMMU)
84778508 69#ifdef __linux__
fbf9eeb3 70 struct ucontext *uc = puc;
84778508
BS		 71#elif defined(__OpenBSD__)
72 struct sigcontext *uc = puc;
73#endif
fbf9eeb3
FB		 74#endif
75
76 env = env1;
77
78 /* XXX: restore cpu registers saved in host registers */
79
80#if !defined(CONFIG_SOFTMMU)
81 if (puc) {
82 /* XXX: use siglongjmp ? */
84778508 83#ifdef __linux__
fbf9eeb3 84 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
84778508
BS		 85#elif defined(__OpenBSD__)
86 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
87#endif
fbf9eeb3
FB		 88 }
89#endif
9a3ea654 90 env->exception_index = -1;
fbf9eeb3
FB		 91 longjmp(env->jmp_env, 1);
92}
93
2e70f6ef
PB		 94/* Execute the code without caching the generated code. An interpreter
95 could be used if available. */
96static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
97{
98 unsigned long next_tb;
99 TranslationBlock *tb;
100
101 /* Should never happen.
102 We only end up here when an existing TB is too long. */
103 if (max_cycles > CF_COUNT_MASK)
104 max_cycles = CF_COUNT_MASK;
105
106 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
107 max_cycles);
108 env->current_tb = tb;
109 /* execute the generated code */
110 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
1c3569fe 111 env->current_tb = NULL;
2e70f6ef
PB		 112
113 if ((next_tb & 3) == 2) {
114 /* Restore PC. This may happen if async event occurs before
115 the TB starts executing. */
622ed360 116 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 117 }
118 tb_phys_invalidate(tb, -1);
119 tb_free(tb);
120}
121
8a40a180
FB		 122static TranslationBlock *tb_find_slow(target_ulong pc,
123 target_ulong cs_base,
c068688b 124 uint64_t flags)
8a40a180
FB		 125{
126 TranslationBlock *tb, **ptb1;
8a40a180
FB		 127 unsigned int h;
128 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
3b46e624 129
8a40a180 130 tb_invalidated_flag = 0;
3b46e624 131
8a40a180
FB		 132 /* find translated block using physical mappings */
133 phys_pc = get_phys_addr_code(env, pc);
134 phys_page1 = phys_pc & TARGET_PAGE_MASK;
135 phys_page2 = -1;
136 h = tb_phys_hash_func(phys_pc);
137 ptb1 = &tb_phys_hash[h];
138 for(;;) {
139 tb = *ptb1;
140 if (!tb)
141 goto not_found;
5fafdf24 142 if (tb->pc == pc &&
8a40a180 143 tb->page_addr[0] == phys_page1 &&
5fafdf24 144 tb->cs_base == cs_base &&
8a40a180
FB		 145 tb->flags == flags) {
146 /* check next page if needed */
147 if (tb->page_addr[1] != -1) {
5fafdf24 148 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180
FB		 149 TARGET_PAGE_SIZE;
150 phys_page2 = get_phys_addr_code(env, virt_page2);
151 if (tb->page_addr[1] == phys_page2)
152 goto found;
153 } else {
154 goto found;
155 }
156 }
157 ptb1 = &tb->phys_hash_next;
158 }
159 not_found:
2e70f6ef
PB		 160 /* if no translated code available, then translate it now */
161 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 162
8a40a180 163 found:
8a40a180
FB		 164 /* we add the TB in the virtual pc hash table */
165 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 166 return tb;
167}
168
169static inline TranslationBlock *tb_find_fast(void)
170{
171 TranslationBlock *tb;
172 target_ulong cs_base, pc;
6b917547 173 int flags;
8a40a180
FB		 174
175 /* we record a subset of the CPU state. It will
176 always be the same before a given translated block
177 is executed. */
6b917547 178 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 179 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 180 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
181 tb->flags != flags)) {
8a40a180
FB		 182 tb = tb_find_slow(pc, cs_base, flags);
183 }
184 return tb;
185}
186
dde2367e
AL		 187static CPUDebugExcpHandler *debug_excp_handler;
188
189CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
190{
191 CPUDebugExcpHandler *old_handler = debug_excp_handler;
192
193 debug_excp_handler = handler;
194 return old_handler;
195}
196
6e140f28
AL		 197static void cpu_handle_debug_exception(CPUState *env)
198{
199 CPUWatchpoint *wp;
200
201 if (!env->watchpoint_hit)
72cf2d4f 202 QTAILQ_FOREACH(wp, &env->watchpoints, entry)
6e140f28 203 wp->flags &= ~BP_WATCHPOINT_HIT;
dde2367e
AL		 204
205 if (debug_excp_handler)
206 debug_excp_handler(env);
6e140f28
AL		 207}
208
7d13299d
FB		 209/* main execution loop */
210
e4533c7a 211int cpu_exec(CPUState *env1)
7d13299d 212{
1d9000e8 213 volatile host_reg_t saved_env_reg;
8a40a180 214 int ret, interrupt_request;
8a40a180 215 TranslationBlock *tb;
c27004ec 216 uint8_t *tc_ptr;
d5975363 217 unsigned long next_tb;
8c6939c0 218
bfed01fc
TS		 219 if (cpu_halted(env1) == EXCP_HALTED)
220 return EXCP_HALTED;
5a1e3cfc 221
5fafdf24 222 cpu_single_env = env1;
6a00d601 223
24ebf5f3
PB		 224 /* the access to env below is actually saving the global register's
225 value, so that files not including target-xyz/exec.h are free to
226 use it. */
227 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
228 saved_env_reg = (host_reg_t) env;
229 asm("");
c27004ec 230 env = env1;
e4533c7a 231
ecb644f4 232#if defined(TARGET_I386)
14dcc3e2
JK		 233 if (!kvm_enabled()) {
234 /* put eflags in CPU temporary format */
235 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
236 DF = 1 - (2 * ((env->eflags >> 10) & 1));
237 CC_OP = CC_OP_EFLAGS;
238 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
239 }
93ac68bc 240#elif defined(TARGET_SPARC)
e6e5906b
PB		 241#elif defined(TARGET_M68K)
242 env->cc_op = CC_OP_FLAGS;
243 env->cc_dest = env->sr & 0xf;
244 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 245#elif defined(TARGET_ALPHA)
246#elif defined(TARGET_ARM)
247#elif defined(TARGET_PPC)
b779e29e 248#elif defined(TARGET_MICROBLAZE)
6af0bf9c 249#elif defined(TARGET_MIPS)
fdf9b3e8 250#elif defined(TARGET_SH4)
f1ccf904 251#elif defined(TARGET_CRIS)
10ec5117 252#elif defined(TARGET_S390X)
fdf9b3e8 253 /* XXXXX */
e4533c7a
FB		 254#else
255#error unsupported target CPU
256#endif
3fb2ded1 257 env->exception_index = -1;
9d27abd9 258
7d13299d 259 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 260 for(;;) {
261 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 262#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 263#undef env
264 env = cpu_single_env;
265#define env cpu_single_env
266#endif
3fb2ded1
FB		 267 /* if an exception is pending, we execute it here */
268 if (env->exception_index >= 0) {
269 if (env->exception_index >= EXCP_INTERRUPT) {
270 /* exit request from the cpu execution loop */
271 ret = env->exception_index;
6e140f28
AL		 272 if (ret == EXCP_DEBUG)
273 cpu_handle_debug_exception(env);
3fb2ded1 274 break;
72d239ed
AJ		 275 } else {
276#if defined(CONFIG_USER_ONLY)
3fb2ded1 277 /* if user mode only, we simulate a fake exception
9f083493 278 which will be handled outside the cpu execution
3fb2ded1 279 loop */
83479e77 280#if defined(TARGET_I386)
5fafdf24
TS		 281 do_interrupt_user(env->exception_index,
282 env->exception_is_int,
283 env->error_code,
3fb2ded1 284 env->exception_next_eip);
eba01623
FB		 285 /* successfully delivered */
286 env->old_exception = -1;
83479e77 287#endif
3fb2ded1
FB		 288 ret = env->exception_index;
289 break;
72d239ed 290#else
83479e77 291#if defined(TARGET_I386)
3fb2ded1
FB		 292 /* simulate a real cpu exception. On i386, it can
293 trigger new exceptions, but we do not handle
294 double or triple faults yet. */
5fafdf24
TS		 295 do_interrupt(env->exception_index,
296 env->exception_is_int,
297 env->error_code,
d05e66d2 298 env->exception_next_eip, 0);
678dde13
TS		 299 /* successfully delivered */
300 env->old_exception = -1;
ce09776b
FB		 301#elif defined(TARGET_PPC)
302 do_interrupt(env);
b779e29e
EI		 303#elif defined(TARGET_MICROBLAZE)
304 do_interrupt(env);
6af0bf9c
FB		 305#elif defined(TARGET_MIPS)
306 do_interrupt(env);
e95c8d51 307#elif defined(TARGET_SPARC)
f2bc7e7f 308 do_interrupt(env);
b5ff1b31
FB		 309#elif defined(TARGET_ARM)
310 do_interrupt(env);
fdf9b3e8
FB		 311#elif defined(TARGET_SH4)
312 do_interrupt(env);
eddf68a6
JM		 313#elif defined(TARGET_ALPHA)
314 do_interrupt(env);
f1ccf904
TS		 315#elif defined(TARGET_CRIS)
316 do_interrupt(env);
0633879f
PB		 317#elif defined(TARGET_M68K)
318 do_interrupt(0);
72d239ed 319#endif
301d2908 320 env->exception_index = -1;
83479e77 321#endif
3fb2ded1 322 }
5fafdf24 323 }
9df217a3 324
7ba1e619 325 if (kvm_enabled()) {
becfc390
AL		 326 kvm_cpu_exec(env);
327 longjmp(env->jmp_env, 1);
7ba1e619
AL		 328 }
329
b5fc09ae 330 next_tb = 0; /* force lookup of first TB */
3fb2ded1 331 for(;;) {
68a79315 332 interrupt_request = env->interrupt_request;
e1638bd8 333 if (unlikely(interrupt_request)) {
334 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
335 /* Mask out external interrupts for this step. */
336 interrupt_request &= ~(CPU_INTERRUPT_HARD |
337 CPU_INTERRUPT_FIQ |
338 CPU_INTERRUPT_SMI |
339 CPU_INTERRUPT_NMI);
340 }
6658ffb8
PB		 341 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
342 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
343 env->exception_index = EXCP_DEBUG;
344 cpu_loop_exit();
345 }
a90b7318 346#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e
EI		 347 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
348 defined(TARGET_MICROBLAZE)
a90b7318
AZ		 349 if (interrupt_request & CPU_INTERRUPT_HALT) {
350 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
351 env->halted = 1;
352 env->exception_index = EXCP_HLT;
353 cpu_loop_exit();
354 }
355#endif
68a79315 356#if defined(TARGET_I386)
b09ea7d5
GN		 357 if (interrupt_request & CPU_INTERRUPT_INIT) {
358 svm_check_intercept(SVM_EXIT_INIT);
359 do_cpu_init(env);
360 env->exception_index = EXCP_HALTED;
361 cpu_loop_exit();
362 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
363 do_cpu_sipi(env);
364 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 365 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
366 !(env->hflags & HF_SMM_MASK)) {
367 svm_check_intercept(SVM_EXIT_SMI);
368 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
369 do_smm_enter();
370 next_tb = 0;
371 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
372 !(env->hflags2 & HF2_NMI_MASK)) {
373 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
374 env->hflags2 |= HF2_NMI_MASK;
375 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
376 next_tb = 0;
79c4f6b0
HY		 377 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
378 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
379 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
380 next_tb = 0;
db620f46
FB		 381 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
382 (((env->hflags2 & HF2_VINTR_MASK) &&
383 (env->hflags2 & HF2_HIF_MASK)) ||
384 (!(env->hflags2 & HF2_VINTR_MASK) &&
385 (env->eflags & IF_MASK &&
386 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
387 int intno;
388 svm_check_intercept(SVM_EXIT_INTR);
389 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
390 intno = cpu_get_pic_interrupt(env);
93fcfe39 391 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 392#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 393#undef env
394 env = cpu_single_env;
395#define env cpu_single_env
396#endif
db620f46
FB		 397 do_interrupt(intno, 0, 0, 0, 1);
398 /* ensure that no TB jump will be modified as
399 the program flow was changed */
400 next_tb = 0;
0573fbfc 401#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 402 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
403 (env->eflags & IF_MASK) &&
404 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
405 int intno;
406 /* FIXME: this should respect TPR */
407 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 408 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 409 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 410 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 411 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 412 next_tb = 0;
907a5b26 413#endif
db620f46 414 }
68a79315 415 }
ce09776b 416#elif defined(TARGET_PPC)
9fddaa0c
FB		 417#if 0
418 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 419 cpu_reset(env);
9fddaa0c
FB		 420 }
421#endif
47103572 422 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 423 ppc_hw_interrupt(env);
424 if (env->pending_interrupts == 0)
425 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 426 next_tb = 0;
ce09776b 427 }
b779e29e
EI		 428#elif defined(TARGET_MICROBLAZE)
429 if ((interrupt_request & CPU_INTERRUPT_HARD)
430 && (env->sregs[SR_MSR] & MSR_IE)
431 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
432 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
433 env->exception_index = EXCP_IRQ;
434 do_interrupt(env);
435 next_tb = 0;
436 }
6af0bf9c
FB		 437#elif defined(TARGET_MIPS)
438 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 439 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 440 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 441 !(env->CP0_Status & (1 << CP0St_EXL)) &&
442 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 443 !(env->hflags & MIPS_HFLAG_DM)) {
444 /* Raise it */
445 env->exception_index = EXCP_EXT_INTERRUPT;
446 env->error_code = 0;
447 do_interrupt(env);
b5fc09ae 448 next_tb = 0;
6af0bf9c 449 }
e95c8d51 450#elif defined(TARGET_SPARC)
d532b26c
IK		 451 if (interrupt_request & CPU_INTERRUPT_HARD) {
452 if (cpu_interrupts_enabled(env) &&
453 env->interrupt_index > 0) {
454 int pil = env->interrupt_index & 0xf;
455 int type = env->interrupt_index & 0xf0;
456
457 if (((type == TT_EXTINT) &&
458 cpu_pil_allowed(env, pil)) ||
459 type != TT_EXTINT) {
460 env->exception_index = env->interrupt_index;
461 do_interrupt(env);
462 next_tb = 0;
463 }
464 }
e95c8d51
FB		 465 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
466 //do_interrupt(0, 0, 0, 0, 0);
467 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 468 }
b5ff1b31
FB		 469#elif defined(TARGET_ARM)
470 if (interrupt_request & CPU_INTERRUPT_FIQ
471 && !(env->uncached_cpsr & CPSR_F)) {
472 env->exception_index = EXCP_FIQ;
473 do_interrupt(env);
b5fc09ae 474 next_tb = 0;
b5ff1b31 475 }
9ee6e8bb
PB		 476 /* ARMv7-M interrupt return works by loading a magic value
477 into the PC. On real hardware the load causes the
478 return to occur. The qemu implementation performs the
479 jump normally, then does the exception return when the
480 CPU tries to execute code at the magic address.
481 This will cause the magic PC value to be pushed to
482 the stack if an interrupt occured at the wrong time.
483 We avoid this by disabling interrupts when
484 pc contains a magic address. */
b5ff1b31 485 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 486 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
487 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 488 env->exception_index = EXCP_IRQ;
489 do_interrupt(env);
b5fc09ae 490 next_tb = 0;
b5ff1b31 491 }
fdf9b3e8 492#elif defined(TARGET_SH4)
e96e2044
TS		 493 if (interrupt_request & CPU_INTERRUPT_HARD) {
494 do_interrupt(env);
b5fc09ae 495 next_tb = 0;
e96e2044 496 }
eddf68a6
JM		 497#elif defined(TARGET_ALPHA)
498 if (interrupt_request & CPU_INTERRUPT_HARD) {
499 do_interrupt(env);
b5fc09ae 500 next_tb = 0;
eddf68a6 501 }
f1ccf904 502#elif defined(TARGET_CRIS)
1b1a38b0 503 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 504 && (env->pregs[PR_CCS] & I_FLAG)
505 && !env->locked_irq) {
1b1a38b0
EI		 506 env->exception_index = EXCP_IRQ;
507 do_interrupt(env);
508 next_tb = 0;
509 }
510 if (interrupt_request & CPU_INTERRUPT_NMI
511 && (env->pregs[PR_CCS] & M_FLAG)) {
512 env->exception_index = EXCP_NMI;
f1ccf904 513 do_interrupt(env);
b5fc09ae 514 next_tb = 0;
f1ccf904 515 }
0633879f
PB		 516#elif defined(TARGET_M68K)
517 if (interrupt_request & CPU_INTERRUPT_HARD
518 && ((env->sr & SR_I) >> SR_I_SHIFT)
519 < env->pending_level) {
520 /* Real hardware gets the interrupt vector via an
521 IACK cycle at this point. Current emulated
522 hardware doesn't rely on this, so we
523 provide/save the vector when the interrupt is
524 first signalled. */
525 env->exception_index = env->pending_vector;
526 do_interrupt(1);
b5fc09ae 527 next_tb = 0;
0633879f 528 }
68a79315 529#endif
9d05095e
FB		 530 /* Don't use the cached interupt_request value,
531 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 532 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 533 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
534 /* ensure that no TB jump will be modified as
535 the program flow was changed */
b5fc09ae 536 next_tb = 0;
bf3e8bf1 537 }
be214e6c
AJ		 538 }
539 if (unlikely(env->exit_request)) {
540 env->exit_request = 0;
541 env->exception_index = EXCP_INTERRUPT;
542 cpu_loop_exit();
3fb2ded1 543 }
f0667e66 544#ifdef CONFIG_DEBUG_EXEC
8fec2b8c 545 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 546 /* restore flags in standard format */
ecb644f4 547#if defined(TARGET_I386)
a7812ae4 548 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 549 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 550 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 551#elif defined(TARGET_ARM)
93fcfe39 552 log_cpu_state(env, 0);
93ac68bc 553#elif defined(TARGET_SPARC)
93fcfe39 554 log_cpu_state(env, 0);
67867308 555#elif defined(TARGET_PPC)
93fcfe39 556 log_cpu_state(env, 0);
e6e5906b
PB		 557#elif defined(TARGET_M68K)
558 cpu_m68k_flush_flags(env, env->cc_op);
559 env->cc_op = CC_OP_FLAGS;
560 env->sr = (env->sr & 0xffe0)
561 | env->cc_dest | (env->cc_x << 4);
93fcfe39 562 log_cpu_state(env, 0);
b779e29e
EI		 563#elif defined(TARGET_MICROBLAZE)
564 log_cpu_state(env, 0);
6af0bf9c 565#elif defined(TARGET_MIPS)
93fcfe39 566 log_cpu_state(env, 0);
fdf9b3e8 567#elif defined(TARGET_SH4)
93fcfe39 568 log_cpu_state(env, 0);
eddf68a6 569#elif defined(TARGET_ALPHA)
93fcfe39 570 log_cpu_state(env, 0);
f1ccf904 571#elif defined(TARGET_CRIS)
93fcfe39 572 log_cpu_state(env, 0);
e4533c7a 573#else
5fafdf24 574#error unsupported target CPU
e4533c7a 575#endif
3fb2ded1 576 }
7d13299d 577#endif
d5975363 578 spin_lock(&tb_lock);
8a40a180 579 tb = tb_find_fast();
d5975363
PB		 580 /* Note: we do it here to avoid a gcc bug on Mac OS X when
581 doing it in tb_find_slow */
582 if (tb_invalidated_flag) {
583 /* as some TB could have been invalidated because
584 of memory exceptions while generating the code, we
585 must recompute the hash index here */
586 next_tb = 0;
2e70f6ef 587 tb_invalidated_flag = 0;
d5975363 588 }
f0667e66 589#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 590 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
591 (long)tb->tc_ptr, tb->pc,
592 lookup_symbol(tb->pc));
9d27abd9 593#endif
8a40a180
FB		 594 /* see if we can patch the calling TB. When the TB
595 spans two pages, we cannot safely do a direct
596 jump. */
040f2fb2 597 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 598 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 599 }
d5975363 600 spin_unlock(&tb_lock);
55e8b85e 601
602 /* cpu_interrupt might be called while translating the
603 TB, but before it is linked into a potentially
604 infinite loop and becomes env->current_tb. Avoid
605 starting execution if there is a pending interrupt. */
6113d6d3
PB		 606 if (!unlikely (env->exit_request)) {
607 env->current_tb = tb;
2e70f6ef 608 tc_ptr = tb->tc_ptr;
3fb2ded1 609 /* execute the generated code */
dfe5fff3 610#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 611#undef env
2e70f6ef 612 env = cpu_single_env;
572a9d4a
BS		 613#define env cpu_single_env
614#endif
2e70f6ef
PB		 615 next_tb = tcg_qemu_tb_exec(tc_ptr);
616 env->current_tb = NULL;
617 if ((next_tb & 3) == 2) {
bf20dc07 618 /* Instruction counter expired. */
2e70f6ef
PB		 619 int insns_left;
620 tb = (TranslationBlock *)(long)(next_tb & ~3);
621 /* Restore PC. */
622ed360 622 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 623 insns_left = env->icount_decr.u32;
624 if (env->icount_extra && insns_left >= 0) {
625 /* Refill decrementer and continue execution. */
626 env->icount_extra += insns_left;
627 if (env->icount_extra > 0xffff) {
628 insns_left = 0xffff;
629 } else {
630 insns_left = env->icount_extra;
631 }
632 env->icount_extra -= insns_left;
633 env->icount_decr.u16.low = insns_left;
634 } else {
635 if (insns_left > 0) {
636 /* Execute remaining instructions. */
637 cpu_exec_nocache(insns_left, tb);
638 }
639 env->exception_index = EXCP_INTERRUPT;
640 next_tb = 0;
641 cpu_loop_exit();
642 }
643 }
644 }
4cbf74b6
FB		 645 /* reset soft MMU for next block (it can currently
646 only be set by a memory fault) */
50a518e3 647 } /* for(;;) */
7d13299d 648 }
3fb2ded1
FB		 649 } /* for(;;) */
650
7d13299d 651
e4533c7a 652#if defined(TARGET_I386)
9de5e440 653 /* restore flags in standard format */
a7812ae4 654 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 655#elif defined(TARGET_ARM)
b7bcbe95 656 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 657#elif defined(TARGET_SPARC)
67867308 658#elif defined(TARGET_PPC)
e6e5906b
PB		 659#elif defined(TARGET_M68K)
660 cpu_m68k_flush_flags(env, env->cc_op);
661 env->cc_op = CC_OP_FLAGS;
662 env->sr = (env->sr & 0xffe0)
663 | env->cc_dest | (env->cc_x << 4);
b779e29e 664#elif defined(TARGET_MICROBLAZE)
6af0bf9c 665#elif defined(TARGET_MIPS)
fdf9b3e8 666#elif defined(TARGET_SH4)
eddf68a6 667#elif defined(TARGET_ALPHA)
f1ccf904 668#elif defined(TARGET_CRIS)
10ec5117 669#elif defined(TARGET_S390X)
fdf9b3e8 670 /* XXXXX */
e4533c7a
FB		 671#else
672#error unsupported target CPU
673#endif
1057eaa7
PB		 674
675 /* restore global registers */
24ebf5f3
PB		 676 asm("");
677 env = (void *) saved_env_reg;
1057eaa7 678
6a00d601 679 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 680 cpu_single_env = NULL;
7d13299d
FB		 681 return ret;
682}
6dbad63e 683
fbf9eeb3
FB		 684/* must only be called from the generated code as an exception can be
685 generated */
686void tb_invalidate_page_range(target_ulong start, target_ulong end)
687{
dc5d0b3d
FB		 688 /* XXX: cannot enable it yet because it yields to MMU exception
689 where NIP != read address on PowerPC */
690#if 0
fbf9eeb3
FB		 691 target_ulong phys_addr;
692 phys_addr = get_phys_addr_code(env, start);
693 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 694#endif
fbf9eeb3
FB		 695}
696
1a18c71b 697#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 698
6dbad63e
FB		 699void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
700{
701 CPUX86State *saved_env;
702
703 saved_env = env;
704 env = s;
a412ac57 705 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 706 selector &= 0xffff;
5fafdf24 707 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 708 (selector << 4), 0xffff, 0);
a513fe19 709 } else {
5d97559d 710 helper_load_seg(seg_reg, selector);
a513fe19 711 }
6dbad63e
FB		 712 env = saved_env;
713}
9de5e440 714
6f12a2a6 715void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 716{
717 CPUX86State *saved_env;
718
719 saved_env = env;
720 env = s;
3b46e624 721
6f12a2a6 722 helper_fsave(ptr, data32);
d0a1ffc9
FB		 723
724 env = saved_env;
725}
726
6f12a2a6 727void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 728{
729 CPUX86State *saved_env;
730
731 saved_env = env;
732 env = s;
3b46e624 733
6f12a2a6 734 helper_frstor(ptr, data32);
d0a1ffc9
FB		 735
736 env = saved_env;
737}
738
e4533c7a
FB		 739#endif /* TARGET_I386 */
740
67b915a5
FB		 741#if !defined(CONFIG_SOFTMMU)
742
3fb2ded1 743#if defined(TARGET_I386)
0b5c1ce8
NF		 744#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
745#else
746#define EXCEPTION_ACTION cpu_loop_exit()
747#endif
3fb2ded1 748
b56dad1c 749/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 750 the effective address of the memory exception. 'is_write' is 1 if a
751 write caused the exception and otherwise 0'. 'old_set' is the
752 signal set which should be restored */
2b413144 753static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 754 int is_write, sigset_t *old_set,
bf3e8bf1 755 void *puc)
9de5e440 756{
a513fe19
FB		 757 TranslationBlock *tb;
758 int ret;
68a79315 759
83479e77
FB		 760 if (cpu_single_env)
761 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 762#if defined(DEBUG_SIGNAL)
5fafdf24 763 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 764 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 765#endif
25eb4484 766 /* XXX: locking issue */
53a5960a 767 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 768 return 1;
769 }
fbf9eeb3 770
3fb2ded1 771 /* see if it is an MMU fault */
0b5c1ce8 772 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 773 if (ret < 0)
774 return 0; /* not an MMU fault */
775 if (ret == 0)
776 return 1; /* the MMU fault was handled without causing real CPU fault */
777 /* now we have a real cpu fault */
778 tb = tb_find_pc(pc);
779 if (tb) {
780 /* the PC is inside the translated code. It means that we have
781 a virtual CPU fault */
782 cpu_restore_state(tb, env, pc, puc);
783 }
68016c62 784
68016c62
FB		 785 /* we restore the process signal mask as the sigreturn should
786 do it (XXX: use sigsetjmp) */
787 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 788 EXCEPTION_ACTION;
e6e5906b 789
e6e5906b 790 /* never comes here */
67867308
FB		 791 return 1;
792}
6af0bf9c 793
2b413144
FB		 794#if defined(__i386__)
795
d8ecc0b9
FB		 796#if defined(__APPLE__)
797# include <sys/ucontext.h>
798
799# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
800# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
801# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 802# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 803#elif defined (__NetBSD__)
804# include <ucontext.h>
805
806# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
807# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
808# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
809# define MASK_sig(context) ((context)->uc_sigmask)
810#elif defined (__FreeBSD__) || defined(__DragonFly__)
811# include <ucontext.h>
812
813# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
814# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
815# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
816# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 817#elif defined(__OpenBSD__)
818# define EIP_sig(context) ((context)->sc_eip)
819# define TRAP_sig(context) ((context)->sc_trapno)
820# define ERROR_sig(context) ((context)->sc_err)
821# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 822#else
823# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
824# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
825# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 826# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 827#endif
828
5fafdf24 829int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 830 void *puc)
9de5e440 831{
5a7b542b 832 siginfo_t *info = pinfo;
78cfb07f
JL		 833#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
834 ucontext_t *uc = puc;
835#elif defined(__OpenBSD__)
d39bb24a
BS		 836 struct sigcontext *uc = puc;
837#else
9de5e440 838 struct ucontext *uc = puc;
d39bb24a 839#endif
9de5e440 840 unsigned long pc;
bf3e8bf1 841 int trapno;
97eb5b14 842
d691f669
FB		 843#ifndef REG_EIP
844/* for glibc 2.1 */
fd6ce8f6
FB		 845#define REG_EIP EIP
846#define REG_ERR ERR
847#define REG_TRAPNO TRAPNO
d691f669 848#endif
d8ecc0b9
FB		 849 pc = EIP_sig(uc);
850 trapno = TRAP_sig(uc);
ec6338ba
FB		 851 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
852 trapno == 0xe ?
853 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 854 &MASK_sig(uc), puc);
2b413144
FB		 855}
856
bc51c5c9
FB		 857#elif defined(__x86_64__)
858
b3efe5c8 859#ifdef __NetBSD__
d397abbd
BS		 860#define PC_sig(context) _UC_MACHINE_PC(context)
861#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
862#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
863#define MASK_sig(context) ((context)->uc_sigmask)
864#elif defined(__OpenBSD__)
865#define PC_sig(context) ((context)->sc_rip)
866#define TRAP_sig(context) ((context)->sc_trapno)
867#define ERROR_sig(context) ((context)->sc_err)
868#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 869#elif defined (__FreeBSD__) || defined(__DragonFly__)
870#include <ucontext.h>
871
872#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
873#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
874#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
875#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 876#else
d397abbd
BS		 877#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
878#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
879#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
880#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 881#endif
882
5a7b542b 883int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 884 void *puc)
885{
5a7b542b 886 siginfo_t *info = pinfo;
bc51c5c9 887 unsigned long pc;
78cfb07f 888#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 889 ucontext_t *uc = puc;
d397abbd
BS		 890#elif defined(__OpenBSD__)
891 struct sigcontext *uc = puc;
b3efe5c8
BS		 892#else
893 struct ucontext *uc = puc;
894#endif
bc51c5c9 895
d397abbd 896 pc = PC_sig(uc);
5fafdf24 897 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 898 TRAP_sig(uc) == 0xe ?
899 (ERROR_sig(uc) >> 1) & 1 : 0,
900 &MASK_sig(uc), puc);
bc51c5c9
FB		 901}
902
e58ffeb3 903#elif defined(_ARCH_PPC)
2b413144 904
83fb7adf
FB		 905/***********************************************************************
906 * signal context platform-specific definitions
907 * From Wine
908 */
909#ifdef linux
910/* All Registers access - only for local access */
911# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
912/* Gpr Registers access */
913# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
914# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
915# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
916# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
917# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
918# define LR_sig(context) REG_sig(link, context) /* Link register */
919# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
920/* Float Registers access */
921# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
922# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
923/* Exception Registers access */
924# define DAR_sig(context) REG_sig(dar, context)
925# define DSISR_sig(context) REG_sig(dsisr, context)
926# define TRAP_sig(context) REG_sig(trap, context)
927#endif /* linux */
928
58d9b1e0
JL		 929#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
930#include <ucontext.h>
931# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
932# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
933# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
934# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
935# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
936# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
937/* Exception Registers access */
938# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
939# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
940# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
941#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
942
83fb7adf
FB		 943#ifdef __APPLE__
944# include <sys/ucontext.h>
945typedef struct ucontext SIGCONTEXT;
946/* All Registers access - only for local access */
947# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
948# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
949# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
950# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
951/* Gpr Registers access */
952# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
953# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
954# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
955# define CTR_sig(context) REG_sig(ctr, context)
956# define XER_sig(context) REG_sig(xer, context) /* Link register */
957# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
958# define CR_sig(context) REG_sig(cr, context) /* Condition register */
959/* Float Registers access */
960# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
961# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
962/* Exception Registers access */
963# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
964# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
965# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
966#endif /* __APPLE__ */
967
5fafdf24 968int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 969 void *puc)
2b413144 970{
5a7b542b 971 siginfo_t *info = pinfo;
58d9b1e0
JL		 972#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
973 ucontext_t *uc = puc;
974#else
25eb4484 975 struct ucontext *uc = puc;
58d9b1e0 976#endif
25eb4484 977 unsigned long pc;
25eb4484
FB		 978 int is_write;
979
83fb7adf 980 pc = IAR_sig(uc);
25eb4484
FB		 981 is_write = 0;
982#if 0
983 /* ppc 4xx case */
83fb7adf 984 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 985 is_write = 1;
986#else
83fb7adf 987 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 988 is_write = 1;
989#endif
5fafdf24 990 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 991 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 992}
993
2f87c607
FB		 994#elif defined(__alpha__)
995
5fafdf24 996int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 997 void *puc)
998{
5a7b542b 999 siginfo_t *info = pinfo;
2f87c607
FB		 1000 struct ucontext *uc = puc;
1001 uint32_t *pc = uc->uc_mcontext.sc_pc;
1002 uint32_t insn = *pc;
1003 int is_write = 0;
1004
8c6939c0 1005 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1006 switch (insn >> 26) {
1007 case 0x0d: // stw
1008 case 0x0e: // stb
1009 case 0x0f: // stq_u
1010 case 0x24: // stf
1011 case 0x25: // stg
1012 case 0x26: // sts
1013 case 0x27: // stt
1014 case 0x2c: // stl
1015 case 0x2d: // stq
1016 case 0x2e: // stl_c
1017 case 0x2f: // stq_c
1018 is_write = 1;
1019 }
1020
5fafdf24 1021 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1022 is_write, &uc->uc_sigmask, puc);
2f87c607 1023}
8c6939c0
FB		 1024#elif defined(__sparc__)
1025
5fafdf24 1026int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1027 void *puc)
8c6939c0 1028{
5a7b542b 1029 siginfo_t *info = pinfo;
8c6939c0
FB		 1030 int is_write;
1031 uint32_t insn;
dfe5fff3 1032#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1033 uint32_t *regs = (uint32_t *)(info + 1);
1034 void *sigmask = (regs + 20);
8c6939c0 1035 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1036 unsigned long pc = regs[1];
1037#else
84778508 1038#ifdef __linux__
c9e1e2b0
BS		 1039 struct sigcontext *sc = puc;
1040 unsigned long pc = sc->sigc_regs.tpc;
1041 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1042#elif defined(__OpenBSD__)
1043 struct sigcontext *uc = puc;
1044 unsigned long pc = uc->sc_pc;
1045 void *sigmask = (void *)(long)uc->sc_mask;
1046#endif
c9e1e2b0
BS		 1047#endif
1048
8c6939c0
FB		 1049 /* XXX: need kernel patch to get write flag faster */
1050 is_write = 0;
1051 insn = *(uint32_t *)pc;
1052 if ((insn >> 30) == 3) {
1053 switch((insn >> 19) & 0x3f) {
1054 case 0x05: // stb
d877fa5a 1055 case 0x15: // stba
8c6939c0 1056 case 0x06: // sth
d877fa5a 1057 case 0x16: // stha
8c6939c0 1058 case 0x04: // st
d877fa5a 1059 case 0x14: // sta
8c6939c0 1060 case 0x07: // std
d877fa5a
BS		 1061 case 0x17: // stda
1062 case 0x0e: // stx
1063 case 0x1e: // stxa
8c6939c0 1064 case 0x24: // stf
d877fa5a 1065 case 0x34: // stfa
8c6939c0 1066 case 0x27: // stdf
d877fa5a
BS		 1067 case 0x37: // stdfa
1068 case 0x26: // stqf
1069 case 0x36: // stqfa
8c6939c0 1070 case 0x25: // stfsr
d877fa5a
BS		 1071 case 0x3c: // casa
1072 case 0x3e: // casxa
8c6939c0
FB		 1073 is_write = 1;
1074 break;
1075 }
1076 }
5fafdf24 1077 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1078 is_write, sigmask, NULL);
8c6939c0
FB		 1079}
1080
1081#elif defined(__arm__)
1082
5fafdf24 1083int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1084 void *puc)
8c6939c0 1085{
5a7b542b 1086 siginfo_t *info = pinfo;
8c6939c0
FB		 1087 struct ucontext *uc = puc;
1088 unsigned long pc;
1089 int is_write;
3b46e624 1090
48bbf11b 1091#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1092 pc = uc->uc_mcontext.gregs[R15];
1093#else
4eee57f5 1094 pc = uc->uc_mcontext.arm_pc;
5c49b363 1095#endif
8c6939c0
FB		 1096 /* XXX: compute is_write */
1097 is_write = 0;
5fafdf24 1098 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1099 is_write,
f3a9676a 1100 &uc->uc_sigmask, puc);
8c6939c0
FB		 1101}
1102
38e584a0
FB		 1103#elif defined(__mc68000)
1104
5fafdf24 1105int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1106 void *puc)
1107{
5a7b542b 1108 siginfo_t *info = pinfo;
38e584a0
FB		 1109 struct ucontext *uc = puc;
1110 unsigned long pc;
1111 int is_write;
3b46e624 1112
38e584a0
FB		 1113 pc = uc->uc_mcontext.gregs[16];
1114 /* XXX: compute is_write */
1115 is_write = 0;
5fafdf24 1116 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1117 is_write,
bf3e8bf1 1118 &uc->uc_sigmask, puc);
38e584a0
FB		 1119}
1120
b8076a74
FB		 1121#elif defined(__ia64)
1122
1123#ifndef __ISR_VALID
1124 /* This ought to be in <bits/siginfo.h>... */
1125# define __ISR_VALID 1
b8076a74
FB		 1126#endif
1127
5a7b542b 1128int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1129{
5a7b542b 1130 siginfo_t *info = pinfo;
b8076a74
FB		 1131 struct ucontext *uc = puc;
1132 unsigned long ip;
1133 int is_write = 0;
1134
1135 ip = uc->uc_mcontext.sc_ip;
1136 switch (host_signum) {
1137 case SIGILL:
1138 case SIGFPE:
1139 case SIGSEGV:
1140 case SIGBUS:
1141 case SIGTRAP:
fd4a43e4 1142 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1143 /* ISR.W (write-access) is bit 33: */
1144 is_write = (info->si_isr >> 33) & 1;
1145 break;
1146
1147 default:
1148 break;
1149 }
1150 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1151 is_write,
1152 &uc->uc_sigmask, puc);
1153}
1154
90cb9493
FB		 1155#elif defined(__s390__)
1156
5fafdf24 1157int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1158 void *puc)
1159{
5a7b542b 1160 siginfo_t *info = pinfo;
90cb9493
FB		 1161 struct ucontext *uc = puc;
1162 unsigned long pc;
1163 int is_write;
3b46e624 1164
90cb9493
FB		 1165 pc = uc->uc_mcontext.psw.addr;
1166 /* XXX: compute is_write */
1167 is_write = 0;
5fafdf24 1168 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1169 is_write, &uc->uc_sigmask, puc);
1170}
1171
1172#elif defined(__mips__)
1173
5fafdf24 1174int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1175 void *puc)
1176{
9617efe8 1177 siginfo_t *info = pinfo;
c4b89d18
TS		 1178 struct ucontext *uc = puc;
1179 greg_t pc = uc->uc_mcontext.pc;
1180 int is_write;
3b46e624 1181
c4b89d18
TS		 1182 /* XXX: compute is_write */
1183 is_write = 0;
5fafdf24 1184 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1185 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1186}
1187
f54b3f92
AJ		 1188#elif defined(__hppa__)
1189
1190int cpu_signal_handler(int host_signum, void *pinfo,
1191 void *puc)
1192{
1193 struct siginfo *info = pinfo;
1194 struct ucontext *uc = puc;
1195 unsigned long pc;
1196 int is_write;
1197
1198 pc = uc->uc_mcontext.sc_iaoq[0];
1199 /* FIXME: compute is_write */
1200 is_write = 0;
1201 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1202 is_write,
1203 &uc->uc_sigmask, puc);
1204}
1205
9de5e440 1206#else
2b413144 1207
3fb2ded1 1208#error host CPU specific signal handler needed
2b413144 1209
9de5e440 1210#endif
67b915a5
FB		 1211
1212#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing