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Honour limited subset of --cpu values instead of ignoring.
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
eddf68a6
JM		 43#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \
44 defined(TARGET_ALPHA)
e4533c7a
FB		 45/* XXX: unify with i386 target */
46void cpu_loop_exit(void)
47{
48 longjmp(env->jmp_env, 1);
49}
50#endif
e6e5906b 51#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
3475187d
FB		 52#define reg_T2
53#endif
e4533c7a 54
fbf9eeb3
FB		 55/* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
58void cpu_resume_from_signal(CPUState *env1, void *puc)
59{
60#if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62#endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68#if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73#endif
74 longjmp(env->jmp_env, 1);
75}
76
8a40a180
FB		 77
78static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
80 unsigned int flags)
81{
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
87
88 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
91
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93
94 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
104 if (tb->pc == pc &&
105 tb->page_addr[0] == phys_page1 &&
106 tb->cs_base == cs_base &&
107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
110 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
15388002 130 tb_invalidated_flag = 1;
8a40a180
FB		 131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138
139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
146
147 found:
8a40a180
FB		 148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152}
153
154static inline TranslationBlock *tb_find_fast(void)
155{
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
158 unsigned int flags;
159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163#if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166 cs_base = env->segs[R_CS].base;
167 pc = cs_base + env->eip;
168#elif defined(TARGET_ARM)
169 flags = env->thumb | (env->vfp.vec_len << 1)
b5ff1b31
FB		 170 | (env->vfp.vec_stride << 4);
171 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
172 flags |= (1 << 6);
40f137e1
PB		 173 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
174 flags |= (1 << 7);
8a40a180
FB		 175 cs_base = 0;
176 pc = env->regs[15];
177#elif defined(TARGET_SPARC)
178#ifdef TARGET_SPARC64
a80dde08
FB		 179 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
180 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
181 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
8a40a180 182#else
a80dde08
FB		 183 // FPU enable . MMU enabled . MMU no-fault . Supervisor
184 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
185 | env->psrs;
8a40a180
FB		 186#endif
187 cs_base = env->npc;
188 pc = env->pc;
189#elif defined(TARGET_PPC)
190 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
191 (msr_se << MSR_SE) | (msr_le << MSR_LE);
192 cs_base = 0;
193 pc = env->nip;
194#elif defined(TARGET_MIPS)
56b19403 195 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cc9442b9 196 cs_base = 0;
8a40a180 197 pc = env->PC;
e6e5906b
PB		 198#elif defined(TARGET_M68K)
199 flags = env->fpcr & M68K_FPCR_PREC;
200 cs_base = 0;
201 pc = env->pc;
fdf9b3e8
FB		 202#elif defined(TARGET_SH4)
203 flags = env->sr & (SR_MD | SR_RB);
204 cs_base = 0; /* XXXXX */
205 pc = env->pc;
eddf68a6
JM		 206#elif defined(TARGET_ALPHA)
207 flags = env->ps;
208 cs_base = 0;
209 pc = env->pc;
8a40a180
FB		 210#else
211#error unsupported CPU
212#endif
213 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
214 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
215 tb->flags != flags, 0)) {
216 tb = tb_find_slow(pc, cs_base, flags);
15388002
FB		 217 /* Note: we do it here to avoid a gcc bug on Mac OS X when
218 doing it in tb_find_slow */
219 if (tb_invalidated_flag) {
220 /* as some TB could have been invalidated because
221 of memory exceptions while generating the code, we
222 must recompute the hash index here */
223 T0 = 0;
224 }
8a40a180
FB		 225 }
226 return tb;
227}
228
229
7d13299d
FB		 230/* main execution loop */
231
e4533c7a 232int cpu_exec(CPUState *env1)
7d13299d 233{
1057eaa7
PB		 234#define DECLARE_HOST_REGS 1
235#include "hostregs_helper.h"
236#if defined(TARGET_SPARC)
3475187d
FB		 237#if defined(reg_REGWPTR)
238 uint32_t *saved_regwptr;
239#endif
240#endif
fdbb4691 241#if defined(__sparc__) && !defined(HOST_SOLARIS)
b49d07ba
TS		 242 int saved_i7;
243 target_ulong tmp_T0;
04369ff2 244#endif
8a40a180 245 int ret, interrupt_request;
7d13299d 246 void (*gen_func)(void);
8a40a180 247 TranslationBlock *tb;
c27004ec 248 uint8_t *tc_ptr;
8c6939c0 249
5a1e3cfc
FB		 250#if defined(TARGET_I386)
251 /* handle exit of HALTED state */
252 if (env1->hflags & HF_HALTED_MASK) {
253 /* disable halt condition */
254 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
255 (env1->eflags & IF_MASK)) {
256 env1->hflags &= ~HF_HALTED_MASK;
257 } else {
258 return EXCP_HALTED;
e80e1cc4
FB		 259 }
260 }
261#elif defined(TARGET_PPC)
50443c98 262 if (env1->halted) {
e80e1cc4 263 if (env1->msr[MSR_EE] &&
47103572 264 (env1->interrupt_request & CPU_INTERRUPT_HARD)) {
50443c98 265 env1->halted = 0;
e80e1cc4
FB		 266 } else {
267 return EXCP_HALTED;
5a1e3cfc
FB		 268 }
269 }
ba3c64fb
FB		 270#elif defined(TARGET_SPARC)
271 if (env1->halted) {
272 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
273 (env1->psret != 0)) {
274 env1->halted = 0;
275 } else {
276 return EXCP_HALTED;
277 }
278 }
9332f9da
FB		 279#elif defined(TARGET_ARM)
280 if (env1->halted) {
281 /* An interrupt wakes the CPU even if the I and F CPSR bits are
282 set. */
283 if (env1->interrupt_request
284 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
285 env1->halted = 0;
286 } else {
287 return EXCP_HALTED;
288 }
289 }
6810e154
FB		 290#elif defined(TARGET_MIPS)
291 if (env1->halted) {
292 if (env1->interrupt_request &
293 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
294 env1->halted = 0;
295 } else {
296 return EXCP_HALTED;
297 }
298 }
eddf68a6
JM		 299#elif defined(TARGET_ALPHA)
300 if (env1->halted) {
301 if (env1->interrupt_request & CPU_INTERRUPT_HARD) {
302 env1->halted = 0;
303 } else {
304 return EXCP_HALTED;
305 }
306 }
5a1e3cfc
FB		 307#endif
308
6a00d601
FB		 309 cpu_single_env = env1;
310
7d13299d 311 /* first we save global registers */
1057eaa7
PB		 312#define SAVE_HOST_REGS 1
313#include "hostregs_helper.h"
c27004ec 314 env = env1;
fdbb4691 315#if defined(__sparc__) && !defined(HOST_SOLARIS)
e4533c7a
FB		 316 /* we also save i7 because longjmp may not restore it */
317 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
318#endif
319
320#if defined(TARGET_I386)
0d1a29f9 321 env_to_regs();
9de5e440 322 /* put eflags in CPU temporary format */
fc2b4c48
FB		 323 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
324 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 325 CC_OP = CC_OP_EFLAGS;
fc2b4c48 326 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 327#elif defined(TARGET_ARM)
93ac68bc 328#elif defined(TARGET_SPARC)
3475187d
FB		 329#if defined(reg_REGWPTR)
330 saved_regwptr = REGWPTR;
331#endif
67867308 332#elif defined(TARGET_PPC)
e6e5906b
PB		 333#elif defined(TARGET_M68K)
334 env->cc_op = CC_OP_FLAGS;
335 env->cc_dest = env->sr & 0xf;
336 env->cc_x = (env->sr >> 4) & 1;
6af0bf9c 337#elif defined(TARGET_MIPS)
fdf9b3e8
FB		 338#elif defined(TARGET_SH4)
339 /* XXXXX */
eddf68a6
JM		 340#elif defined(TARGET_ALPHA)
341 env_to_regs();
e4533c7a
FB		 342#else
343#error unsupported target CPU
344#endif
3fb2ded1 345 env->exception_index = -1;
9d27abd9 346
7d13299d 347 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 348 for(;;) {
349 if (setjmp(env->jmp_env) == 0) {
ee8b7021 350 env->current_tb = NULL;
3fb2ded1
FB		 351 /* if an exception is pending, we execute it here */
352 if (env->exception_index >= 0) {
353 if (env->exception_index >= EXCP_INTERRUPT) {
354 /* exit request from the cpu execution loop */
355 ret = env->exception_index;
356 break;
357 } else if (env->user_mode_only) {
358 /* if user mode only, we simulate a fake exception
9f083493 359 which will be handled outside the cpu execution
3fb2ded1 360 loop */
83479e77 361#if defined(TARGET_I386)
3fb2ded1
FB		 362 do_interrupt_user(env->exception_index,
363 env->exception_is_int,
364 env->error_code,
365 env->exception_next_eip);
83479e77 366#endif
3fb2ded1
FB		 367 ret = env->exception_index;
368 break;
369 } else {
83479e77 370#if defined(TARGET_I386)
3fb2ded1
FB		 371 /* simulate a real cpu exception. On i386, it can
372 trigger new exceptions, but we do not handle
373 double or triple faults yet. */
374 do_interrupt(env->exception_index,
375 env->exception_is_int,
376 env->error_code,
d05e66d2 377 env->exception_next_eip, 0);
678dde13
TS		 378 /* successfully delivered */
379 env->old_exception = -1;
ce09776b
FB		 380#elif defined(TARGET_PPC)
381 do_interrupt(env);
6af0bf9c
FB		 382#elif defined(TARGET_MIPS)
383 do_interrupt(env);
e95c8d51 384#elif defined(TARGET_SPARC)
1a0c3292 385 do_interrupt(env->exception_index);
b5ff1b31
FB		 386#elif defined(TARGET_ARM)
387 do_interrupt(env);
fdf9b3e8
FB		 388#elif defined(TARGET_SH4)
389 do_interrupt(env);
eddf68a6
JM		 390#elif defined(TARGET_ALPHA)
391 do_interrupt(env);
83479e77 392#endif
3fb2ded1
FB		 393 }
394 env->exception_index = -1;
9df217a3
FB		 395 }
396#ifdef USE_KQEMU
397 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
398 int ret;
399 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
400 ret = kqemu_cpu_exec(env);
401 /* put eflags in CPU temporary format */
402 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
403 DF = 1 - (2 * ((env->eflags >> 10) & 1));
404 CC_OP = CC_OP_EFLAGS;
405 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
406 if (ret == 1) {
407 /* exception */
408 longjmp(env->jmp_env, 1);
409 } else if (ret == 2) {
410 /* softmmu execution needed */
411 } else {
412 if (env->interrupt_request != 0) {
413 /* hardware interrupt will be executed just after */
414 } else {
415 /* otherwise, we restart */
416 longjmp(env->jmp_env, 1);
417 }
418 }
3fb2ded1 419 }
9df217a3
FB		 420#endif
421
3fb2ded1
FB		 422 T0 = 0; /* force lookup of first TB */
423 for(;;) {
fdbb4691 424#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1
FB		 425 /* g1 can be modified by some libc? functions */
426 tmp_T0 = T0;
8c6939c0 427#endif
68a79315 428 interrupt_request = env->interrupt_request;
2e255c6b 429 if (__builtin_expect(interrupt_request, 0)) {
6658ffb8
PB		 430 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
431 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
432 env->exception_index = EXCP_DEBUG;
433 cpu_loop_exit();
434 }
68a79315 435#if defined(TARGET_I386)
3b21e03e
FB		 436 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
437 !(env->hflags & HF_SMM_MASK)) {
438 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
439 do_smm_enter();
440#if defined(__sparc__) && !defined(HOST_SOLARIS)
441 tmp_T0 = 0;
442#else
443 T0 = 0;
444#endif
445 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 446 (env->eflags & IF_MASK) &&
447 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 448 int intno;
fbf9eeb3 449 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 450 intno = cpu_get_pic_interrupt(env);
f193c797 451 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 452 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
453 }
d05e66d2 454 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 455 /* ensure that no TB jump will be modified as
456 the program flow was changed */
fdbb4691 457#if defined(__sparc__) && !defined(HOST_SOLARIS)
907a5b26
FB		 458 tmp_T0 = 0;
459#else
460 T0 = 0;
461#endif
68a79315 462 }
ce09776b 463#elif defined(TARGET_PPC)
9fddaa0c
FB		 464#if 0
465 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
466 cpu_ppc_reset(env);
467 }
468#endif
47103572 469 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 470 ppc_hw_interrupt(env);
471 if (env->pending_interrupts == 0)
472 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
fdbb4691 473#if defined(__sparc__) && !defined(HOST_SOLARIS)
e9df014c 474 tmp_T0 = 0;
8a40a180 475#else
e9df014c 476 T0 = 0;
8a40a180 477#endif
ce09776b 478 }
6af0bf9c
FB		 479#elif defined(TARGET_MIPS)
480 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 481 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 482 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 483 !(env->CP0_Status & (1 << CP0St_EXL)) &&
484 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 485 !(env->hflags & MIPS_HFLAG_DM)) {
486 /* Raise it */
487 env->exception_index = EXCP_EXT_INTERRUPT;
488 env->error_code = 0;
489 do_interrupt(env);
fdbb4691 490#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 491 tmp_T0 = 0;
492#else
493 T0 = 0;
494#endif
6af0bf9c 495 }
e95c8d51 496#elif defined(TARGET_SPARC)
66321a11
FB		 497 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
498 (env->psret != 0)) {
499 int pil = env->interrupt_index & 15;
500 int type = env->interrupt_index & 0xf0;
501
502 if (((type == TT_EXTINT) &&
503 (pil == 15 || pil > env->psrpil)) ||
504 type != TT_EXTINT) {
505 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
506 do_interrupt(env->interrupt_index);
507 env->interrupt_index = 0;
fdbb4691 508#if defined(__sparc__) && !defined(HOST_SOLARIS)
8a40a180
FB		 509 tmp_T0 = 0;
510#else
511 T0 = 0;
512#endif
66321a11 513 }
e95c8d51
FB		 514 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
515 //do_interrupt(0, 0, 0, 0, 0);
516 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
ba3c64fb 517 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
df52b000
FB		 518 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
519 env->halted = 1;
520 env->exception_index = EXCP_HLT;
521 cpu_loop_exit();
ba3c64fb 522 }
b5ff1b31
FB		 523#elif defined(TARGET_ARM)
524 if (interrupt_request & CPU_INTERRUPT_FIQ
525 && !(env->uncached_cpsr & CPSR_F)) {
526 env->exception_index = EXCP_FIQ;
527 do_interrupt(env);
528 }
529 if (interrupt_request & CPU_INTERRUPT_HARD
530 && !(env->uncached_cpsr & CPSR_I)) {
531 env->exception_index = EXCP_IRQ;
532 do_interrupt(env);
533 }
fdf9b3e8
FB		 534#elif defined(TARGET_SH4)
535 /* XXXXX */
eddf68a6
JM		 536#elif defined(TARGET_ALPHA)
537 if (interrupt_request & CPU_INTERRUPT_HARD) {
538 do_interrupt(env);
539 }
68a79315 540#endif
9d05095e
FB		 541 /* Don't use the cached interupt_request value,
542 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 543 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 544 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
545 /* ensure that no TB jump will be modified as
546 the program flow was changed */
fdbb4691 547#if defined(__sparc__) && !defined(HOST_SOLARIS)
bf3e8bf1
FB		 548 tmp_T0 = 0;
549#else
550 T0 = 0;
551#endif
552 }
68a79315
FB		 553 if (interrupt_request & CPU_INTERRUPT_EXIT) {
554 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
555 env->exception_index = EXCP_INTERRUPT;
556 cpu_loop_exit();
557 }
3fb2ded1 558 }
7d13299d 559#ifdef DEBUG_EXEC
b5ff1b31 560 if ((loglevel & CPU_LOG_TB_CPU)) {
e4533c7a 561#if defined(TARGET_I386)
3fb2ded1 562 /* restore flags in standard format */
fc9f715d 563#ifdef reg_EAX
3fb2ded1 564 env->regs[R_EAX] = EAX;
fc9f715d
FB		 565#endif
566#ifdef reg_EBX
3fb2ded1 567 env->regs[R_EBX] = EBX;
fc9f715d
FB		 568#endif
569#ifdef reg_ECX
3fb2ded1 570 env->regs[R_ECX] = ECX;
fc9f715d
FB		 571#endif
572#ifdef reg_EDX
3fb2ded1 573 env->regs[R_EDX] = EDX;
fc9f715d
FB		 574#endif
575#ifdef reg_ESI
3fb2ded1 576 env->regs[R_ESI] = ESI;
fc9f715d
FB		 577#endif
578#ifdef reg_EDI
3fb2ded1 579 env->regs[R_EDI] = EDI;
fc9f715d
FB		 580#endif
581#ifdef reg_EBP
3fb2ded1 582 env->regs[R_EBP] = EBP;
fc9f715d
FB		 583#endif
584#ifdef reg_ESP
3fb2ded1 585 env->regs[R_ESP] = ESP;
fc9f715d 586#endif
3fb2ded1 587 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 588 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 589 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 590#elif defined(TARGET_ARM)
7fe48483 591 cpu_dump_state(env, logfile, fprintf, 0);
93ac68bc 592#elif defined(TARGET_SPARC)
3475187d
FB		 593 REGWPTR = env->regbase + (env->cwp * 16);
594 env->regwptr = REGWPTR;
595 cpu_dump_state(env, logfile, fprintf, 0);
67867308 596#elif defined(TARGET_PPC)
7fe48483 597 cpu_dump_state(env, logfile, fprintf, 0);
e6e5906b
PB		 598#elif defined(TARGET_M68K)
599 cpu_m68k_flush_flags(env, env->cc_op);
600 env->cc_op = CC_OP_FLAGS;
601 env->sr = (env->sr & 0xffe0)
602 | env->cc_dest | (env->cc_x << 4);
603 cpu_dump_state(env, logfile, fprintf, 0);
6af0bf9c
FB		 604#elif defined(TARGET_MIPS)
605 cpu_dump_state(env, logfile, fprintf, 0);
fdf9b3e8
FB		 606#elif defined(TARGET_SH4)
607 cpu_dump_state(env, logfile, fprintf, 0);
eddf68a6
JM		 608#elif defined(TARGET_ALPHA)
609 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 610#else
611#error unsupported target CPU
612#endif
3fb2ded1 613 }
7d13299d 614#endif
8a40a180 615 tb = tb_find_fast();
9d27abd9 616#ifdef DEBUG_EXEC
c1135f61 617 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 618 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
619 (long)tb->tc_ptr, tb->pc,
620 lookup_symbol(tb->pc));
3fb2ded1 621 }
9d27abd9 622#endif
fdbb4691 623#if defined(__sparc__) && !defined(HOST_SOLARIS)
3fb2ded1 624 T0 = tmp_T0;
8c6939c0 625#endif
8a40a180
FB		 626 /* see if we can patch the calling TB. When the TB
627 spans two pages, we cannot safely do a direct
628 jump. */
c27004ec 629 {
8a40a180 630 if (T0 != 0 &&
f32fc648
FB		 631#if USE_KQEMU
632 (env->kqemu_enabled != 2) &&
633#endif
8a40a180 634 tb->page_addr[1] == -1
bf3e8bf1
FB		 635#if defined(TARGET_I386) && defined(USE_CODE_COPY)
636 && (tb->cflags & CF_CODE_COPY) ==
637 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
638#endif
639 ) {
3fb2ded1 640 spin_lock(&tb_lock);
c27004ec 641 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 642#if defined(USE_CODE_COPY)
643 /* propagates the FP use info */
644 ((TranslationBlock *)(T0 & ~3))->cflags |=
645 (tb->cflags & CF_FP_USED);
646#endif
3fb2ded1
FB		 647 spin_unlock(&tb_lock);
648 }
c27004ec 649 }
3fb2ded1 650 tc_ptr = tb->tc_ptr;
83479e77 651 env->current_tb = tb;
3fb2ded1
FB		 652 /* execute the generated code */
653 gen_func = (void *)tc_ptr;
8c6939c0 654#if defined(__sparc__)
3fb2ded1
FB		 655 __asm__ __volatile__("call %0\n\t"
656 "mov %%o7,%%i0"
657 : /* no outputs */
658 : "r" (gen_func)
fdbb4691 659 : "i0", "i1", "i2", "i3", "i4", "i5",
faab7592 660 "o0", "o1", "o2", "o3", "o4", "o5",
fdbb4691
FB		 661 "l0", "l1", "l2", "l3", "l4", "l5",
662 "l6", "l7");
8c6939c0 663#elif defined(__arm__)
3fb2ded1
FB		 664 asm volatile ("mov pc, %0\n\t"
665 ".global exec_loop\n\t"
666 "exec_loop:\n\t"
667 : /* no outputs */
668 : "r" (gen_func)
669 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 670#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
671{
672 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 673 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
674 save_native_fp_state(env);
675 }
bf3e8bf1
FB		 676 gen_func();
677 } else {
97eb5b14
FB		 678 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
679 restore_native_fp_state(env);
680 }
bf3e8bf1
FB		 681 /* we work with native eflags */
682 CC_SRC = cc_table[CC_OP].compute_all();
683 CC_OP = CC_OP_EFLAGS;
684 asm(".globl exec_loop\n"
685 "\n"
686 "debug1:\n"
687 " pushl %%ebp\n"
688 " fs movl %10, %9\n"
689 " fs movl %11, %%eax\n"
690 " andl $0x400, %%eax\n"
691 " fs orl %8, %%eax\n"
692 " pushl %%eax\n"
693 " popf\n"
694 " fs movl %%esp, %12\n"
695 " fs movl %0, %%eax\n"
696 " fs movl %1, %%ecx\n"
697 " fs movl %2, %%edx\n"
698 " fs movl %3, %%ebx\n"
699 " fs movl %4, %%esp\n"
700 " fs movl %5, %%ebp\n"
701 " fs movl %6, %%esi\n"
702 " fs movl %7, %%edi\n"
703 " fs jmp *%9\n"
704 "exec_loop:\n"
705 " fs movl %%esp, %4\n"
706 " fs movl %12, %%esp\n"
707 " fs movl %%eax, %0\n"
708 " fs movl %%ecx, %1\n"
709 " fs movl %%edx, %2\n"
710 " fs movl %%ebx, %3\n"
711 " fs movl %%ebp, %5\n"
712 " fs movl %%esi, %6\n"
713 " fs movl %%edi, %7\n"
714 " pushf\n"
715 " popl %%eax\n"
716 " movl %%eax, %%ecx\n"
717 " andl $0x400, %%ecx\n"
718 " shrl $9, %%ecx\n"
719 " andl $0x8d5, %%eax\n"
720 " fs movl %%eax, %8\n"
721 " movl $1, %%eax\n"
722 " subl %%ecx, %%eax\n"
723 " fs movl %%eax, %11\n"
724 " fs movl %9, %%ebx\n" /* get T0 value */
725 " popl %%ebp\n"
726 :
727 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
728 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
729 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
730 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
731 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
732 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
733 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
734 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
735 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
736 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
737 "a" (gen_func),
738 "m" (*(uint8_t *)offsetof(CPUState, df)),
739 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
740 : "%ecx", "%edx"
741 );
742 }
743}
b8076a74
FB		 744#elif defined(__ia64)
745 struct fptr {
746 void *ip;
747 void *gp;
748 } fp;
749
750 fp.ip = tc_ptr;
751 fp.gp = code_gen_buffer + 2 * (1 << 20);
752 (*(void (*)(void)) &fp)();
ae228531 753#else
3fb2ded1 754 gen_func();
ae228531 755#endif
83479e77 756 env->current_tb = NULL;
4cbf74b6
FB		 757 /* reset soft MMU for next block (it can currently
758 only be set by a memory fault) */
759#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 760 if (env->hflags & HF_SOFTMMU_MASK) {
761 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 762 /* do not allow linking to another block */
763 T0 = 0;
764 }
f32fc648
FB		 765#endif
766#if defined(USE_KQEMU)
767#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
768 if (kqemu_is_ok(env) &&
769 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
770 cpu_loop_exit();
771 }
4cbf74b6 772#endif
3fb2ded1
FB		 773 }
774 } else {
0d1a29f9 775 env_to_regs();
7d13299d 776 }
3fb2ded1
FB		 777 } /* for(;;) */
778
7d13299d 779
e4533c7a 780#if defined(TARGET_I386)
97eb5b14
FB		 781#if defined(USE_CODE_COPY)
782 if (env->native_fp_regs) {
783 save_native_fp_state(env);
784 }
785#endif
9de5e440 786 /* restore flags in standard format */
fc2b4c48 787 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
e4533c7a 788#elif defined(TARGET_ARM)
b7bcbe95 789 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 790#elif defined(TARGET_SPARC)
3475187d
FB		 791#if defined(reg_REGWPTR)
792 REGWPTR = saved_regwptr;
793#endif
67867308 794#elif defined(TARGET_PPC)
e6e5906b
PB		 795#elif defined(TARGET_M68K)
796 cpu_m68k_flush_flags(env, env->cc_op);
797 env->cc_op = CC_OP_FLAGS;
798 env->sr = (env->sr & 0xffe0)
799 | env->cc_dest | (env->cc_x << 4);
6af0bf9c 800#elif defined(TARGET_MIPS)
fdf9b3e8 801#elif defined(TARGET_SH4)
eddf68a6 802#elif defined(TARGET_ALPHA)
fdf9b3e8 803 /* XXXXX */
e4533c7a
FB		 804#else
805#error unsupported target CPU
806#endif
1057eaa7
PB		 807
808 /* restore global registers */
fdbb4691 809#if defined(__sparc__) && !defined(HOST_SOLARIS)
8c6939c0 810 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 811#endif
1057eaa7
PB		 812#include "hostregs_helper.h"
813
6a00d601
FB		 814 /* fail safe : never use cpu_single_env outside cpu_exec() */
815 cpu_single_env = NULL;
7d13299d
FB		 816 return ret;
817}
6dbad63e 818
fbf9eeb3
FB		 819/* must only be called from the generated code as an exception can be
820 generated */
821void tb_invalidate_page_range(target_ulong start, target_ulong end)
822{
dc5d0b3d
FB		 823 /* XXX: cannot enable it yet because it yields to MMU exception
824 where NIP != read address on PowerPC */
825#if 0
fbf9eeb3
FB		 826 target_ulong phys_addr;
827 phys_addr = get_phys_addr_code(env, start);
828 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 829#endif
fbf9eeb3
FB		 830}
831
1a18c71b 832#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 833
6dbad63e
FB		 834void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
835{
836 CPUX86State *saved_env;
837
838 saved_env = env;
839 env = s;
a412ac57 840 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 841 selector &= 0xffff;
2e255c6b 842 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 843 (selector << 4), 0xffff, 0);
a513fe19 844 } else {
b453b70b 845 load_seg(seg_reg, selector);
a513fe19 846 }
6dbad63e
FB		 847 env = saved_env;
848}
9de5e440 849
d0a1ffc9
FB		 850void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
851{
852 CPUX86State *saved_env;
853
854 saved_env = env;
855 env = s;
856
c27004ec 857 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 858
859 env = saved_env;
860}
861
862void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
863{
864 CPUX86State *saved_env;
865
866 saved_env = env;
867 env = s;
868
c27004ec 869 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 870
871 env = saved_env;
872}
873
e4533c7a
FB		 874#endif /* TARGET_I386 */
875
67b915a5
FB		 876#if !defined(CONFIG_SOFTMMU)
877
3fb2ded1
FB		 878#if defined(TARGET_I386)
879
b56dad1c 880/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 881 the effective address of the memory exception. 'is_write' is 1 if a
882 write caused the exception and otherwise 0'. 'old_set' is the
883 signal set which should be restored */
2b413144 884static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 885 int is_write, sigset_t *old_set,
886 void *puc)
9de5e440 887{
a513fe19
FB		 888 TranslationBlock *tb;
889 int ret;
68a79315 890
83479e77
FB		 891 if (cpu_single_env)
892 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 893#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 894 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
895 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 896#endif
25eb4484 897 /* XXX: locking issue */
53a5960a 898 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 899 return 1;
900 }
fbf9eeb3 901
3fb2ded1 902 /* see if it is an MMU fault */
93a40ea9
FB		 903 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
904 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 905 if (ret < 0)
906 return 0; /* not an MMU fault */
907 if (ret == 0)
908 return 1; /* the MMU fault was handled without causing real CPU fault */
909 /* now we have a real cpu fault */
a513fe19
FB		 910 tb = tb_find_pc(pc);
911 if (tb) {
9de5e440
FB		 912 /* the PC is inside the translated code. It means that we have
913 a virtual CPU fault */
bf3e8bf1 914 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 915 }
4cbf74b6 916 if (ret == 1) {
3fb2ded1 917#if 0
4cbf74b6
FB		 918 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
919 env->eip, env->cr[2], env->error_code);
3fb2ded1 920#endif
4cbf74b6
FB		 921 /* we restore the process signal mask as the sigreturn should
922 do it (XXX: use sigsetjmp) */
923 sigprocmask(SIG_SETMASK, old_set, NULL);
54ca9095 924 raise_exception_err(env->exception_index, env->error_code);
4cbf74b6
FB		 925 } else {
926 /* activate soft MMU for this block */
3f337316 927 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 928 cpu_resume_from_signal(env, puc);
4cbf74b6 929 }
3fb2ded1
FB		 930 /* never comes here */
931 return 1;
932}
933
e4533c7a 934#elif defined(TARGET_ARM)
3fb2ded1 935static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 936 int is_write, sigset_t *old_set,
937 void *puc)
3fb2ded1 938{
68016c62
FB		 939 TranslationBlock *tb;
940 int ret;
941
942 if (cpu_single_env)
943 env = cpu_single_env; /* XXX: find a correct solution for multithread */
944#if defined(DEBUG_SIGNAL)
945 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
946 pc, address, is_write, *(unsigned long *)old_set);
947#endif
9f0777ed 948 /* XXX: locking issue */
53a5960a 949 if (is_write && page_unprotect(h2g(address), pc, puc)) {
9f0777ed
FB		 950 return 1;
951 }
68016c62
FB		 952 /* see if it is an MMU fault */
953 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
954 if (ret < 0)
955 return 0; /* not an MMU fault */
956 if (ret == 0)
957 return 1; /* the MMU fault was handled without causing real CPU fault */
958 /* now we have a real cpu fault */
959 tb = tb_find_pc(pc);
960 if (tb) {
961 /* the PC is inside the translated code. It means that we have
962 a virtual CPU fault */
963 cpu_restore_state(tb, env, pc, puc);
964 }
965 /* we restore the process signal mask as the sigreturn should
966 do it (XXX: use sigsetjmp) */
967 sigprocmask(SIG_SETMASK, old_set, NULL);
968 cpu_loop_exit();
3fb2ded1 969}
93ac68bc
FB		 970#elif defined(TARGET_SPARC)
971static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 972 int is_write, sigset_t *old_set,
973 void *puc)
93ac68bc 974{
68016c62
FB		 975 TranslationBlock *tb;
976 int ret;
977
978 if (cpu_single_env)
979 env = cpu_single_env; /* XXX: find a correct solution for multithread */
980#if defined(DEBUG_SIGNAL)
981 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
982 pc, address, is_write, *(unsigned long *)old_set);
983#endif
b453b70b 984 /* XXX: locking issue */
53a5960a 985 if (is_write && page_unprotect(h2g(address), pc, puc)) {
b453b70b
FB		 986 return 1;
987 }
68016c62
FB		 988 /* see if it is an MMU fault */
989 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
990 if (ret < 0)
991 return 0; /* not an MMU fault */
992 if (ret == 0)
993 return 1; /* the MMU fault was handled without causing real CPU fault */
994 /* now we have a real cpu fault */
995 tb = tb_find_pc(pc);
996 if (tb) {
997 /* the PC is inside the translated code. It means that we have
998 a virtual CPU fault */
999 cpu_restore_state(tb, env, pc, puc);
1000 }
1001 /* we restore the process signal mask as the sigreturn should
1002 do it (XXX: use sigsetjmp) */
1003 sigprocmask(SIG_SETMASK, old_set, NULL);
1004 cpu_loop_exit();
93ac68bc 1005}
67867308
FB		 1006#elif defined (TARGET_PPC)
1007static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 1008 int is_write, sigset_t *old_set,
1009 void *puc)
67867308
FB		 1010{
1011 TranslationBlock *tb;
ce09776b 1012 int ret;
67867308 1013
67867308
FB		 1014 if (cpu_single_env)
1015 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 1016#if defined(DEBUG_SIGNAL)
1017 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1018 pc, address, is_write, *(unsigned long *)old_set);
1019#endif
1020 /* XXX: locking issue */
53a5960a 1021 if (is_write && page_unprotect(h2g(address), pc, puc)) {
67867308
FB		 1022 return 1;
1023 }
1024
ce09776b 1025 /* see if it is an MMU fault */
7f957d28 1026 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 1027 if (ret < 0)
1028 return 0; /* not an MMU fault */
1029 if (ret == 0)
1030 return 1; /* the MMU fault was handled without causing real CPU fault */
1031
67867308
FB		 1032 /* now we have a real cpu fault */
1033 tb = tb_find_pc(pc);
1034 if (tb) {
1035 /* the PC is inside the translated code. It means that we have
1036 a virtual CPU fault */
bf3e8bf1 1037 cpu_restore_state(tb, env, pc, puc);
67867308 1038 }
ce09776b 1039 if (ret == 1) {
67867308 1040#if 0
ce09776b
FB		 1041 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1042 env->nip, env->error_code, tb);
67867308
FB		 1043#endif
1044 /* we restore the process signal mask as the sigreturn should
1045 do it (XXX: use sigsetjmp) */
bf3e8bf1 1046 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 1047 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 1048 } else {
1049 /* activate soft MMU for this block */
fbf9eeb3 1050 cpu_resume_from_signal(env, puc);
ce09776b 1051 }
67867308 1052 /* never comes here */
e6e5906b
PB		 1053 return 1;
1054}
1055
1056#elif defined(TARGET_M68K)
1057static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1058 int is_write, sigset_t *old_set,
1059 void *puc)
1060{
1061 TranslationBlock *tb;
1062 int ret;
1063
1064 if (cpu_single_env)
1065 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1066#if defined(DEBUG_SIGNAL)
1067 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1068 pc, address, is_write, *(unsigned long *)old_set);
1069#endif
1070 /* XXX: locking issue */
1071 if (is_write && page_unprotect(address, pc, puc)) {
1072 return 1;
1073 }
1074 /* see if it is an MMU fault */
1075 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1076 if (ret < 0)
1077 return 0; /* not an MMU fault */
1078 if (ret == 0)
1079 return 1; /* the MMU fault was handled without causing real CPU fault */
1080 /* now we have a real cpu fault */
1081 tb = tb_find_pc(pc);
1082 if (tb) {
1083 /* the PC is inside the translated code. It means that we have
1084 a virtual CPU fault */
1085 cpu_restore_state(tb, env, pc, puc);
1086 }
1087 /* we restore the process signal mask as the sigreturn should
1088 do it (XXX: use sigsetjmp) */
1089 sigprocmask(SIG_SETMASK, old_set, NULL);
1090 cpu_loop_exit();
1091 /* never comes here */
67867308
FB		 1092 return 1;
1093}
6af0bf9c
FB		 1094
1095#elif defined (TARGET_MIPS)
1096static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1097 int is_write, sigset_t *old_set,
1098 void *puc)
1099{
1100 TranslationBlock *tb;
1101 int ret;
1102
1103 if (cpu_single_env)
1104 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1105#if defined(DEBUG_SIGNAL)
1106 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1107 pc, address, is_write, *(unsigned long *)old_set);
1108#endif
1109 /* XXX: locking issue */
53a5960a 1110 if (is_write && page_unprotect(h2g(address), pc, puc)) {
6af0bf9c
FB		 1111 return 1;
1112 }
1113
1114 /* see if it is an MMU fault */
cc9442b9 1115 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
6af0bf9c
FB		 1116 if (ret < 0)
1117 return 0; /* not an MMU fault */
1118 if (ret == 0)
1119 return 1; /* the MMU fault was handled without causing real CPU fault */
1120
1121 /* now we have a real cpu fault */
1122 tb = tb_find_pc(pc);
1123 if (tb) {
1124 /* the PC is inside the translated code. It means that we have
1125 a virtual CPU fault */
1126 cpu_restore_state(tb, env, pc, puc);
1127 }
1128 if (ret == 1) {
1129#if 0
1130 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1131 env->nip, env->error_code, tb);
1132#endif
1133 /* we restore the process signal mask as the sigreturn should
1134 do it (XXX: use sigsetjmp) */
1135 sigprocmask(SIG_SETMASK, old_set, NULL);
1136 do_raise_exception_err(env->exception_index, env->error_code);
1137 } else {
1138 /* activate soft MMU for this block */
1139 cpu_resume_from_signal(env, puc);
1140 }
1141 /* never comes here */
1142 return 1;
1143}
1144
fdf9b3e8
FB		 1145#elif defined (TARGET_SH4)
1146static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1147 int is_write, sigset_t *old_set,
1148 void *puc)
1149{
1150 TranslationBlock *tb;
1151 int ret;
1152
1153 if (cpu_single_env)
1154 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1155#if defined(DEBUG_SIGNAL)
1156 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1157 pc, address, is_write, *(unsigned long *)old_set);
1158#endif
1159 /* XXX: locking issue */
1160 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1161 return 1;
1162 }
1163
1164 /* see if it is an MMU fault */
1165 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1166 if (ret < 0)
1167 return 0; /* not an MMU fault */
1168 if (ret == 0)
1169 return 1; /* the MMU fault was handled without causing real CPU fault */
1170
1171 /* now we have a real cpu fault */
eddf68a6
JM		 1172 tb = tb_find_pc(pc);
1173 if (tb) {
1174 /* the PC is inside the translated code. It means that we have
1175 a virtual CPU fault */
1176 cpu_restore_state(tb, env, pc, puc);
1177 }
1178#if 0
1179 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1180 env->nip, env->error_code, tb);
1181#endif
1182 /* we restore the process signal mask as the sigreturn should
1183 do it (XXX: use sigsetjmp) */
1184 sigprocmask(SIG_SETMASK, old_set, NULL);
1185 cpu_loop_exit();
1186 /* never comes here */
1187 return 1;
1188}
1189
1190#elif defined (TARGET_ALPHA)
1191static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1192 int is_write, sigset_t *old_set,
1193 void *puc)
1194{
1195 TranslationBlock *tb;
1196 int ret;
1197
1198 if (cpu_single_env)
1199 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1200#if defined(DEBUG_SIGNAL)
1201 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1202 pc, address, is_write, *(unsigned long *)old_set);
1203#endif
1204 /* XXX: locking issue */
1205 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1206 return 1;
1207 }
1208
1209 /* see if it is an MMU fault */
1210 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1211 if (ret < 0)
1212 return 0; /* not an MMU fault */
1213 if (ret == 0)
1214 return 1; /* the MMU fault was handled without causing real CPU fault */
1215
1216 /* now we have a real cpu fault */
fdf9b3e8
FB		 1217 tb = tb_find_pc(pc);
1218 if (tb) {
1219 /* the PC is inside the translated code. It means that we have
1220 a virtual CPU fault */
1221 cpu_restore_state(tb, env, pc, puc);
1222 }
fdf9b3e8
FB		 1223#if 0
1224 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1225 env->nip, env->error_code, tb);
1226#endif
1227 /* we restore the process signal mask as the sigreturn should
1228 do it (XXX: use sigsetjmp) */
355fb23d
PB		 1229 sigprocmask(SIG_SETMASK, old_set, NULL);
1230 cpu_loop_exit();
fdf9b3e8
FB		 1231 /* never comes here */
1232 return 1;
1233}
e4533c7a
FB		 1234#else
1235#error unsupported target CPU
1236#endif
9de5e440 1237
2b413144
FB		 1238#if defined(__i386__)
1239
d8ecc0b9
FB		 1240#if defined(__APPLE__)
1241# include <sys/ucontext.h>
1242
1243# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1244# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1245# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1246#else
1247# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1248# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1249# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1250#endif
1251
bf3e8bf1
FB		 1252#if defined(USE_CODE_COPY)
1253static void cpu_send_trap(unsigned long pc, int trap,
1254 struct ucontext *uc)
1255{
1256 TranslationBlock *tb;
1257
1258 if (cpu_single_env)
1259 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1260 /* now we have a real cpu fault */
1261 tb = tb_find_pc(pc);
1262 if (tb) {
1263 /* the PC is inside the translated code. It means that we have
1264 a virtual CPU fault */
1265 cpu_restore_state(tb, env, pc, uc);
1266 }
1267 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1268 raise_exception_err(trap, env->error_code);
1269}
1270#endif
1271
5a7b542b 1272int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1273 void *puc)
9de5e440 1274{
5a7b542b 1275 siginfo_t *info = pinfo;
9de5e440
FB		 1276 struct ucontext *uc = puc;
1277 unsigned long pc;
bf3e8bf1 1278 int trapno;
97eb5b14 1279
d691f669
FB		 1280#ifndef REG_EIP
1281/* for glibc 2.1 */
fd6ce8f6
FB		 1282#define REG_EIP EIP
1283#define REG_ERR ERR
1284#define REG_TRAPNO TRAPNO
d691f669 1285#endif
d8ecc0b9
FB		 1286 pc = EIP_sig(uc);
1287 trapno = TRAP_sig(uc);
bf3e8bf1
FB		 1288#if defined(TARGET_I386) && defined(USE_CODE_COPY)
1289 if (trapno == 0x00 || trapno == 0x05) {
1290 /* send division by zero or bound exception */
1291 cpu_send_trap(pc, trapno, uc);
1292 return 1;
1293 } else
1294#endif
1295 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1296 trapno == 0xe ?
d8ecc0b9 1297 (ERROR_sig(uc) >> 1) & 1 : 0,
bf3e8bf1 1298 &uc->uc_sigmask, puc);
2b413144
FB		 1299}
1300
bc51c5c9
FB		 1301#elif defined(__x86_64__)
1302
5a7b542b 1303int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 1304 void *puc)
1305{
5a7b542b 1306 siginfo_t *info = pinfo;
bc51c5c9
FB		 1307 struct ucontext *uc = puc;
1308 unsigned long pc;
1309
1310 pc = uc->uc_mcontext.gregs[REG_RIP];
1311 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1312 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1313 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1314 &uc->uc_sigmask, puc);
1315}
1316
83fb7adf 1317#elif defined(__powerpc__)
2b413144 1318
83fb7adf
FB		 1319/***********************************************************************
1320 * signal context platform-specific definitions
1321 * From Wine
1322 */
1323#ifdef linux
1324/* All Registers access - only for local access */
1325# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1326/* Gpr Registers access */
1327# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1328# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1329# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1330# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1331# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1332# define LR_sig(context) REG_sig(link, context) /* Link register */
1333# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1334/* Float Registers access */
1335# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1336# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1337/* Exception Registers access */
1338# define DAR_sig(context) REG_sig(dar, context)
1339# define DSISR_sig(context) REG_sig(dsisr, context)
1340# define TRAP_sig(context) REG_sig(trap, context)
1341#endif /* linux */
1342
1343#ifdef __APPLE__
1344# include <sys/ucontext.h>
1345typedef struct ucontext SIGCONTEXT;
1346/* All Registers access - only for local access */
1347# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1348# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1349# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1350# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1351/* Gpr Registers access */
1352# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1353# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1354# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1355# define CTR_sig(context) REG_sig(ctr, context)
1356# define XER_sig(context) REG_sig(xer, context) /* Link register */
1357# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1358# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1359/* Float Registers access */
1360# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1361# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1362/* Exception Registers access */
1363# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1364# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1365# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1366#endif /* __APPLE__ */
1367
5a7b542b 1368int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1369 void *puc)
2b413144 1370{
5a7b542b 1371 siginfo_t *info = pinfo;
25eb4484 1372 struct ucontext *uc = puc;
25eb4484 1373 unsigned long pc;
25eb4484
FB		 1374 int is_write;
1375
83fb7adf 1376 pc = IAR_sig(uc);
25eb4484
FB		 1377 is_write = 0;
1378#if 0
1379 /* ppc 4xx case */
83fb7adf 1380 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1381 is_write = 1;
1382#else
83fb7adf 1383 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1384 is_write = 1;
1385#endif
1386 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1387 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1388}
1389
2f87c607
FB		 1390#elif defined(__alpha__)
1391
5a7b542b 1392int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1393 void *puc)
1394{
5a7b542b 1395 siginfo_t *info = pinfo;
2f87c607
FB		 1396 struct ucontext *uc = puc;
1397 uint32_t *pc = uc->uc_mcontext.sc_pc;
1398 uint32_t insn = *pc;
1399 int is_write = 0;
1400
8c6939c0 1401 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1402 switch (insn >> 26) {
1403 case 0x0d: // stw
1404 case 0x0e: // stb
1405 case 0x0f: // stq_u
1406 case 0x24: // stf
1407 case 0x25: // stg
1408 case 0x26: // sts
1409 case 0x27: // stt
1410 case 0x2c: // stl
1411 case 0x2d: // stq
1412 case 0x2e: // stl_c
1413 case 0x2f: // stq_c
1414 is_write = 1;
1415 }
1416
1417 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1418 is_write, &uc->uc_sigmask, puc);
2f87c607 1419}
8c6939c0
FB		 1420#elif defined(__sparc__)
1421
5a7b542b 1422int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1423 void *puc)
8c6939c0 1424{
5a7b542b 1425 siginfo_t *info = pinfo;
8c6939c0
FB		 1426 uint32_t *regs = (uint32_t *)(info + 1);
1427 void *sigmask = (regs + 20);
1428 unsigned long pc;
1429 int is_write;
1430 uint32_t insn;
1431
1432 /* XXX: is there a standard glibc define ? */
1433 pc = regs[1];
1434 /* XXX: need kernel patch to get write flag faster */
1435 is_write = 0;
1436 insn = *(uint32_t *)pc;
1437 if ((insn >> 30) == 3) {
1438 switch((insn >> 19) & 0x3f) {
1439 case 0x05: // stb
1440 case 0x06: // sth
1441 case 0x04: // st
1442 case 0x07: // std
1443 case 0x24: // stf
1444 case 0x27: // stdf
1445 case 0x25: // stfsr
1446 is_write = 1;
1447 break;
1448 }
1449 }
1450 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1451 is_write, sigmask, NULL);
8c6939c0
FB		 1452}
1453
1454#elif defined(__arm__)
1455
5a7b542b 1456int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1457 void *puc)
8c6939c0 1458{
5a7b542b 1459 siginfo_t *info = pinfo;
8c6939c0
FB		 1460 struct ucontext *uc = puc;
1461 unsigned long pc;
1462 int is_write;
1463
1464 pc = uc->uc_mcontext.gregs[R15];
1465 /* XXX: compute is_write */
1466 is_write = 0;
1467 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1468 is_write,
f3a9676a 1469 &uc->uc_sigmask, puc);
8c6939c0
FB		 1470}
1471
38e584a0
FB		 1472#elif defined(__mc68000)
1473
5a7b542b 1474int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1475 void *puc)
1476{
5a7b542b 1477 siginfo_t *info = pinfo;
38e584a0
FB		 1478 struct ucontext *uc = puc;
1479 unsigned long pc;
1480 int is_write;
1481
1482 pc = uc->uc_mcontext.gregs[16];
1483 /* XXX: compute is_write */
1484 is_write = 0;
1485 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1486 is_write,
bf3e8bf1 1487 &uc->uc_sigmask, puc);
38e584a0
FB		 1488}
1489
b8076a74
FB		 1490#elif defined(__ia64)
1491
1492#ifndef __ISR_VALID
1493 /* This ought to be in <bits/siginfo.h>... */
1494# define __ISR_VALID 1
b8076a74
FB		 1495#endif
1496
5a7b542b 1497int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1498{
5a7b542b 1499 siginfo_t *info = pinfo;
b8076a74
FB		 1500 struct ucontext *uc = puc;
1501 unsigned long ip;
1502 int is_write = 0;
1503
1504 ip = uc->uc_mcontext.sc_ip;
1505 switch (host_signum) {
1506 case SIGILL:
1507 case SIGFPE:
1508 case SIGSEGV:
1509 case SIGBUS:
1510 case SIGTRAP:
fd4a43e4 1511 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1512 /* ISR.W (write-access) is bit 33: */
1513 is_write = (info->si_isr >> 33) & 1;
1514 break;
1515
1516 default:
1517 break;
1518 }
1519 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1520 is_write,
1521 &uc->uc_sigmask, puc);
1522}
1523
90cb9493
FB		 1524#elif defined(__s390__)
1525
5a7b542b 1526int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1527 void *puc)
1528{
5a7b542b 1529 siginfo_t *info = pinfo;
90cb9493
FB		 1530 struct ucontext *uc = puc;
1531 unsigned long pc;
1532 int is_write;
1533
1534 pc = uc->uc_mcontext.psw.addr;
1535 /* XXX: compute is_write */
1536 is_write = 0;
1537 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1538 is_write,
1539 &uc->uc_sigmask, puc);
1540}
1541
9de5e440 1542#else
2b413144 1543
3fb2ded1 1544#error host CPU specific signal handler needed
2b413144 1545
9de5e440 1546#endif
67b915a5
FB		 1547
1548#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing