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MIPS disas support
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0
FB		 16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d 19 */
e4533c7a 20#include "config.h"
93ac68bc 21#include "exec.h"
956034d7 22#include "disas.h"
7d13299d 23
fbf9eeb3
FB		 24#if !defined(CONFIG_SOFTMMU)
25#undef EAX
26#undef ECX
27#undef EDX
28#undef EBX
29#undef ESP
30#undef EBP
31#undef ESI
32#undef EDI
33#undef EIP
34#include <signal.h>
35#include <sys/ucontext.h>
36#endif
37
36bdbe54
FB		 38int tb_invalidated_flag;
39
dc99065b 40//#define DEBUG_EXEC
9de5e440 41//#define DEBUG_SIGNAL
7d13299d 42
93ac68bc 43#if defined(TARGET_ARM) || defined(TARGET_SPARC)
e4533c7a
FB		 44/* XXX: unify with i386 target */
45void cpu_loop_exit(void)
46{
47 longjmp(env->jmp_env, 1);
48}
49#endif
3475187d
FB		 50#ifndef TARGET_SPARC
51#define reg_T2
52#endif
e4533c7a 53
fbf9eeb3
FB		 54/* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57void cpu_resume_from_signal(CPUState *env1, void *puc)
58{
59#if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61#endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67#if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72#endif
73 longjmp(env->jmp_env, 1);
74}
75
7d13299d
FB		 76/* main execution loop */
77
e4533c7a 78int cpu_exec(CPUState *env1)
7d13299d 79{
3475187d
FB		 80 int saved_T0, saved_T1;
81#if defined(reg_T2)
82 int saved_T2;
83#endif
e4533c7a 84 CPUState *saved_env;
3475187d 85#if defined(TARGET_I386)
04369ff2
FB		 86#ifdef reg_EAX
87 int saved_EAX;
88#endif
89#ifdef reg_ECX
90 int saved_ECX;
91#endif
92#ifdef reg_EDX
93 int saved_EDX;
94#endif
95#ifdef reg_EBX
96 int saved_EBX;
97#endif
98#ifdef reg_ESP
99 int saved_ESP;
100#endif
101#ifdef reg_EBP
102 int saved_EBP;
103#endif
104#ifdef reg_ESI
105 int saved_ESI;
106#endif
107#ifdef reg_EDI
108 int saved_EDI;
8c6939c0 109#endif
3475187d
FB		 110#elif defined(TARGET_SPARC)
111#if defined(reg_REGWPTR)
112 uint32_t *saved_regwptr;
113#endif
114#endif
8c6939c0
FB		 115#ifdef __sparc__
116 int saved_i7, tmp_T0;
04369ff2 117#endif
68a79315 118 int code_gen_size, ret, interrupt_request;
7d13299d 119 void (*gen_func)(void);
9de5e440 120 TranslationBlock *tb, **ptb;
c27004ec
FB		 121 target_ulong cs_base, pc;
122 uint8_t *tc_ptr;
6dbad63e 123 unsigned int flags;
8c6939c0 124
7d13299d 125 /* first we save global registers */
c27004ec
FB		 126 saved_env = env;
127 env = env1;
7d13299d
FB		 128 saved_T0 = T0;
129 saved_T1 = T1;
3475187d 130#if defined(reg_T2)
e4533c7a 131 saved_T2 = T2;
3475187d 132#endif
e4533c7a
FB		 133#ifdef __sparc__
134 /* we also save i7 because longjmp may not restore it */
135 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
136#endif
137
138#if defined(TARGET_I386)
04369ff2
FB		 139#ifdef reg_EAX
140 saved_EAX = EAX;
04369ff2
FB		 141#endif
142#ifdef reg_ECX
143 saved_ECX = ECX;
04369ff2
FB		 144#endif
145#ifdef reg_EDX
146 saved_EDX = EDX;
04369ff2
FB		 147#endif
148#ifdef reg_EBX
149 saved_EBX = EBX;
04369ff2
FB		 150#endif
151#ifdef reg_ESP
152 saved_ESP = ESP;
04369ff2
FB		 153#endif
154#ifdef reg_EBP
155 saved_EBP = EBP;
04369ff2
FB		 156#endif
157#ifdef reg_ESI
158 saved_ESI = ESI;
04369ff2
FB		 159#endif
160#ifdef reg_EDI
161 saved_EDI = EDI;
04369ff2 162#endif
0d1a29f9
FB		 163
164 env_to_regs();
9de5e440 165 /* put eflags in CPU temporary format */
fc2b4c48
FB		 166 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
167 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 168 CC_OP = CC_OP_EFLAGS;
fc2b4c48 169 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a
FB		 170#elif defined(TARGET_ARM)
171 {
172 unsigned int psr;
173 psr = env->cpsr;
174 env->CF = (psr >> 29) & 1;
175 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
176 env->VF = (psr << 3) & 0x80000000;
99c475ab
FB		 177 env->QF = (psr >> 27) & 1;
178 env->cpsr = psr & ~CACHED_CPSR_BITS;
e4533c7a 179 }
93ac68bc 180#elif defined(TARGET_SPARC)
3475187d
FB		 181#if defined(reg_REGWPTR)
182 saved_regwptr = REGWPTR;
183#endif
67867308 184#elif defined(TARGET_PPC)
e4533c7a
FB		 185#else
186#error unsupported target CPU
187#endif
3fb2ded1 188 env->exception_index = -1;
9d27abd9 189
7d13299d 190 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 191 for(;;) {
192 if (setjmp(env->jmp_env) == 0) {
ee8b7021 193 env->current_tb = NULL;
3fb2ded1
FB		 194 /* if an exception is pending, we execute it here */
195 if (env->exception_index >= 0) {
196 if (env->exception_index >= EXCP_INTERRUPT) {
197 /* exit request from the cpu execution loop */
198 ret = env->exception_index;
199 break;
200 } else if (env->user_mode_only) {
201 /* if user mode only, we simulate a fake exception
202 which will be hanlded outside the cpu execution
203 loop */
83479e77 204#if defined(TARGET_I386)
3fb2ded1
FB		 205 do_interrupt_user(env->exception_index,
206 env->exception_is_int,
207 env->error_code,
208 env->exception_next_eip);
83479e77 209#endif
3fb2ded1
FB		 210 ret = env->exception_index;
211 break;
212 } else {
83479e77 213#if defined(TARGET_I386)
3fb2ded1
FB		 214 /* simulate a real cpu exception. On i386, it can
215 trigger new exceptions, but we do not handle
216 double or triple faults yet. */
217 do_interrupt(env->exception_index,
218 env->exception_is_int,
219 env->error_code,
d05e66d2 220 env->exception_next_eip, 0);
ce09776b
FB		 221#elif defined(TARGET_PPC)
222 do_interrupt(env);
e95c8d51 223#elif defined(TARGET_SPARC)
1a0c3292 224 do_interrupt(env->exception_index);
83479e77 225#endif
3fb2ded1
FB		 226 }
227 env->exception_index = -1;
9df217a3
FB		 228 }
229#ifdef USE_KQEMU
230 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
231 int ret;
232 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
233 ret = kqemu_cpu_exec(env);
234 /* put eflags in CPU temporary format */
235 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
236 DF = 1 - (2 * ((env->eflags >> 10) & 1));
237 CC_OP = CC_OP_EFLAGS;
238 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
239 if (ret == 1) {
240 /* exception */
241 longjmp(env->jmp_env, 1);
242 } else if (ret == 2) {
243 /* softmmu execution needed */
244 } else {
245 if (env->interrupt_request != 0) {
246 /* hardware interrupt will be executed just after */
247 } else {
248 /* otherwise, we restart */
249 longjmp(env->jmp_env, 1);
250 }
251 }
3fb2ded1 252 }
9df217a3
FB		 253#endif
254
3fb2ded1
FB		 255 T0 = 0; /* force lookup of first TB */
256 for(;;) {
8c6939c0 257#ifdef __sparc__
3fb2ded1
FB		 258 /* g1 can be modified by some libc? functions */
259 tmp_T0 = T0;
8c6939c0 260#endif
68a79315 261 interrupt_request = env->interrupt_request;
2e255c6b 262 if (__builtin_expect(interrupt_request, 0)) {
68a79315
FB		 263#if defined(TARGET_I386)
264 /* if hardware interrupt pending, we execute it */
265 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316
FB		 266 (env->eflags & IF_MASK) &&
267 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 268 int intno;
fbf9eeb3 269 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
a541f297 270 intno = cpu_get_pic_interrupt(env);
f193c797 271 if (loglevel & CPU_LOG_TB_IN_ASM) {
68a79315
FB		 272 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
273 }
d05e66d2 274 do_interrupt(intno, 0, 0, 0, 1);
907a5b26
FB		 275 /* ensure that no TB jump will be modified as
276 the program flow was changed */
277#ifdef __sparc__
278 tmp_T0 = 0;
279#else
280 T0 = 0;
281#endif
68a79315 282 }
ce09776b 283#elif defined(TARGET_PPC)
9fddaa0c
FB		 284#if 0
285 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
286 cpu_ppc_reset(env);
287 }
288#endif
289 if (msr_ee != 0) {
ce09776b 290 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
9fddaa0c
FB		 291 /* Raise it */
292 env->exception_index = EXCP_EXTERNAL;
293 env->error_code = 0;
ce09776b
FB		 294 do_interrupt(env);
295 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
9fddaa0c
FB		 296 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
297 /* Raise it */
298 env->exception_index = EXCP_DECR;
299 env->error_code = 0;
300 do_interrupt(env);
301 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
302 }
ce09776b 303 }
e95c8d51 304#elif defined(TARGET_SPARC)
66321a11
FB		 305 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
306 (env->psret != 0)) {
307 int pil = env->interrupt_index & 15;
308 int type = env->interrupt_index & 0xf0;
309
310 if (((type == TT_EXTINT) &&
311 (pil == 15 || pil > env->psrpil)) ||
312 type != TT_EXTINT) {
313 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
314 do_interrupt(env->interrupt_index);
315 env->interrupt_index = 0;
316 }
e95c8d51
FB		 317 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
318 //do_interrupt(0, 0, 0, 0, 0);
319 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
320 }
68a79315 321#endif
bf3e8bf1
FB		 322 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
323 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
324 /* ensure that no TB jump will be modified as
325 the program flow was changed */
326#ifdef __sparc__
327 tmp_T0 = 0;
328#else
329 T0 = 0;
330#endif
331 }
68a79315
FB		 332 if (interrupt_request & CPU_INTERRUPT_EXIT) {
333 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
334 env->exception_index = EXCP_INTERRUPT;
335 cpu_loop_exit();
336 }
3fb2ded1 337 }
7d13299d 338#ifdef DEBUG_EXEC
c27004ec 339 if ((loglevel & CPU_LOG_EXEC)) {
e4533c7a 340#if defined(TARGET_I386)
3fb2ded1 341 /* restore flags in standard format */
fc9f715d 342#ifdef reg_EAX
3fb2ded1 343 env->regs[R_EAX] = EAX;
fc9f715d
FB		 344#endif
345#ifdef reg_EBX
3fb2ded1 346 env->regs[R_EBX] = EBX;
fc9f715d
FB		 347#endif
348#ifdef reg_ECX
3fb2ded1 349 env->regs[R_ECX] = ECX;
fc9f715d
FB		 350#endif
351#ifdef reg_EDX
3fb2ded1 352 env->regs[R_EDX] = EDX;
fc9f715d
FB		 353#endif
354#ifdef reg_ESI
3fb2ded1 355 env->regs[R_ESI] = ESI;
fc9f715d
FB		 356#endif
357#ifdef reg_EDI
3fb2ded1 358 env->regs[R_EDI] = EDI;
fc9f715d
FB		 359#endif
360#ifdef reg_EBP
3fb2ded1 361 env->regs[R_EBP] = EBP;
fc9f715d
FB		 362#endif
363#ifdef reg_ESP
3fb2ded1 364 env->regs[R_ESP] = ESP;
fc9f715d 365#endif
3fb2ded1 366 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
7fe48483 367 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
3fb2ded1 368 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 369#elif defined(TARGET_ARM)
1b21b62a 370 env->cpsr = compute_cpsr();
7fe48483 371 cpu_dump_state(env, logfile, fprintf, 0);
99c475ab 372 env->cpsr &= ~CACHED_CPSR_BITS;
93ac68bc 373#elif defined(TARGET_SPARC)
3475187d
FB		 374 REGWPTR = env->regbase + (env->cwp * 16);
375 env->regwptr = REGWPTR;
376 cpu_dump_state(env, logfile, fprintf, 0);
67867308 377#elif defined(TARGET_PPC)
7fe48483 378 cpu_dump_state(env, logfile, fprintf, 0);
e4533c7a
FB		 379#else
380#error unsupported target CPU
381#endif
3fb2ded1 382 }
7d13299d 383#endif
3f337316
FB		 384 /* we record a subset of the CPU state. It will
385 always be the same before a given translated block
386 is executed. */
e4533c7a 387#if defined(TARGET_I386)
2e255c6b 388 flags = env->hflags;
3f337316 389 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
3fb2ded1
FB		 390 cs_base = env->segs[R_CS].base;
391 pc = cs_base + env->eip;
e4533c7a 392#elif defined(TARGET_ARM)
b7bcbe95
FB		 393 flags = env->thumb | (env->vfp.vec_len << 1)
394 | (env->vfp.vec_stride << 4);
3fb2ded1 395 cs_base = 0;
c27004ec 396 pc = env->regs[15];
93ac68bc 397#elif defined(TARGET_SPARC)
3475187d
FB		 398#ifdef TARGET_SPARC64
399 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
400#else
401 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
402#endif
c27004ec
FB		 403 cs_base = env->npc;
404 pc = env->pc;
67867308 405#elif defined(TARGET_PPC)
111bfab3
FB		 406 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
407 (msr_se << MSR_SE) | (msr_le << MSR_LE);
67867308 408 cs_base = 0;
c27004ec 409 pc = env->nip;
e4533c7a
FB		 410#else
411#error unsupported CPU
412#endif
c27004ec 413 tb = tb_find(&ptb, pc, cs_base,
3fb2ded1 414 flags);
d4e8164f 415 if (!tb) {
1376847f
FB		 416 TranslationBlock **ptb1;
417 unsigned int h;
418 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
419
420
3fb2ded1 421 spin_lock(&tb_lock);
1376847f
FB		 422
423 tb_invalidated_flag = 0;
0d1a29f9
FB		 424
425 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
1376847f
FB		 426
427 /* find translated block using physical mappings */
c27004ec 428 phys_pc = get_phys_addr_code(env, pc);
1376847f
FB		 429 phys_page1 = phys_pc & TARGET_PAGE_MASK;
430 phys_page2 = -1;
431 h = tb_phys_hash_func(phys_pc);
432 ptb1 = &tb_phys_hash[h];
433 for(;;) {
434 tb = *ptb1;
435 if (!tb)
436 goto not_found;
c27004ec 437 if (tb->pc == pc &&
1376847f 438 tb->page_addr[0] == phys_page1 &&
c27004ec 439 tb->cs_base == cs_base &&
1376847f
FB		 440 tb->flags == flags) {
441 /* check next page if needed */
b516f85c 442 if (tb->page_addr[1] != -1) {
c27004ec 443 virt_page2 = (pc & TARGET_PAGE_MASK) +
b516f85c 444 TARGET_PAGE_SIZE;
1376847f
FB		 445 phys_page2 = get_phys_addr_code(env, virt_page2);
446 if (tb->page_addr[1] == phys_page2)
447 goto found;
448 } else {
449 goto found;
450 }
451 }
452 ptb1 = &tb->phys_hash_next;
453 }
454 not_found:
3fb2ded1 455 /* if no translated code available, then translate it now */
c27004ec 456 tb = tb_alloc(pc);
3fb2ded1
FB		 457 if (!tb) {
458 /* flush must be done */
b453b70b 459 tb_flush(env);
3fb2ded1 460 /* cannot fail at this point */
c27004ec 461 tb = tb_alloc(pc);
3fb2ded1 462 /* don't forget to invalidate previous TB info */
c27004ec 463 ptb = &tb_hash[tb_hash_func(pc)];
3fb2ded1
FB		 464 T0 = 0;
465 }
466 tc_ptr = code_gen_ptr;
467 tb->tc_ptr = tc_ptr;
c27004ec 468 tb->cs_base = cs_base;
3fb2ded1 469 tb->flags = flags;
facc68be 470 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
1376847f
FB		 471 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
472
473 /* check next page if needed */
c27004ec 474 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
1376847f 475 phys_page2 = -1;
c27004ec 476 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
1376847f
FB		 477 phys_page2 = get_phys_addr_code(env, virt_page2);
478 }
479 tb_link_phys(tb, phys_pc, phys_page2);
480
481 found:
36bdbe54
FB		 482 if (tb_invalidated_flag) {
483 /* as some TB could have been invalidated because
484 of memory exceptions while generating the code, we
485 must recompute the hash index here */
c27004ec 486 ptb = &tb_hash[tb_hash_func(pc)];
36bdbe54
FB		 487 while (*ptb != NULL)
488 ptb = &(*ptb)->hash_next;
489 T0 = 0;
490 }
1376847f 491 /* we add the TB in the virtual pc hash table */
3fb2ded1
FB		 492 *ptb = tb;
493 tb->hash_next = NULL;
494 tb_link(tb);
25eb4484 495 spin_unlock(&tb_lock);
9de5e440 496 }
9d27abd9 497#ifdef DEBUG_EXEC
c1135f61 498 if ((loglevel & CPU_LOG_EXEC)) {
c27004ec
FB		 499 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
500 (long)tb->tc_ptr, tb->pc,
501 lookup_symbol(tb->pc));
3fb2ded1 502 }
9d27abd9 503#endif
8c6939c0 504#ifdef __sparc__
3fb2ded1 505 T0 = tmp_T0;
8c6939c0 506#endif
facc68be 507 /* see if we can patch the calling TB. */
c27004ec
FB		 508 {
509 if (T0 != 0
bf3e8bf1
FB		 510#if defined(TARGET_I386) && defined(USE_CODE_COPY)
511 && (tb->cflags & CF_CODE_COPY) ==
512 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
513#endif
514 ) {
3fb2ded1 515 spin_lock(&tb_lock);
c27004ec 516 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
97eb5b14
FB		 517#if defined(USE_CODE_COPY)
518 /* propagates the FP use info */
519 ((TranslationBlock *)(T0 & ~3))->cflags |=
520 (tb->cflags & CF_FP_USED);
521#endif
3fb2ded1
FB		 522 spin_unlock(&tb_lock);
523 }
c27004ec 524 }
3fb2ded1 525 tc_ptr = tb->tc_ptr;
83479e77 526 env->current_tb = tb;
3fb2ded1
FB		 527 /* execute the generated code */
528 gen_func = (void *)tc_ptr;
8c6939c0 529#if defined(__sparc__)
3fb2ded1
FB		 530 __asm__ __volatile__("call %0\n\t"
531 "mov %%o7,%%i0"
532 : /* no outputs */
533 : "r" (gen_func)
534 : "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0 535#elif defined(__arm__)
3fb2ded1
FB		 536 asm volatile ("mov pc, %0\n\t"
537 ".global exec_loop\n\t"
538 "exec_loop:\n\t"
539 : /* no outputs */
540 : "r" (gen_func)
541 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
bf3e8bf1
FB		 542#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
543{
544 if (!(tb->cflags & CF_CODE_COPY)) {
97eb5b14
FB		 545 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
546 save_native_fp_state(env);
547 }
bf3e8bf1
FB		 548 gen_func();
549 } else {
97eb5b14
FB		 550 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
551 restore_native_fp_state(env);
552 }
bf3e8bf1
FB		 553 /* we work with native eflags */
554 CC_SRC = cc_table[CC_OP].compute_all();
555 CC_OP = CC_OP_EFLAGS;
556 asm(".globl exec_loop\n"
557 "\n"
558 "debug1:\n"
559 " pushl %%ebp\n"
560 " fs movl %10, %9\n"
561 " fs movl %11, %%eax\n"
562 " andl $0x400, %%eax\n"
563 " fs orl %8, %%eax\n"
564 " pushl %%eax\n"
565 " popf\n"
566 " fs movl %%esp, %12\n"
567 " fs movl %0, %%eax\n"
568 " fs movl %1, %%ecx\n"
569 " fs movl %2, %%edx\n"
570 " fs movl %3, %%ebx\n"
571 " fs movl %4, %%esp\n"
572 " fs movl %5, %%ebp\n"
573 " fs movl %6, %%esi\n"
574 " fs movl %7, %%edi\n"
575 " fs jmp *%9\n"
576 "exec_loop:\n"
577 " fs movl %%esp, %4\n"
578 " fs movl %12, %%esp\n"
579 " fs movl %%eax, %0\n"
580 " fs movl %%ecx, %1\n"
581 " fs movl %%edx, %2\n"
582 " fs movl %%ebx, %3\n"
583 " fs movl %%ebp, %5\n"
584 " fs movl %%esi, %6\n"
585 " fs movl %%edi, %7\n"
586 " pushf\n"
587 " popl %%eax\n"
588 " movl %%eax, %%ecx\n"
589 " andl $0x400, %%ecx\n"
590 " shrl $9, %%ecx\n"
591 " andl $0x8d5, %%eax\n"
592 " fs movl %%eax, %8\n"
593 " movl $1, %%eax\n"
594 " subl %%ecx, %%eax\n"
595 " fs movl %%eax, %11\n"
596 " fs movl %9, %%ebx\n" /* get T0 value */
597 " popl %%ebp\n"
598 :
599 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
600 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
601 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
602 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
603 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
604 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
605 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
606 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
607 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
608 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
609 "a" (gen_func),
610 "m" (*(uint8_t *)offsetof(CPUState, df)),
611 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
612 : "%ecx", "%edx"
613 );
614 }
615}
b8076a74
FB		 616#elif defined(__ia64)
617 struct fptr {
618 void *ip;
619 void *gp;
620 } fp;
621
622 fp.ip = tc_ptr;
623 fp.gp = code_gen_buffer + 2 * (1 << 20);
624 (*(void (*)(void)) &fp)();
ae228531 625#else
3fb2ded1 626 gen_func();
ae228531 627#endif
83479e77 628 env->current_tb = NULL;
4cbf74b6
FB		 629 /* reset soft MMU for next block (it can currently
630 only be set by a memory fault) */
631#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316
FB		 632 if (env->hflags & HF_SOFTMMU_MASK) {
633 env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6
FB		 634 /* do not allow linking to another block */
635 T0 = 0;
636 }
637#endif
3fb2ded1
FB		 638 }
639 } else {
0d1a29f9 640 env_to_regs();
7d13299d 641 }
3fb2ded1
FB		 642 } /* for(;;) */
643
7d13299d 644
e4533c7a 645#if defined(TARGET_I386)
97eb5b14
FB		 646#if defined(USE_CODE_COPY)
647 if (env->native_fp_regs) {
648 save_native_fp_state(env);
649 }
650#endif
9de5e440 651 /* restore flags in standard format */
fc2b4c48 652 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
9de5e440 653
7d13299d 654 /* restore global registers */
04369ff2
FB		 655#ifdef reg_EAX
656 EAX = saved_EAX;
657#endif
658#ifdef reg_ECX
659 ECX = saved_ECX;
660#endif
661#ifdef reg_EDX
662 EDX = saved_EDX;
663#endif
664#ifdef reg_EBX
665 EBX = saved_EBX;
666#endif
667#ifdef reg_ESP
668 ESP = saved_ESP;
669#endif
670#ifdef reg_EBP
671 EBP = saved_EBP;
672#endif
673#ifdef reg_ESI
674 ESI = saved_ESI;
675#endif
676#ifdef reg_EDI
677 EDI = saved_EDI;
8c6939c0 678#endif
e4533c7a 679#elif defined(TARGET_ARM)
1b21b62a 680 env->cpsr = compute_cpsr();
b7bcbe95 681 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 682#elif defined(TARGET_SPARC)
3475187d
FB		 683#if defined(reg_REGWPTR)
684 REGWPTR = saved_regwptr;
685#endif
67867308 686#elif defined(TARGET_PPC)
e4533c7a
FB		 687#else
688#error unsupported target CPU
689#endif
8c6939c0
FB		 690#ifdef __sparc__
691 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2 692#endif
7d13299d
FB		 693 T0 = saved_T0;
694 T1 = saved_T1;
3475187d 695#if defined(reg_T2)
e4533c7a 696 T2 = saved_T2;
3475187d 697#endif
7d13299d
FB		 698 env = saved_env;
699 return ret;
700}
6dbad63e 701
fbf9eeb3
FB		 702/* must only be called from the generated code as an exception can be
703 generated */
704void tb_invalidate_page_range(target_ulong start, target_ulong end)
705{
dc5d0b3d
FB		 706 /* XXX: cannot enable it yet because it yields to MMU exception
707 where NIP != read address on PowerPC */
708#if 0
fbf9eeb3
FB		 709 target_ulong phys_addr;
710 phys_addr = get_phys_addr_code(env, start);
711 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 712#endif
fbf9eeb3
FB		 713}
714
1a18c71b 715#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 716
6dbad63e
FB		 717void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
718{
719 CPUX86State *saved_env;
720
721 saved_env = env;
722 env = s;
a412ac57 723 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 724 selector &= 0xffff;
2e255c6b 725 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 726 (selector << 4), 0xffff, 0);
a513fe19 727 } else {
b453b70b 728 load_seg(seg_reg, selector);
a513fe19 729 }
6dbad63e
FB		 730 env = saved_env;
731}
9de5e440 732
d0a1ffc9
FB		 733void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
734{
735 CPUX86State *saved_env;
736
737 saved_env = env;
738 env = s;
739
c27004ec 740 helper_fsave((target_ulong)ptr, data32);
d0a1ffc9
FB		 741
742 env = saved_env;
743}
744
745void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
746{
747 CPUX86State *saved_env;
748
749 saved_env = env;
750 env = s;
751
c27004ec 752 helper_frstor((target_ulong)ptr, data32);
d0a1ffc9
FB		 753
754 env = saved_env;
755}
756
e4533c7a
FB		 757#endif /* TARGET_I386 */
758
67b915a5
FB		 759#if !defined(CONFIG_SOFTMMU)
760
3fb2ded1
FB		 761#if defined(TARGET_I386)
762
b56dad1c 763/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 764 the effective address of the memory exception. 'is_write' is 1 if a
765 write caused the exception and otherwise 0'. 'old_set' is the
766 signal set which should be restored */
2b413144 767static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 768 int is_write, sigset_t *old_set,
769 void *puc)
9de5e440 770{
a513fe19
FB		 771 TranslationBlock *tb;
772 int ret;
68a79315 773
83479e77
FB		 774 if (cpu_single_env)
775 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 776#if defined(DEBUG_SIGNAL)
bf3e8bf1
FB		 777 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
778 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 779#endif
25eb4484 780 /* XXX: locking issue */
fbf9eeb3 781 if (is_write && page_unprotect(address, pc, puc)) {
fd6ce8f6
FB		 782 return 1;
783 }
fbf9eeb3 784
3fb2ded1 785 /* see if it is an MMU fault */
93a40ea9
FB		 786 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
787 ((env->hflags & HF_CPL_MASK) == 3), 0);
3fb2ded1
FB		 788 if (ret < 0)
789 return 0; /* not an MMU fault */
790 if (ret == 0)
791 return 1; /* the MMU fault was handled without causing real CPU fault */
792 /* now we have a real cpu fault */
a513fe19
FB		 793 tb = tb_find_pc(pc);
794 if (tb) {
9de5e440
FB		 795 /* the PC is inside the translated code. It means that we have
796 a virtual CPU fault */
bf3e8bf1 797 cpu_restore_state(tb, env, pc, puc);
3fb2ded1 798 }
4cbf74b6 799 if (ret == 1) {
3fb2ded1 800#if 0
4cbf74b6
FB		 801 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
802 env->eip, env->cr[2], env->error_code);
3fb2ded1 803#endif
4cbf74b6
FB		 804 /* we restore the process signal mask as the sigreturn should
805 do it (XXX: use sigsetjmp) */
806 sigprocmask(SIG_SETMASK, old_set, NULL);
807 raise_exception_err(EXCP0E_PAGE, env->error_code);
808 } else {
809 /* activate soft MMU for this block */
3f337316 810 env->hflags |= HF_SOFTMMU_MASK;
fbf9eeb3 811 cpu_resume_from_signal(env, puc);
4cbf74b6 812 }
3fb2ded1
FB		 813 /* never comes here */
814 return 1;
815}
816
e4533c7a 817#elif defined(TARGET_ARM)
3fb2ded1 818static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 819 int is_write, sigset_t *old_set,
820 void *puc)
3fb2ded1 821{
68016c62
FB		 822 TranslationBlock *tb;
823 int ret;
824
825 if (cpu_single_env)
826 env = cpu_single_env; /* XXX: find a correct solution for multithread */
827#if defined(DEBUG_SIGNAL)
828 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
829 pc, address, is_write, *(unsigned long *)old_set);
830#endif
9f0777ed
FB		 831 /* XXX: locking issue */
832 if (is_write && page_unprotect(address, pc, puc)) {
833 return 1;
834 }
68016c62
FB		 835 /* see if it is an MMU fault */
836 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
837 if (ret < 0)
838 return 0; /* not an MMU fault */
839 if (ret == 0)
840 return 1; /* the MMU fault was handled without causing real CPU fault */
841 /* now we have a real cpu fault */
842 tb = tb_find_pc(pc);
843 if (tb) {
844 /* the PC is inside the translated code. It means that we have
845 a virtual CPU fault */
846 cpu_restore_state(tb, env, pc, puc);
847 }
848 /* we restore the process signal mask as the sigreturn should
849 do it (XXX: use sigsetjmp) */
850 sigprocmask(SIG_SETMASK, old_set, NULL);
851 cpu_loop_exit();
3fb2ded1 852}
93ac68bc
FB		 853#elif defined(TARGET_SPARC)
854static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 855 int is_write, sigset_t *old_set,
856 void *puc)
93ac68bc 857{
68016c62
FB		 858 TranslationBlock *tb;
859 int ret;
860
861 if (cpu_single_env)
862 env = cpu_single_env; /* XXX: find a correct solution for multithread */
863#if defined(DEBUG_SIGNAL)
864 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
865 pc, address, is_write, *(unsigned long *)old_set);
866#endif
b453b70b 867 /* XXX: locking issue */
fbf9eeb3 868 if (is_write && page_unprotect(address, pc, puc)) {
b453b70b
FB		 869 return 1;
870 }
68016c62
FB		 871 /* see if it is an MMU fault */
872 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
873 if (ret < 0)
874 return 0; /* not an MMU fault */
875 if (ret == 0)
876 return 1; /* the MMU fault was handled without causing real CPU fault */
877 /* now we have a real cpu fault */
878 tb = tb_find_pc(pc);
879 if (tb) {
880 /* the PC is inside the translated code. It means that we have
881 a virtual CPU fault */
882 cpu_restore_state(tb, env, pc, puc);
883 }
884 /* we restore the process signal mask as the sigreturn should
885 do it (XXX: use sigsetjmp) */
886 sigprocmask(SIG_SETMASK, old_set, NULL);
887 cpu_loop_exit();
93ac68bc 888}
67867308
FB		 889#elif defined (TARGET_PPC)
890static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
bf3e8bf1
FB		 891 int is_write, sigset_t *old_set,
892 void *puc)
67867308
FB		 893{
894 TranslationBlock *tb;
ce09776b 895 int ret;
67867308 896
67867308
FB		 897 if (cpu_single_env)
898 env = cpu_single_env; /* XXX: find a correct solution for multithread */
67867308
FB		 899#if defined(DEBUG_SIGNAL)
900 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
901 pc, address, is_write, *(unsigned long *)old_set);
902#endif
903 /* XXX: locking issue */
fbf9eeb3 904 if (is_write && page_unprotect(address, pc, puc)) {
67867308
FB		 905 return 1;
906 }
907
ce09776b 908 /* see if it is an MMU fault */
7f957d28 909 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
ce09776b
FB		 910 if (ret < 0)
911 return 0; /* not an MMU fault */
912 if (ret == 0)
913 return 1; /* the MMU fault was handled without causing real CPU fault */
914
67867308
FB		 915 /* now we have a real cpu fault */
916 tb = tb_find_pc(pc);
917 if (tb) {
918 /* the PC is inside the translated code. It means that we have
919 a virtual CPU fault */
bf3e8bf1 920 cpu_restore_state(tb, env, pc, puc);
67867308 921 }
ce09776b 922 if (ret == 1) {
67867308 923#if 0
ce09776b
FB		 924 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
925 env->nip, env->error_code, tb);
67867308
FB		 926#endif
927 /* we restore the process signal mask as the sigreturn should
928 do it (XXX: use sigsetjmp) */
bf3e8bf1 929 sigprocmask(SIG_SETMASK, old_set, NULL);
9fddaa0c 930 do_raise_exception_err(env->exception_index, env->error_code);
ce09776b
FB		 931 } else {
932 /* activate soft MMU for this block */
fbf9eeb3 933 cpu_resume_from_signal(env, puc);
ce09776b 934 }
67867308
FB		 935 /* never comes here */
936 return 1;
937}
e4533c7a
FB		 938#else
939#error unsupported target CPU
940#endif
9de5e440 941
2b413144
FB		 942#if defined(__i386__)
943
bf3e8bf1
FB		 944#if defined(USE_CODE_COPY)
945static void cpu_send_trap(unsigned long pc, int trap,
946 struct ucontext *uc)
947{
948 TranslationBlock *tb;
949
950 if (cpu_single_env)
951 env = cpu_single_env; /* XXX: find a correct solution for multithread */
952 /* now we have a real cpu fault */
953 tb = tb_find_pc(pc);
954 if (tb) {
955 /* the PC is inside the translated code. It means that we have
956 a virtual CPU fault */
957 cpu_restore_state(tb, env, pc, uc);
958 }
959 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
960 raise_exception_err(trap, env->error_code);
961}
962#endif
963
e4533c7a
FB		 964int cpu_signal_handler(int host_signum, struct siginfo *info,
965 void *puc)
9de5e440 966{
9de5e440
FB		 967 struct ucontext *uc = puc;
968 unsigned long pc;
bf3e8bf1 969 int trapno;
97eb5b14 970
d691f669
FB		 971#ifndef REG_EIP
972/* for glibc 2.1 */
fd6ce8f6
FB		 973#define REG_EIP EIP
974#define REG_ERR ERR
975#define REG_TRAPNO TRAPNO
d691f669 976#endif
fc2b4c48 977 pc = uc->uc_mcontext.gregs[REG_EIP];
bf3e8bf1
FB		 978 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
979#if defined(TARGET_I386) && defined(USE_CODE_COPY)
980 if (trapno == 0x00 || trapno == 0x05) {
981 /* send division by zero or bound exception */
982 cpu_send_trap(pc, trapno, uc);
983 return 1;
984 } else
985#endif
986 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
987 trapno == 0xe ?
988 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
989 &uc->uc_sigmask, puc);
2b413144
FB		 990}
991
bc51c5c9
FB		 992#elif defined(__x86_64__)
993
994int cpu_signal_handler(int host_signum, struct siginfo *info,
995 void *puc)
996{
997 struct ucontext *uc = puc;
998 unsigned long pc;
999
1000 pc = uc->uc_mcontext.gregs[REG_RIP];
1001 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1002 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1003 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1004 &uc->uc_sigmask, puc);
1005}
1006
83fb7adf 1007#elif defined(__powerpc__)
2b413144 1008
83fb7adf
FB		 1009/***********************************************************************
1010 * signal context platform-specific definitions
1011 * From Wine
1012 */
1013#ifdef linux
1014/* All Registers access - only for local access */
1015# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1016/* Gpr Registers access */
1017# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1018# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1019# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1020# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1021# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1022# define LR_sig(context) REG_sig(link, context) /* Link register */
1023# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1024/* Float Registers access */
1025# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1026# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1027/* Exception Registers access */
1028# define DAR_sig(context) REG_sig(dar, context)
1029# define DSISR_sig(context) REG_sig(dsisr, context)
1030# define TRAP_sig(context) REG_sig(trap, context)
1031#endif /* linux */
1032
1033#ifdef __APPLE__
1034# include <sys/ucontext.h>
1035typedef struct ucontext SIGCONTEXT;
1036/* All Registers access - only for local access */
1037# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1038# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1039# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1040# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1041/* Gpr Registers access */
1042# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1043# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1044# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1045# define CTR_sig(context) REG_sig(ctr, context)
1046# define XER_sig(context) REG_sig(xer, context) /* Link register */
1047# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1048# define CR_sig(context) REG_sig(cr, context) /* Condition register */
1049/* Float Registers access */
1050# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1051# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1052/* Exception Registers access */
1053# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1054# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1055# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1056#endif /* __APPLE__ */
1057
d1d9f421 1058int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a 1059 void *puc)
2b413144 1060{
25eb4484 1061 struct ucontext *uc = puc;
25eb4484 1062 unsigned long pc;
25eb4484
FB		 1063 int is_write;
1064
83fb7adf 1065 pc = IAR_sig(uc);
25eb4484
FB		 1066 is_write = 0;
1067#if 0
1068 /* ppc 4xx case */
83fb7adf 1069 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1070 is_write = 1;
1071#else
83fb7adf 1072 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1073 is_write = 1;
1074#endif
1075 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1076 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1077}
1078
2f87c607
FB		 1079#elif defined(__alpha__)
1080
e4533c7a 1081int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607
FB		 1082 void *puc)
1083{
1084 struct ucontext *uc = puc;
1085 uint32_t *pc = uc->uc_mcontext.sc_pc;
1086 uint32_t insn = *pc;
1087 int is_write = 0;
1088
8c6939c0 1089 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1090 switch (insn >> 26) {
1091 case 0x0d: // stw
1092 case 0x0e: // stb
1093 case 0x0f: // stq_u
1094 case 0x24: // stf
1095 case 0x25: // stg
1096 case 0x26: // sts
1097 case 0x27: // stt
1098 case 0x2c: // stl
1099 case 0x2d: // stq
1100 case 0x2e: // stl_c
1101 case 0x2f: // stq_c
1102 is_write = 1;
1103 }
1104
1105 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1106 is_write, &uc->uc_sigmask, puc);
2f87c607 1107}
8c6939c0
FB		 1108#elif defined(__sparc__)
1109
e4533c7a
FB		 1110int cpu_signal_handler(int host_signum, struct siginfo *info,
1111 void *puc)
8c6939c0
FB		 1112{
1113 uint32_t *regs = (uint32_t *)(info + 1);
1114 void *sigmask = (regs + 20);
1115 unsigned long pc;
1116 int is_write;
1117 uint32_t insn;
1118
1119 /* XXX: is there a standard glibc define ? */
1120 pc = regs[1];
1121 /* XXX: need kernel patch to get write flag faster */
1122 is_write = 0;
1123 insn = *(uint32_t *)pc;
1124 if ((insn >> 30) == 3) {
1125 switch((insn >> 19) & 0x3f) {
1126 case 0x05: // stb
1127 case 0x06: // sth
1128 case 0x04: // st
1129 case 0x07: // std
1130 case 0x24: // stf
1131 case 0x27: // stdf
1132 case 0x25: // stfsr
1133 is_write = 1;
1134 break;
1135 }
1136 }
1137 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1138 is_write, sigmask, NULL);
8c6939c0
FB		 1139}
1140
1141#elif defined(__arm__)
1142
e4533c7a
FB		 1143int cpu_signal_handler(int host_signum, struct siginfo *info,
1144 void *puc)
8c6939c0
FB		 1145{
1146 struct ucontext *uc = puc;
1147 unsigned long pc;
1148 int is_write;
1149
1150 pc = uc->uc_mcontext.gregs[R15];
1151 /* XXX: compute is_write */
1152 is_write = 0;
1153 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1154 is_write,
1155 &uc->uc_sigmask);
1156}
1157
38e584a0
FB		 1158#elif defined(__mc68000)
1159
1160int cpu_signal_handler(int host_signum, struct siginfo *info,
1161 void *puc)
1162{
1163 struct ucontext *uc = puc;
1164 unsigned long pc;
1165 int is_write;
1166
1167 pc = uc->uc_mcontext.gregs[16];
1168 /* XXX: compute is_write */
1169 is_write = 0;
1170 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1171 is_write,
bf3e8bf1 1172 &uc->uc_sigmask, puc);
38e584a0
FB		 1173}
1174
b8076a74
FB		 1175#elif defined(__ia64)
1176
1177#ifndef __ISR_VALID
1178 /* This ought to be in <bits/siginfo.h>... */
1179# define __ISR_VALID 1
1180# define si_flags _sifields._sigfault._si_pad0
1181#endif
1182
1183int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1184{
1185 struct ucontext *uc = puc;
1186 unsigned long ip;
1187 int is_write = 0;
1188
1189 ip = uc->uc_mcontext.sc_ip;
1190 switch (host_signum) {
1191 case SIGILL:
1192 case SIGFPE:
1193 case SIGSEGV:
1194 case SIGBUS:
1195 case SIGTRAP:
1196 if (info->si_code && (info->si_flags & __ISR_VALID))
1197 /* ISR.W (write-access) is bit 33: */
1198 is_write = (info->si_isr >> 33) & 1;
1199 break;
1200
1201 default:
1202 break;
1203 }
1204 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1205 is_write,
1206 &uc->uc_sigmask, puc);
1207}
1208
9de5e440 1209#else
2b413144 1210
3fb2ded1 1211#error host CPU specific signal handler needed
2b413144 1212
9de5e440 1213#endif
67b915a5
FB		 1214
1215#endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing