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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
7d13299d | 5 | * |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d | 19 | */ |
e4533c7a | 20 | #include "config.h" |
93ac68bc | 21 | #include "exec.h" |
956034d7 | 22 | #include "disas.h" |
7d13299d | 23 | |
fbf9eeb3 FB |
24 | #if !defined(CONFIG_SOFTMMU) |
25 | #undef EAX | |
26 | #undef ECX | |
27 | #undef EDX | |
28 | #undef EBX | |
29 | #undef ESP | |
30 | #undef EBP | |
31 | #undef ESI | |
32 | #undef EDI | |
33 | #undef EIP | |
34 | #include <signal.h> | |
35 | #include <sys/ucontext.h> | |
36 | #endif | |
37 | ||
36bdbe54 FB |
38 | int tb_invalidated_flag; |
39 | ||
dc99065b | 40 | //#define DEBUG_EXEC |
9de5e440 | 41 | //#define DEBUG_SIGNAL |
7d13299d | 42 | |
e6e5906b | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) |
e4533c7a FB |
44 | /* XXX: unify with i386 target */ |
45 | void cpu_loop_exit(void) | |
46 | { | |
47 | longjmp(env->jmp_env, 1); | |
48 | } | |
49 | #endif | |
e6e5906b | 50 | #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K)) |
3475187d FB |
51 | #define reg_T2 |
52 | #endif | |
e4533c7a | 53 | |
fbf9eeb3 FB |
54 | /* exit the current TB from a signal handler. The host registers are |
55 | restored in a state compatible with the CPU emulator | |
56 | */ | |
57 | void cpu_resume_from_signal(CPUState *env1, void *puc) | |
58 | { | |
59 | #if !defined(CONFIG_SOFTMMU) | |
60 | struct ucontext *uc = puc; | |
61 | #endif | |
62 | ||
63 | env = env1; | |
64 | ||
65 | /* XXX: restore cpu registers saved in host registers */ | |
66 | ||
67 | #if !defined(CONFIG_SOFTMMU) | |
68 | if (puc) { | |
69 | /* XXX: use siglongjmp ? */ | |
70 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
71 | } | |
72 | #endif | |
73 | longjmp(env->jmp_env, 1); | |
74 | } | |
75 | ||
8a40a180 FB |
76 | |
77 | static TranslationBlock *tb_find_slow(target_ulong pc, | |
78 | target_ulong cs_base, | |
79 | unsigned int flags) | |
80 | { | |
81 | TranslationBlock *tb, **ptb1; | |
82 | int code_gen_size; | |
83 | unsigned int h; | |
84 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; | |
85 | uint8_t *tc_ptr; | |
86 | ||
87 | spin_lock(&tb_lock); | |
88 | ||
89 | tb_invalidated_flag = 0; | |
90 | ||
91 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ | |
92 | ||
93 | /* find translated block using physical mappings */ | |
94 | phys_pc = get_phys_addr_code(env, pc); | |
95 | phys_page1 = phys_pc & TARGET_PAGE_MASK; | |
96 | phys_page2 = -1; | |
97 | h = tb_phys_hash_func(phys_pc); | |
98 | ptb1 = &tb_phys_hash[h]; | |
99 | for(;;) { | |
100 | tb = *ptb1; | |
101 | if (!tb) | |
102 | goto not_found; | |
103 | if (tb->pc == pc && | |
104 | tb->page_addr[0] == phys_page1 && | |
105 | tb->cs_base == cs_base && | |
106 | tb->flags == flags) { | |
107 | /* check next page if needed */ | |
108 | if (tb->page_addr[1] != -1) { | |
109 | virt_page2 = (pc & TARGET_PAGE_MASK) + | |
110 | TARGET_PAGE_SIZE; | |
111 | phys_page2 = get_phys_addr_code(env, virt_page2); | |
112 | if (tb->page_addr[1] == phys_page2) | |
113 | goto found; | |
114 | } else { | |
115 | goto found; | |
116 | } | |
117 | } | |
118 | ptb1 = &tb->phys_hash_next; | |
119 | } | |
120 | not_found: | |
121 | /* if no translated code available, then translate it now */ | |
122 | tb = tb_alloc(pc); | |
123 | if (!tb) { | |
124 | /* flush must be done */ | |
125 | tb_flush(env); | |
126 | /* cannot fail at this point */ | |
127 | tb = tb_alloc(pc); | |
128 | /* don't forget to invalidate previous TB info */ | |
15388002 | 129 | tb_invalidated_flag = 1; |
8a40a180 FB |
130 | } |
131 | tc_ptr = code_gen_ptr; | |
132 | tb->tc_ptr = tc_ptr; | |
133 | tb->cs_base = cs_base; | |
134 | tb->flags = flags; | |
135 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); | |
136 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); | |
137 | ||
138 | /* check next page if needed */ | |
139 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
140 | phys_page2 = -1; | |
141 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
142 | phys_page2 = get_phys_addr_code(env, virt_page2); | |
143 | } | |
144 | tb_link_phys(tb, phys_pc, phys_page2); | |
145 | ||
146 | found: | |
8a40a180 FB |
147 | /* we add the TB in the virtual pc hash table */ |
148 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; | |
149 | spin_unlock(&tb_lock); | |
150 | return tb; | |
151 | } | |
152 | ||
153 | static inline TranslationBlock *tb_find_fast(void) | |
154 | { | |
155 | TranslationBlock *tb; | |
156 | target_ulong cs_base, pc; | |
157 | unsigned int flags; | |
158 | ||
159 | /* we record a subset of the CPU state. It will | |
160 | always be the same before a given translated block | |
161 | is executed. */ | |
162 | #if defined(TARGET_I386) | |
163 | flags = env->hflags; | |
164 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); | |
165 | cs_base = env->segs[R_CS].base; | |
166 | pc = cs_base + env->eip; | |
167 | #elif defined(TARGET_ARM) | |
168 | flags = env->thumb | (env->vfp.vec_len << 1) | |
b5ff1b31 FB |
169 | | (env->vfp.vec_stride << 4); |
170 | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) | |
171 | flags |= (1 << 6); | |
40f137e1 PB |
172 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
173 | flags |= (1 << 7); | |
8a40a180 FB |
174 | cs_base = 0; |
175 | pc = env->regs[15]; | |
176 | #elif defined(TARGET_SPARC) | |
177 | #ifdef TARGET_SPARC64 | |
a80dde08 FB |
178 | // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled |
179 | flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) | |
180 | | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); | |
8a40a180 | 181 | #else |
a80dde08 FB |
182 | // FPU enable . MMU enabled . MMU no-fault . Supervisor |
183 | flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) | |
184 | | env->psrs; | |
8a40a180 FB |
185 | #endif |
186 | cs_base = env->npc; | |
187 | pc = env->pc; | |
188 | #elif defined(TARGET_PPC) | |
189 | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | | |
190 | (msr_se << MSR_SE) | (msr_le << MSR_LE); | |
191 | cs_base = 0; | |
192 | pc = env->nip; | |
193 | #elif defined(TARGET_MIPS) | |
56b19403 | 194 | flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
cc9442b9 | 195 | cs_base = 0; |
8a40a180 | 196 | pc = env->PC; |
e6e5906b PB |
197 | #elif defined(TARGET_M68K) |
198 | flags = env->fpcr & M68K_FPCR_PREC; | |
199 | cs_base = 0; | |
200 | pc = env->pc; | |
fdf9b3e8 FB |
201 | #elif defined(TARGET_SH4) |
202 | flags = env->sr & (SR_MD | SR_RB); | |
203 | cs_base = 0; /* XXXXX */ | |
204 | pc = env->pc; | |
8a40a180 FB |
205 | #else |
206 | #error unsupported CPU | |
207 | #endif | |
208 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; | |
209 | if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base || | |
210 | tb->flags != flags, 0)) { | |
211 | tb = tb_find_slow(pc, cs_base, flags); | |
15388002 FB |
212 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
213 | doing it in tb_find_slow */ | |
214 | if (tb_invalidated_flag) { | |
215 | /* as some TB could have been invalidated because | |
216 | of memory exceptions while generating the code, we | |
217 | must recompute the hash index here */ | |
218 | T0 = 0; | |
219 | } | |
8a40a180 FB |
220 | } |
221 | return tb; | |
222 | } | |
223 | ||
224 | ||
7d13299d FB |
225 | /* main execution loop */ |
226 | ||
e4533c7a | 227 | int cpu_exec(CPUState *env1) |
7d13299d | 228 | { |
1057eaa7 PB |
229 | #define DECLARE_HOST_REGS 1 |
230 | #include "hostregs_helper.h" | |
231 | #if defined(TARGET_SPARC) | |
3475187d FB |
232 | #if defined(reg_REGWPTR) |
233 | uint32_t *saved_regwptr; | |
234 | #endif | |
235 | #endif | |
fdbb4691 | 236 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
b49d07ba TS |
237 | int saved_i7; |
238 | target_ulong tmp_T0; | |
04369ff2 | 239 | #endif |
8a40a180 | 240 | int ret, interrupt_request; |
7d13299d | 241 | void (*gen_func)(void); |
8a40a180 | 242 | TranslationBlock *tb; |
c27004ec | 243 | uint8_t *tc_ptr; |
8c6939c0 | 244 | |
5a1e3cfc FB |
245 | #if defined(TARGET_I386) |
246 | /* handle exit of HALTED state */ | |
247 | if (env1->hflags & HF_HALTED_MASK) { | |
248 | /* disable halt condition */ | |
249 | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && | |
250 | (env1->eflags & IF_MASK)) { | |
251 | env1->hflags &= ~HF_HALTED_MASK; | |
252 | } else { | |
253 | return EXCP_HALTED; | |
e80e1cc4 FB |
254 | } |
255 | } | |
256 | #elif defined(TARGET_PPC) | |
50443c98 | 257 | if (env1->halted) { |
e80e1cc4 FB |
258 | if (env1->msr[MSR_EE] && |
259 | (env1->interrupt_request & | |
260 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) { | |
50443c98 | 261 | env1->halted = 0; |
e80e1cc4 FB |
262 | } else { |
263 | return EXCP_HALTED; | |
5a1e3cfc FB |
264 | } |
265 | } | |
ba3c64fb FB |
266 | #elif defined(TARGET_SPARC) |
267 | if (env1->halted) { | |
268 | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && | |
269 | (env1->psret != 0)) { | |
270 | env1->halted = 0; | |
271 | } else { | |
272 | return EXCP_HALTED; | |
273 | } | |
274 | } | |
9332f9da FB |
275 | #elif defined(TARGET_ARM) |
276 | if (env1->halted) { | |
277 | /* An interrupt wakes the CPU even if the I and F CPSR bits are | |
278 | set. */ | |
279 | if (env1->interrupt_request | |
280 | & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) { | |
281 | env1->halted = 0; | |
282 | } else { | |
283 | return EXCP_HALTED; | |
284 | } | |
285 | } | |
6810e154 FB |
286 | #elif defined(TARGET_MIPS) |
287 | if (env1->halted) { | |
288 | if (env1->interrupt_request & | |
289 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { | |
290 | env1->halted = 0; | |
291 | } else { | |
292 | return EXCP_HALTED; | |
293 | } | |
294 | } | |
5a1e3cfc FB |
295 | #endif |
296 | ||
6a00d601 FB |
297 | cpu_single_env = env1; |
298 | ||
7d13299d | 299 | /* first we save global registers */ |
1057eaa7 PB |
300 | #define SAVE_HOST_REGS 1 |
301 | #include "hostregs_helper.h" | |
c27004ec | 302 | env = env1; |
fdbb4691 | 303 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
e4533c7a FB |
304 | /* we also save i7 because longjmp may not restore it */ |
305 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); | |
306 | #endif | |
307 | ||
308 | #if defined(TARGET_I386) | |
0d1a29f9 | 309 | env_to_regs(); |
9de5e440 | 310 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
311 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
312 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 313 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 314 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 315 | #elif defined(TARGET_ARM) |
93ac68bc | 316 | #elif defined(TARGET_SPARC) |
3475187d FB |
317 | #if defined(reg_REGWPTR) |
318 | saved_regwptr = REGWPTR; | |
319 | #endif | |
67867308 | 320 | #elif defined(TARGET_PPC) |
e6e5906b PB |
321 | #elif defined(TARGET_M68K) |
322 | env->cc_op = CC_OP_FLAGS; | |
323 | env->cc_dest = env->sr & 0xf; | |
324 | env->cc_x = (env->sr >> 4) & 1; | |
6af0bf9c | 325 | #elif defined(TARGET_MIPS) |
fdf9b3e8 FB |
326 | #elif defined(TARGET_SH4) |
327 | /* XXXXX */ | |
e4533c7a FB |
328 | #else |
329 | #error unsupported target CPU | |
330 | #endif | |
3fb2ded1 | 331 | env->exception_index = -1; |
9d27abd9 | 332 | |
7d13299d | 333 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
334 | for(;;) { |
335 | if (setjmp(env->jmp_env) == 0) { | |
ee8b7021 | 336 | env->current_tb = NULL; |
3fb2ded1 FB |
337 | /* if an exception is pending, we execute it here */ |
338 | if (env->exception_index >= 0) { | |
339 | if (env->exception_index >= EXCP_INTERRUPT) { | |
340 | /* exit request from the cpu execution loop */ | |
341 | ret = env->exception_index; | |
342 | break; | |
343 | } else if (env->user_mode_only) { | |
344 | /* if user mode only, we simulate a fake exception | |
9f083493 | 345 | which will be handled outside the cpu execution |
3fb2ded1 | 346 | loop */ |
83479e77 | 347 | #if defined(TARGET_I386) |
3fb2ded1 FB |
348 | do_interrupt_user(env->exception_index, |
349 | env->exception_is_int, | |
350 | env->error_code, | |
351 | env->exception_next_eip); | |
83479e77 | 352 | #endif |
3fb2ded1 FB |
353 | ret = env->exception_index; |
354 | break; | |
355 | } else { | |
83479e77 | 356 | #if defined(TARGET_I386) |
3fb2ded1 FB |
357 | /* simulate a real cpu exception. On i386, it can |
358 | trigger new exceptions, but we do not handle | |
359 | double or triple faults yet. */ | |
360 | do_interrupt(env->exception_index, | |
361 | env->exception_is_int, | |
362 | env->error_code, | |
d05e66d2 | 363 | env->exception_next_eip, 0); |
ce09776b FB |
364 | #elif defined(TARGET_PPC) |
365 | do_interrupt(env); | |
6af0bf9c FB |
366 | #elif defined(TARGET_MIPS) |
367 | do_interrupt(env); | |
e95c8d51 | 368 | #elif defined(TARGET_SPARC) |
1a0c3292 | 369 | do_interrupt(env->exception_index); |
b5ff1b31 FB |
370 | #elif defined(TARGET_ARM) |
371 | do_interrupt(env); | |
fdf9b3e8 FB |
372 | #elif defined(TARGET_SH4) |
373 | do_interrupt(env); | |
83479e77 | 374 | #endif |
3fb2ded1 FB |
375 | } |
376 | env->exception_index = -1; | |
9df217a3 FB |
377 | } |
378 | #ifdef USE_KQEMU | |
379 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { | |
380 | int ret; | |
381 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
382 | ret = kqemu_cpu_exec(env); | |
383 | /* put eflags in CPU temporary format */ | |
384 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
385 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
386 | CC_OP = CC_OP_EFLAGS; | |
387 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
388 | if (ret == 1) { | |
389 | /* exception */ | |
390 | longjmp(env->jmp_env, 1); | |
391 | } else if (ret == 2) { | |
392 | /* softmmu execution needed */ | |
393 | } else { | |
394 | if (env->interrupt_request != 0) { | |
395 | /* hardware interrupt will be executed just after */ | |
396 | } else { | |
397 | /* otherwise, we restart */ | |
398 | longjmp(env->jmp_env, 1); | |
399 | } | |
400 | } | |
3fb2ded1 | 401 | } |
9df217a3 FB |
402 | #endif |
403 | ||
3fb2ded1 FB |
404 | T0 = 0; /* force lookup of first TB */ |
405 | for(;;) { | |
fdbb4691 | 406 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
3fb2ded1 FB |
407 | /* g1 can be modified by some libc? functions */ |
408 | tmp_T0 = T0; | |
8c6939c0 | 409 | #endif |
68a79315 | 410 | interrupt_request = env->interrupt_request; |
2e255c6b | 411 | if (__builtin_expect(interrupt_request, 0)) { |
6658ffb8 PB |
412 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
413 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; | |
414 | env->exception_index = EXCP_DEBUG; | |
415 | cpu_loop_exit(); | |
416 | } | |
68a79315 | 417 | #if defined(TARGET_I386) |
3b21e03e FB |
418 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
419 | !(env->hflags & HF_SMM_MASK)) { | |
420 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; | |
421 | do_smm_enter(); | |
422 | #if defined(__sparc__) && !defined(HOST_SOLARIS) | |
423 | tmp_T0 = 0; | |
424 | #else | |
425 | T0 = 0; | |
426 | #endif | |
427 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
3f337316 FB |
428 | (env->eflags & IF_MASK) && |
429 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
68a79315 | 430 | int intno; |
fbf9eeb3 | 431 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
a541f297 | 432 | intno = cpu_get_pic_interrupt(env); |
f193c797 | 433 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
68a79315 FB |
434 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
435 | } | |
d05e66d2 | 436 | do_interrupt(intno, 0, 0, 0, 1); |
907a5b26 FB |
437 | /* ensure that no TB jump will be modified as |
438 | the program flow was changed */ | |
fdbb4691 | 439 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
907a5b26 FB |
440 | tmp_T0 = 0; |
441 | #else | |
442 | T0 = 0; | |
443 | #endif | |
68a79315 | 444 | } |
ce09776b | 445 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
446 | #if 0 |
447 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
448 | cpu_ppc_reset(env); | |
449 | } | |
450 | #endif | |
451 | if (msr_ee != 0) { | |
8a40a180 | 452 | if ((interrupt_request & CPU_INTERRUPT_HARD)) { |
9fddaa0c FB |
453 | /* Raise it */ |
454 | env->exception_index = EXCP_EXTERNAL; | |
455 | env->error_code = 0; | |
ce09776b | 456 | do_interrupt(env); |
8a40a180 | 457 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
fdbb4691 | 458 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
8a40a180 FB |
459 | tmp_T0 = 0; |
460 | #else | |
461 | T0 = 0; | |
462 | #endif | |
463 | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { | |
464 | /* Raise it */ | |
465 | env->exception_index = EXCP_DECR; | |
466 | env->error_code = 0; | |
467 | do_interrupt(env); | |
9fddaa0c | 468 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
fdbb4691 | 469 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
8a40a180 FB |
470 | tmp_T0 = 0; |
471 | #else | |
472 | T0 = 0; | |
473 | #endif | |
474 | } | |
ce09776b | 475 | } |
6af0bf9c FB |
476 | #elif defined(TARGET_MIPS) |
477 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
478 | (env->CP0_Status & (1 << CP0St_IE)) && | |
7ebab699 | 479 | (env->CP0_Status & env->CP0_Cause & 0x0000FF00) && |
6af0bf9c FB |
480 | !(env->hflags & MIPS_HFLAG_EXL) && |
481 | !(env->hflags & MIPS_HFLAG_ERL) && | |
482 | !(env->hflags & MIPS_HFLAG_DM)) { | |
483 | /* Raise it */ | |
484 | env->exception_index = EXCP_EXT_INTERRUPT; | |
485 | env->error_code = 0; | |
486 | do_interrupt(env); | |
fdbb4691 | 487 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
8a40a180 FB |
488 | tmp_T0 = 0; |
489 | #else | |
490 | T0 = 0; | |
491 | #endif | |
6af0bf9c | 492 | } |
e95c8d51 | 493 | #elif defined(TARGET_SPARC) |
66321a11 FB |
494 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
495 | (env->psret != 0)) { | |
496 | int pil = env->interrupt_index & 15; | |
497 | int type = env->interrupt_index & 0xf0; | |
498 | ||
499 | if (((type == TT_EXTINT) && | |
500 | (pil == 15 || pil > env->psrpil)) || | |
501 | type != TT_EXTINT) { | |
502 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
503 | do_interrupt(env->interrupt_index); | |
504 | env->interrupt_index = 0; | |
fdbb4691 | 505 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
8a40a180 FB |
506 | tmp_T0 = 0; |
507 | #else | |
508 | T0 = 0; | |
509 | #endif | |
66321a11 | 510 | } |
e95c8d51 FB |
511 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
512 | //do_interrupt(0, 0, 0, 0, 0); | |
513 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
ba3c64fb | 514 | } else if (interrupt_request & CPU_INTERRUPT_HALT) { |
df52b000 FB |
515 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
516 | env->halted = 1; | |
517 | env->exception_index = EXCP_HLT; | |
518 | cpu_loop_exit(); | |
ba3c64fb | 519 | } |
b5ff1b31 FB |
520 | #elif defined(TARGET_ARM) |
521 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
522 | && !(env->uncached_cpsr & CPSR_F)) { | |
523 | env->exception_index = EXCP_FIQ; | |
524 | do_interrupt(env); | |
525 | } | |
526 | if (interrupt_request & CPU_INTERRUPT_HARD | |
527 | && !(env->uncached_cpsr & CPSR_I)) { | |
528 | env->exception_index = EXCP_IRQ; | |
529 | do_interrupt(env); | |
530 | } | |
fdf9b3e8 FB |
531 | #elif defined(TARGET_SH4) |
532 | /* XXXXX */ | |
68a79315 | 533 | #endif |
9d05095e FB |
534 | /* Don't use the cached interupt_request value, |
535 | do_interrupt may have updated the EXITTB flag. */ | |
b5ff1b31 | 536 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bf3e8bf1 FB |
537 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
538 | /* ensure that no TB jump will be modified as | |
539 | the program flow was changed */ | |
fdbb4691 | 540 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
bf3e8bf1 FB |
541 | tmp_T0 = 0; |
542 | #else | |
543 | T0 = 0; | |
544 | #endif | |
545 | } | |
68a79315 FB |
546 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
547 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; | |
548 | env->exception_index = EXCP_INTERRUPT; | |
549 | cpu_loop_exit(); | |
550 | } | |
3fb2ded1 | 551 | } |
7d13299d | 552 | #ifdef DEBUG_EXEC |
b5ff1b31 | 553 | if ((loglevel & CPU_LOG_TB_CPU)) { |
e4533c7a | 554 | #if defined(TARGET_I386) |
3fb2ded1 | 555 | /* restore flags in standard format */ |
fc9f715d | 556 | #ifdef reg_EAX |
3fb2ded1 | 557 | env->regs[R_EAX] = EAX; |
fc9f715d FB |
558 | #endif |
559 | #ifdef reg_EBX | |
3fb2ded1 | 560 | env->regs[R_EBX] = EBX; |
fc9f715d FB |
561 | #endif |
562 | #ifdef reg_ECX | |
3fb2ded1 | 563 | env->regs[R_ECX] = ECX; |
fc9f715d FB |
564 | #endif |
565 | #ifdef reg_EDX | |
3fb2ded1 | 566 | env->regs[R_EDX] = EDX; |
fc9f715d FB |
567 | #endif |
568 | #ifdef reg_ESI | |
3fb2ded1 | 569 | env->regs[R_ESI] = ESI; |
fc9f715d FB |
570 | #endif |
571 | #ifdef reg_EDI | |
3fb2ded1 | 572 | env->regs[R_EDI] = EDI; |
fc9f715d FB |
573 | #endif |
574 | #ifdef reg_EBP | |
3fb2ded1 | 575 | env->regs[R_EBP] = EBP; |
fc9f715d FB |
576 | #endif |
577 | #ifdef reg_ESP | |
3fb2ded1 | 578 | env->regs[R_ESP] = ESP; |
fc9f715d | 579 | #endif |
3fb2ded1 | 580 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
7fe48483 | 581 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
3fb2ded1 | 582 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 583 | #elif defined(TARGET_ARM) |
7fe48483 | 584 | cpu_dump_state(env, logfile, fprintf, 0); |
93ac68bc | 585 | #elif defined(TARGET_SPARC) |
3475187d FB |
586 | REGWPTR = env->regbase + (env->cwp * 16); |
587 | env->regwptr = REGWPTR; | |
588 | cpu_dump_state(env, logfile, fprintf, 0); | |
67867308 | 589 | #elif defined(TARGET_PPC) |
7fe48483 | 590 | cpu_dump_state(env, logfile, fprintf, 0); |
e6e5906b PB |
591 | #elif defined(TARGET_M68K) |
592 | cpu_m68k_flush_flags(env, env->cc_op); | |
593 | env->cc_op = CC_OP_FLAGS; | |
594 | env->sr = (env->sr & 0xffe0) | |
595 | | env->cc_dest | (env->cc_x << 4); | |
596 | cpu_dump_state(env, logfile, fprintf, 0); | |
6af0bf9c FB |
597 | #elif defined(TARGET_MIPS) |
598 | cpu_dump_state(env, logfile, fprintf, 0); | |
fdf9b3e8 FB |
599 | #elif defined(TARGET_SH4) |
600 | cpu_dump_state(env, logfile, fprintf, 0); | |
e4533c7a FB |
601 | #else |
602 | #error unsupported target CPU | |
603 | #endif | |
3fb2ded1 | 604 | } |
7d13299d | 605 | #endif |
8a40a180 | 606 | tb = tb_find_fast(); |
9d27abd9 | 607 | #ifdef DEBUG_EXEC |
c1135f61 | 608 | if ((loglevel & CPU_LOG_EXEC)) { |
c27004ec FB |
609 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
610 | (long)tb->tc_ptr, tb->pc, | |
611 | lookup_symbol(tb->pc)); | |
3fb2ded1 | 612 | } |
9d27abd9 | 613 | #endif |
fdbb4691 | 614 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
3fb2ded1 | 615 | T0 = tmp_T0; |
8c6939c0 | 616 | #endif |
8a40a180 FB |
617 | /* see if we can patch the calling TB. When the TB |
618 | spans two pages, we cannot safely do a direct | |
619 | jump. */ | |
c27004ec | 620 | { |
8a40a180 | 621 | if (T0 != 0 && |
f32fc648 FB |
622 | #if USE_KQEMU |
623 | (env->kqemu_enabled != 2) && | |
624 | #endif | |
8a40a180 | 625 | tb->page_addr[1] == -1 |
bf3e8bf1 FB |
626 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
627 | && (tb->cflags & CF_CODE_COPY) == | |
628 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) | |
629 | #endif | |
630 | ) { | |
3fb2ded1 | 631 | spin_lock(&tb_lock); |
c27004ec | 632 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
97eb5b14 FB |
633 | #if defined(USE_CODE_COPY) |
634 | /* propagates the FP use info */ | |
635 | ((TranslationBlock *)(T0 & ~3))->cflags |= | |
636 | (tb->cflags & CF_FP_USED); | |
637 | #endif | |
3fb2ded1 FB |
638 | spin_unlock(&tb_lock); |
639 | } | |
c27004ec | 640 | } |
3fb2ded1 | 641 | tc_ptr = tb->tc_ptr; |
83479e77 | 642 | env->current_tb = tb; |
3fb2ded1 FB |
643 | /* execute the generated code */ |
644 | gen_func = (void *)tc_ptr; | |
8c6939c0 | 645 | #if defined(__sparc__) |
3fb2ded1 FB |
646 | __asm__ __volatile__("call %0\n\t" |
647 | "mov %%o7,%%i0" | |
648 | : /* no outputs */ | |
649 | : "r" (gen_func) | |
fdbb4691 FB |
650 | : "i0", "i1", "i2", "i3", "i4", "i5", |
651 | "l0", "l1", "l2", "l3", "l4", "l5", | |
652 | "l6", "l7"); | |
8c6939c0 | 653 | #elif defined(__arm__) |
3fb2ded1 FB |
654 | asm volatile ("mov pc, %0\n\t" |
655 | ".global exec_loop\n\t" | |
656 | "exec_loop:\n\t" | |
657 | : /* no outputs */ | |
658 | : "r" (gen_func) | |
659 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); | |
bf3e8bf1 FB |
660 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
661 | { | |
662 | if (!(tb->cflags & CF_CODE_COPY)) { | |
97eb5b14 FB |
663 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
664 | save_native_fp_state(env); | |
665 | } | |
bf3e8bf1 FB |
666 | gen_func(); |
667 | } else { | |
97eb5b14 FB |
668 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
669 | restore_native_fp_state(env); | |
670 | } | |
bf3e8bf1 FB |
671 | /* we work with native eflags */ |
672 | CC_SRC = cc_table[CC_OP].compute_all(); | |
673 | CC_OP = CC_OP_EFLAGS; | |
674 | asm(".globl exec_loop\n" | |
675 | "\n" | |
676 | "debug1:\n" | |
677 | " pushl %%ebp\n" | |
678 | " fs movl %10, %9\n" | |
679 | " fs movl %11, %%eax\n" | |
680 | " andl $0x400, %%eax\n" | |
681 | " fs orl %8, %%eax\n" | |
682 | " pushl %%eax\n" | |
683 | " popf\n" | |
684 | " fs movl %%esp, %12\n" | |
685 | " fs movl %0, %%eax\n" | |
686 | " fs movl %1, %%ecx\n" | |
687 | " fs movl %2, %%edx\n" | |
688 | " fs movl %3, %%ebx\n" | |
689 | " fs movl %4, %%esp\n" | |
690 | " fs movl %5, %%ebp\n" | |
691 | " fs movl %6, %%esi\n" | |
692 | " fs movl %7, %%edi\n" | |
693 | " fs jmp *%9\n" | |
694 | "exec_loop:\n" | |
695 | " fs movl %%esp, %4\n" | |
696 | " fs movl %12, %%esp\n" | |
697 | " fs movl %%eax, %0\n" | |
698 | " fs movl %%ecx, %1\n" | |
699 | " fs movl %%edx, %2\n" | |
700 | " fs movl %%ebx, %3\n" | |
701 | " fs movl %%ebp, %5\n" | |
702 | " fs movl %%esi, %6\n" | |
703 | " fs movl %%edi, %7\n" | |
704 | " pushf\n" | |
705 | " popl %%eax\n" | |
706 | " movl %%eax, %%ecx\n" | |
707 | " andl $0x400, %%ecx\n" | |
708 | " shrl $9, %%ecx\n" | |
709 | " andl $0x8d5, %%eax\n" | |
710 | " fs movl %%eax, %8\n" | |
711 | " movl $1, %%eax\n" | |
712 | " subl %%ecx, %%eax\n" | |
713 | " fs movl %%eax, %11\n" | |
714 | " fs movl %9, %%ebx\n" /* get T0 value */ | |
715 | " popl %%ebp\n" | |
716 | : | |
717 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), | |
718 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), | |
719 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), | |
720 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), | |
721 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), | |
722 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), | |
723 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), | |
724 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), | |
725 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), | |
726 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), | |
727 | "a" (gen_func), | |
728 | "m" (*(uint8_t *)offsetof(CPUState, df)), | |
729 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) | |
730 | : "%ecx", "%edx" | |
731 | ); | |
732 | } | |
733 | } | |
b8076a74 FB |
734 | #elif defined(__ia64) |
735 | struct fptr { | |
736 | void *ip; | |
737 | void *gp; | |
738 | } fp; | |
739 | ||
740 | fp.ip = tc_ptr; | |
741 | fp.gp = code_gen_buffer + 2 * (1 << 20); | |
742 | (*(void (*)(void)) &fp)(); | |
ae228531 | 743 | #else |
3fb2ded1 | 744 | gen_func(); |
ae228531 | 745 | #endif |
83479e77 | 746 | env->current_tb = NULL; |
4cbf74b6 FB |
747 | /* reset soft MMU for next block (it can currently |
748 | only be set by a memory fault) */ | |
749 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) | |
3f337316 FB |
750 | if (env->hflags & HF_SOFTMMU_MASK) { |
751 | env->hflags &= ~HF_SOFTMMU_MASK; | |
4cbf74b6 FB |
752 | /* do not allow linking to another block */ |
753 | T0 = 0; | |
754 | } | |
f32fc648 FB |
755 | #endif |
756 | #if defined(USE_KQEMU) | |
757 | #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) | |
758 | if (kqemu_is_ok(env) && | |
759 | (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { | |
760 | cpu_loop_exit(); | |
761 | } | |
4cbf74b6 | 762 | #endif |
3fb2ded1 FB |
763 | } |
764 | } else { | |
0d1a29f9 | 765 | env_to_regs(); |
7d13299d | 766 | } |
3fb2ded1 FB |
767 | } /* for(;;) */ |
768 | ||
7d13299d | 769 | |
e4533c7a | 770 | #if defined(TARGET_I386) |
97eb5b14 FB |
771 | #if defined(USE_CODE_COPY) |
772 | if (env->native_fp_regs) { | |
773 | save_native_fp_state(env); | |
774 | } | |
775 | #endif | |
9de5e440 | 776 | /* restore flags in standard format */ |
fc2b4c48 | 777 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
e4533c7a | 778 | #elif defined(TARGET_ARM) |
b7bcbe95 | 779 | /* XXX: Save/restore host fpu exception state?. */ |
93ac68bc | 780 | #elif defined(TARGET_SPARC) |
3475187d FB |
781 | #if defined(reg_REGWPTR) |
782 | REGWPTR = saved_regwptr; | |
783 | #endif | |
67867308 | 784 | #elif defined(TARGET_PPC) |
e6e5906b PB |
785 | #elif defined(TARGET_M68K) |
786 | cpu_m68k_flush_flags(env, env->cc_op); | |
787 | env->cc_op = CC_OP_FLAGS; | |
788 | env->sr = (env->sr & 0xffe0) | |
789 | | env->cc_dest | (env->cc_x << 4); | |
6af0bf9c | 790 | #elif defined(TARGET_MIPS) |
fdf9b3e8 FB |
791 | #elif defined(TARGET_SH4) |
792 | /* XXXXX */ | |
e4533c7a FB |
793 | #else |
794 | #error unsupported target CPU | |
795 | #endif | |
1057eaa7 PB |
796 | |
797 | /* restore global registers */ | |
fdbb4691 | 798 | #if defined(__sparc__) && !defined(HOST_SOLARIS) |
8c6939c0 | 799 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
04369ff2 | 800 | #endif |
1057eaa7 PB |
801 | #include "hostregs_helper.h" |
802 | ||
6a00d601 FB |
803 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
804 | cpu_single_env = NULL; | |
7d13299d FB |
805 | return ret; |
806 | } | |
6dbad63e | 807 | |
fbf9eeb3 FB |
808 | /* must only be called from the generated code as an exception can be |
809 | generated */ | |
810 | void tb_invalidate_page_range(target_ulong start, target_ulong end) | |
811 | { | |
dc5d0b3d FB |
812 | /* XXX: cannot enable it yet because it yields to MMU exception |
813 | where NIP != read address on PowerPC */ | |
814 | #if 0 | |
fbf9eeb3 FB |
815 | target_ulong phys_addr; |
816 | phys_addr = get_phys_addr_code(env, start); | |
817 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); | |
dc5d0b3d | 818 | #endif |
fbf9eeb3 FB |
819 | } |
820 | ||
1a18c71b | 821 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 822 | |
6dbad63e FB |
823 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
824 | { | |
825 | CPUX86State *saved_env; | |
826 | ||
827 | saved_env = env; | |
828 | env = s; | |
a412ac57 | 829 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 830 | selector &= 0xffff; |
2e255c6b | 831 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
c27004ec | 832 | (selector << 4), 0xffff, 0); |
a513fe19 | 833 | } else { |
b453b70b | 834 | load_seg(seg_reg, selector); |
a513fe19 | 835 | } |
6dbad63e FB |
836 | env = saved_env; |
837 | } | |
9de5e440 | 838 | |
d0a1ffc9 FB |
839 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
840 | { | |
841 | CPUX86State *saved_env; | |
842 | ||
843 | saved_env = env; | |
844 | env = s; | |
845 | ||
c27004ec | 846 | helper_fsave((target_ulong)ptr, data32); |
d0a1ffc9 FB |
847 | |
848 | env = saved_env; | |
849 | } | |
850 | ||
851 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) | |
852 | { | |
853 | CPUX86State *saved_env; | |
854 | ||
855 | saved_env = env; | |
856 | env = s; | |
857 | ||
c27004ec | 858 | helper_frstor((target_ulong)ptr, data32); |
d0a1ffc9 FB |
859 | |
860 | env = saved_env; | |
861 | } | |
862 | ||
e4533c7a FB |
863 | #endif /* TARGET_I386 */ |
864 | ||
67b915a5 FB |
865 | #if !defined(CONFIG_SOFTMMU) |
866 | ||
3fb2ded1 FB |
867 | #if defined(TARGET_I386) |
868 | ||
b56dad1c | 869 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
870 | the effective address of the memory exception. 'is_write' is 1 if a |
871 | write caused the exception and otherwise 0'. 'old_set' is the | |
872 | signal set which should be restored */ | |
2b413144 | 873 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
874 | int is_write, sigset_t *old_set, |
875 | void *puc) | |
9de5e440 | 876 | { |
a513fe19 FB |
877 | TranslationBlock *tb; |
878 | int ret; | |
68a79315 | 879 | |
83479e77 FB |
880 | if (cpu_single_env) |
881 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 882 | #if defined(DEBUG_SIGNAL) |
bf3e8bf1 FB |
883 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
884 | pc, address, is_write, *(unsigned long *)old_set); | |
9de5e440 | 885 | #endif |
25eb4484 | 886 | /* XXX: locking issue */ |
53a5960a | 887 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
fd6ce8f6 FB |
888 | return 1; |
889 | } | |
fbf9eeb3 | 890 | |
3fb2ded1 | 891 | /* see if it is an MMU fault */ |
93a40ea9 FB |
892 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
893 | ((env->hflags & HF_CPL_MASK) == 3), 0); | |
3fb2ded1 FB |
894 | if (ret < 0) |
895 | return 0; /* not an MMU fault */ | |
896 | if (ret == 0) | |
897 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
898 | /* now we have a real cpu fault */ | |
a513fe19 FB |
899 | tb = tb_find_pc(pc); |
900 | if (tb) { | |
9de5e440 FB |
901 | /* the PC is inside the translated code. It means that we have |
902 | a virtual CPU fault */ | |
bf3e8bf1 | 903 | cpu_restore_state(tb, env, pc, puc); |
3fb2ded1 | 904 | } |
4cbf74b6 | 905 | if (ret == 1) { |
3fb2ded1 | 906 | #if 0 |
4cbf74b6 FB |
907 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
908 | env->eip, env->cr[2], env->error_code); | |
3fb2ded1 | 909 | #endif |
4cbf74b6 FB |
910 | /* we restore the process signal mask as the sigreturn should |
911 | do it (XXX: use sigsetjmp) */ | |
912 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
54ca9095 | 913 | raise_exception_err(env->exception_index, env->error_code); |
4cbf74b6 FB |
914 | } else { |
915 | /* activate soft MMU for this block */ | |
3f337316 | 916 | env->hflags |= HF_SOFTMMU_MASK; |
fbf9eeb3 | 917 | cpu_resume_from_signal(env, puc); |
4cbf74b6 | 918 | } |
3fb2ded1 FB |
919 | /* never comes here */ |
920 | return 1; | |
921 | } | |
922 | ||
e4533c7a | 923 | #elif defined(TARGET_ARM) |
3fb2ded1 | 924 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
925 | int is_write, sigset_t *old_set, |
926 | void *puc) | |
3fb2ded1 | 927 | { |
68016c62 FB |
928 | TranslationBlock *tb; |
929 | int ret; | |
930 | ||
931 | if (cpu_single_env) | |
932 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
933 | #if defined(DEBUG_SIGNAL) | |
934 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
935 | pc, address, is_write, *(unsigned long *)old_set); | |
936 | #endif | |
9f0777ed | 937 | /* XXX: locking issue */ |
53a5960a | 938 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
9f0777ed FB |
939 | return 1; |
940 | } | |
68016c62 FB |
941 | /* see if it is an MMU fault */ |
942 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); | |
943 | if (ret < 0) | |
944 | return 0; /* not an MMU fault */ | |
945 | if (ret == 0) | |
946 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
947 | /* now we have a real cpu fault */ | |
948 | tb = tb_find_pc(pc); | |
949 | if (tb) { | |
950 | /* the PC is inside the translated code. It means that we have | |
951 | a virtual CPU fault */ | |
952 | cpu_restore_state(tb, env, pc, puc); | |
953 | } | |
954 | /* we restore the process signal mask as the sigreturn should | |
955 | do it (XXX: use sigsetjmp) */ | |
956 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
957 | cpu_loop_exit(); | |
3fb2ded1 | 958 | } |
93ac68bc FB |
959 | #elif defined(TARGET_SPARC) |
960 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
961 | int is_write, sigset_t *old_set, |
962 | void *puc) | |
93ac68bc | 963 | { |
68016c62 FB |
964 | TranslationBlock *tb; |
965 | int ret; | |
966 | ||
967 | if (cpu_single_env) | |
968 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
969 | #if defined(DEBUG_SIGNAL) | |
970 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
971 | pc, address, is_write, *(unsigned long *)old_set); | |
972 | #endif | |
b453b70b | 973 | /* XXX: locking issue */ |
53a5960a | 974 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
b453b70b FB |
975 | return 1; |
976 | } | |
68016c62 FB |
977 | /* see if it is an MMU fault */ |
978 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); | |
979 | if (ret < 0) | |
980 | return 0; /* not an MMU fault */ | |
981 | if (ret == 0) | |
982 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
983 | /* now we have a real cpu fault */ | |
984 | tb = tb_find_pc(pc); | |
985 | if (tb) { | |
986 | /* the PC is inside the translated code. It means that we have | |
987 | a virtual CPU fault */ | |
988 | cpu_restore_state(tb, env, pc, puc); | |
989 | } | |
990 | /* we restore the process signal mask as the sigreturn should | |
991 | do it (XXX: use sigsetjmp) */ | |
992 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
993 | cpu_loop_exit(); | |
93ac68bc | 994 | } |
67867308 FB |
995 | #elif defined (TARGET_PPC) |
996 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
997 | int is_write, sigset_t *old_set, |
998 | void *puc) | |
67867308 FB |
999 | { |
1000 | TranslationBlock *tb; | |
ce09776b | 1001 | int ret; |
67867308 | 1002 | |
67867308 FB |
1003 | if (cpu_single_env) |
1004 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
67867308 FB |
1005 | #if defined(DEBUG_SIGNAL) |
1006 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
1007 | pc, address, is_write, *(unsigned long *)old_set); | |
1008 | #endif | |
1009 | /* XXX: locking issue */ | |
53a5960a | 1010 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
67867308 FB |
1011 | return 1; |
1012 | } | |
1013 | ||
ce09776b | 1014 | /* see if it is an MMU fault */ |
7f957d28 | 1015 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
ce09776b FB |
1016 | if (ret < 0) |
1017 | return 0; /* not an MMU fault */ | |
1018 | if (ret == 0) | |
1019 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
1020 | ||
67867308 FB |
1021 | /* now we have a real cpu fault */ |
1022 | tb = tb_find_pc(pc); | |
1023 | if (tb) { | |
1024 | /* the PC is inside the translated code. It means that we have | |
1025 | a virtual CPU fault */ | |
bf3e8bf1 | 1026 | cpu_restore_state(tb, env, pc, puc); |
67867308 | 1027 | } |
ce09776b | 1028 | if (ret == 1) { |
67867308 | 1029 | #if 0 |
ce09776b FB |
1030 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
1031 | env->nip, env->error_code, tb); | |
67867308 FB |
1032 | #endif |
1033 | /* we restore the process signal mask as the sigreturn should | |
1034 | do it (XXX: use sigsetjmp) */ | |
bf3e8bf1 | 1035 | sigprocmask(SIG_SETMASK, old_set, NULL); |
9fddaa0c | 1036 | do_raise_exception_err(env->exception_index, env->error_code); |
ce09776b FB |
1037 | } else { |
1038 | /* activate soft MMU for this block */ | |
fbf9eeb3 | 1039 | cpu_resume_from_signal(env, puc); |
ce09776b | 1040 | } |
67867308 | 1041 | /* never comes here */ |
e6e5906b PB |
1042 | return 1; |
1043 | } | |
1044 | ||
1045 | #elif defined(TARGET_M68K) | |
1046 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
1047 | int is_write, sigset_t *old_set, | |
1048 | void *puc) | |
1049 | { | |
1050 | TranslationBlock *tb; | |
1051 | int ret; | |
1052 | ||
1053 | if (cpu_single_env) | |
1054 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
1055 | #if defined(DEBUG_SIGNAL) | |
1056 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
1057 | pc, address, is_write, *(unsigned long *)old_set); | |
1058 | #endif | |
1059 | /* XXX: locking issue */ | |
1060 | if (is_write && page_unprotect(address, pc, puc)) { | |
1061 | return 1; | |
1062 | } | |
1063 | /* see if it is an MMU fault */ | |
1064 | ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0); | |
1065 | if (ret < 0) | |
1066 | return 0; /* not an MMU fault */ | |
1067 | if (ret == 0) | |
1068 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
1069 | /* now we have a real cpu fault */ | |
1070 | tb = tb_find_pc(pc); | |
1071 | if (tb) { | |
1072 | /* the PC is inside the translated code. It means that we have | |
1073 | a virtual CPU fault */ | |
1074 | cpu_restore_state(tb, env, pc, puc); | |
1075 | } | |
1076 | /* we restore the process signal mask as the sigreturn should | |
1077 | do it (XXX: use sigsetjmp) */ | |
1078 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
1079 | cpu_loop_exit(); | |
1080 | /* never comes here */ | |
67867308 FB |
1081 | return 1; |
1082 | } | |
6af0bf9c FB |
1083 | |
1084 | #elif defined (TARGET_MIPS) | |
1085 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
1086 | int is_write, sigset_t *old_set, | |
1087 | void *puc) | |
1088 | { | |
1089 | TranslationBlock *tb; | |
1090 | int ret; | |
1091 | ||
1092 | if (cpu_single_env) | |
1093 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
1094 | #if defined(DEBUG_SIGNAL) | |
1095 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
1096 | pc, address, is_write, *(unsigned long *)old_set); | |
1097 | #endif | |
1098 | /* XXX: locking issue */ | |
53a5960a | 1099 | if (is_write && page_unprotect(h2g(address), pc, puc)) { |
6af0bf9c FB |
1100 | return 1; |
1101 | } | |
1102 | ||
1103 | /* see if it is an MMU fault */ | |
cc9442b9 | 1104 | ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0); |
6af0bf9c FB |
1105 | if (ret < 0) |
1106 | return 0; /* not an MMU fault */ | |
1107 | if (ret == 0) | |
1108 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
1109 | ||
1110 | /* now we have a real cpu fault */ | |
1111 | tb = tb_find_pc(pc); | |
1112 | if (tb) { | |
1113 | /* the PC is inside the translated code. It means that we have | |
1114 | a virtual CPU fault */ | |
1115 | cpu_restore_state(tb, env, pc, puc); | |
1116 | } | |
1117 | if (ret == 1) { | |
1118 | #if 0 | |
1119 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", | |
1120 | env->nip, env->error_code, tb); | |
1121 | #endif | |
1122 | /* we restore the process signal mask as the sigreturn should | |
1123 | do it (XXX: use sigsetjmp) */ | |
1124 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
1125 | do_raise_exception_err(env->exception_index, env->error_code); | |
1126 | } else { | |
1127 | /* activate soft MMU for this block */ | |
1128 | cpu_resume_from_signal(env, puc); | |
1129 | } | |
1130 | /* never comes here */ | |
1131 | return 1; | |
1132 | } | |
1133 | ||
fdf9b3e8 FB |
1134 | #elif defined (TARGET_SH4) |
1135 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
1136 | int is_write, sigset_t *old_set, | |
1137 | void *puc) | |
1138 | { | |
1139 | TranslationBlock *tb; | |
1140 | int ret; | |
1141 | ||
1142 | if (cpu_single_env) | |
1143 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
1144 | #if defined(DEBUG_SIGNAL) | |
1145 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
1146 | pc, address, is_write, *(unsigned long *)old_set); | |
1147 | #endif | |
1148 | /* XXX: locking issue */ | |
1149 | if (is_write && page_unprotect(h2g(address), pc, puc)) { | |
1150 | return 1; | |
1151 | } | |
1152 | ||
1153 | /* see if it is an MMU fault */ | |
1154 | ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0); | |
1155 | if (ret < 0) | |
1156 | return 0; /* not an MMU fault */ | |
1157 | if (ret == 0) | |
1158 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
1159 | ||
1160 | /* now we have a real cpu fault */ | |
1161 | tb = tb_find_pc(pc); | |
1162 | if (tb) { | |
1163 | /* the PC is inside the translated code. It means that we have | |
1164 | a virtual CPU fault */ | |
1165 | cpu_restore_state(tb, env, pc, puc); | |
1166 | } | |
fdf9b3e8 FB |
1167 | #if 0 |
1168 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", | |
1169 | env->nip, env->error_code, tb); | |
1170 | #endif | |
1171 | /* we restore the process signal mask as the sigreturn should | |
1172 | do it (XXX: use sigsetjmp) */ | |
355fb23d PB |
1173 | sigprocmask(SIG_SETMASK, old_set, NULL); |
1174 | cpu_loop_exit(); | |
fdf9b3e8 FB |
1175 | /* never comes here */ |
1176 | return 1; | |
1177 | } | |
e4533c7a FB |
1178 | #else |
1179 | #error unsupported target CPU | |
1180 | #endif | |
9de5e440 | 1181 | |
2b413144 FB |
1182 | #if defined(__i386__) |
1183 | ||
d8ecc0b9 FB |
1184 | #if defined(__APPLE__) |
1185 | # include <sys/ucontext.h> | |
1186 | ||
1187 | # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip)) | |
1188 | # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno) | |
1189 | # define ERROR_sig(context) ((context)->uc_mcontext->es.err) | |
1190 | #else | |
1191 | # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) | |
1192 | # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) | |
1193 | # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) | |
1194 | #endif | |
1195 | ||
bf3e8bf1 FB |
1196 | #if defined(USE_CODE_COPY) |
1197 | static void cpu_send_trap(unsigned long pc, int trap, | |
1198 | struct ucontext *uc) | |
1199 | { | |
1200 | TranslationBlock *tb; | |
1201 | ||
1202 | if (cpu_single_env) | |
1203 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
1204 | /* now we have a real cpu fault */ | |
1205 | tb = tb_find_pc(pc); | |
1206 | if (tb) { | |
1207 | /* the PC is inside the translated code. It means that we have | |
1208 | a virtual CPU fault */ | |
1209 | cpu_restore_state(tb, env, pc, uc); | |
1210 | } | |
1211 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
1212 | raise_exception_err(trap, env->error_code); | |
1213 | } | |
1214 | #endif | |
1215 | ||
5a7b542b | 1216 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 1217 | void *puc) |
9de5e440 | 1218 | { |
5a7b542b | 1219 | siginfo_t *info = pinfo; |
9de5e440 FB |
1220 | struct ucontext *uc = puc; |
1221 | unsigned long pc; | |
bf3e8bf1 | 1222 | int trapno; |
97eb5b14 | 1223 | |
d691f669 FB |
1224 | #ifndef REG_EIP |
1225 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
1226 | #define REG_EIP EIP |
1227 | #define REG_ERR ERR | |
1228 | #define REG_TRAPNO TRAPNO | |
d691f669 | 1229 | #endif |
d8ecc0b9 FB |
1230 | pc = EIP_sig(uc); |
1231 | trapno = TRAP_sig(uc); | |
bf3e8bf1 FB |
1232 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
1233 | if (trapno == 0x00 || trapno == 0x05) { | |
1234 | /* send division by zero or bound exception */ | |
1235 | cpu_send_trap(pc, trapno, uc); | |
1236 | return 1; | |
1237 | } else | |
1238 | #endif | |
1239 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1240 | trapno == 0xe ? | |
d8ecc0b9 | 1241 | (ERROR_sig(uc) >> 1) & 1 : 0, |
bf3e8bf1 | 1242 | &uc->uc_sigmask, puc); |
2b413144 FB |
1243 | } |
1244 | ||
bc51c5c9 FB |
1245 | #elif defined(__x86_64__) |
1246 | ||
5a7b542b | 1247 | int cpu_signal_handler(int host_signum, void *pinfo, |
bc51c5c9 FB |
1248 | void *puc) |
1249 | { | |
5a7b542b | 1250 | siginfo_t *info = pinfo; |
bc51c5c9 FB |
1251 | struct ucontext *uc = puc; |
1252 | unsigned long pc; | |
1253 | ||
1254 | pc = uc->uc_mcontext.gregs[REG_RIP]; | |
1255 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1256 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
1257 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
1258 | &uc->uc_sigmask, puc); | |
1259 | } | |
1260 | ||
83fb7adf | 1261 | #elif defined(__powerpc__) |
2b413144 | 1262 | |
83fb7adf FB |
1263 | /*********************************************************************** |
1264 | * signal context platform-specific definitions | |
1265 | * From Wine | |
1266 | */ | |
1267 | #ifdef linux | |
1268 | /* All Registers access - only for local access */ | |
1269 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) | |
1270 | /* Gpr Registers access */ | |
1271 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
1272 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ | |
1273 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ | |
1274 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ | |
1275 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ | |
1276 | # define LR_sig(context) REG_sig(link, context) /* Link register */ | |
1277 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ | |
1278 | /* Float Registers access */ | |
1279 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) | |
1280 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) | |
1281 | /* Exception Registers access */ | |
1282 | # define DAR_sig(context) REG_sig(dar, context) | |
1283 | # define DSISR_sig(context) REG_sig(dsisr, context) | |
1284 | # define TRAP_sig(context) REG_sig(trap, context) | |
1285 | #endif /* linux */ | |
1286 | ||
1287 | #ifdef __APPLE__ | |
1288 | # include <sys/ucontext.h> | |
1289 | typedef struct ucontext SIGCONTEXT; | |
1290 | /* All Registers access - only for local access */ | |
1291 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) | |
1292 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) | |
1293 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) | |
1294 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) | |
1295 | /* Gpr Registers access */ | |
1296 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) | |
1297 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ | |
1298 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ | |
1299 | # define CTR_sig(context) REG_sig(ctr, context) | |
1300 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ | |
1301 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ | |
1302 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ | |
1303 | /* Float Registers access */ | |
1304 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) | |
1305 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) | |
1306 | /* Exception Registers access */ | |
1307 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ | |
1308 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) | |
1309 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ | |
1310 | #endif /* __APPLE__ */ | |
1311 | ||
5a7b542b | 1312 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 1313 | void *puc) |
2b413144 | 1314 | { |
5a7b542b | 1315 | siginfo_t *info = pinfo; |
25eb4484 | 1316 | struct ucontext *uc = puc; |
25eb4484 | 1317 | unsigned long pc; |
25eb4484 FB |
1318 | int is_write; |
1319 | ||
83fb7adf | 1320 | pc = IAR_sig(uc); |
25eb4484 FB |
1321 | is_write = 0; |
1322 | #if 0 | |
1323 | /* ppc 4xx case */ | |
83fb7adf | 1324 | if (DSISR_sig(uc) & 0x00800000) |
25eb4484 FB |
1325 | is_write = 1; |
1326 | #else | |
83fb7adf | 1327 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
25eb4484 FB |
1328 | is_write = 1; |
1329 | #endif | |
1330 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1331 | is_write, &uc->uc_sigmask, puc); |
2b413144 FB |
1332 | } |
1333 | ||
2f87c607 FB |
1334 | #elif defined(__alpha__) |
1335 | ||
5a7b542b | 1336 | int cpu_signal_handler(int host_signum, void *pinfo, |
2f87c607 FB |
1337 | void *puc) |
1338 | { | |
5a7b542b | 1339 | siginfo_t *info = pinfo; |
2f87c607 FB |
1340 | struct ucontext *uc = puc; |
1341 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
1342 | uint32_t insn = *pc; | |
1343 | int is_write = 0; | |
1344 | ||
8c6939c0 | 1345 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
1346 | switch (insn >> 26) { |
1347 | case 0x0d: // stw | |
1348 | case 0x0e: // stb | |
1349 | case 0x0f: // stq_u | |
1350 | case 0x24: // stf | |
1351 | case 0x25: // stg | |
1352 | case 0x26: // sts | |
1353 | case 0x27: // stt | |
1354 | case 0x2c: // stl | |
1355 | case 0x2d: // stq | |
1356 | case 0x2e: // stl_c | |
1357 | case 0x2f: // stq_c | |
1358 | is_write = 1; | |
1359 | } | |
1360 | ||
1361 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1362 | is_write, &uc->uc_sigmask, puc); |
2f87c607 | 1363 | } |
8c6939c0 FB |
1364 | #elif defined(__sparc__) |
1365 | ||
5a7b542b | 1366 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 1367 | void *puc) |
8c6939c0 | 1368 | { |
5a7b542b | 1369 | siginfo_t *info = pinfo; |
8c6939c0 FB |
1370 | uint32_t *regs = (uint32_t *)(info + 1); |
1371 | void *sigmask = (regs + 20); | |
1372 | unsigned long pc; | |
1373 | int is_write; | |
1374 | uint32_t insn; | |
1375 | ||
1376 | /* XXX: is there a standard glibc define ? */ | |
1377 | pc = regs[1]; | |
1378 | /* XXX: need kernel patch to get write flag faster */ | |
1379 | is_write = 0; | |
1380 | insn = *(uint32_t *)pc; | |
1381 | if ((insn >> 30) == 3) { | |
1382 | switch((insn >> 19) & 0x3f) { | |
1383 | case 0x05: // stb | |
1384 | case 0x06: // sth | |
1385 | case 0x04: // st | |
1386 | case 0x07: // std | |
1387 | case 0x24: // stf | |
1388 | case 0x27: // stdf | |
1389 | case 0x25: // stfsr | |
1390 | is_write = 1; | |
1391 | break; | |
1392 | } | |
1393 | } | |
1394 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1395 | is_write, sigmask, NULL); |
8c6939c0 FB |
1396 | } |
1397 | ||
1398 | #elif defined(__arm__) | |
1399 | ||
5a7b542b | 1400 | int cpu_signal_handler(int host_signum, void *pinfo, |
e4533c7a | 1401 | void *puc) |
8c6939c0 | 1402 | { |
5a7b542b | 1403 | siginfo_t *info = pinfo; |
8c6939c0 FB |
1404 | struct ucontext *uc = puc; |
1405 | unsigned long pc; | |
1406 | int is_write; | |
1407 | ||
1408 | pc = uc->uc_mcontext.gregs[R15]; | |
1409 | /* XXX: compute is_write */ | |
1410 | is_write = 0; | |
1411 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1412 | is_write, | |
f3a9676a | 1413 | &uc->uc_sigmask, puc); |
8c6939c0 FB |
1414 | } |
1415 | ||
38e584a0 FB |
1416 | #elif defined(__mc68000) |
1417 | ||
5a7b542b | 1418 | int cpu_signal_handler(int host_signum, void *pinfo, |
38e584a0 FB |
1419 | void *puc) |
1420 | { | |
5a7b542b | 1421 | siginfo_t *info = pinfo; |
38e584a0 FB |
1422 | struct ucontext *uc = puc; |
1423 | unsigned long pc; | |
1424 | int is_write; | |
1425 | ||
1426 | pc = uc->uc_mcontext.gregs[16]; | |
1427 | /* XXX: compute is_write */ | |
1428 | is_write = 0; | |
1429 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1430 | is_write, | |
bf3e8bf1 | 1431 | &uc->uc_sigmask, puc); |
38e584a0 FB |
1432 | } |
1433 | ||
b8076a74 FB |
1434 | #elif defined(__ia64) |
1435 | ||
1436 | #ifndef __ISR_VALID | |
1437 | /* This ought to be in <bits/siginfo.h>... */ | |
1438 | # define __ISR_VALID 1 | |
b8076a74 FB |
1439 | #endif |
1440 | ||
5a7b542b | 1441 | int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
b8076a74 | 1442 | { |
5a7b542b | 1443 | siginfo_t *info = pinfo; |
b8076a74 FB |
1444 | struct ucontext *uc = puc; |
1445 | unsigned long ip; | |
1446 | int is_write = 0; | |
1447 | ||
1448 | ip = uc->uc_mcontext.sc_ip; | |
1449 | switch (host_signum) { | |
1450 | case SIGILL: | |
1451 | case SIGFPE: | |
1452 | case SIGSEGV: | |
1453 | case SIGBUS: | |
1454 | case SIGTRAP: | |
fd4a43e4 | 1455 | if (info->si_code && (info->si_segvflags & __ISR_VALID)) |
b8076a74 FB |
1456 | /* ISR.W (write-access) is bit 33: */ |
1457 | is_write = (info->si_isr >> 33) & 1; | |
1458 | break; | |
1459 | ||
1460 | default: | |
1461 | break; | |
1462 | } | |
1463 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, | |
1464 | is_write, | |
1465 | &uc->uc_sigmask, puc); | |
1466 | } | |
1467 | ||
90cb9493 FB |
1468 | #elif defined(__s390__) |
1469 | ||
5a7b542b | 1470 | int cpu_signal_handler(int host_signum, void *pinfo, |
90cb9493 FB |
1471 | void *puc) |
1472 | { | |
5a7b542b | 1473 | siginfo_t *info = pinfo; |
90cb9493 FB |
1474 | struct ucontext *uc = puc; |
1475 | unsigned long pc; | |
1476 | int is_write; | |
1477 | ||
1478 | pc = uc->uc_mcontext.psw.addr; | |
1479 | /* XXX: compute is_write */ | |
1480 | is_write = 0; | |
1481 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1482 | is_write, | |
1483 | &uc->uc_sigmask, puc); | |
1484 | } | |
1485 | ||
9de5e440 | 1486 | #else |
2b413144 | 1487 | |
3fb2ded1 | 1488 | #error host CPU specific signal handler needed |
2b413144 | 1489 | |
9de5e440 | 1490 | #endif |
67b915a5 FB |
1491 | |
1492 | #endif /* !defined(CONFIG_SOFTMMU) */ |