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Commit | Line | Data |
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7d13299d | 1 | /* |
e965fc38 | 2 | * emulator main execution loop |
5fafdf24 | 3 | * |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
7d13299d | 5 | * |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 | 16 | * You should have received a copy of the GNU Lesser General Public |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
7d13299d | 18 | */ |
e4533c7a | 19 | #include "config.h" |
cea5f9a2 | 20 | #include "cpu.h" |
76cad711 | 21 | #include "disas/disas.h" |
7cb69cae | 22 | #include "tcg.h" |
1de7afc9 | 23 | #include "qemu/atomic.h" |
9c17d615 | 24 | #include "sysemu/qtest.h" |
7d13299d | 25 | |
f0667e66 | 26 | //#define CONFIG_DEBUG_EXEC |
7d13299d | 27 | |
3993c6bd | 28 | bool qemu_cpu_has_work(CPUState *cpu) |
6a4955a8 | 29 | { |
3993c6bd | 30 | return cpu_has_work(cpu); |
6a4955a8 AL |
31 | } |
32 | ||
9349b4f9 | 33 | void cpu_loop_exit(CPUArchState *env) |
e4533c7a | 34 | { |
d77953b9 AF |
35 | CPUState *cpu = ENV_GET_CPU(env); |
36 | ||
37 | cpu->current_tb = NULL; | |
6ab7e546 | 38 | siglongjmp(env->jmp_env, 1); |
e4533c7a | 39 | } |
bfed01fc | 40 | |
fbf9eeb3 FB |
41 | /* exit the current TB from a signal handler. The host registers are |
42 | restored in a state compatible with the CPU emulator | |
43 | */ | |
9eff14f3 | 44 | #if defined(CONFIG_SOFTMMU) |
9349b4f9 | 45 | void cpu_resume_from_signal(CPUArchState *env, void *puc) |
9eff14f3 | 46 | { |
9eff14f3 BS |
47 | /* XXX: restore cpu registers saved in host registers */ |
48 | ||
49 | env->exception_index = -1; | |
6ab7e546 | 50 | siglongjmp(env->jmp_env, 1); |
9eff14f3 | 51 | } |
9eff14f3 | 52 | #endif |
fbf9eeb3 | 53 | |
77211379 PM |
54 | /* Execute a TB, and fix up the CPU state afterwards if necessary */ |
55 | static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr) | |
56 | { | |
57 | CPUArchState *env = cpu->env_ptr; | |
58 | tcg_target_ulong next_tb = tcg_qemu_tb_exec(env, tb_ptr); | |
59 | if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) { | |
60 | /* We didn't start executing this TB (eg because the instruction | |
61 | * counter hit zero); we must restore the guest PC to the address | |
62 | * of the start of the TB. | |
63 | */ | |
64 | TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); | |
65 | cpu_pc_from_tb(env, tb); | |
66 | } | |
67 | return next_tb; | |
68 | } | |
69 | ||
2e70f6ef PB |
70 | /* Execute the code without caching the generated code. An interpreter |
71 | could be used if available. */ | |
9349b4f9 | 72 | static void cpu_exec_nocache(CPUArchState *env, int max_cycles, |
cea5f9a2 | 73 | TranslationBlock *orig_tb) |
2e70f6ef | 74 | { |
d77953b9 | 75 | CPUState *cpu = ENV_GET_CPU(env); |
2e70f6ef PB |
76 | TranslationBlock *tb; |
77 | ||
78 | /* Should never happen. | |
79 | We only end up here when an existing TB is too long. */ | |
80 | if (max_cycles > CF_COUNT_MASK) | |
81 | max_cycles = CF_COUNT_MASK; | |
82 | ||
83 | tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, | |
84 | max_cycles); | |
d77953b9 | 85 | cpu->current_tb = tb; |
2e70f6ef | 86 | /* execute the generated code */ |
77211379 | 87 | cpu_tb_exec(cpu, tb->tc_ptr); |
d77953b9 | 88 | cpu->current_tb = NULL; |
2e70f6ef PB |
89 | tb_phys_invalidate(tb, -1); |
90 | tb_free(tb); | |
91 | } | |
92 | ||
9349b4f9 | 93 | static TranslationBlock *tb_find_slow(CPUArchState *env, |
cea5f9a2 | 94 | target_ulong pc, |
8a40a180 | 95 | target_ulong cs_base, |
c068688b | 96 | uint64_t flags) |
8a40a180 FB |
97 | { |
98 | TranslationBlock *tb, **ptb1; | |
8a40a180 | 99 | unsigned int h; |
337fc758 | 100 | tb_page_addr_t phys_pc, phys_page1; |
41c1b1c9 | 101 | target_ulong virt_page2; |
3b46e624 | 102 | |
5e5f07e0 | 103 | tcg_ctx.tb_ctx.tb_invalidated_flag = 0; |
3b46e624 | 104 | |
8a40a180 | 105 | /* find translated block using physical mappings */ |
41c1b1c9 | 106 | phys_pc = get_page_addr_code(env, pc); |
8a40a180 | 107 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
8a40a180 | 108 | h = tb_phys_hash_func(phys_pc); |
5e5f07e0 | 109 | ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h]; |
8a40a180 FB |
110 | for(;;) { |
111 | tb = *ptb1; | |
112 | if (!tb) | |
113 | goto not_found; | |
5fafdf24 | 114 | if (tb->pc == pc && |
8a40a180 | 115 | tb->page_addr[0] == phys_page1 && |
5fafdf24 | 116 | tb->cs_base == cs_base && |
8a40a180 FB |
117 | tb->flags == flags) { |
118 | /* check next page if needed */ | |
119 | if (tb->page_addr[1] != -1) { | |
337fc758 BS |
120 | tb_page_addr_t phys_page2; |
121 | ||
5fafdf24 | 122 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
8a40a180 | 123 | TARGET_PAGE_SIZE; |
41c1b1c9 | 124 | phys_page2 = get_page_addr_code(env, virt_page2); |
8a40a180 FB |
125 | if (tb->page_addr[1] == phys_page2) |
126 | goto found; | |
127 | } else { | |
128 | goto found; | |
129 | } | |
130 | } | |
131 | ptb1 = &tb->phys_hash_next; | |
132 | } | |
133 | not_found: | |
2e70f6ef PB |
134 | /* if no translated code available, then translate it now */ |
135 | tb = tb_gen_code(env, pc, cs_base, flags, 0); | |
3b46e624 | 136 | |
8a40a180 | 137 | found: |
2c90fe2b KB |
138 | /* Move the last found TB to the head of the list */ |
139 | if (likely(*ptb1)) { | |
140 | *ptb1 = tb->phys_hash_next; | |
5e5f07e0 EV |
141 | tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h]; |
142 | tcg_ctx.tb_ctx.tb_phys_hash[h] = tb; | |
2c90fe2b | 143 | } |
8a40a180 FB |
144 | /* we add the TB in the virtual pc hash table */ |
145 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; | |
8a40a180 FB |
146 | return tb; |
147 | } | |
148 | ||
9349b4f9 | 149 | static inline TranslationBlock *tb_find_fast(CPUArchState *env) |
8a40a180 FB |
150 | { |
151 | TranslationBlock *tb; | |
152 | target_ulong cs_base, pc; | |
6b917547 | 153 | int flags; |
8a40a180 FB |
154 | |
155 | /* we record a subset of the CPU state. It will | |
156 | always be the same before a given translated block | |
157 | is executed. */ | |
6b917547 | 158 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); |
bce61846 | 159 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
551bd27f TS |
160 | if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || |
161 | tb->flags != flags)) { | |
cea5f9a2 | 162 | tb = tb_find_slow(env, pc, cs_base, flags); |
8a40a180 FB |
163 | } |
164 | return tb; | |
165 | } | |
166 | ||
1009d2ed JK |
167 | static CPUDebugExcpHandler *debug_excp_handler; |
168 | ||
84e3b602 | 169 | void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) |
1009d2ed | 170 | { |
1009d2ed | 171 | debug_excp_handler = handler; |
1009d2ed JK |
172 | } |
173 | ||
9349b4f9 | 174 | static void cpu_handle_debug_exception(CPUArchState *env) |
1009d2ed JK |
175 | { |
176 | CPUWatchpoint *wp; | |
177 | ||
178 | if (!env->watchpoint_hit) { | |
179 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { | |
180 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
181 | } | |
182 | } | |
183 | if (debug_excp_handler) { | |
184 | debug_excp_handler(env); | |
185 | } | |
186 | } | |
187 | ||
7d13299d FB |
188 | /* main execution loop */ |
189 | ||
1a28cac3 MT |
190 | volatile sig_atomic_t exit_request; |
191 | ||
9349b4f9 | 192 | int cpu_exec(CPUArchState *env) |
7d13299d | 193 | { |
c356a1bc | 194 | CPUState *cpu = ENV_GET_CPU(env); |
8a40a180 | 195 | int ret, interrupt_request; |
8a40a180 | 196 | TranslationBlock *tb; |
c27004ec | 197 | uint8_t *tc_ptr; |
69784eae | 198 | tcg_target_ulong next_tb; |
8c6939c0 | 199 | |
cea5f9a2 | 200 | if (env->halted) { |
3993c6bd | 201 | if (!cpu_has_work(cpu)) { |
eda48c34 PB |
202 | return EXCP_HALTED; |
203 | } | |
204 | ||
cea5f9a2 | 205 | env->halted = 0; |
eda48c34 | 206 | } |
5a1e3cfc | 207 | |
cea5f9a2 | 208 | cpu_single_env = env; |
e4533c7a | 209 | |
c629a4bc | 210 | if (unlikely(exit_request)) { |
fcd7d003 | 211 | cpu->exit_request = 1; |
1a28cac3 MT |
212 | } |
213 | ||
ecb644f4 | 214 | #if defined(TARGET_I386) |
6792a57b JK |
215 | /* put eflags in CPU temporary format */ |
216 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
217 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
218 | CC_OP = CC_OP_EFLAGS; | |
219 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
93ac68bc | 220 | #elif defined(TARGET_SPARC) |
e6e5906b PB |
221 | #elif defined(TARGET_M68K) |
222 | env->cc_op = CC_OP_FLAGS; | |
223 | env->cc_dest = env->sr & 0xf; | |
224 | env->cc_x = (env->sr >> 4) & 1; | |
ecb644f4 TS |
225 | #elif defined(TARGET_ALPHA) |
226 | #elif defined(TARGET_ARM) | |
d2fbca94 | 227 | #elif defined(TARGET_UNICORE32) |
ecb644f4 | 228 | #elif defined(TARGET_PPC) |
4e85f82c | 229 | env->reserve_addr = -1; |
81ea0e13 | 230 | #elif defined(TARGET_LM32) |
b779e29e | 231 | #elif defined(TARGET_MICROBLAZE) |
6af0bf9c | 232 | #elif defined(TARGET_MIPS) |
e67db06e | 233 | #elif defined(TARGET_OPENRISC) |
fdf9b3e8 | 234 | #elif defined(TARGET_SH4) |
f1ccf904 | 235 | #elif defined(TARGET_CRIS) |
10ec5117 | 236 | #elif defined(TARGET_S390X) |
2328826b | 237 | #elif defined(TARGET_XTENSA) |
fdf9b3e8 | 238 | /* XXXXX */ |
e4533c7a FB |
239 | #else |
240 | #error unsupported target CPU | |
241 | #endif | |
3fb2ded1 | 242 | env->exception_index = -1; |
9d27abd9 | 243 | |
7d13299d | 244 | /* prepare setjmp context for exception handling */ |
3fb2ded1 | 245 | for(;;) { |
6ab7e546 | 246 | if (sigsetjmp(env->jmp_env, 0) == 0) { |
3fb2ded1 FB |
247 | /* if an exception is pending, we execute it here */ |
248 | if (env->exception_index >= 0) { | |
249 | if (env->exception_index >= EXCP_INTERRUPT) { | |
250 | /* exit request from the cpu execution loop */ | |
251 | ret = env->exception_index; | |
1009d2ed JK |
252 | if (ret == EXCP_DEBUG) { |
253 | cpu_handle_debug_exception(env); | |
254 | } | |
3fb2ded1 | 255 | break; |
72d239ed AJ |
256 | } else { |
257 | #if defined(CONFIG_USER_ONLY) | |
3fb2ded1 | 258 | /* if user mode only, we simulate a fake exception |
9f083493 | 259 | which will be handled outside the cpu execution |
3fb2ded1 | 260 | loop */ |
83479e77 | 261 | #if defined(TARGET_I386) |
e694d4e2 | 262 | do_interrupt(env); |
83479e77 | 263 | #endif |
3fb2ded1 FB |
264 | ret = env->exception_index; |
265 | break; | |
72d239ed | 266 | #else |
b5ff1b31 | 267 | do_interrupt(env); |
301d2908 | 268 | env->exception_index = -1; |
83479e77 | 269 | #endif |
3fb2ded1 | 270 | } |
5fafdf24 | 271 | } |
9df217a3 | 272 | |
b5fc09ae | 273 | next_tb = 0; /* force lookup of first TB */ |
3fb2ded1 | 274 | for(;;) { |
68a79315 | 275 | interrupt_request = env->interrupt_request; |
e1638bd8 | 276 | if (unlikely(interrupt_request)) { |
277 | if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { | |
278 | /* Mask out external interrupts for this step. */ | |
3125f763 | 279 | interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; |
e1638bd8 | 280 | } |
6658ffb8 PB |
281 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
282 | env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; | |
283 | env->exception_index = EXCP_DEBUG; | |
1162c041 | 284 | cpu_loop_exit(env); |
6658ffb8 | 285 | } |
a90b7318 | 286 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
b779e29e | 287 | defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ |
d2fbca94 | 288 | defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32) |
a90b7318 AZ |
289 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
290 | env->interrupt_request &= ~CPU_INTERRUPT_HALT; | |
291 | env->halted = 1; | |
292 | env->exception_index = EXCP_HLT; | |
1162c041 | 293 | cpu_loop_exit(env); |
a90b7318 AZ |
294 | } |
295 | #endif | |
68a79315 | 296 | #if defined(TARGET_I386) |
5d62c43a JK |
297 | #if !defined(CONFIG_USER_ONLY) |
298 | if (interrupt_request & CPU_INTERRUPT_POLL) { | |
299 | env->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
300 | apic_poll_irq(env->apic_state); | |
301 | } | |
302 | #endif | |
b09ea7d5 | 303 | if (interrupt_request & CPU_INTERRUPT_INIT) { |
77b2bc2c BS |
304 | cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, |
305 | 0); | |
232fc23b | 306 | do_cpu_init(x86_env_get_cpu(env)); |
b09ea7d5 | 307 | env->exception_index = EXCP_HALTED; |
1162c041 | 308 | cpu_loop_exit(env); |
b09ea7d5 | 309 | } else if (interrupt_request & CPU_INTERRUPT_SIPI) { |
232fc23b | 310 | do_cpu_sipi(x86_env_get_cpu(env)); |
b09ea7d5 | 311 | } else if (env->hflags2 & HF2_GIF_MASK) { |
db620f46 FB |
312 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
313 | !(env->hflags & HF_SMM_MASK)) { | |
77b2bc2c BS |
314 | cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, |
315 | 0); | |
db620f46 | 316 | env->interrupt_request &= ~CPU_INTERRUPT_SMI; |
e694d4e2 | 317 | do_smm_enter(env); |
db620f46 FB |
318 | next_tb = 0; |
319 | } else if ((interrupt_request & CPU_INTERRUPT_NMI) && | |
320 | !(env->hflags2 & HF2_NMI_MASK)) { | |
321 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
322 | env->hflags2 |= HF2_NMI_MASK; | |
e694d4e2 | 323 | do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); |
db620f46 | 324 | next_tb = 0; |
e965fc38 | 325 | } else if (interrupt_request & CPU_INTERRUPT_MCE) { |
79c4f6b0 | 326 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; |
e694d4e2 | 327 | do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); |
79c4f6b0 | 328 | next_tb = 0; |
db620f46 FB |
329 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
330 | (((env->hflags2 & HF2_VINTR_MASK) && | |
331 | (env->hflags2 & HF2_HIF_MASK)) || | |
332 | (!(env->hflags2 & HF2_VINTR_MASK) && | |
333 | (env->eflags & IF_MASK && | |
334 | !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { | |
335 | int intno; | |
77b2bc2c BS |
336 | cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, |
337 | 0); | |
db620f46 FB |
338 | env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); |
339 | intno = cpu_get_pic_interrupt(env); | |
4f213879 | 340 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); |
341 | do_interrupt_x86_hardirq(env, intno, 1); | |
342 | /* ensure that no TB jump will be modified as | |
343 | the program flow was changed */ | |
344 | next_tb = 0; | |
0573fbfc | 345 | #if !defined(CONFIG_USER_ONLY) |
db620f46 FB |
346 | } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && |
347 | (env->eflags & IF_MASK) && | |
348 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
349 | int intno; | |
350 | /* FIXME: this should respect TPR */ | |
77b2bc2c BS |
351 | cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, |
352 | 0); | |
db620f46 | 353 | intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); |
93fcfe39 | 354 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); |
e694d4e2 | 355 | do_interrupt_x86_hardirq(env, intno, 1); |
d40c54d6 | 356 | env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
db620f46 | 357 | next_tb = 0; |
907a5b26 | 358 | #endif |
db620f46 | 359 | } |
68a79315 | 360 | } |
ce09776b | 361 | #elif defined(TARGET_PPC) |
9fddaa0c | 362 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
c356a1bc | 363 | cpu_reset(cpu); |
9fddaa0c | 364 | } |
47103572 | 365 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
e9df014c JM |
366 | ppc_hw_interrupt(env); |
367 | if (env->pending_interrupts == 0) | |
368 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
b5fc09ae | 369 | next_tb = 0; |
ce09776b | 370 | } |
81ea0e13 MW |
371 | #elif defined(TARGET_LM32) |
372 | if ((interrupt_request & CPU_INTERRUPT_HARD) | |
373 | && (env->ie & IE_IE)) { | |
374 | env->exception_index = EXCP_IRQ; | |
375 | do_interrupt(env); | |
376 | next_tb = 0; | |
377 | } | |
b779e29e EI |
378 | #elif defined(TARGET_MICROBLAZE) |
379 | if ((interrupt_request & CPU_INTERRUPT_HARD) | |
380 | && (env->sregs[SR_MSR] & MSR_IE) | |
381 | && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) | |
382 | && !(env->iflags & (D_FLAG | IMM_FLAG))) { | |
383 | env->exception_index = EXCP_IRQ; | |
384 | do_interrupt(env); | |
385 | next_tb = 0; | |
386 | } | |
6af0bf9c FB |
387 | #elif defined(TARGET_MIPS) |
388 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
4cdc1cd1 | 389 | cpu_mips_hw_interrupts_pending(env)) { |
6af0bf9c FB |
390 | /* Raise it */ |
391 | env->exception_index = EXCP_EXT_INTERRUPT; | |
392 | env->error_code = 0; | |
393 | do_interrupt(env); | |
b5fc09ae | 394 | next_tb = 0; |
6af0bf9c | 395 | } |
b6a71ef7 JL |
396 | #elif defined(TARGET_OPENRISC) |
397 | { | |
398 | int idx = -1; | |
399 | if ((interrupt_request & CPU_INTERRUPT_HARD) | |
400 | && (env->sr & SR_IEE)) { | |
401 | idx = EXCP_INT; | |
402 | } | |
403 | if ((interrupt_request & CPU_INTERRUPT_TIMER) | |
404 | && (env->sr & SR_TEE)) { | |
405 | idx = EXCP_TICK; | |
406 | } | |
407 | if (idx >= 0) { | |
408 | env->exception_index = idx; | |
409 | do_interrupt(env); | |
410 | next_tb = 0; | |
411 | } | |
412 | } | |
e95c8d51 | 413 | #elif defined(TARGET_SPARC) |
d532b26c IK |
414 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
415 | if (cpu_interrupts_enabled(env) && | |
416 | env->interrupt_index > 0) { | |
417 | int pil = env->interrupt_index & 0xf; | |
418 | int type = env->interrupt_index & 0xf0; | |
419 | ||
420 | if (((type == TT_EXTINT) && | |
421 | cpu_pil_allowed(env, pil)) || | |
422 | type != TT_EXTINT) { | |
423 | env->exception_index = env->interrupt_index; | |
424 | do_interrupt(env); | |
425 | next_tb = 0; | |
426 | } | |
427 | } | |
e965fc38 | 428 | } |
b5ff1b31 FB |
429 | #elif defined(TARGET_ARM) |
430 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
431 | && !(env->uncached_cpsr & CPSR_F)) { | |
432 | env->exception_index = EXCP_FIQ; | |
433 | do_interrupt(env); | |
b5fc09ae | 434 | next_tb = 0; |
b5ff1b31 | 435 | } |
9ee6e8bb PB |
436 | /* ARMv7-M interrupt return works by loading a magic value |
437 | into the PC. On real hardware the load causes the | |
438 | return to occur. The qemu implementation performs the | |
439 | jump normally, then does the exception return when the | |
440 | CPU tries to execute code at the magic address. | |
441 | This will cause the magic PC value to be pushed to | |
a1c7273b | 442 | the stack if an interrupt occurred at the wrong time. |
9ee6e8bb PB |
443 | We avoid this by disabling interrupts when |
444 | pc contains a magic address. */ | |
b5ff1b31 | 445 | if (interrupt_request & CPU_INTERRUPT_HARD |
9ee6e8bb PB |
446 | && ((IS_M(env) && env->regs[15] < 0xfffffff0) |
447 | || !(env->uncached_cpsr & CPSR_I))) { | |
b5ff1b31 FB |
448 | env->exception_index = EXCP_IRQ; |
449 | do_interrupt(env); | |
b5fc09ae | 450 | next_tb = 0; |
b5ff1b31 | 451 | } |
d2fbca94 GX |
452 | #elif defined(TARGET_UNICORE32) |
453 | if (interrupt_request & CPU_INTERRUPT_HARD | |
454 | && !(env->uncached_asr & ASR_I)) { | |
d48813dd | 455 | env->exception_index = UC32_EXCP_INTR; |
d2fbca94 GX |
456 | do_interrupt(env); |
457 | next_tb = 0; | |
458 | } | |
fdf9b3e8 | 459 | #elif defined(TARGET_SH4) |
e96e2044 TS |
460 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
461 | do_interrupt(env); | |
b5fc09ae | 462 | next_tb = 0; |
e96e2044 | 463 | } |
eddf68a6 | 464 | #elif defined(TARGET_ALPHA) |
6a80e088 RH |
465 | { |
466 | int idx = -1; | |
467 | /* ??? This hard-codes the OSF/1 interrupt levels. */ | |
e965fc38 | 468 | switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { |
6a80e088 RH |
469 | case 0 ... 3: |
470 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
471 | idx = EXCP_DEV_INTERRUPT; | |
472 | } | |
473 | /* FALLTHRU */ | |
474 | case 4: | |
475 | if (interrupt_request & CPU_INTERRUPT_TIMER) { | |
476 | idx = EXCP_CLK_INTERRUPT; | |
477 | } | |
478 | /* FALLTHRU */ | |
479 | case 5: | |
480 | if (interrupt_request & CPU_INTERRUPT_SMP) { | |
481 | idx = EXCP_SMP_INTERRUPT; | |
482 | } | |
483 | /* FALLTHRU */ | |
484 | case 6: | |
485 | if (interrupt_request & CPU_INTERRUPT_MCHK) { | |
486 | idx = EXCP_MCHK; | |
487 | } | |
488 | } | |
489 | if (idx >= 0) { | |
490 | env->exception_index = idx; | |
491 | env->error_code = 0; | |
492 | do_interrupt(env); | |
493 | next_tb = 0; | |
494 | } | |
eddf68a6 | 495 | } |
f1ccf904 | 496 | #elif defined(TARGET_CRIS) |
1b1a38b0 | 497 | if (interrupt_request & CPU_INTERRUPT_HARD |
fb9fb692 EI |
498 | && (env->pregs[PR_CCS] & I_FLAG) |
499 | && !env->locked_irq) { | |
1b1a38b0 EI |
500 | env->exception_index = EXCP_IRQ; |
501 | do_interrupt(env); | |
502 | next_tb = 0; | |
503 | } | |
8219314b LP |
504 | if (interrupt_request & CPU_INTERRUPT_NMI) { |
505 | unsigned int m_flag_archval; | |
506 | if (env->pregs[PR_VR] < 32) { | |
507 | m_flag_archval = M_FLAG_V10; | |
508 | } else { | |
509 | m_flag_archval = M_FLAG_V32; | |
510 | } | |
511 | if ((env->pregs[PR_CCS] & m_flag_archval)) { | |
512 | env->exception_index = EXCP_NMI; | |
513 | do_interrupt(env); | |
514 | next_tb = 0; | |
515 | } | |
f1ccf904 | 516 | } |
0633879f PB |
517 | #elif defined(TARGET_M68K) |
518 | if (interrupt_request & CPU_INTERRUPT_HARD | |
519 | && ((env->sr & SR_I) >> SR_I_SHIFT) | |
520 | < env->pending_level) { | |
521 | /* Real hardware gets the interrupt vector via an | |
522 | IACK cycle at this point. Current emulated | |
523 | hardware doesn't rely on this, so we | |
524 | provide/save the vector when the interrupt is | |
525 | first signalled. */ | |
526 | env->exception_index = env->pending_vector; | |
3c688828 | 527 | do_interrupt_m68k_hardirq(env); |
b5fc09ae | 528 | next_tb = 0; |
0633879f | 529 | } |
3110e292 AG |
530 | #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY) |
531 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
532 | (env->psw.mask & PSW_MASK_EXT)) { | |
533 | do_interrupt(env); | |
534 | next_tb = 0; | |
535 | } | |
40643d7c MF |
536 | #elif defined(TARGET_XTENSA) |
537 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
538 | env->exception_index = EXC_IRQ; | |
539 | do_interrupt(env); | |
540 | next_tb = 0; | |
541 | } | |
68a79315 | 542 | #endif |
ff2712ba | 543 | /* Don't use the cached interrupt_request value, |
9d05095e | 544 | do_interrupt may have updated the EXITTB flag. */ |
b5ff1b31 | 545 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bf3e8bf1 FB |
546 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
547 | /* ensure that no TB jump will be modified as | |
548 | the program flow was changed */ | |
b5fc09ae | 549 | next_tb = 0; |
bf3e8bf1 | 550 | } |
be214e6c | 551 | } |
fcd7d003 AF |
552 | if (unlikely(cpu->exit_request)) { |
553 | cpu->exit_request = 0; | |
be214e6c | 554 | env->exception_index = EXCP_INTERRUPT; |
1162c041 | 555 | cpu_loop_exit(env); |
3fb2ded1 | 556 | } |
a73b1fd9 | 557 | #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC) |
8fec2b8c | 558 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
3fb2ded1 | 559 | /* restore flags in standard format */ |
ecb644f4 | 560 | #if defined(TARGET_I386) |
e694d4e2 BS |
561 | env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP) |
562 | | (DF & DF_MASK); | |
6fd2a026 | 563 | log_cpu_state(env, CPU_DUMP_CCOP); |
3fb2ded1 | 564 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e6e5906b PB |
565 | #elif defined(TARGET_M68K) |
566 | cpu_m68k_flush_flags(env, env->cc_op); | |
567 | env->cc_op = CC_OP_FLAGS; | |
568 | env->sr = (env->sr & 0xffe0) | |
569 | | env->cc_dest | (env->cc_x << 4); | |
93fcfe39 | 570 | log_cpu_state(env, 0); |
e4533c7a | 571 | #else |
a73b1fd9 | 572 | log_cpu_state(env, 0); |
e4533c7a | 573 | #endif |
3fb2ded1 | 574 | } |
a73b1fd9 | 575 | #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */ |
5e5f07e0 | 576 | spin_lock(&tcg_ctx.tb_ctx.tb_lock); |
cea5f9a2 | 577 | tb = tb_find_fast(env); |
d5975363 PB |
578 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
579 | doing it in tb_find_slow */ | |
5e5f07e0 | 580 | if (tcg_ctx.tb_ctx.tb_invalidated_flag) { |
d5975363 PB |
581 | /* as some TB could have been invalidated because |
582 | of memory exceptions while generating the code, we | |
583 | must recompute the hash index here */ | |
584 | next_tb = 0; | |
5e5f07e0 | 585 | tcg_ctx.tb_ctx.tb_invalidated_flag = 0; |
d5975363 | 586 | } |
f0667e66 | 587 | #ifdef CONFIG_DEBUG_EXEC |
3ba19255 SW |
588 | qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n", |
589 | tb->tc_ptr, tb->pc, | |
93fcfe39 | 590 | lookup_symbol(tb->pc)); |
9d27abd9 | 591 | #endif |
8a40a180 FB |
592 | /* see if we can patch the calling TB. When the TB |
593 | spans two pages, we cannot safely do a direct | |
594 | jump. */ | |
040f2fb2 | 595 | if (next_tb != 0 && tb->page_addr[1] == -1) { |
0980011b PM |
596 | tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK), |
597 | next_tb & TB_EXIT_MASK, tb); | |
3fb2ded1 | 598 | } |
5e5f07e0 | 599 | spin_unlock(&tcg_ctx.tb_ctx.tb_lock); |
55e8b85e | 600 | |
601 | /* cpu_interrupt might be called while translating the | |
602 | TB, but before it is linked into a potentially | |
603 | infinite loop and becomes env->current_tb. Avoid | |
604 | starting execution if there is a pending interrupt. */ | |
d77953b9 | 605 | cpu->current_tb = tb; |
b0052d15 | 606 | barrier(); |
fcd7d003 | 607 | if (likely(!cpu->exit_request)) { |
2e70f6ef | 608 | tc_ptr = tb->tc_ptr; |
e965fc38 | 609 | /* execute the generated code */ |
77211379 | 610 | next_tb = cpu_tb_exec(cpu, tc_ptr); |
0980011b | 611 | if ((next_tb & TB_EXIT_MASK) == TB_EXIT_ICOUNT_EXPIRED) { |
bf20dc07 | 612 | /* Instruction counter expired. */ |
2e70f6ef | 613 | int insns_left; |
0980011b | 614 | tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); |
2e70f6ef PB |
615 | insns_left = env->icount_decr.u32; |
616 | if (env->icount_extra && insns_left >= 0) { | |
617 | /* Refill decrementer and continue execution. */ | |
618 | env->icount_extra += insns_left; | |
619 | if (env->icount_extra > 0xffff) { | |
620 | insns_left = 0xffff; | |
621 | } else { | |
622 | insns_left = env->icount_extra; | |
623 | } | |
624 | env->icount_extra -= insns_left; | |
625 | env->icount_decr.u16.low = insns_left; | |
626 | } else { | |
627 | if (insns_left > 0) { | |
628 | /* Execute remaining instructions. */ | |
cea5f9a2 | 629 | cpu_exec_nocache(env, insns_left, tb); |
2e70f6ef PB |
630 | } |
631 | env->exception_index = EXCP_INTERRUPT; | |
632 | next_tb = 0; | |
1162c041 | 633 | cpu_loop_exit(env); |
2e70f6ef PB |
634 | } |
635 | } | |
636 | } | |
d77953b9 | 637 | cpu->current_tb = NULL; |
4cbf74b6 FB |
638 | /* reset soft MMU for next block (it can currently |
639 | only be set by a memory fault) */ | |
50a518e3 | 640 | } /* for(;;) */ |
0d101938 JK |
641 | } else { |
642 | /* Reload env after longjmp - the compiler may have smashed all | |
643 | * local variables as longjmp is marked 'noreturn'. */ | |
644 | env = cpu_single_env; | |
7d13299d | 645 | } |
3fb2ded1 FB |
646 | } /* for(;;) */ |
647 | ||
7d13299d | 648 | |
e4533c7a | 649 | #if defined(TARGET_I386) |
9de5e440 | 650 | /* restore flags in standard format */ |
e694d4e2 BS |
651 | env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP) |
652 | | (DF & DF_MASK); | |
e4533c7a | 653 | #elif defined(TARGET_ARM) |
b7bcbe95 | 654 | /* XXX: Save/restore host fpu exception state?. */ |
d2fbca94 | 655 | #elif defined(TARGET_UNICORE32) |
93ac68bc | 656 | #elif defined(TARGET_SPARC) |
67867308 | 657 | #elif defined(TARGET_PPC) |
81ea0e13 | 658 | #elif defined(TARGET_LM32) |
e6e5906b PB |
659 | #elif defined(TARGET_M68K) |
660 | cpu_m68k_flush_flags(env, env->cc_op); | |
661 | env->cc_op = CC_OP_FLAGS; | |
662 | env->sr = (env->sr & 0xffe0) | |
663 | | env->cc_dest | (env->cc_x << 4); | |
b779e29e | 664 | #elif defined(TARGET_MICROBLAZE) |
6af0bf9c | 665 | #elif defined(TARGET_MIPS) |
e67db06e | 666 | #elif defined(TARGET_OPENRISC) |
fdf9b3e8 | 667 | #elif defined(TARGET_SH4) |
eddf68a6 | 668 | #elif defined(TARGET_ALPHA) |
f1ccf904 | 669 | #elif defined(TARGET_CRIS) |
10ec5117 | 670 | #elif defined(TARGET_S390X) |
2328826b | 671 | #elif defined(TARGET_XTENSA) |
fdf9b3e8 | 672 | /* XXXXX */ |
e4533c7a FB |
673 | #else |
674 | #error unsupported target CPU | |
675 | #endif | |
1057eaa7 | 676 | |
6a00d601 | 677 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
5fafdf24 | 678 | cpu_single_env = NULL; |
7d13299d FB |
679 | return ret; |
680 | } |