[qemu.git] / cpu-exec.c

/*
 *  i386 emulator main execution loop
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "config.h"
#include "exec.h"
#include "disas.h"

//#define DEBUG_EXEC
//#define DEBUG_SIGNAL

#if defined(TARGET_ARM) || defined(TARGET_SPARC)
/* XXX: unify with i386 target */
void cpu_loop_exit(void)
{
    longjmp(env->jmp_env, 1);
}
#endif

/* main execution loop */

int cpu_exec(CPUState *env1)
{
    int saved_T0, saved_T1, saved_T2;
    CPUState *saved_env;
#ifdef reg_EAX
    int saved_EAX;
#endif
#ifdef reg_ECX
    int saved_ECX;
#endif
#ifdef reg_EDX
    int saved_EDX;
#endif
#ifdef reg_EBX
    int saved_EBX;
#endif
#ifdef reg_ESP
    int saved_ESP;
#endif
#ifdef reg_EBP
    int saved_EBP;
#endif
#ifdef reg_ESI
    int saved_ESI;
#endif
#ifdef reg_EDI
    int saved_EDI;
#endif
#ifdef __sparc__
    int saved_i7, tmp_T0;
#endif
    int code_gen_size, ret, interrupt_request;
    void (*gen_func)(void);
    TranslationBlock *tb, **ptb;
    uint8_t *tc_ptr, *cs_base, *pc;
    unsigned int flags;

    /* first we save global registers */
    saved_T0 = T0;
    saved_T1 = T1;
    saved_T2 = T2;
    saved_env = env;
    env = env1;
#ifdef __sparc__
    /* we also save i7 because longjmp may not restore it */
    asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
#endif

#if defined(TARGET_I386)
#ifdef reg_EAX
    saved_EAX = EAX;
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    saved_ECX = ECX;
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    saved_EDX = EDX;
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    saved_EBX = EBX;
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    saved_ESP = ESP;
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    saved_EBP = EBP;
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    saved_ESI = ESI;
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    saved_EDI = EDI;
    EDI = env->regs[R_EDI];
#endif
    
    /* put eflags in CPU temporary format */
    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((env->eflags >> 10) & 1));
    CC_OP = CC_OP_EFLAGS;
    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
    {
        unsigned int psr;
        psr = env->cpsr;
        env->CF = (psr >> 29) & 1;
        env->NZF = (psr & 0xc0000000) ^ 0x40000000;
        env->VF = (psr << 3) & 0x80000000;
        env->cpsr = psr & ~0xf0000000;
    }
#elif defined(TARGET_SPARC)
#else
#error unsupported target CPU
#endif
    env->exception_index = -1;

    /* prepare setjmp context for exception handling */
    for(;;) {
        if (setjmp(env->jmp_env) == 0) {
            /* if an exception is pending, we execute it here */
            if (env->exception_index >= 0) {
                if (env->exception_index >= EXCP_INTERRUPT) {
                    /* exit request from the cpu execution loop */
                    ret = env->exception_index;
                    break;
                } else if (env->user_mode_only) {
                    /* if user mode only, we simulate a fake exception
                       which will be hanlded outside the cpu execution
                       loop */
#if defined(TARGET_I386)
                    do_interrupt_user(env->exception_index, 
                                      env->exception_is_int, 
                                      env->error_code, 
                                      env->exception_next_eip);
#endif
                    ret = env->exception_index;
                    break;
                } else {
#if defined(TARGET_I386)
                    /* simulate a real cpu exception. On i386, it can
                       trigger new exceptions, but we do not handle
                       double or triple faults yet. */
                    do_interrupt(env->exception_index, 
                                 env->exception_is_int, 
                                 env->error_code, 
                                 env->exception_next_eip, 0);
#endif
                }
                env->exception_index = -1;
            }
            T0 = 0; /* force lookup of first TB */
            for(;;) {
#ifdef __sparc__
                /* g1 can be modified by some libc? functions */ 
                tmp_T0 = T0;
#endif	    
                interrupt_request = env->interrupt_request;
                if (__builtin_expect(interrupt_request, 0)) {
#if defined(TARGET_I386)
                    /* if hardware interrupt pending, we execute it */
                    if ((interrupt_request & CPU_INTERRUPT_HARD) &&
                        (env->eflags & IF_MASK) && 
                        !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
                        int intno;
                        intno = cpu_x86_get_pic_interrupt(env);
                        if (loglevel) {
                            fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
                        }
                        do_interrupt(intno, 0, 0, 0, 1);
                        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
                        /* ensure that no TB jump will be modified as
                           the program flow was changed */
#ifdef __sparc__
                        tmp_T0 = 0;
#else
                        T0 = 0;
#endif
                    }
#endif
                    if (interrupt_request & CPU_INTERRUPT_EXIT) {
                        env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
                        env->exception_index = EXCP_INTERRUPT;
                        cpu_loop_exit();
                    }
                }
#ifdef DEBUG_EXEC
                if (loglevel) {
#if defined(TARGET_I386)
                    /* restore flags in standard format */
                    env->regs[R_EAX] = EAX;
                    env->regs[R_EBX] = EBX;
                    env->regs[R_ECX] = ECX;
                    env->regs[R_EDX] = EDX;
                    env->regs[R_ESI] = ESI;
                    env->regs[R_EDI] = EDI;
                    env->regs[R_EBP] = EBP;
                    env->regs[R_ESP] = ESP;
                    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
                    cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
                    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
                    env->cpsr = compute_cpsr();
                    cpu_arm_dump_state(env, logfile, 0);
                    env->cpsr &= ~0xf0000000;
#elif defined(TARGET_SPARC)
					cpu_sparc_dump_state (env, logfile, 0);
#else
#error unsupported target CPU 
#endif
                }
#endif
                /* we record a subset of the CPU state. It will
                   always be the same before a given translated block
                   is executed. */
#if defined(TARGET_I386)
                flags = env->hflags;
                flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
                cs_base = env->segs[R_CS].base;
                pc = cs_base + env->eip;
#elif defined(TARGET_ARM)
                flags = 0;
                cs_base = 0;
                pc = (uint8_t *)env->regs[15];
#elif defined(TARGET_SPARC)
				flags = 0;
				cs_base = 0;
				if (env->npc) {
					env->pc = env->npc;
					env->npc = 0;
				}
				pc = (uint8_t *) env->pc;
#else
#error unsupported CPU
#endif
                tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, 
                             flags);
                if (!tb) {
                    spin_lock(&tb_lock);
                    /* if no translated code available, then translate it now */
                    tb = tb_alloc((unsigned long)pc);
                    if (!tb) {
                        /* flush must be done */
                        tb_flush();
                        /* cannot fail at this point */
                        tb = tb_alloc((unsigned long)pc);
                        /* don't forget to invalidate previous TB info */
                        ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
                        T0 = 0;
                    }
                    tc_ptr = code_gen_ptr;
                    tb->tc_ptr = tc_ptr;
                    tb->cs_base = (unsigned long)cs_base;
                    tb->flags = flags;
                    cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
                    *ptb = tb;
                    tb->hash_next = NULL;
                    tb_link(tb);
                    code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
                    spin_unlock(&tb_lock);
                }
#ifdef DEBUG_EXEC
                if (loglevel) {
                    fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
                            (long)tb->tc_ptr, (long)tb->pc,
                            lookup_symbol((void *)tb->pc));
                }
#endif
#ifdef __sparc__
                T0 = tmp_T0;
#endif	    
                /* see if we can patch the calling TB. */
                if (T0 != 0) {
                    spin_lock(&tb_lock);
                    tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
                    spin_unlock(&tb_lock);
                }
                tc_ptr = tb->tc_ptr;
                env->current_tb = tb;
                /* execute the generated code */
                gen_func = (void *)tc_ptr;
#if defined(__sparc__)
                __asm__ __volatile__("call	%0\n\t"
                                     "mov	%%o7,%%i0"
                                     : /* no outputs */
                                     : "r" (gen_func) 
                                     : "i0", "i1", "i2", "i3", "i4", "i5");
#elif defined(__arm__)
                asm volatile ("mov pc, %0\n\t"
                              ".global exec_loop\n\t"
                              "exec_loop:\n\t"
                              : /* no outputs */
                              : "r" (gen_func)
                              : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
#else
                gen_func();
#endif
                env->current_tb = NULL;
                /* reset soft MMU for next block (it can currently
                   only be set by a memory fault) */
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
                if (env->hflags & HF_SOFTMMU_MASK) {
                    env->hflags &= ~HF_SOFTMMU_MASK;
                    /* do not allow linking to another block */
                    T0 = 0;
                }
#endif
            }
        } else {
        }
    } /* for(;;) */


#if defined(TARGET_I386)
    /* restore flags in standard format */
    env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);

    /* restore global registers */
#ifdef reg_EAX
    EAX = saved_EAX;
#endif
#ifdef reg_ECX
    ECX = saved_ECX;
#endif
#ifdef reg_EDX
    EDX = saved_EDX;
#endif
#ifdef reg_EBX
    EBX = saved_EBX;
#endif
#ifdef reg_ESP
    ESP = saved_ESP;
#endif
#ifdef reg_EBP
    EBP = saved_EBP;
#endif
#ifdef reg_ESI
    ESI = saved_ESI;
#endif
#ifdef reg_EDI
    EDI = saved_EDI;
#endif
#elif defined(TARGET_ARM)
    env->cpsr = compute_cpsr();
#elif defined(TARGET_SPARC)
#else
#error unsupported target CPU
#endif
#ifdef __sparc__
    asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
#endif
    T0 = saved_T0;
    T1 = saved_T1;
    T2 = saved_T2;
    env = saved_env;
    return ret;
}

#if defined(TARGET_I386)

void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
        selector &= 0xffff;
        cpu_x86_load_seg_cache(env, seg_reg, selector, 
                               (uint8_t *)(selector << 4), 0xffff, 0);
    } else {
        load_seg(seg_reg, selector, 0);
    }
    env = saved_env;
}

void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_fsave(ptr, data32);

    env = saved_env;
}

void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
{
    CPUX86State *saved_env;

    saved_env = env;
    env = s;
    
    helper_frstor(ptr, data32);

    env = saved_env;
}

#endif /* TARGET_I386 */

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#include <sys/ucontext.h>

#if defined(TARGET_I386)

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    TranslationBlock *tb;
    int ret;

    if (cpu_single_env)
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
#if defined(DEBUG_SIGNAL)
    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 
           pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && page_unprotect(address)) {
        return 1;
    }
    /* see if it is an MMU fault */
    ret = cpu_x86_handle_mmu_fault(env, address, is_write);
    if (ret < 0)
        return 0; /* not an MMU fault */
    if (ret == 0)
        return 1; /* the MMU fault was handled without causing real CPU fault */
    /* now we have a real cpu fault */
    tb = tb_find_pc(pc);
    if (tb) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        cpu_restore_state(tb, env, pc);
    }
    if (ret == 1) {
#if 0
        printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", 
               env->eip, env->cr[2], env->error_code);
#endif
        /* we restore the process signal mask as the sigreturn should
           do it (XXX: use sigsetjmp) */
        sigprocmask(SIG_SETMASK, old_set, NULL);
        raise_exception_err(EXCP0E_PAGE, env->error_code);
    } else {
        /* activate soft MMU for this block */
        env->hflags |= HF_SOFTMMU_MASK;
        sigprocmask(SIG_SETMASK, old_set, NULL);
        cpu_loop_exit();
    }
    /* never comes here */
    return 1;
}

#elif defined(TARGET_ARM)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
    /* XXX: do more */
    return 0;
}
#elif defined(TARGET_SPARC)
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
                                    int is_write, sigset_t *old_set)
{
	return 0;
}
#else
#error unsupported target CPU
#endif

#if defined(__i386__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    
#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = uc->uc_mcontext.gregs[REG_EIP];
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? 
                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
                             &uc->uc_sigmask);
}

#elif defined(__powerpc)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    struct pt_regs *regs = uc->uc_mcontext.regs;
    unsigned long pc;
    int is_write;

    pc = regs->nip;
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (regs->dsisr & 0x00800000)
        is_write = 1;
#else
    if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
        is_write = 1;
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}

#elif defined(__alpha__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc)
{
    struct ucontext *uc = puc;
    uint32_t *pc = uc->uc_mcontext.sc_pc;
    uint32_t insn = *pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster */
    switch (insn >> 26) {
    case 0x0d: // stw
    case 0x0e: // stb
    case 0x0f: // stq_u
    case 0x24: // stf
    case 0x25: // stg
    case 0x26: // sts
    case 0x27: // stt
    case 0x2c: // stl
    case 0x2d: // stq
    case 0x2e: // stl_c
    case 0x2f: // stq_c
	is_write = 1;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, &uc->uc_sigmask);
}
#elif defined(__sparc__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    uint32_t *regs = (uint32_t *)(info + 1);
    void *sigmask = (regs + 20);
    unsigned long pc;
    int is_write;
    uint32_t insn;
    
    /* XXX: is there a standard glibc define ? */
    pc = regs[1];
    /* XXX: need kernel patch to get write flag faster */
    is_write = 0;
    insn = *(uint32_t *)pc;
    if ((insn >> 30) == 3) {
      switch((insn >> 19) & 0x3f) {
      case 0x05: // stb
      case 0x06: // sth
      case 0x04: // st
      case 0x07: // std
      case 0x24: // stf
      case 0x27: // stdf
      case 0x25: // stfsr
	is_write = 1;
	break;
      }
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write, sigmask);
}

#elif defined(__arm__)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;
    
    pc = uc->uc_mcontext.gregs[R15];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write,
                             &uc->uc_sigmask);
}

#elif defined(__mc68000)

int cpu_signal_handler(int host_signum, struct siginfo *info, 
                       void *puc)
{
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;
    
    pc = uc->uc_mcontext.gregs[16];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
                             is_write,
                             &uc->uc_sigmask);
}

#else

#error host CPU specific signal handler needed

#endif
Commit	Line	Data
7d13299d FB	1	/*
	2	* i386 emulator main execution loop
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
3ef693a0 FB	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
7d13299d	10	*
3ef693a0 FB	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
7d13299d	15	*
3ef693a0 FB	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7d13299d	19	*/
e4533c7a	20	#include "config.h"
93ac68bc	21	#include "exec.h"
956034d7	22	#include "disas.h"
7d13299d	23
dc99065b	24	//#define DEBUG_EXEC
9de5e440	25	//#define DEBUG_SIGNAL
7d13299d	26
93ac68bc	27	#if defined(TARGET_ARM) \|\| defined(TARGET_SPARC)
e4533c7a FB	28	/* XXX: unify with i386 target */
	29	void cpu_loop_exit(void)
	30	{
	31	longjmp(env->jmp_env, 1);
	32	}
	33	#endif
	34
7d13299d FB	35	/* main execution loop */
7d13299d FB	36
e4533c7a	37	int cpu_exec(CPUState *env1)
7d13299d	38	{
e4533c7a FB	39	int saved_T0, saved_T1, saved_T2;
e4533c7a FB	40	CPUState *saved_env;
04369ff2 FB	41	#ifdef reg_EAX
	42	int saved_EAX;
	43	#endif
	44	#ifdef reg_ECX
	45	int saved_ECX;
	46	#endif
	47	#ifdef reg_EDX
	48	int saved_EDX;
	49	#endif
	50	#ifdef reg_EBX
	51	int saved_EBX;
	52	#endif
	53	#ifdef reg_ESP
	54	int saved_ESP;
	55	#endif
	56	#ifdef reg_EBP
	57	int saved_EBP;
	58	#endif
	59	#ifdef reg_ESI
	60	int saved_ESI;
	61	#endif
	62	#ifdef reg_EDI
	63	int saved_EDI;
8c6939c0 FB	64	#endif
	65	#ifdef __sparc__
	66	int saved_i7, tmp_T0;
04369ff2	67	#endif
68a79315	68	int code_gen_size, ret, interrupt_request;
7d13299d	69	void (*gen_func)(void);
9de5e440	70	TranslationBlock tb, *ptb;
dab2ed99	71	uint8_t tc_ptr, cs_base, *pc;
6dbad63e	72	unsigned int flags;
8c6939c0	73
7d13299d FB	74	/* first we save global registers */
	75	saved_T0 = T0;
	76	saved_T1 = T1;
e4533c7a	77	saved_T2 = T2;
7d13299d FB	78	saved_env = env;
7d13299d FB	79	env = env1;
e4533c7a FB	80	#ifdef __sparc__
	81	/* we also save i7 because longjmp may not restore it */
	82	asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
	83	#endif
	84
	85	#if defined(TARGET_I386)
04369ff2 FB	86	#ifdef reg_EAX
	87	saved_EAX = EAX;
	88	EAX = env->regs[R_EAX];
	89	#endif
	90	#ifdef reg_ECX
	91	saved_ECX = ECX;
	92	ECX = env->regs[R_ECX];
	93	#endif
	94	#ifdef reg_EDX
	95	saved_EDX = EDX;
	96	EDX = env->regs[R_EDX];
	97	#endif
	98	#ifdef reg_EBX
	99	saved_EBX = EBX;
	100	EBX = env->regs[R_EBX];
	101	#endif
	102	#ifdef reg_ESP
	103	saved_ESP = ESP;
	104	ESP = env->regs[R_ESP];
	105	#endif
	106	#ifdef reg_EBP
	107	saved_EBP = EBP;
	108	EBP = env->regs[R_EBP];
	109	#endif
	110	#ifdef reg_ESI
	111	saved_ESI = ESI;
	112	ESI = env->regs[R_ESI];
	113	#endif
	114	#ifdef reg_EDI
	115	saved_EDI = EDI;
	116	EDI = env->regs[R_EDI];
	117	#endif
7d13299d	118
9de5e440	119	/* put eflags in CPU temporary format */
fc2b4c48 FB	120	CC_SRC = env->eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
fc2b4c48 FB	121	DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440	122	CC_OP = CC_OP_EFLAGS;
fc2b4c48	123	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a FB	124	#elif defined(TARGET_ARM)
	125	{
	126	unsigned int psr;
	127	psr = env->cpsr;
	128	env->CF = (psr >> 29) & 1;
	129	env->NZF = (psr & 0xc0000000) ^ 0x40000000;
	130	env->VF = (psr << 3) & 0x80000000;
	131	env->cpsr = psr & ~0xf0000000;
	132	}
93ac68bc	133	#elif defined(TARGET_SPARC)
e4533c7a FB	134	#else
	135	#error unsupported target CPU
	136	#endif
3fb2ded1	137	env->exception_index = -1;
9d27abd9	138
7d13299d	139	/* prepare setjmp context for exception handling */
3fb2ded1 FB	140	for(;;) {
	141	if (setjmp(env->jmp_env) == 0) {
	142	/* if an exception is pending, we execute it here */
	143	if (env->exception_index >= 0) {
	144	if (env->exception_index >= EXCP_INTERRUPT) {
	145	/* exit request from the cpu execution loop */
	146	ret = env->exception_index;
	147	break;
	148	} else if (env->user_mode_only) {
	149	/* if user mode only, we simulate a fake exception
	150	which will be hanlded outside the cpu execution
	151	loop */
83479e77	152	#if defined(TARGET_I386)
3fb2ded1 FB	153	do_interrupt_user(env->exception_index,
	154	env->exception_is_int,
	155	env->error_code,
	156	env->exception_next_eip);
83479e77	157	#endif
3fb2ded1 FB	158	ret = env->exception_index;
	159	break;
	160	} else {
83479e77	161	#if defined(TARGET_I386)
3fb2ded1 FB	162	/* simulate a real cpu exception. On i386, it can
	163	trigger new exceptions, but we do not handle
	164	double or triple faults yet. */
	165	do_interrupt(env->exception_index,
	166	env->exception_is_int,
	167	env->error_code,
d05e66d2	168	env->exception_next_eip, 0);
83479e77	169	#endif
3fb2ded1 FB	170	}
	171	env->exception_index = -1;
	172	}
3fb2ded1 FB	173	T0 = 0; /* force lookup of first TB */
3fb2ded1 FB	174	for(;;) {
8c6939c0	175	#ifdef __sparc__
3fb2ded1 FB	176	/* g1 can be modified by some libc? functions */
3fb2ded1 FB	177	tmp_T0 = T0;
8c6939c0	178	#endif
68a79315	179	interrupt_request = env->interrupt_request;
2e255c6b	180	if (__builtin_expect(interrupt_request, 0)) {
68a79315 FB	181	#if defined(TARGET_I386)
	182	/* if hardware interrupt pending, we execute it */
	183	if ((interrupt_request & CPU_INTERRUPT_HARD) &&
3f337316 FB	184	(env->eflags & IF_MASK) &&
3f337316 FB	185	!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
68a79315 FB	186	int intno;
	187	intno = cpu_x86_get_pic_interrupt(env);
	188	if (loglevel) {
	189	fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
	190	}
d05e66d2	191	do_interrupt(intno, 0, 0, 0, 1);
68a79315	192	env->interrupt_request &= ~CPU_INTERRUPT_HARD;
907a5b26 FB	193	/* ensure that no TB jump will be modified as
	194	the program flow was changed */
	195	#ifdef __sparc__
	196	tmp_T0 = 0;
	197	#else
	198	T0 = 0;
	199	#endif
68a79315 FB	200	}
	201	#endif
	202	if (interrupt_request & CPU_INTERRUPT_EXIT) {
	203	env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
	204	env->exception_index = EXCP_INTERRUPT;
	205	cpu_loop_exit();
	206	}
3fb2ded1	207	}
7d13299d	208	#ifdef DEBUG_EXEC
3fb2ded1	209	if (loglevel) {
e4533c7a	210	#if defined(TARGET_I386)
3fb2ded1 FB	211	/* restore flags in standard format */
	212	env->regs[R_EAX] = EAX;
	213	env->regs[R_EBX] = EBX;
	214	env->regs[R_ECX] = ECX;
	215	env->regs[R_EDX] = EDX;
	216	env->regs[R_ESI] = ESI;
	217	env->regs[R_EDI] = EDI;
	218	env->regs[R_EBP] = EBP;
	219	env->regs[R_ESP] = ESP;
	220	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
68a79315	221	cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
3fb2ded1	222	env->eflags &= ~(DF_MASK \| CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
e4533c7a	223	#elif defined(TARGET_ARM)
1b21b62a	224	env->cpsr = compute_cpsr();
3fb2ded1	225	cpu_arm_dump_state(env, logfile, 0);
1b21b62a	226	env->cpsr &= ~0xf0000000;
93ac68bc FB	227	#elif defined(TARGET_SPARC)
93ac68bc FB	228	cpu_sparc_dump_state (env, logfile, 0);
e4533c7a FB	229	#else
	230	#error unsupported target CPU
	231	#endif
3fb2ded1	232	}
7d13299d	233	#endif
3f337316 FB	234	/* we record a subset of the CPU state. It will
	235	always be the same before a given translated block
	236	is executed. */
e4533c7a	237	#if defined(TARGET_I386)
2e255c6b	238	flags = env->hflags;
3f337316	239	flags \|= (env->eflags & (IOPL_MASK \| TF_MASK \| VM_MASK));
3fb2ded1 FB	240	cs_base = env->segs[R_CS].base;
3fb2ded1 FB	241	pc = cs_base + env->eip;
e4533c7a	242	#elif defined(TARGET_ARM)
3fb2ded1 FB	243	flags = 0;
	244	cs_base = 0;
	245	pc = (uint8_t *)env->regs[15];
93ac68bc FB	246	#elif defined(TARGET_SPARC)
	247	flags = 0;
	248	cs_base = 0;
	249	if (env->npc) {
	250	env->pc = env->npc;
	251	env->npc = 0;
	252	}
	253	pc = (uint8_t *) env->pc;
e4533c7a FB	254	#else
	255	#error unsupported CPU
	256	#endif
3fb2ded1 FB	257	tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
3fb2ded1 FB	258	flags);
d4e8164f	259	if (!tb) {
3fb2ded1 FB	260	spin_lock(&tb_lock);
3fb2ded1 FB	261	/* if no translated code available, then translate it now */
d4e8164f	262	tb = tb_alloc((unsigned long)pc);
3fb2ded1 FB	263	if (!tb) {
	264	/* flush must be done */
	265	tb_flush();
	266	/* cannot fail at this point */
	267	tb = tb_alloc((unsigned long)pc);
	268	/* don't forget to invalidate previous TB info */
	269	ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
	270	T0 = 0;
	271	}
	272	tc_ptr = code_gen_ptr;
	273	tb->tc_ptr = tc_ptr;
	274	tb->cs_base = (unsigned long)cs_base;
	275	tb->flags = flags;
facc68be	276	cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
3fb2ded1 FB	277	*ptb = tb;
	278	tb->hash_next = NULL;
	279	tb_link(tb);
	280	code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
25eb4484	281	spin_unlock(&tb_lock);
9de5e440	282	}
9d27abd9	283	#ifdef DEBUG_EXEC
3fb2ded1 FB	284	if (loglevel) {
	285	fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
	286	(long)tb->tc_ptr, (long)tb->pc,
	287	lookup_symbol((void *)tb->pc));
	288	}
9d27abd9	289	#endif
8c6939c0	290	#ifdef __sparc__
3fb2ded1	291	T0 = tmp_T0;
8c6939c0	292	#endif
facc68be FB	293	/* see if we can patch the calling TB. */
facc68be FB	294	if (T0 != 0) {
3fb2ded1 FB	295	spin_lock(&tb_lock);
	296	tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
	297	spin_unlock(&tb_lock);
	298	}
3fb2ded1	299	tc_ptr = tb->tc_ptr;
83479e77	300	env->current_tb = tb;
3fb2ded1 FB	301	/* execute the generated code */
3fb2ded1 FB	302	gen_func = (void *)tc_ptr;
8c6939c0	303	#if defined(__sparc__)
3fb2ded1 FB	304	__asm__ __volatile__("call %0\n\t"
	305	"mov %%o7,%%i0"
	306	: /* no outputs */
	307	: "r" (gen_func)
	308	: "i0", "i1", "i2", "i3", "i4", "i5");
8c6939c0	309	#elif defined(__arm__)
3fb2ded1 FB	310	asm volatile ("mov pc, %0\n\t"
	311	".global exec_loop\n\t"
	312	"exec_loop:\n\t"
	313	: /* no outputs */
	314	: "r" (gen_func)
	315	: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
ae228531	316	#else
3fb2ded1	317	gen_func();
ae228531	318	#endif
83479e77	319	env->current_tb = NULL;
4cbf74b6 FB	320	/* reset soft MMU for next block (it can currently
	321	only be set by a memory fault) */
	322	#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
3f337316 FB	323	if (env->hflags & HF_SOFTMMU_MASK) {
3f337316 FB	324	env->hflags &= ~HF_SOFTMMU_MASK;
4cbf74b6 FB	325	/* do not allow linking to another block */
	326	T0 = 0;
	327	}
	328	#endif
3fb2ded1 FB	329	}
3fb2ded1 FB	330	} else {
7d13299d	331	}
3fb2ded1 FB	332	} /* for(;;) */
3fb2ded1 FB	333
7d13299d	334
e4533c7a	335	#if defined(TARGET_I386)
9de5e440	336	/* restore flags in standard format */
fc2b4c48	337	env->eflags = env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
9de5e440	338
7d13299d	339	/* restore global registers */
04369ff2 FB	340	#ifdef reg_EAX
	341	EAX = saved_EAX;
	342	#endif
	343	#ifdef reg_ECX
	344	ECX = saved_ECX;
	345	#endif
	346	#ifdef reg_EDX
	347	EDX = saved_EDX;
	348	#endif
	349	#ifdef reg_EBX
	350	EBX = saved_EBX;
	351	#endif
	352	#ifdef reg_ESP
	353	ESP = saved_ESP;
	354	#endif
	355	#ifdef reg_EBP
	356	EBP = saved_EBP;
	357	#endif
	358	#ifdef reg_ESI
	359	ESI = saved_ESI;
	360	#endif
	361	#ifdef reg_EDI
	362	EDI = saved_EDI;
8c6939c0	363	#endif
e4533c7a	364	#elif defined(TARGET_ARM)
1b21b62a	365	env->cpsr = compute_cpsr();
93ac68bc	366	#elif defined(TARGET_SPARC)
e4533c7a FB	367	#else
	368	#error unsupported target CPU
	369	#endif
8c6939c0 FB	370	#ifdef __sparc__
8c6939c0 FB	371	asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
04369ff2	372	#endif
7d13299d FB	373	T0 = saved_T0;
7d13299d FB	374	T1 = saved_T1;
e4533c7a	375	T2 = saved_T2;
7d13299d FB	376	env = saved_env;
	377	return ret;
	378	}
6dbad63e	379
e4533c7a FB	380	#if defined(TARGET_I386)
e4533c7a FB	381
6dbad63e FB	382	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
	383	{
	384	CPUX86State *saved_env;
	385
	386	saved_env = env;
	387	env = s;
a412ac57	388	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
a513fe19	389	selector &= 0xffff;
2e255c6b FB	390	cpu_x86_load_seg_cache(env, seg_reg, selector,
2e255c6b FB	391	(uint8_t *)(selector << 4), 0xffff, 0);
a513fe19 FB	392	} else {
	393	load_seg(seg_reg, selector, 0);
	394	}
6dbad63e FB	395	env = saved_env;
6dbad63e FB	396	}
9de5e440	397
d0a1ffc9 FB	398	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32)
	399	{
	400	CPUX86State *saved_env;
	401
	402	saved_env = env;
	403	env = s;
	404
	405	helper_fsave(ptr, data32);
	406
	407	env = saved_env;
	408	}
	409
	410	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32)
	411	{
	412	CPUX86State *saved_env;
	413
	414	saved_env = env;
	415	env = s;
	416
	417	helper_frstor(ptr, data32);
	418
	419	env = saved_env;
	420	}
	421
e4533c7a FB	422	#endif /* TARGET_I386 */
e4533c7a FB	423
9de5e440 FB	424	#undef EAX
	425	#undef ECX
	426	#undef EDX
	427	#undef EBX
	428	#undef ESP
	429	#undef EBP
	430	#undef ESI
	431	#undef EDI
	432	#undef EIP
	433	#include <signal.h>
	434	#include <sys/ucontext.h>
	435
3fb2ded1 FB	436	#if defined(TARGET_I386)
3fb2ded1 FB	437
b56dad1c	438	/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6 FB	439	the effective address of the memory exception. 'is_write' is 1 if a
	440	write caused the exception and otherwise 0'. 'old_set' is the
	441	signal set which should be restored */
2b413144 FB	442	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
2b413144 FB	443	int is_write, sigset_t *old_set)
9de5e440	444	{
a513fe19 FB	445	TranslationBlock *tb;
a513fe19 FB	446	int ret;
68a79315	447
83479e77 FB	448	if (cpu_single_env)
83479e77 FB	449	env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6	450	#if defined(DEBUG_SIGNAL)
3fb2ded1	451	printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
fd6ce8f6	452	pc, address, is_write, (unsigned long )old_set);
9de5e440	453	#endif
25eb4484	454	/* XXX: locking issue */
fd6ce8f6	455	if (is_write && page_unprotect(address)) {
fd6ce8f6 FB	456	return 1;
fd6ce8f6 FB	457	}
3fb2ded1 FB	458	/* see if it is an MMU fault */
	459	ret = cpu_x86_handle_mmu_fault(env, address, is_write);
	460	if (ret < 0)
	461	return 0; /* not an MMU fault */
	462	if (ret == 0)
	463	return 1; /* the MMU fault was handled without causing real CPU fault */
	464	/* now we have a real cpu fault */
a513fe19 FB	465	tb = tb_find_pc(pc);
a513fe19 FB	466	if (tb) {
9de5e440 FB	467	/* the PC is inside the translated code. It means that we have
9de5e440 FB	468	a virtual CPU fault */
3fb2ded1 FB	469	cpu_restore_state(tb, env, pc);
3fb2ded1 FB	470	}
4cbf74b6	471	if (ret == 1) {
3fb2ded1	472	#if 0
4cbf74b6 FB	473	printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
4cbf74b6 FB	474	env->eip, env->cr[2], env->error_code);
3fb2ded1	475	#endif
4cbf74b6 FB	476	/* we restore the process signal mask as the sigreturn should
	477	do it (XXX: use sigsetjmp) */
	478	sigprocmask(SIG_SETMASK, old_set, NULL);
	479	raise_exception_err(EXCP0E_PAGE, env->error_code);
	480	} else {
	481	/* activate soft MMU for this block */
3f337316	482	env->hflags \|= HF_SOFTMMU_MASK;
4cbf74b6 FB	483	sigprocmask(SIG_SETMASK, old_set, NULL);
	484	cpu_loop_exit();
	485	}
3fb2ded1 FB	486	/* never comes here */
	487	return 1;
	488	}
	489
e4533c7a	490	#elif defined(TARGET_ARM)
3fb2ded1 FB	491	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
	492	int is_write, sigset_t *old_set)
	493	{
	494	/* XXX: do more */
	495	return 0;
	496	}
93ac68bc FB	497	#elif defined(TARGET_SPARC)
	498	static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
	499	int is_write, sigset_t *old_set)
	500	{
	501	return 0;
	502	}
e4533c7a FB	503	#else
	504	#error unsupported target CPU
	505	#endif
9de5e440	506
2b413144 FB	507	#if defined(__i386__)
2b413144 FB	508
e4533c7a FB	509	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	510	void *puc)
9de5e440	511	{
9de5e440 FB	512	struct ucontext *uc = puc;
9de5e440 FB	513	unsigned long pc;
9de5e440	514
d691f669 FB	515	#ifndef REG_EIP
d691f669 FB	516	/* for glibc 2.1 */
fd6ce8f6 FB	517	#define REG_EIP EIP
	518	#define REG_ERR ERR
	519	#define REG_TRAPNO TRAPNO
d691f669	520	#endif
fc2b4c48	521	pc = uc->uc_mcontext.gregs[REG_EIP];
fd6ce8f6 FB	522	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	523	uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
	524	(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
2b413144 FB	525	&uc->uc_sigmask);
	526	}
	527
25eb4484	528	#elif defined(__powerpc)
2b413144	529
e4533c7a FB	530	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	531	void *puc)
2b413144	532	{
25eb4484 FB	533	struct ucontext *uc = puc;
	534	struct pt_regs *regs = uc->uc_mcontext.regs;
	535	unsigned long pc;
25eb4484 FB	536	int is_write;
	537
	538	pc = regs->nip;
25eb4484 FB	539	is_write = 0;
	540	#if 0
	541	/* ppc 4xx case */
	542	if (regs->dsisr & 0x00800000)
	543	is_write = 1;
	544	#else
	545	if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
	546	is_write = 1;
	547	#endif
	548	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
2b413144 FB	549	is_write, &uc->uc_sigmask);
	550	}
	551
2f87c607 FB	552	#elif defined(__alpha__)
2f87c607 FB	553
e4533c7a	554	int cpu_signal_handler(int host_signum, struct siginfo *info,
2f87c607 FB	555	void *puc)
	556	{
	557	struct ucontext *uc = puc;
	558	uint32_t *pc = uc->uc_mcontext.sc_pc;
	559	uint32_t insn = *pc;
	560	int is_write = 0;
	561
8c6939c0	562	/* XXX: need kernel patch to get write flag faster */
2f87c607 FB	563	switch (insn >> 26) {
	564	case 0x0d: // stw
	565	case 0x0e: // stb
	566	case 0x0f: // stq_u
	567	case 0x24: // stf
	568	case 0x25: // stg
	569	case 0x26: // sts
	570	case 0x27: // stt
	571	case 0x2c: // stl
	572	case 0x2d: // stq
	573	case 0x2e: // stl_c
	574	case 0x2f: // stq_c
	575	is_write = 1;
	576	}
	577
	578	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	579	is_write, &uc->uc_sigmask);
	580	}
8c6939c0 FB	581	#elif defined(__sparc__)
8c6939c0 FB	582
e4533c7a FB	583	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	584	void *puc)
8c6939c0 FB	585	{
	586	uint32_t regs = (uint32_t )(info + 1);
	587	void *sigmask = (regs + 20);
	588	unsigned long pc;
	589	int is_write;
	590	uint32_t insn;
	591
	592	/* XXX: is there a standard glibc define ? */
	593	pc = regs[1];
	594	/* XXX: need kernel patch to get write flag faster */
	595	is_write = 0;
	596	insn = (uint32_t )pc;
	597	if ((insn >> 30) == 3) {
	598	switch((insn >> 19) & 0x3f) {
	599	case 0x05: // stb
	600	case 0x06: // sth
	601	case 0x04: // st
	602	case 0x07: // std
	603	case 0x24: // stf
	604	case 0x27: // stdf
	605	case 0x25: // stfsr
	606	is_write = 1;
	607	break;
	608	}
	609	}
	610	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	611	is_write, sigmask);
	612	}
	613
	614	#elif defined(__arm__)
	615
e4533c7a FB	616	int cpu_signal_handler(int host_signum, struct siginfo *info,
e4533c7a FB	617	void *puc)
8c6939c0 FB	618	{
	619	struct ucontext *uc = puc;
	620	unsigned long pc;
	621	int is_write;
	622
	623	pc = uc->uc_mcontext.gregs[R15];
	624	/* XXX: compute is_write */
	625	is_write = 0;
	626	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	627	is_write,
	628	&uc->uc_sigmask);
	629	}
	630
38e584a0 FB	631	#elif defined(__mc68000)
	632
	633	int cpu_signal_handler(int host_signum, struct siginfo *info,
	634	void *puc)
	635	{
	636	struct ucontext *uc = puc;
	637	unsigned long pc;
	638	int is_write;
	639
	640	pc = uc->uc_mcontext.gregs[16];
	641	/* XXX: compute is_write */
	642	is_write = 0;
	643	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	644	is_write,
	645	&uc->uc_sigmask);
	646	}
	647
9de5e440	648	#else
2b413144	649
3fb2ded1	650	#error host CPU specific signal handler needed
2b413144	651
9de5e440	652	#endif