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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
7d13299d | 5 | * |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d | 19 | */ |
e4533c7a | 20 | #include "config.h" |
93ac68bc | 21 | #include "exec.h" |
956034d7 | 22 | #include "disas.h" |
7d13299d | 23 | |
fbf9eeb3 FB |
24 | #if !defined(CONFIG_SOFTMMU) |
25 | #undef EAX | |
26 | #undef ECX | |
27 | #undef EDX | |
28 | #undef EBX | |
29 | #undef ESP | |
30 | #undef EBP | |
31 | #undef ESI | |
32 | #undef EDI | |
33 | #undef EIP | |
34 | #include <signal.h> | |
35 | #include <sys/ucontext.h> | |
36 | #endif | |
37 | ||
36bdbe54 FB |
38 | int tb_invalidated_flag; |
39 | ||
dc99065b | 40 | //#define DEBUG_EXEC |
9de5e440 | 41 | //#define DEBUG_SIGNAL |
7d13299d | 42 | |
93ac68bc | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) |
e4533c7a FB |
44 | /* XXX: unify with i386 target */ |
45 | void cpu_loop_exit(void) | |
46 | { | |
47 | longjmp(env->jmp_env, 1); | |
48 | } | |
49 | #endif | |
3475187d FB |
50 | #ifndef TARGET_SPARC |
51 | #define reg_T2 | |
52 | #endif | |
e4533c7a | 53 | |
fbf9eeb3 FB |
54 | /* exit the current TB from a signal handler. The host registers are |
55 | restored in a state compatible with the CPU emulator | |
56 | */ | |
57 | void cpu_resume_from_signal(CPUState *env1, void *puc) | |
58 | { | |
59 | #if !defined(CONFIG_SOFTMMU) | |
60 | struct ucontext *uc = puc; | |
61 | #endif | |
62 | ||
63 | env = env1; | |
64 | ||
65 | /* XXX: restore cpu registers saved in host registers */ | |
66 | ||
67 | #if !defined(CONFIG_SOFTMMU) | |
68 | if (puc) { | |
69 | /* XXX: use siglongjmp ? */ | |
70 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
71 | } | |
72 | #endif | |
73 | longjmp(env->jmp_env, 1); | |
74 | } | |
75 | ||
8a40a180 FB |
76 | |
77 | static TranslationBlock *tb_find_slow(target_ulong pc, | |
78 | target_ulong cs_base, | |
79 | unsigned int flags) | |
80 | { | |
81 | TranslationBlock *tb, **ptb1; | |
82 | int code_gen_size; | |
83 | unsigned int h; | |
84 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; | |
85 | uint8_t *tc_ptr; | |
86 | ||
87 | spin_lock(&tb_lock); | |
88 | ||
89 | tb_invalidated_flag = 0; | |
90 | ||
91 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ | |
92 | ||
93 | /* find translated block using physical mappings */ | |
94 | phys_pc = get_phys_addr_code(env, pc); | |
95 | phys_page1 = phys_pc & TARGET_PAGE_MASK; | |
96 | phys_page2 = -1; | |
97 | h = tb_phys_hash_func(phys_pc); | |
98 | ptb1 = &tb_phys_hash[h]; | |
99 | for(;;) { | |
100 | tb = *ptb1; | |
101 | if (!tb) | |
102 | goto not_found; | |
103 | if (tb->pc == pc && | |
104 | tb->page_addr[0] == phys_page1 && | |
105 | tb->cs_base == cs_base && | |
106 | tb->flags == flags) { | |
107 | /* check next page if needed */ | |
108 | if (tb->page_addr[1] != -1) { | |
109 | virt_page2 = (pc & TARGET_PAGE_MASK) + | |
110 | TARGET_PAGE_SIZE; | |
111 | phys_page2 = get_phys_addr_code(env, virt_page2); | |
112 | if (tb->page_addr[1] == phys_page2) | |
113 | goto found; | |
114 | } else { | |
115 | goto found; | |
116 | } | |
117 | } | |
118 | ptb1 = &tb->phys_hash_next; | |
119 | } | |
120 | not_found: | |
121 | /* if no translated code available, then translate it now */ | |
122 | tb = tb_alloc(pc); | |
123 | if (!tb) { | |
124 | /* flush must be done */ | |
125 | tb_flush(env); | |
126 | /* cannot fail at this point */ | |
127 | tb = tb_alloc(pc); | |
128 | /* don't forget to invalidate previous TB info */ | |
15388002 | 129 | tb_invalidated_flag = 1; |
8a40a180 FB |
130 | } |
131 | tc_ptr = code_gen_ptr; | |
132 | tb->tc_ptr = tc_ptr; | |
133 | tb->cs_base = cs_base; | |
134 | tb->flags = flags; | |
135 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); | |
136 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); | |
137 | ||
138 | /* check next page if needed */ | |
139 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
140 | phys_page2 = -1; | |
141 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
142 | phys_page2 = get_phys_addr_code(env, virt_page2); | |
143 | } | |
144 | tb_link_phys(tb, phys_pc, phys_page2); | |
145 | ||
146 | found: | |
8a40a180 FB |
147 | /* we add the TB in the virtual pc hash table */ |
148 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; | |
149 | spin_unlock(&tb_lock); | |
150 | return tb; | |
151 | } | |
152 | ||
153 | static inline TranslationBlock *tb_find_fast(void) | |
154 | { | |
155 | TranslationBlock *tb; | |
156 | target_ulong cs_base, pc; | |
157 | unsigned int flags; | |
158 | ||
159 | /* we record a subset of the CPU state. It will | |
160 | always be the same before a given translated block | |
161 | is executed. */ | |
162 | #if defined(TARGET_I386) | |
163 | flags = env->hflags; | |
164 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); | |
165 | cs_base = env->segs[R_CS].base; | |
166 | pc = cs_base + env->eip; | |
167 | #elif defined(TARGET_ARM) | |
168 | flags = env->thumb | (env->vfp.vec_len << 1) | |
b5ff1b31 FB |
169 | | (env->vfp.vec_stride << 4); |
170 | if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) | |
171 | flags |= (1 << 6); | |
40f137e1 PB |
172 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
173 | flags |= (1 << 7); | |
8a40a180 FB |
174 | cs_base = 0; |
175 | pc = env->regs[15]; | |
176 | #elif defined(TARGET_SPARC) | |
177 | #ifdef TARGET_SPARC64 | |
178 | flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); | |
179 | #else | |
180 | flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1); | |
181 | #endif | |
182 | cs_base = env->npc; | |
183 | pc = env->pc; | |
184 | #elif defined(TARGET_PPC) | |
185 | flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | | |
186 | (msr_se << MSR_SE) | (msr_le << MSR_LE); | |
187 | cs_base = 0; | |
188 | pc = env->nip; | |
189 | #elif defined(TARGET_MIPS) | |
6810e154 | 190 | flags = env->hflags & (MIPS_HFLAGS_TMASK | MIPS_HFLAG_BMASK); |
cc9442b9 | 191 | cs_base = 0; |
8a40a180 FB |
192 | pc = env->PC; |
193 | #else | |
194 | #error unsupported CPU | |
195 | #endif | |
196 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; | |
197 | if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base || | |
198 | tb->flags != flags, 0)) { | |
199 | tb = tb_find_slow(pc, cs_base, flags); | |
15388002 FB |
200 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
201 | doing it in tb_find_slow */ | |
202 | if (tb_invalidated_flag) { | |
203 | /* as some TB could have been invalidated because | |
204 | of memory exceptions while generating the code, we | |
205 | must recompute the hash index here */ | |
206 | T0 = 0; | |
207 | } | |
8a40a180 FB |
208 | } |
209 | return tb; | |
210 | } | |
211 | ||
212 | ||
7d13299d FB |
213 | /* main execution loop */ |
214 | ||
e4533c7a | 215 | int cpu_exec(CPUState *env1) |
7d13299d | 216 | { |
3475187d FB |
217 | int saved_T0, saved_T1; |
218 | #if defined(reg_T2) | |
219 | int saved_T2; | |
220 | #endif | |
e4533c7a | 221 | CPUState *saved_env; |
3475187d | 222 | #if defined(TARGET_I386) |
04369ff2 FB |
223 | #ifdef reg_EAX |
224 | int saved_EAX; | |
225 | #endif | |
226 | #ifdef reg_ECX | |
227 | int saved_ECX; | |
228 | #endif | |
229 | #ifdef reg_EDX | |
230 | int saved_EDX; | |
231 | #endif | |
232 | #ifdef reg_EBX | |
233 | int saved_EBX; | |
234 | #endif | |
235 | #ifdef reg_ESP | |
236 | int saved_ESP; | |
237 | #endif | |
238 | #ifdef reg_EBP | |
239 | int saved_EBP; | |
240 | #endif | |
241 | #ifdef reg_ESI | |
242 | int saved_ESI; | |
243 | #endif | |
244 | #ifdef reg_EDI | |
245 | int saved_EDI; | |
8c6939c0 | 246 | #endif |
3475187d FB |
247 | #elif defined(TARGET_SPARC) |
248 | #if defined(reg_REGWPTR) | |
249 | uint32_t *saved_regwptr; | |
250 | #endif | |
251 | #endif | |
8c6939c0 FB |
252 | #ifdef __sparc__ |
253 | int saved_i7, tmp_T0; | |
04369ff2 | 254 | #endif |
8a40a180 | 255 | int ret, interrupt_request; |
7d13299d | 256 | void (*gen_func)(void); |
8a40a180 | 257 | TranslationBlock *tb; |
c27004ec | 258 | uint8_t *tc_ptr; |
8c6939c0 | 259 | |
5a1e3cfc FB |
260 | #if defined(TARGET_I386) |
261 | /* handle exit of HALTED state */ | |
262 | if (env1->hflags & HF_HALTED_MASK) { | |
263 | /* disable halt condition */ | |
264 | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && | |
265 | (env1->eflags & IF_MASK)) { | |
266 | env1->hflags &= ~HF_HALTED_MASK; | |
267 | } else { | |
268 | return EXCP_HALTED; | |
e80e1cc4 FB |
269 | } |
270 | } | |
271 | #elif defined(TARGET_PPC) | |
50443c98 | 272 | if (env1->halted) { |
e80e1cc4 FB |
273 | if (env1->msr[MSR_EE] && |
274 | (env1->interrupt_request & | |
275 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) { | |
50443c98 | 276 | env1->halted = 0; |
e80e1cc4 FB |
277 | } else { |
278 | return EXCP_HALTED; | |
5a1e3cfc FB |
279 | } |
280 | } | |
ba3c64fb FB |
281 | #elif defined(TARGET_SPARC) |
282 | if (env1->halted) { | |
283 | if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && | |
284 | (env1->psret != 0)) { | |
285 | env1->halted = 0; | |
286 | } else { | |
287 | return EXCP_HALTED; | |
288 | } | |
289 | } | |
9332f9da FB |
290 | #elif defined(TARGET_ARM) |
291 | if (env1->halted) { | |
292 | /* An interrupt wakes the CPU even if the I and F CPSR bits are | |
293 | set. */ | |
294 | if (env1->interrupt_request | |
295 | & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) { | |
296 | env1->halted = 0; | |
297 | } else { | |
298 | return EXCP_HALTED; | |
299 | } | |
300 | } | |
6810e154 FB |
301 | #elif defined(TARGET_MIPS) |
302 | if (env1->halted) { | |
303 | if (env1->interrupt_request & | |
304 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { | |
305 | env1->halted = 0; | |
306 | } else { | |
307 | return EXCP_HALTED; | |
308 | } | |
309 | } | |
5a1e3cfc FB |
310 | #endif |
311 | ||
6a00d601 FB |
312 | cpu_single_env = env1; |
313 | ||
7d13299d | 314 | /* first we save global registers */ |
c27004ec FB |
315 | saved_env = env; |
316 | env = env1; | |
7d13299d FB |
317 | saved_T0 = T0; |
318 | saved_T1 = T1; | |
3475187d | 319 | #if defined(reg_T2) |
e4533c7a | 320 | saved_T2 = T2; |
3475187d | 321 | #endif |
e4533c7a FB |
322 | #ifdef __sparc__ |
323 | /* we also save i7 because longjmp may not restore it */ | |
324 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); | |
325 | #endif | |
326 | ||
327 | #if defined(TARGET_I386) | |
04369ff2 FB |
328 | #ifdef reg_EAX |
329 | saved_EAX = EAX; | |
04369ff2 FB |
330 | #endif |
331 | #ifdef reg_ECX | |
332 | saved_ECX = ECX; | |
04369ff2 FB |
333 | #endif |
334 | #ifdef reg_EDX | |
335 | saved_EDX = EDX; | |
04369ff2 FB |
336 | #endif |
337 | #ifdef reg_EBX | |
338 | saved_EBX = EBX; | |
04369ff2 FB |
339 | #endif |
340 | #ifdef reg_ESP | |
341 | saved_ESP = ESP; | |
04369ff2 FB |
342 | #endif |
343 | #ifdef reg_EBP | |
344 | saved_EBP = EBP; | |
04369ff2 FB |
345 | #endif |
346 | #ifdef reg_ESI | |
347 | saved_ESI = ESI; | |
04369ff2 FB |
348 | #endif |
349 | #ifdef reg_EDI | |
350 | saved_EDI = EDI; | |
04369ff2 | 351 | #endif |
0d1a29f9 FB |
352 | |
353 | env_to_regs(); | |
9de5e440 | 354 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
355 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
356 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 357 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 358 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 359 | #elif defined(TARGET_ARM) |
93ac68bc | 360 | #elif defined(TARGET_SPARC) |
3475187d FB |
361 | #if defined(reg_REGWPTR) |
362 | saved_regwptr = REGWPTR; | |
363 | #endif | |
67867308 | 364 | #elif defined(TARGET_PPC) |
6af0bf9c | 365 | #elif defined(TARGET_MIPS) |
e4533c7a FB |
366 | #else |
367 | #error unsupported target CPU | |
368 | #endif | |
3fb2ded1 | 369 | env->exception_index = -1; |
9d27abd9 | 370 | |
7d13299d | 371 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
372 | for(;;) { |
373 | if (setjmp(env->jmp_env) == 0) { | |
ee8b7021 | 374 | env->current_tb = NULL; |
3fb2ded1 FB |
375 | /* if an exception is pending, we execute it here */ |
376 | if (env->exception_index >= 0) { | |
377 | if (env->exception_index >= EXCP_INTERRUPT) { | |
378 | /* exit request from the cpu execution loop */ | |
379 | ret = env->exception_index; | |
380 | break; | |
381 | } else if (env->user_mode_only) { | |
382 | /* if user mode only, we simulate a fake exception | |
383 | which will be hanlded outside the cpu execution | |
384 | loop */ | |
83479e77 | 385 | #if defined(TARGET_I386) |
3fb2ded1 FB |
386 | do_interrupt_user(env->exception_index, |
387 | env->exception_is_int, | |
388 | env->error_code, | |
389 | env->exception_next_eip); | |
83479e77 | 390 | #endif |
3fb2ded1 FB |
391 | ret = env->exception_index; |
392 | break; | |
393 | } else { | |
83479e77 | 394 | #if defined(TARGET_I386) |
3fb2ded1 FB |
395 | /* simulate a real cpu exception. On i386, it can |
396 | trigger new exceptions, but we do not handle | |
397 | double or triple faults yet. */ | |
398 | do_interrupt(env->exception_index, | |
399 | env->exception_is_int, | |
400 | env->error_code, | |
d05e66d2 | 401 | env->exception_next_eip, 0); |
ce09776b FB |
402 | #elif defined(TARGET_PPC) |
403 | do_interrupt(env); | |
6af0bf9c FB |
404 | #elif defined(TARGET_MIPS) |
405 | do_interrupt(env); | |
e95c8d51 | 406 | #elif defined(TARGET_SPARC) |
1a0c3292 | 407 | do_interrupt(env->exception_index); |
b5ff1b31 FB |
408 | #elif defined(TARGET_ARM) |
409 | do_interrupt(env); | |
83479e77 | 410 | #endif |
3fb2ded1 FB |
411 | } |
412 | env->exception_index = -1; | |
9df217a3 FB |
413 | } |
414 | #ifdef USE_KQEMU | |
415 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { | |
416 | int ret; | |
417 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
418 | ret = kqemu_cpu_exec(env); | |
419 | /* put eflags in CPU temporary format */ | |
420 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
421 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
422 | CC_OP = CC_OP_EFLAGS; | |
423 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
424 | if (ret == 1) { | |
425 | /* exception */ | |
426 | longjmp(env->jmp_env, 1); | |
427 | } else if (ret == 2) { | |
428 | /* softmmu execution needed */ | |
429 | } else { | |
430 | if (env->interrupt_request != 0) { | |
431 | /* hardware interrupt will be executed just after */ | |
432 | } else { | |
433 | /* otherwise, we restart */ | |
434 | longjmp(env->jmp_env, 1); | |
435 | } | |
436 | } | |
3fb2ded1 | 437 | } |
9df217a3 FB |
438 | #endif |
439 | ||
3fb2ded1 FB |
440 | T0 = 0; /* force lookup of first TB */ |
441 | for(;;) { | |
8c6939c0 | 442 | #ifdef __sparc__ |
3fb2ded1 FB |
443 | /* g1 can be modified by some libc? functions */ |
444 | tmp_T0 = T0; | |
8c6939c0 | 445 | #endif |
68a79315 | 446 | interrupt_request = env->interrupt_request; |
2e255c6b | 447 | if (__builtin_expect(interrupt_request, 0)) { |
68a79315 FB |
448 | #if defined(TARGET_I386) |
449 | /* if hardware interrupt pending, we execute it */ | |
450 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
3f337316 FB |
451 | (env->eflags & IF_MASK) && |
452 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
68a79315 | 453 | int intno; |
fbf9eeb3 | 454 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
a541f297 | 455 | intno = cpu_get_pic_interrupt(env); |
f193c797 | 456 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
68a79315 FB |
457 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
458 | } | |
d05e66d2 | 459 | do_interrupt(intno, 0, 0, 0, 1); |
907a5b26 FB |
460 | /* ensure that no TB jump will be modified as |
461 | the program flow was changed */ | |
462 | #ifdef __sparc__ | |
463 | tmp_T0 = 0; | |
464 | #else | |
465 | T0 = 0; | |
466 | #endif | |
68a79315 | 467 | } |
ce09776b | 468 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
469 | #if 0 |
470 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
471 | cpu_ppc_reset(env); | |
472 | } | |
473 | #endif | |
474 | if (msr_ee != 0) { | |
8a40a180 | 475 | if ((interrupt_request & CPU_INTERRUPT_HARD)) { |
9fddaa0c FB |
476 | /* Raise it */ |
477 | env->exception_index = EXCP_EXTERNAL; | |
478 | env->error_code = 0; | |
ce09776b | 479 | do_interrupt(env); |
8a40a180 FB |
480 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
481 | #ifdef __sparc__ | |
482 | tmp_T0 = 0; | |
483 | #else | |
484 | T0 = 0; | |
485 | #endif | |
486 | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { | |
487 | /* Raise it */ | |
488 | env->exception_index = EXCP_DECR; | |
489 | env->error_code = 0; | |
490 | do_interrupt(env); | |
9fddaa0c | 491 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
8a40a180 FB |
492 | #ifdef __sparc__ |
493 | tmp_T0 = 0; | |
494 | #else | |
495 | T0 = 0; | |
496 | #endif | |
497 | } | |
ce09776b | 498 | } |
6af0bf9c FB |
499 | #elif defined(TARGET_MIPS) |
500 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
501 | (env->CP0_Status & (1 << CP0St_IE)) && | |
7ebab699 | 502 | (env->CP0_Status & env->CP0_Cause & 0x0000FF00) && |
6af0bf9c FB |
503 | !(env->hflags & MIPS_HFLAG_EXL) && |
504 | !(env->hflags & MIPS_HFLAG_ERL) && | |
505 | !(env->hflags & MIPS_HFLAG_DM)) { | |
506 | /* Raise it */ | |
507 | env->exception_index = EXCP_EXT_INTERRUPT; | |
508 | env->error_code = 0; | |
509 | do_interrupt(env); | |
510 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
8a40a180 FB |
511 | #ifdef __sparc__ |
512 | tmp_T0 = 0; | |
513 | #else | |
514 | T0 = 0; | |
515 | #endif | |
6af0bf9c | 516 | } |
e95c8d51 | 517 | #elif defined(TARGET_SPARC) |
66321a11 FB |
518 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
519 | (env->psret != 0)) { | |
520 | int pil = env->interrupt_index & 15; | |
521 | int type = env->interrupt_index & 0xf0; | |
522 | ||
523 | if (((type == TT_EXTINT) && | |
524 | (pil == 15 || pil > env->psrpil)) || | |
525 | type != TT_EXTINT) { | |
526 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
527 | do_interrupt(env->interrupt_index); | |
528 | env->interrupt_index = 0; | |
8a40a180 FB |
529 | #ifdef __sparc__ |
530 | tmp_T0 = 0; | |
531 | #else | |
532 | T0 = 0; | |
533 | #endif | |
66321a11 | 534 | } |
e95c8d51 FB |
535 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
536 | //do_interrupt(0, 0, 0, 0, 0); | |
537 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
ba3c64fb FB |
538 | } else if (interrupt_request & CPU_INTERRUPT_HALT) { |
539 | env1->halted = 1; | |
540 | return EXCP_HALTED; | |
541 | } | |
b5ff1b31 FB |
542 | #elif defined(TARGET_ARM) |
543 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
544 | && !(env->uncached_cpsr & CPSR_F)) { | |
545 | env->exception_index = EXCP_FIQ; | |
546 | do_interrupt(env); | |
547 | } | |
548 | if (interrupt_request & CPU_INTERRUPT_HARD | |
549 | && !(env->uncached_cpsr & CPSR_I)) { | |
550 | env->exception_index = EXCP_IRQ; | |
551 | do_interrupt(env); | |
552 | } | |
68a79315 | 553 | #endif |
b5ff1b31 | 554 | if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
bf3e8bf1 FB |
555 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
556 | /* ensure that no TB jump will be modified as | |
557 | the program flow was changed */ | |
558 | #ifdef __sparc__ | |
559 | tmp_T0 = 0; | |
560 | #else | |
561 | T0 = 0; | |
562 | #endif | |
563 | } | |
68a79315 FB |
564 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
565 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; | |
566 | env->exception_index = EXCP_INTERRUPT; | |
567 | cpu_loop_exit(); | |
568 | } | |
3fb2ded1 | 569 | } |
7d13299d | 570 | #ifdef DEBUG_EXEC |
b5ff1b31 | 571 | if ((loglevel & CPU_LOG_TB_CPU)) { |
e4533c7a | 572 | #if defined(TARGET_I386) |
3fb2ded1 | 573 | /* restore flags in standard format */ |
fc9f715d | 574 | #ifdef reg_EAX |
3fb2ded1 | 575 | env->regs[R_EAX] = EAX; |
fc9f715d FB |
576 | #endif |
577 | #ifdef reg_EBX | |
3fb2ded1 | 578 | env->regs[R_EBX] = EBX; |
fc9f715d FB |
579 | #endif |
580 | #ifdef reg_ECX | |
3fb2ded1 | 581 | env->regs[R_ECX] = ECX; |
fc9f715d FB |
582 | #endif |
583 | #ifdef reg_EDX | |
3fb2ded1 | 584 | env->regs[R_EDX] = EDX; |
fc9f715d FB |
585 | #endif |
586 | #ifdef reg_ESI | |
3fb2ded1 | 587 | env->regs[R_ESI] = ESI; |
fc9f715d FB |
588 | #endif |
589 | #ifdef reg_EDI | |
3fb2ded1 | 590 | env->regs[R_EDI] = EDI; |
fc9f715d FB |
591 | #endif |
592 | #ifdef reg_EBP | |
3fb2ded1 | 593 | env->regs[R_EBP] = EBP; |
fc9f715d FB |
594 | #endif |
595 | #ifdef reg_ESP | |
3fb2ded1 | 596 | env->regs[R_ESP] = ESP; |
fc9f715d | 597 | #endif |
3fb2ded1 | 598 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
7fe48483 | 599 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
3fb2ded1 | 600 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 601 | #elif defined(TARGET_ARM) |
7fe48483 | 602 | cpu_dump_state(env, logfile, fprintf, 0); |
93ac68bc | 603 | #elif defined(TARGET_SPARC) |
3475187d FB |
604 | REGWPTR = env->regbase + (env->cwp * 16); |
605 | env->regwptr = REGWPTR; | |
606 | cpu_dump_state(env, logfile, fprintf, 0); | |
67867308 | 607 | #elif defined(TARGET_PPC) |
7fe48483 | 608 | cpu_dump_state(env, logfile, fprintf, 0); |
6af0bf9c FB |
609 | #elif defined(TARGET_MIPS) |
610 | cpu_dump_state(env, logfile, fprintf, 0); | |
e4533c7a FB |
611 | #else |
612 | #error unsupported target CPU | |
613 | #endif | |
3fb2ded1 | 614 | } |
7d13299d | 615 | #endif |
8a40a180 | 616 | tb = tb_find_fast(); |
9d27abd9 | 617 | #ifdef DEBUG_EXEC |
c1135f61 | 618 | if ((loglevel & CPU_LOG_EXEC)) { |
c27004ec FB |
619 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
620 | (long)tb->tc_ptr, tb->pc, | |
621 | lookup_symbol(tb->pc)); | |
3fb2ded1 | 622 | } |
9d27abd9 | 623 | #endif |
8c6939c0 | 624 | #ifdef __sparc__ |
3fb2ded1 | 625 | T0 = tmp_T0; |
8c6939c0 | 626 | #endif |
8a40a180 FB |
627 | /* see if we can patch the calling TB. When the TB |
628 | spans two pages, we cannot safely do a direct | |
629 | jump. */ | |
c27004ec | 630 | { |
8a40a180 | 631 | if (T0 != 0 && |
f32fc648 FB |
632 | #if USE_KQEMU |
633 | (env->kqemu_enabled != 2) && | |
634 | #endif | |
8a40a180 | 635 | tb->page_addr[1] == -1 |
bf3e8bf1 FB |
636 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
637 | && (tb->cflags & CF_CODE_COPY) == | |
638 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) | |
639 | #endif | |
640 | ) { | |
3fb2ded1 | 641 | spin_lock(&tb_lock); |
c27004ec | 642 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
97eb5b14 FB |
643 | #if defined(USE_CODE_COPY) |
644 | /* propagates the FP use info */ | |
645 | ((TranslationBlock *)(T0 & ~3))->cflags |= | |
646 | (tb->cflags & CF_FP_USED); | |
647 | #endif | |
3fb2ded1 FB |
648 | spin_unlock(&tb_lock); |
649 | } | |
c27004ec | 650 | } |
3fb2ded1 | 651 | tc_ptr = tb->tc_ptr; |
83479e77 | 652 | env->current_tb = tb; |
3fb2ded1 FB |
653 | /* execute the generated code */ |
654 | gen_func = (void *)tc_ptr; | |
8c6939c0 | 655 | #if defined(__sparc__) |
3fb2ded1 FB |
656 | __asm__ __volatile__("call %0\n\t" |
657 | "mov %%o7,%%i0" | |
658 | : /* no outputs */ | |
659 | : "r" (gen_func) | |
660 | : "i0", "i1", "i2", "i3", "i4", "i5"); | |
8c6939c0 | 661 | #elif defined(__arm__) |
3fb2ded1 FB |
662 | asm volatile ("mov pc, %0\n\t" |
663 | ".global exec_loop\n\t" | |
664 | "exec_loop:\n\t" | |
665 | : /* no outputs */ | |
666 | : "r" (gen_func) | |
667 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); | |
bf3e8bf1 FB |
668 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
669 | { | |
670 | if (!(tb->cflags & CF_CODE_COPY)) { | |
97eb5b14 FB |
671 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
672 | save_native_fp_state(env); | |
673 | } | |
bf3e8bf1 FB |
674 | gen_func(); |
675 | } else { | |
97eb5b14 FB |
676 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
677 | restore_native_fp_state(env); | |
678 | } | |
bf3e8bf1 FB |
679 | /* we work with native eflags */ |
680 | CC_SRC = cc_table[CC_OP].compute_all(); | |
681 | CC_OP = CC_OP_EFLAGS; | |
682 | asm(".globl exec_loop\n" | |
683 | "\n" | |
684 | "debug1:\n" | |
685 | " pushl %%ebp\n" | |
686 | " fs movl %10, %9\n" | |
687 | " fs movl %11, %%eax\n" | |
688 | " andl $0x400, %%eax\n" | |
689 | " fs orl %8, %%eax\n" | |
690 | " pushl %%eax\n" | |
691 | " popf\n" | |
692 | " fs movl %%esp, %12\n" | |
693 | " fs movl %0, %%eax\n" | |
694 | " fs movl %1, %%ecx\n" | |
695 | " fs movl %2, %%edx\n" | |
696 | " fs movl %3, %%ebx\n" | |
697 | " fs movl %4, %%esp\n" | |
698 | " fs movl %5, %%ebp\n" | |
699 | " fs movl %6, %%esi\n" | |
700 | " fs movl %7, %%edi\n" | |
701 | " fs jmp *%9\n" | |
702 | "exec_loop:\n" | |
703 | " fs movl %%esp, %4\n" | |
704 | " fs movl %12, %%esp\n" | |
705 | " fs movl %%eax, %0\n" | |
706 | " fs movl %%ecx, %1\n" | |
707 | " fs movl %%edx, %2\n" | |
708 | " fs movl %%ebx, %3\n" | |
709 | " fs movl %%ebp, %5\n" | |
710 | " fs movl %%esi, %6\n" | |
711 | " fs movl %%edi, %7\n" | |
712 | " pushf\n" | |
713 | " popl %%eax\n" | |
714 | " movl %%eax, %%ecx\n" | |
715 | " andl $0x400, %%ecx\n" | |
716 | " shrl $9, %%ecx\n" | |
717 | " andl $0x8d5, %%eax\n" | |
718 | " fs movl %%eax, %8\n" | |
719 | " movl $1, %%eax\n" | |
720 | " subl %%ecx, %%eax\n" | |
721 | " fs movl %%eax, %11\n" | |
722 | " fs movl %9, %%ebx\n" /* get T0 value */ | |
723 | " popl %%ebp\n" | |
724 | : | |
725 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), | |
726 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), | |
727 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), | |
728 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), | |
729 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), | |
730 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), | |
731 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), | |
732 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), | |
733 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), | |
734 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), | |
735 | "a" (gen_func), | |
736 | "m" (*(uint8_t *)offsetof(CPUState, df)), | |
737 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) | |
738 | : "%ecx", "%edx" | |
739 | ); | |
740 | } | |
741 | } | |
b8076a74 FB |
742 | #elif defined(__ia64) |
743 | struct fptr { | |
744 | void *ip; | |
745 | void *gp; | |
746 | } fp; | |
747 | ||
748 | fp.ip = tc_ptr; | |
749 | fp.gp = code_gen_buffer + 2 * (1 << 20); | |
750 | (*(void (*)(void)) &fp)(); | |
ae228531 | 751 | #else |
3fb2ded1 | 752 | gen_func(); |
ae228531 | 753 | #endif |
83479e77 | 754 | env->current_tb = NULL; |
4cbf74b6 FB |
755 | /* reset soft MMU for next block (it can currently |
756 | only be set by a memory fault) */ | |
757 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) | |
3f337316 FB |
758 | if (env->hflags & HF_SOFTMMU_MASK) { |
759 | env->hflags &= ~HF_SOFTMMU_MASK; | |
4cbf74b6 FB |
760 | /* do not allow linking to another block */ |
761 | T0 = 0; | |
762 | } | |
f32fc648 FB |
763 | #endif |
764 | #if defined(USE_KQEMU) | |
765 | #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) | |
766 | if (kqemu_is_ok(env) && | |
767 | (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { | |
768 | cpu_loop_exit(); | |
769 | } | |
4cbf74b6 | 770 | #endif |
3fb2ded1 FB |
771 | } |
772 | } else { | |
0d1a29f9 | 773 | env_to_regs(); |
7d13299d | 774 | } |
3fb2ded1 FB |
775 | } /* for(;;) */ |
776 | ||
7d13299d | 777 | |
e4533c7a | 778 | #if defined(TARGET_I386) |
97eb5b14 FB |
779 | #if defined(USE_CODE_COPY) |
780 | if (env->native_fp_regs) { | |
781 | save_native_fp_state(env); | |
782 | } | |
783 | #endif | |
9de5e440 | 784 | /* restore flags in standard format */ |
fc2b4c48 | 785 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
9de5e440 | 786 | |
7d13299d | 787 | /* restore global registers */ |
04369ff2 FB |
788 | #ifdef reg_EAX |
789 | EAX = saved_EAX; | |
790 | #endif | |
791 | #ifdef reg_ECX | |
792 | ECX = saved_ECX; | |
793 | #endif | |
794 | #ifdef reg_EDX | |
795 | EDX = saved_EDX; | |
796 | #endif | |
797 | #ifdef reg_EBX | |
798 | EBX = saved_EBX; | |
799 | #endif | |
800 | #ifdef reg_ESP | |
801 | ESP = saved_ESP; | |
802 | #endif | |
803 | #ifdef reg_EBP | |
804 | EBP = saved_EBP; | |
805 | #endif | |
806 | #ifdef reg_ESI | |
807 | ESI = saved_ESI; | |
808 | #endif | |
809 | #ifdef reg_EDI | |
810 | EDI = saved_EDI; | |
8c6939c0 | 811 | #endif |
e4533c7a | 812 | #elif defined(TARGET_ARM) |
b7bcbe95 | 813 | /* XXX: Save/restore host fpu exception state?. */ |
93ac68bc | 814 | #elif defined(TARGET_SPARC) |
3475187d FB |
815 | #if defined(reg_REGWPTR) |
816 | REGWPTR = saved_regwptr; | |
817 | #endif | |
67867308 | 818 | #elif defined(TARGET_PPC) |
6af0bf9c | 819 | #elif defined(TARGET_MIPS) |
e4533c7a FB |
820 | #else |
821 | #error unsupported target CPU | |
822 | #endif | |
8c6939c0 FB |
823 | #ifdef __sparc__ |
824 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); | |
04369ff2 | 825 | #endif |
7d13299d FB |
826 | T0 = saved_T0; |
827 | T1 = saved_T1; | |
3475187d | 828 | #if defined(reg_T2) |
e4533c7a | 829 | T2 = saved_T2; |
3475187d | 830 | #endif |
7d13299d | 831 | env = saved_env; |
6a00d601 FB |
832 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
833 | cpu_single_env = NULL; | |
7d13299d FB |
834 | return ret; |
835 | } | |
6dbad63e | 836 | |
fbf9eeb3 FB |
837 | /* must only be called from the generated code as an exception can be |
838 | generated */ | |
839 | void tb_invalidate_page_range(target_ulong start, target_ulong end) | |
840 | { | |
dc5d0b3d FB |
841 | /* XXX: cannot enable it yet because it yields to MMU exception |
842 | where NIP != read address on PowerPC */ | |
843 | #if 0 | |
fbf9eeb3 FB |
844 | target_ulong phys_addr; |
845 | phys_addr = get_phys_addr_code(env, start); | |
846 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); | |
dc5d0b3d | 847 | #endif |
fbf9eeb3 FB |
848 | } |
849 | ||
1a18c71b | 850 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 851 | |
6dbad63e FB |
852 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
853 | { | |
854 | CPUX86State *saved_env; | |
855 | ||
856 | saved_env = env; | |
857 | env = s; | |
a412ac57 | 858 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 859 | selector &= 0xffff; |
2e255c6b | 860 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
c27004ec | 861 | (selector << 4), 0xffff, 0); |
a513fe19 | 862 | } else { |
b453b70b | 863 | load_seg(seg_reg, selector); |
a513fe19 | 864 | } |
6dbad63e FB |
865 | env = saved_env; |
866 | } | |
9de5e440 | 867 | |
d0a1ffc9 FB |
868 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
869 | { | |
870 | CPUX86State *saved_env; | |
871 | ||
872 | saved_env = env; | |
873 | env = s; | |
874 | ||
c27004ec | 875 | helper_fsave((target_ulong)ptr, data32); |
d0a1ffc9 FB |
876 | |
877 | env = saved_env; | |
878 | } | |
879 | ||
880 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) | |
881 | { | |
882 | CPUX86State *saved_env; | |
883 | ||
884 | saved_env = env; | |
885 | env = s; | |
886 | ||
c27004ec | 887 | helper_frstor((target_ulong)ptr, data32); |
d0a1ffc9 FB |
888 | |
889 | env = saved_env; | |
890 | } | |
891 | ||
e4533c7a FB |
892 | #endif /* TARGET_I386 */ |
893 | ||
67b915a5 FB |
894 | #if !defined(CONFIG_SOFTMMU) |
895 | ||
3fb2ded1 FB |
896 | #if defined(TARGET_I386) |
897 | ||
b56dad1c | 898 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
899 | the effective address of the memory exception. 'is_write' is 1 if a |
900 | write caused the exception and otherwise 0'. 'old_set' is the | |
901 | signal set which should be restored */ | |
2b413144 | 902 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
903 | int is_write, sigset_t *old_set, |
904 | void *puc) | |
9de5e440 | 905 | { |
a513fe19 FB |
906 | TranslationBlock *tb; |
907 | int ret; | |
68a79315 | 908 | |
83479e77 FB |
909 | if (cpu_single_env) |
910 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 911 | #if defined(DEBUG_SIGNAL) |
bf3e8bf1 FB |
912 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
913 | pc, address, is_write, *(unsigned long *)old_set); | |
9de5e440 | 914 | #endif |
25eb4484 | 915 | /* XXX: locking issue */ |
fbf9eeb3 | 916 | if (is_write && page_unprotect(address, pc, puc)) { |
fd6ce8f6 FB |
917 | return 1; |
918 | } | |
fbf9eeb3 | 919 | |
3fb2ded1 | 920 | /* see if it is an MMU fault */ |
93a40ea9 FB |
921 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
922 | ((env->hflags & HF_CPL_MASK) == 3), 0); | |
3fb2ded1 FB |
923 | if (ret < 0) |
924 | return 0; /* not an MMU fault */ | |
925 | if (ret == 0) | |
926 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
927 | /* now we have a real cpu fault */ | |
a513fe19 FB |
928 | tb = tb_find_pc(pc); |
929 | if (tb) { | |
9de5e440 FB |
930 | /* the PC is inside the translated code. It means that we have |
931 | a virtual CPU fault */ | |
bf3e8bf1 | 932 | cpu_restore_state(tb, env, pc, puc); |
3fb2ded1 | 933 | } |
4cbf74b6 | 934 | if (ret == 1) { |
3fb2ded1 | 935 | #if 0 |
4cbf74b6 FB |
936 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
937 | env->eip, env->cr[2], env->error_code); | |
3fb2ded1 | 938 | #endif |
4cbf74b6 FB |
939 | /* we restore the process signal mask as the sigreturn should |
940 | do it (XXX: use sigsetjmp) */ | |
941 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
54ca9095 | 942 | raise_exception_err(env->exception_index, env->error_code); |
4cbf74b6 FB |
943 | } else { |
944 | /* activate soft MMU for this block */ | |
3f337316 | 945 | env->hflags |= HF_SOFTMMU_MASK; |
fbf9eeb3 | 946 | cpu_resume_from_signal(env, puc); |
4cbf74b6 | 947 | } |
3fb2ded1 FB |
948 | /* never comes here */ |
949 | return 1; | |
950 | } | |
951 | ||
e4533c7a | 952 | #elif defined(TARGET_ARM) |
3fb2ded1 | 953 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
954 | int is_write, sigset_t *old_set, |
955 | void *puc) | |
3fb2ded1 | 956 | { |
68016c62 FB |
957 | TranslationBlock *tb; |
958 | int ret; | |
959 | ||
960 | if (cpu_single_env) | |
961 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
962 | #if defined(DEBUG_SIGNAL) | |
963 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
964 | pc, address, is_write, *(unsigned long *)old_set); | |
965 | #endif | |
9f0777ed FB |
966 | /* XXX: locking issue */ |
967 | if (is_write && page_unprotect(address, pc, puc)) { | |
968 | return 1; | |
969 | } | |
68016c62 FB |
970 | /* see if it is an MMU fault */ |
971 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); | |
972 | if (ret < 0) | |
973 | return 0; /* not an MMU fault */ | |
974 | if (ret == 0) | |
975 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
976 | /* now we have a real cpu fault */ | |
977 | tb = tb_find_pc(pc); | |
978 | if (tb) { | |
979 | /* the PC is inside the translated code. It means that we have | |
980 | a virtual CPU fault */ | |
981 | cpu_restore_state(tb, env, pc, puc); | |
982 | } | |
983 | /* we restore the process signal mask as the sigreturn should | |
984 | do it (XXX: use sigsetjmp) */ | |
985 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
986 | cpu_loop_exit(); | |
3fb2ded1 | 987 | } |
93ac68bc FB |
988 | #elif defined(TARGET_SPARC) |
989 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
990 | int is_write, sigset_t *old_set, |
991 | void *puc) | |
93ac68bc | 992 | { |
68016c62 FB |
993 | TranslationBlock *tb; |
994 | int ret; | |
995 | ||
996 | if (cpu_single_env) | |
997 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
998 | #if defined(DEBUG_SIGNAL) | |
999 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
1000 | pc, address, is_write, *(unsigned long *)old_set); | |
1001 | #endif | |
b453b70b | 1002 | /* XXX: locking issue */ |
fbf9eeb3 | 1003 | if (is_write && page_unprotect(address, pc, puc)) { |
b453b70b FB |
1004 | return 1; |
1005 | } | |
68016c62 FB |
1006 | /* see if it is an MMU fault */ |
1007 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); | |
1008 | if (ret < 0) | |
1009 | return 0; /* not an MMU fault */ | |
1010 | if (ret == 0) | |
1011 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
1012 | /* now we have a real cpu fault */ | |
1013 | tb = tb_find_pc(pc); | |
1014 | if (tb) { | |
1015 | /* the PC is inside the translated code. It means that we have | |
1016 | a virtual CPU fault */ | |
1017 | cpu_restore_state(tb, env, pc, puc); | |
1018 | } | |
1019 | /* we restore the process signal mask as the sigreturn should | |
1020 | do it (XXX: use sigsetjmp) */ | |
1021 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
1022 | cpu_loop_exit(); | |
93ac68bc | 1023 | } |
67867308 FB |
1024 | #elif defined (TARGET_PPC) |
1025 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
1026 | int is_write, sigset_t *old_set, |
1027 | void *puc) | |
67867308 FB |
1028 | { |
1029 | TranslationBlock *tb; | |
ce09776b | 1030 | int ret; |
67867308 | 1031 | |
67867308 FB |
1032 | if (cpu_single_env) |
1033 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
67867308 FB |
1034 | #if defined(DEBUG_SIGNAL) |
1035 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
1036 | pc, address, is_write, *(unsigned long *)old_set); | |
1037 | #endif | |
1038 | /* XXX: locking issue */ | |
fbf9eeb3 | 1039 | if (is_write && page_unprotect(address, pc, puc)) { |
67867308 FB |
1040 | return 1; |
1041 | } | |
1042 | ||
ce09776b | 1043 | /* see if it is an MMU fault */ |
7f957d28 | 1044 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
ce09776b FB |
1045 | if (ret < 0) |
1046 | return 0; /* not an MMU fault */ | |
1047 | if (ret == 0) | |
1048 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
1049 | ||
67867308 FB |
1050 | /* now we have a real cpu fault */ |
1051 | tb = tb_find_pc(pc); | |
1052 | if (tb) { | |
1053 | /* the PC is inside the translated code. It means that we have | |
1054 | a virtual CPU fault */ | |
bf3e8bf1 | 1055 | cpu_restore_state(tb, env, pc, puc); |
67867308 | 1056 | } |
ce09776b | 1057 | if (ret == 1) { |
67867308 | 1058 | #if 0 |
ce09776b FB |
1059 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
1060 | env->nip, env->error_code, tb); | |
67867308 FB |
1061 | #endif |
1062 | /* we restore the process signal mask as the sigreturn should | |
1063 | do it (XXX: use sigsetjmp) */ | |
bf3e8bf1 | 1064 | sigprocmask(SIG_SETMASK, old_set, NULL); |
9fddaa0c | 1065 | do_raise_exception_err(env->exception_index, env->error_code); |
ce09776b FB |
1066 | } else { |
1067 | /* activate soft MMU for this block */ | |
fbf9eeb3 | 1068 | cpu_resume_from_signal(env, puc); |
ce09776b | 1069 | } |
67867308 FB |
1070 | /* never comes here */ |
1071 | return 1; | |
1072 | } | |
6af0bf9c FB |
1073 | |
1074 | #elif defined (TARGET_MIPS) | |
1075 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
1076 | int is_write, sigset_t *old_set, | |
1077 | void *puc) | |
1078 | { | |
1079 | TranslationBlock *tb; | |
1080 | int ret; | |
1081 | ||
1082 | if (cpu_single_env) | |
1083 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
1084 | #if defined(DEBUG_SIGNAL) | |
1085 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
1086 | pc, address, is_write, *(unsigned long *)old_set); | |
1087 | #endif | |
1088 | /* XXX: locking issue */ | |
1089 | if (is_write && page_unprotect(address, pc, puc)) { | |
1090 | return 1; | |
1091 | } | |
1092 | ||
1093 | /* see if it is an MMU fault */ | |
cc9442b9 | 1094 | ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0); |
6af0bf9c FB |
1095 | if (ret < 0) |
1096 | return 0; /* not an MMU fault */ | |
1097 | if (ret == 0) | |
1098 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
1099 | ||
1100 | /* now we have a real cpu fault */ | |
1101 | tb = tb_find_pc(pc); | |
1102 | if (tb) { | |
1103 | /* the PC is inside the translated code. It means that we have | |
1104 | a virtual CPU fault */ | |
1105 | cpu_restore_state(tb, env, pc, puc); | |
1106 | } | |
1107 | if (ret == 1) { | |
1108 | #if 0 | |
1109 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", | |
1110 | env->nip, env->error_code, tb); | |
1111 | #endif | |
1112 | /* we restore the process signal mask as the sigreturn should | |
1113 | do it (XXX: use sigsetjmp) */ | |
1114 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
1115 | do_raise_exception_err(env->exception_index, env->error_code); | |
1116 | } else { | |
1117 | /* activate soft MMU for this block */ | |
1118 | cpu_resume_from_signal(env, puc); | |
1119 | } | |
1120 | /* never comes here */ | |
1121 | return 1; | |
1122 | } | |
1123 | ||
e4533c7a FB |
1124 | #else |
1125 | #error unsupported target CPU | |
1126 | #endif | |
9de5e440 | 1127 | |
2b413144 FB |
1128 | #if defined(__i386__) |
1129 | ||
bf3e8bf1 FB |
1130 | #if defined(USE_CODE_COPY) |
1131 | static void cpu_send_trap(unsigned long pc, int trap, | |
1132 | struct ucontext *uc) | |
1133 | { | |
1134 | TranslationBlock *tb; | |
1135 | ||
1136 | if (cpu_single_env) | |
1137 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
1138 | /* now we have a real cpu fault */ | |
1139 | tb = tb_find_pc(pc); | |
1140 | if (tb) { | |
1141 | /* the PC is inside the translated code. It means that we have | |
1142 | a virtual CPU fault */ | |
1143 | cpu_restore_state(tb, env, pc, uc); | |
1144 | } | |
1145 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
1146 | raise_exception_err(trap, env->error_code); | |
1147 | } | |
1148 | #endif | |
1149 | ||
e4533c7a FB |
1150 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1151 | void *puc) | |
9de5e440 | 1152 | { |
9de5e440 FB |
1153 | struct ucontext *uc = puc; |
1154 | unsigned long pc; | |
bf3e8bf1 | 1155 | int trapno; |
97eb5b14 | 1156 | |
d691f669 FB |
1157 | #ifndef REG_EIP |
1158 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
1159 | #define REG_EIP EIP |
1160 | #define REG_ERR ERR | |
1161 | #define REG_TRAPNO TRAPNO | |
d691f669 | 1162 | #endif |
fc2b4c48 | 1163 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bf3e8bf1 FB |
1164 | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
1165 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) | |
1166 | if (trapno == 0x00 || trapno == 0x05) { | |
1167 | /* send division by zero or bound exception */ | |
1168 | cpu_send_trap(pc, trapno, uc); | |
1169 | return 1; | |
1170 | } else | |
1171 | #endif | |
1172 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1173 | trapno == 0xe ? | |
1174 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
1175 | &uc->uc_sigmask, puc); | |
2b413144 FB |
1176 | } |
1177 | ||
bc51c5c9 FB |
1178 | #elif defined(__x86_64__) |
1179 | ||
1180 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
1181 | void *puc) | |
1182 | { | |
1183 | struct ucontext *uc = puc; | |
1184 | unsigned long pc; | |
1185 | ||
1186 | pc = uc->uc_mcontext.gregs[REG_RIP]; | |
1187 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1188 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
1189 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
1190 | &uc->uc_sigmask, puc); | |
1191 | } | |
1192 | ||
83fb7adf | 1193 | #elif defined(__powerpc__) |
2b413144 | 1194 | |
83fb7adf FB |
1195 | /*********************************************************************** |
1196 | * signal context platform-specific definitions | |
1197 | * From Wine | |
1198 | */ | |
1199 | #ifdef linux | |
1200 | /* All Registers access - only for local access */ | |
1201 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) | |
1202 | /* Gpr Registers access */ | |
1203 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
1204 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ | |
1205 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ | |
1206 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ | |
1207 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ | |
1208 | # define LR_sig(context) REG_sig(link, context) /* Link register */ | |
1209 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ | |
1210 | /* Float Registers access */ | |
1211 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) | |
1212 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) | |
1213 | /* Exception Registers access */ | |
1214 | # define DAR_sig(context) REG_sig(dar, context) | |
1215 | # define DSISR_sig(context) REG_sig(dsisr, context) | |
1216 | # define TRAP_sig(context) REG_sig(trap, context) | |
1217 | #endif /* linux */ | |
1218 | ||
1219 | #ifdef __APPLE__ | |
1220 | # include <sys/ucontext.h> | |
1221 | typedef struct ucontext SIGCONTEXT; | |
1222 | /* All Registers access - only for local access */ | |
1223 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) | |
1224 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) | |
1225 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) | |
1226 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) | |
1227 | /* Gpr Registers access */ | |
1228 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) | |
1229 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ | |
1230 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ | |
1231 | # define CTR_sig(context) REG_sig(ctr, context) | |
1232 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ | |
1233 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ | |
1234 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ | |
1235 | /* Float Registers access */ | |
1236 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) | |
1237 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) | |
1238 | /* Exception Registers access */ | |
1239 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ | |
1240 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) | |
1241 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ | |
1242 | #endif /* __APPLE__ */ | |
1243 | ||
d1d9f421 | 1244 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
e4533c7a | 1245 | void *puc) |
2b413144 | 1246 | { |
25eb4484 | 1247 | struct ucontext *uc = puc; |
25eb4484 | 1248 | unsigned long pc; |
25eb4484 FB |
1249 | int is_write; |
1250 | ||
83fb7adf | 1251 | pc = IAR_sig(uc); |
25eb4484 FB |
1252 | is_write = 0; |
1253 | #if 0 | |
1254 | /* ppc 4xx case */ | |
83fb7adf | 1255 | if (DSISR_sig(uc) & 0x00800000) |
25eb4484 FB |
1256 | is_write = 1; |
1257 | #else | |
83fb7adf | 1258 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
25eb4484 FB |
1259 | is_write = 1; |
1260 | #endif | |
1261 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1262 | is_write, &uc->uc_sigmask, puc); |
2b413144 FB |
1263 | } |
1264 | ||
2f87c607 FB |
1265 | #elif defined(__alpha__) |
1266 | ||
e4533c7a | 1267 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
2f87c607 FB |
1268 | void *puc) |
1269 | { | |
1270 | struct ucontext *uc = puc; | |
1271 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
1272 | uint32_t insn = *pc; | |
1273 | int is_write = 0; | |
1274 | ||
8c6939c0 | 1275 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
1276 | switch (insn >> 26) { |
1277 | case 0x0d: // stw | |
1278 | case 0x0e: // stb | |
1279 | case 0x0f: // stq_u | |
1280 | case 0x24: // stf | |
1281 | case 0x25: // stg | |
1282 | case 0x26: // sts | |
1283 | case 0x27: // stt | |
1284 | case 0x2c: // stl | |
1285 | case 0x2d: // stq | |
1286 | case 0x2e: // stl_c | |
1287 | case 0x2f: // stq_c | |
1288 | is_write = 1; | |
1289 | } | |
1290 | ||
1291 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1292 | is_write, &uc->uc_sigmask, puc); |
2f87c607 | 1293 | } |
8c6939c0 FB |
1294 | #elif defined(__sparc__) |
1295 | ||
e4533c7a FB |
1296 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1297 | void *puc) | |
8c6939c0 FB |
1298 | { |
1299 | uint32_t *regs = (uint32_t *)(info + 1); | |
1300 | void *sigmask = (regs + 20); | |
1301 | unsigned long pc; | |
1302 | int is_write; | |
1303 | uint32_t insn; | |
1304 | ||
1305 | /* XXX: is there a standard glibc define ? */ | |
1306 | pc = regs[1]; | |
1307 | /* XXX: need kernel patch to get write flag faster */ | |
1308 | is_write = 0; | |
1309 | insn = *(uint32_t *)pc; | |
1310 | if ((insn >> 30) == 3) { | |
1311 | switch((insn >> 19) & 0x3f) { | |
1312 | case 0x05: // stb | |
1313 | case 0x06: // sth | |
1314 | case 0x04: // st | |
1315 | case 0x07: // std | |
1316 | case 0x24: // stf | |
1317 | case 0x27: // stdf | |
1318 | case 0x25: // stfsr | |
1319 | is_write = 1; | |
1320 | break; | |
1321 | } | |
1322 | } | |
1323 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1324 | is_write, sigmask, NULL); |
8c6939c0 FB |
1325 | } |
1326 | ||
1327 | #elif defined(__arm__) | |
1328 | ||
e4533c7a FB |
1329 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1330 | void *puc) | |
8c6939c0 FB |
1331 | { |
1332 | struct ucontext *uc = puc; | |
1333 | unsigned long pc; | |
1334 | int is_write; | |
1335 | ||
1336 | pc = uc->uc_mcontext.gregs[R15]; | |
1337 | /* XXX: compute is_write */ | |
1338 | is_write = 0; | |
1339 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1340 | is_write, | |
1341 | &uc->uc_sigmask); | |
1342 | } | |
1343 | ||
38e584a0 FB |
1344 | #elif defined(__mc68000) |
1345 | ||
1346 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
1347 | void *puc) | |
1348 | { | |
1349 | struct ucontext *uc = puc; | |
1350 | unsigned long pc; | |
1351 | int is_write; | |
1352 | ||
1353 | pc = uc->uc_mcontext.gregs[16]; | |
1354 | /* XXX: compute is_write */ | |
1355 | is_write = 0; | |
1356 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1357 | is_write, | |
bf3e8bf1 | 1358 | &uc->uc_sigmask, puc); |
38e584a0 FB |
1359 | } |
1360 | ||
b8076a74 FB |
1361 | #elif defined(__ia64) |
1362 | ||
1363 | #ifndef __ISR_VALID | |
1364 | /* This ought to be in <bits/siginfo.h>... */ | |
1365 | # define __ISR_VALID 1 | |
1366 | # define si_flags _sifields._sigfault._si_pad0 | |
1367 | #endif | |
1368 | ||
1369 | int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) | |
1370 | { | |
1371 | struct ucontext *uc = puc; | |
1372 | unsigned long ip; | |
1373 | int is_write = 0; | |
1374 | ||
1375 | ip = uc->uc_mcontext.sc_ip; | |
1376 | switch (host_signum) { | |
1377 | case SIGILL: | |
1378 | case SIGFPE: | |
1379 | case SIGSEGV: | |
1380 | case SIGBUS: | |
1381 | case SIGTRAP: | |
1382 | if (info->si_code && (info->si_flags & __ISR_VALID)) | |
1383 | /* ISR.W (write-access) is bit 33: */ | |
1384 | is_write = (info->si_isr >> 33) & 1; | |
1385 | break; | |
1386 | ||
1387 | default: | |
1388 | break; | |
1389 | } | |
1390 | return handle_cpu_signal(ip, (unsigned long)info->si_addr, | |
1391 | is_write, | |
1392 | &uc->uc_sigmask, puc); | |
1393 | } | |
1394 | ||
90cb9493 FB |
1395 | #elif defined(__s390__) |
1396 | ||
1397 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
1398 | void *puc) | |
1399 | { | |
1400 | struct ucontext *uc = puc; | |
1401 | unsigned long pc; | |
1402 | int is_write; | |
1403 | ||
1404 | pc = uc->uc_mcontext.psw.addr; | |
1405 | /* XXX: compute is_write */ | |
1406 | is_write = 0; | |
1407 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1408 | is_write, | |
1409 | &uc->uc_sigmask, puc); | |
1410 | } | |
1411 | ||
9de5e440 | 1412 | #else |
2b413144 | 1413 | |
3fb2ded1 | 1414 | #error host CPU specific signal handler needed |
2b413144 | 1415 | |
9de5e440 | 1416 | #endif |
67b915a5 FB |
1417 | |
1418 | #endif /* !defined(CONFIG_SOFTMMU) */ |