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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d | 19 | */ |
e4533c7a | 20 | #include "config.h" |
93ac68bc | 21 | #include "exec.h" |
956034d7 | 22 | #include "disas.h" |
7d13299d | 23 | |
fbf9eeb3 FB |
24 | #if !defined(CONFIG_SOFTMMU) |
25 | #undef EAX | |
26 | #undef ECX | |
27 | #undef EDX | |
28 | #undef EBX | |
29 | #undef ESP | |
30 | #undef EBP | |
31 | #undef ESI | |
32 | #undef EDI | |
33 | #undef EIP | |
34 | #include <signal.h> | |
35 | #include <sys/ucontext.h> | |
36 | #endif | |
37 | ||
36bdbe54 FB |
38 | int tb_invalidated_flag; |
39 | ||
dc99065b | 40 | //#define DEBUG_EXEC |
9de5e440 | 41 | //#define DEBUG_SIGNAL |
7d13299d | 42 | |
93ac68bc | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) |
e4533c7a FB |
44 | /* XXX: unify with i386 target */ |
45 | void cpu_loop_exit(void) | |
46 | { | |
47 | longjmp(env->jmp_env, 1); | |
48 | } | |
49 | #endif | |
50 | ||
fbf9eeb3 FB |
51 | /* exit the current TB from a signal handler. The host registers are |
52 | restored in a state compatible with the CPU emulator | |
53 | */ | |
54 | void cpu_resume_from_signal(CPUState *env1, void *puc) | |
55 | { | |
56 | #if !defined(CONFIG_SOFTMMU) | |
57 | struct ucontext *uc = puc; | |
58 | #endif | |
59 | ||
60 | env = env1; | |
61 | ||
62 | /* XXX: restore cpu registers saved in host registers */ | |
63 | ||
64 | #if !defined(CONFIG_SOFTMMU) | |
65 | if (puc) { | |
66 | /* XXX: use siglongjmp ? */ | |
67 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
68 | } | |
69 | #endif | |
70 | longjmp(env->jmp_env, 1); | |
71 | } | |
72 | ||
7d13299d FB |
73 | /* main execution loop */ |
74 | ||
e4533c7a | 75 | int cpu_exec(CPUState *env1) |
7d13299d | 76 | { |
e4533c7a FB |
77 | int saved_T0, saved_T1, saved_T2; |
78 | CPUState *saved_env; | |
04369ff2 FB |
79 | #ifdef reg_EAX |
80 | int saved_EAX; | |
81 | #endif | |
82 | #ifdef reg_ECX | |
83 | int saved_ECX; | |
84 | #endif | |
85 | #ifdef reg_EDX | |
86 | int saved_EDX; | |
87 | #endif | |
88 | #ifdef reg_EBX | |
89 | int saved_EBX; | |
90 | #endif | |
91 | #ifdef reg_ESP | |
92 | int saved_ESP; | |
93 | #endif | |
94 | #ifdef reg_EBP | |
95 | int saved_EBP; | |
96 | #endif | |
97 | #ifdef reg_ESI | |
98 | int saved_ESI; | |
99 | #endif | |
100 | #ifdef reg_EDI | |
101 | int saved_EDI; | |
8c6939c0 FB |
102 | #endif |
103 | #ifdef __sparc__ | |
104 | int saved_i7, tmp_T0; | |
04369ff2 | 105 | #endif |
68a79315 | 106 | int code_gen_size, ret, interrupt_request; |
7d13299d | 107 | void (*gen_func)(void); |
9de5e440 | 108 | TranslationBlock *tb, **ptb; |
c27004ec FB |
109 | target_ulong cs_base, pc; |
110 | uint8_t *tc_ptr; | |
6dbad63e | 111 | unsigned int flags; |
8c6939c0 | 112 | |
7d13299d | 113 | /* first we save global registers */ |
c27004ec FB |
114 | saved_env = env; |
115 | env = env1; | |
7d13299d FB |
116 | saved_T0 = T0; |
117 | saved_T1 = T1; | |
e4533c7a | 118 | saved_T2 = T2; |
e4533c7a FB |
119 | #ifdef __sparc__ |
120 | /* we also save i7 because longjmp may not restore it */ | |
121 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); | |
122 | #endif | |
123 | ||
124 | #if defined(TARGET_I386) | |
04369ff2 FB |
125 | #ifdef reg_EAX |
126 | saved_EAX = EAX; | |
04369ff2 FB |
127 | #endif |
128 | #ifdef reg_ECX | |
129 | saved_ECX = ECX; | |
04369ff2 FB |
130 | #endif |
131 | #ifdef reg_EDX | |
132 | saved_EDX = EDX; | |
04369ff2 FB |
133 | #endif |
134 | #ifdef reg_EBX | |
135 | saved_EBX = EBX; | |
04369ff2 FB |
136 | #endif |
137 | #ifdef reg_ESP | |
138 | saved_ESP = ESP; | |
04369ff2 FB |
139 | #endif |
140 | #ifdef reg_EBP | |
141 | saved_EBP = EBP; | |
04369ff2 FB |
142 | #endif |
143 | #ifdef reg_ESI | |
144 | saved_ESI = ESI; | |
04369ff2 FB |
145 | #endif |
146 | #ifdef reg_EDI | |
147 | saved_EDI = EDI; | |
04369ff2 | 148 | #endif |
0d1a29f9 FB |
149 | |
150 | env_to_regs(); | |
9de5e440 | 151 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
152 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
153 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 154 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 155 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a FB |
156 | #elif defined(TARGET_ARM) |
157 | { | |
158 | unsigned int psr; | |
159 | psr = env->cpsr; | |
160 | env->CF = (psr >> 29) & 1; | |
161 | env->NZF = (psr & 0xc0000000) ^ 0x40000000; | |
162 | env->VF = (psr << 3) & 0x80000000; | |
99c475ab FB |
163 | env->QF = (psr >> 27) & 1; |
164 | env->cpsr = psr & ~CACHED_CPSR_BITS; | |
e4533c7a | 165 | } |
93ac68bc | 166 | #elif defined(TARGET_SPARC) |
67867308 | 167 | #elif defined(TARGET_PPC) |
e4533c7a FB |
168 | #else |
169 | #error unsupported target CPU | |
170 | #endif | |
3fb2ded1 | 171 | env->exception_index = -1; |
9d27abd9 | 172 | |
7d13299d | 173 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
174 | for(;;) { |
175 | if (setjmp(env->jmp_env) == 0) { | |
ee8b7021 | 176 | env->current_tb = NULL; |
3fb2ded1 FB |
177 | /* if an exception is pending, we execute it here */ |
178 | if (env->exception_index >= 0) { | |
179 | if (env->exception_index >= EXCP_INTERRUPT) { | |
180 | /* exit request from the cpu execution loop */ | |
181 | ret = env->exception_index; | |
182 | break; | |
183 | } else if (env->user_mode_only) { | |
184 | /* if user mode only, we simulate a fake exception | |
185 | which will be hanlded outside the cpu execution | |
186 | loop */ | |
83479e77 | 187 | #if defined(TARGET_I386) |
3fb2ded1 FB |
188 | do_interrupt_user(env->exception_index, |
189 | env->exception_is_int, | |
190 | env->error_code, | |
191 | env->exception_next_eip); | |
83479e77 | 192 | #endif |
3fb2ded1 FB |
193 | ret = env->exception_index; |
194 | break; | |
195 | } else { | |
83479e77 | 196 | #if defined(TARGET_I386) |
3fb2ded1 FB |
197 | /* simulate a real cpu exception. On i386, it can |
198 | trigger new exceptions, but we do not handle | |
199 | double or triple faults yet. */ | |
200 | do_interrupt(env->exception_index, | |
201 | env->exception_is_int, | |
202 | env->error_code, | |
d05e66d2 | 203 | env->exception_next_eip, 0); |
ce09776b FB |
204 | #elif defined(TARGET_PPC) |
205 | do_interrupt(env); | |
e95c8d51 FB |
206 | #elif defined(TARGET_SPARC) |
207 | do_interrupt(env->exception_index, | |
68016c62 | 208 | env->error_code); |
83479e77 | 209 | #endif |
3fb2ded1 FB |
210 | } |
211 | env->exception_index = -1; | |
9df217a3 FB |
212 | } |
213 | #ifdef USE_KQEMU | |
214 | if (kqemu_is_ok(env) && env->interrupt_request == 0) { | |
215 | int ret; | |
216 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
217 | ret = kqemu_cpu_exec(env); | |
218 | /* put eflags in CPU temporary format */ | |
219 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
220 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
221 | CC_OP = CC_OP_EFLAGS; | |
222 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
223 | if (ret == 1) { | |
224 | /* exception */ | |
225 | longjmp(env->jmp_env, 1); | |
226 | } else if (ret == 2) { | |
227 | /* softmmu execution needed */ | |
228 | } else { | |
229 | if (env->interrupt_request != 0) { | |
230 | /* hardware interrupt will be executed just after */ | |
231 | } else { | |
232 | /* otherwise, we restart */ | |
233 | longjmp(env->jmp_env, 1); | |
234 | } | |
235 | } | |
3fb2ded1 | 236 | } |
9df217a3 FB |
237 | #endif |
238 | ||
3fb2ded1 FB |
239 | T0 = 0; /* force lookup of first TB */ |
240 | for(;;) { | |
8c6939c0 | 241 | #ifdef __sparc__ |
3fb2ded1 FB |
242 | /* g1 can be modified by some libc? functions */ |
243 | tmp_T0 = T0; | |
8c6939c0 | 244 | #endif |
68a79315 | 245 | interrupt_request = env->interrupt_request; |
2e255c6b | 246 | if (__builtin_expect(interrupt_request, 0)) { |
68a79315 FB |
247 | #if defined(TARGET_I386) |
248 | /* if hardware interrupt pending, we execute it */ | |
249 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
3f337316 FB |
250 | (env->eflags & IF_MASK) && |
251 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
68a79315 | 252 | int intno; |
fbf9eeb3 | 253 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
a541f297 | 254 | intno = cpu_get_pic_interrupt(env); |
f193c797 | 255 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
68a79315 FB |
256 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
257 | } | |
d05e66d2 | 258 | do_interrupt(intno, 0, 0, 0, 1); |
907a5b26 FB |
259 | /* ensure that no TB jump will be modified as |
260 | the program flow was changed */ | |
261 | #ifdef __sparc__ | |
262 | tmp_T0 = 0; | |
263 | #else | |
264 | T0 = 0; | |
265 | #endif | |
68a79315 | 266 | } |
ce09776b | 267 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
268 | #if 0 |
269 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
270 | cpu_ppc_reset(env); | |
271 | } | |
272 | #endif | |
273 | if (msr_ee != 0) { | |
ce09776b | 274 | if ((interrupt_request & CPU_INTERRUPT_HARD)) { |
9fddaa0c FB |
275 | /* Raise it */ |
276 | env->exception_index = EXCP_EXTERNAL; | |
277 | env->error_code = 0; | |
ce09776b FB |
278 | do_interrupt(env); |
279 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
9fddaa0c FB |
280 | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
281 | /* Raise it */ | |
282 | env->exception_index = EXCP_DECR; | |
283 | env->error_code = 0; | |
284 | do_interrupt(env); | |
285 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
286 | } | |
ce09776b | 287 | } |
e95c8d51 FB |
288 | #elif defined(TARGET_SPARC) |
289 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
68016c62 | 290 | do_interrupt(env->interrupt_index, 0); |
e95c8d51 FB |
291 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
292 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { | |
293 | //do_interrupt(0, 0, 0, 0, 0); | |
294 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
295 | } | |
68a79315 | 296 | #endif |
bf3e8bf1 FB |
297 | if (interrupt_request & CPU_INTERRUPT_EXITTB) { |
298 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; | |
299 | /* ensure that no TB jump will be modified as | |
300 | the program flow was changed */ | |
301 | #ifdef __sparc__ | |
302 | tmp_T0 = 0; | |
303 | #else | |
304 | T0 = 0; | |
305 | #endif | |
306 | } | |
68a79315 FB |
307 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
308 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; | |
309 | env->exception_index = EXCP_INTERRUPT; | |
310 | cpu_loop_exit(); | |
311 | } | |
3fb2ded1 | 312 | } |
7d13299d | 313 | #ifdef DEBUG_EXEC |
c27004ec | 314 | if ((loglevel & CPU_LOG_EXEC)) { |
e4533c7a | 315 | #if defined(TARGET_I386) |
3fb2ded1 FB |
316 | /* restore flags in standard format */ |
317 | env->regs[R_EAX] = EAX; | |
318 | env->regs[R_EBX] = EBX; | |
319 | env->regs[R_ECX] = ECX; | |
320 | env->regs[R_EDX] = EDX; | |
321 | env->regs[R_ESI] = ESI; | |
322 | env->regs[R_EDI] = EDI; | |
323 | env->regs[R_EBP] = EBP; | |
324 | env->regs[R_ESP] = ESP; | |
325 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
7fe48483 | 326 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
3fb2ded1 | 327 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 328 | #elif defined(TARGET_ARM) |
1b21b62a | 329 | env->cpsr = compute_cpsr(); |
7fe48483 | 330 | cpu_dump_state(env, logfile, fprintf, 0); |
99c475ab | 331 | env->cpsr &= ~CACHED_CPSR_BITS; |
93ac68bc | 332 | #elif defined(TARGET_SPARC) |
7fe48483 | 333 | cpu_dump_state (env, logfile, fprintf, 0); |
67867308 | 334 | #elif defined(TARGET_PPC) |
7fe48483 | 335 | cpu_dump_state(env, logfile, fprintf, 0); |
e4533c7a FB |
336 | #else |
337 | #error unsupported target CPU | |
338 | #endif | |
3fb2ded1 | 339 | } |
7d13299d | 340 | #endif |
3f337316 FB |
341 | /* we record a subset of the CPU state. It will |
342 | always be the same before a given translated block | |
343 | is executed. */ | |
e4533c7a | 344 | #if defined(TARGET_I386) |
2e255c6b | 345 | flags = env->hflags; |
3f337316 | 346 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
3fb2ded1 FB |
347 | cs_base = env->segs[R_CS].base; |
348 | pc = cs_base + env->eip; | |
e4533c7a | 349 | #elif defined(TARGET_ARM) |
99c475ab | 350 | flags = env->thumb; |
3fb2ded1 | 351 | cs_base = 0; |
c27004ec | 352 | pc = env->regs[15]; |
93ac68bc | 353 | #elif defined(TARGET_SPARC) |
67867308 | 354 | flags = 0; |
c27004ec FB |
355 | cs_base = env->npc; |
356 | pc = env->pc; | |
67867308 FB |
357 | #elif defined(TARGET_PPC) |
358 | flags = 0; | |
359 | cs_base = 0; | |
c27004ec | 360 | pc = env->nip; |
e4533c7a FB |
361 | #else |
362 | #error unsupported CPU | |
363 | #endif | |
c27004ec | 364 | tb = tb_find(&ptb, pc, cs_base, |
3fb2ded1 | 365 | flags); |
d4e8164f | 366 | if (!tb) { |
1376847f FB |
367 | TranslationBlock **ptb1; |
368 | unsigned int h; | |
369 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; | |
370 | ||
371 | ||
3fb2ded1 | 372 | spin_lock(&tb_lock); |
1376847f FB |
373 | |
374 | tb_invalidated_flag = 0; | |
0d1a29f9 FB |
375 | |
376 | regs_to_env(); /* XXX: do it just before cpu_gen_code() */ | |
1376847f FB |
377 | |
378 | /* find translated block using physical mappings */ | |
c27004ec | 379 | phys_pc = get_phys_addr_code(env, pc); |
1376847f FB |
380 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
381 | phys_page2 = -1; | |
382 | h = tb_phys_hash_func(phys_pc); | |
383 | ptb1 = &tb_phys_hash[h]; | |
384 | for(;;) { | |
385 | tb = *ptb1; | |
386 | if (!tb) | |
387 | goto not_found; | |
c27004ec | 388 | if (tb->pc == pc && |
1376847f | 389 | tb->page_addr[0] == phys_page1 && |
c27004ec | 390 | tb->cs_base == cs_base && |
1376847f FB |
391 | tb->flags == flags) { |
392 | /* check next page if needed */ | |
b516f85c | 393 | if (tb->page_addr[1] != -1) { |
c27004ec | 394 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
b516f85c | 395 | TARGET_PAGE_SIZE; |
1376847f FB |
396 | phys_page2 = get_phys_addr_code(env, virt_page2); |
397 | if (tb->page_addr[1] == phys_page2) | |
398 | goto found; | |
399 | } else { | |
400 | goto found; | |
401 | } | |
402 | } | |
403 | ptb1 = &tb->phys_hash_next; | |
404 | } | |
405 | not_found: | |
3fb2ded1 | 406 | /* if no translated code available, then translate it now */ |
c27004ec | 407 | tb = tb_alloc(pc); |
3fb2ded1 FB |
408 | if (!tb) { |
409 | /* flush must be done */ | |
b453b70b | 410 | tb_flush(env); |
3fb2ded1 | 411 | /* cannot fail at this point */ |
c27004ec | 412 | tb = tb_alloc(pc); |
3fb2ded1 | 413 | /* don't forget to invalidate previous TB info */ |
c27004ec | 414 | ptb = &tb_hash[tb_hash_func(pc)]; |
3fb2ded1 FB |
415 | T0 = 0; |
416 | } | |
417 | tc_ptr = code_gen_ptr; | |
418 | tb->tc_ptr = tc_ptr; | |
c27004ec | 419 | tb->cs_base = cs_base; |
3fb2ded1 | 420 | tb->flags = flags; |
facc68be | 421 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
1376847f FB |
422 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
423 | ||
424 | /* check next page if needed */ | |
c27004ec | 425 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
1376847f | 426 | phys_page2 = -1; |
c27004ec | 427 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
1376847f FB |
428 | phys_page2 = get_phys_addr_code(env, virt_page2); |
429 | } | |
430 | tb_link_phys(tb, phys_pc, phys_page2); | |
431 | ||
432 | found: | |
36bdbe54 FB |
433 | if (tb_invalidated_flag) { |
434 | /* as some TB could have been invalidated because | |
435 | of memory exceptions while generating the code, we | |
436 | must recompute the hash index here */ | |
c27004ec | 437 | ptb = &tb_hash[tb_hash_func(pc)]; |
36bdbe54 FB |
438 | while (*ptb != NULL) |
439 | ptb = &(*ptb)->hash_next; | |
440 | T0 = 0; | |
441 | } | |
1376847f | 442 | /* we add the TB in the virtual pc hash table */ |
3fb2ded1 FB |
443 | *ptb = tb; |
444 | tb->hash_next = NULL; | |
445 | tb_link(tb); | |
25eb4484 | 446 | spin_unlock(&tb_lock); |
9de5e440 | 447 | } |
9d27abd9 | 448 | #ifdef DEBUG_EXEC |
c1135f61 | 449 | if ((loglevel & CPU_LOG_EXEC)) { |
c27004ec FB |
450 | fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
451 | (long)tb->tc_ptr, tb->pc, | |
452 | lookup_symbol(tb->pc)); | |
3fb2ded1 | 453 | } |
9d27abd9 | 454 | #endif |
8c6939c0 | 455 | #ifdef __sparc__ |
3fb2ded1 | 456 | T0 = tmp_T0; |
8c6939c0 | 457 | #endif |
facc68be | 458 | /* see if we can patch the calling TB. */ |
c27004ec FB |
459 | { |
460 | if (T0 != 0 | |
bf3e8bf1 FB |
461 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) |
462 | && (tb->cflags & CF_CODE_COPY) == | |
463 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) | |
464 | #endif | |
465 | ) { | |
3fb2ded1 | 466 | spin_lock(&tb_lock); |
c27004ec | 467 | tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
97eb5b14 FB |
468 | #if defined(USE_CODE_COPY) |
469 | /* propagates the FP use info */ | |
470 | ((TranslationBlock *)(T0 & ~3))->cflags |= | |
471 | (tb->cflags & CF_FP_USED); | |
472 | #endif | |
3fb2ded1 FB |
473 | spin_unlock(&tb_lock); |
474 | } | |
c27004ec | 475 | } |
3fb2ded1 | 476 | tc_ptr = tb->tc_ptr; |
83479e77 | 477 | env->current_tb = tb; |
3fb2ded1 FB |
478 | /* execute the generated code */ |
479 | gen_func = (void *)tc_ptr; | |
8c6939c0 | 480 | #if defined(__sparc__) |
3fb2ded1 FB |
481 | __asm__ __volatile__("call %0\n\t" |
482 | "mov %%o7,%%i0" | |
483 | : /* no outputs */ | |
484 | : "r" (gen_func) | |
485 | : "i0", "i1", "i2", "i3", "i4", "i5"); | |
8c6939c0 | 486 | #elif defined(__arm__) |
3fb2ded1 FB |
487 | asm volatile ("mov pc, %0\n\t" |
488 | ".global exec_loop\n\t" | |
489 | "exec_loop:\n\t" | |
490 | : /* no outputs */ | |
491 | : "r" (gen_func) | |
492 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); | |
bf3e8bf1 FB |
493 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
494 | { | |
495 | if (!(tb->cflags & CF_CODE_COPY)) { | |
97eb5b14 FB |
496 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
497 | save_native_fp_state(env); | |
498 | } | |
bf3e8bf1 FB |
499 | gen_func(); |
500 | } else { | |
97eb5b14 FB |
501 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
502 | restore_native_fp_state(env); | |
503 | } | |
bf3e8bf1 FB |
504 | /* we work with native eflags */ |
505 | CC_SRC = cc_table[CC_OP].compute_all(); | |
506 | CC_OP = CC_OP_EFLAGS; | |
507 | asm(".globl exec_loop\n" | |
508 | "\n" | |
509 | "debug1:\n" | |
510 | " pushl %%ebp\n" | |
511 | " fs movl %10, %9\n" | |
512 | " fs movl %11, %%eax\n" | |
513 | " andl $0x400, %%eax\n" | |
514 | " fs orl %8, %%eax\n" | |
515 | " pushl %%eax\n" | |
516 | " popf\n" | |
517 | " fs movl %%esp, %12\n" | |
518 | " fs movl %0, %%eax\n" | |
519 | " fs movl %1, %%ecx\n" | |
520 | " fs movl %2, %%edx\n" | |
521 | " fs movl %3, %%ebx\n" | |
522 | " fs movl %4, %%esp\n" | |
523 | " fs movl %5, %%ebp\n" | |
524 | " fs movl %6, %%esi\n" | |
525 | " fs movl %7, %%edi\n" | |
526 | " fs jmp *%9\n" | |
527 | "exec_loop:\n" | |
528 | " fs movl %%esp, %4\n" | |
529 | " fs movl %12, %%esp\n" | |
530 | " fs movl %%eax, %0\n" | |
531 | " fs movl %%ecx, %1\n" | |
532 | " fs movl %%edx, %2\n" | |
533 | " fs movl %%ebx, %3\n" | |
534 | " fs movl %%ebp, %5\n" | |
535 | " fs movl %%esi, %6\n" | |
536 | " fs movl %%edi, %7\n" | |
537 | " pushf\n" | |
538 | " popl %%eax\n" | |
539 | " movl %%eax, %%ecx\n" | |
540 | " andl $0x400, %%ecx\n" | |
541 | " shrl $9, %%ecx\n" | |
542 | " andl $0x8d5, %%eax\n" | |
543 | " fs movl %%eax, %8\n" | |
544 | " movl $1, %%eax\n" | |
545 | " subl %%ecx, %%eax\n" | |
546 | " fs movl %%eax, %11\n" | |
547 | " fs movl %9, %%ebx\n" /* get T0 value */ | |
548 | " popl %%ebp\n" | |
549 | : | |
550 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), | |
551 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), | |
552 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), | |
553 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), | |
554 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), | |
555 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), | |
556 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), | |
557 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), | |
558 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), | |
559 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), | |
560 | "a" (gen_func), | |
561 | "m" (*(uint8_t *)offsetof(CPUState, df)), | |
562 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) | |
563 | : "%ecx", "%edx" | |
564 | ); | |
565 | } | |
566 | } | |
ae228531 | 567 | #else |
3fb2ded1 | 568 | gen_func(); |
ae228531 | 569 | #endif |
83479e77 | 570 | env->current_tb = NULL; |
4cbf74b6 FB |
571 | /* reset soft MMU for next block (it can currently |
572 | only be set by a memory fault) */ | |
573 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) | |
3f337316 FB |
574 | if (env->hflags & HF_SOFTMMU_MASK) { |
575 | env->hflags &= ~HF_SOFTMMU_MASK; | |
4cbf74b6 FB |
576 | /* do not allow linking to another block */ |
577 | T0 = 0; | |
578 | } | |
579 | #endif | |
3fb2ded1 FB |
580 | } |
581 | } else { | |
0d1a29f9 | 582 | env_to_regs(); |
7d13299d | 583 | } |
3fb2ded1 FB |
584 | } /* for(;;) */ |
585 | ||
7d13299d | 586 | |
e4533c7a | 587 | #if defined(TARGET_I386) |
97eb5b14 FB |
588 | #if defined(USE_CODE_COPY) |
589 | if (env->native_fp_regs) { | |
590 | save_native_fp_state(env); | |
591 | } | |
592 | #endif | |
9de5e440 | 593 | /* restore flags in standard format */ |
fc2b4c48 | 594 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
9de5e440 | 595 | |
7d13299d | 596 | /* restore global registers */ |
04369ff2 FB |
597 | #ifdef reg_EAX |
598 | EAX = saved_EAX; | |
599 | #endif | |
600 | #ifdef reg_ECX | |
601 | ECX = saved_ECX; | |
602 | #endif | |
603 | #ifdef reg_EDX | |
604 | EDX = saved_EDX; | |
605 | #endif | |
606 | #ifdef reg_EBX | |
607 | EBX = saved_EBX; | |
608 | #endif | |
609 | #ifdef reg_ESP | |
610 | ESP = saved_ESP; | |
611 | #endif | |
612 | #ifdef reg_EBP | |
613 | EBP = saved_EBP; | |
614 | #endif | |
615 | #ifdef reg_ESI | |
616 | ESI = saved_ESI; | |
617 | #endif | |
618 | #ifdef reg_EDI | |
619 | EDI = saved_EDI; | |
8c6939c0 | 620 | #endif |
e4533c7a | 621 | #elif defined(TARGET_ARM) |
1b21b62a | 622 | env->cpsr = compute_cpsr(); |
93ac68bc | 623 | #elif defined(TARGET_SPARC) |
67867308 | 624 | #elif defined(TARGET_PPC) |
e4533c7a FB |
625 | #else |
626 | #error unsupported target CPU | |
627 | #endif | |
8c6939c0 FB |
628 | #ifdef __sparc__ |
629 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); | |
04369ff2 | 630 | #endif |
7d13299d FB |
631 | T0 = saved_T0; |
632 | T1 = saved_T1; | |
e4533c7a | 633 | T2 = saved_T2; |
7d13299d FB |
634 | env = saved_env; |
635 | return ret; | |
636 | } | |
6dbad63e | 637 | |
fbf9eeb3 FB |
638 | /* must only be called from the generated code as an exception can be |
639 | generated */ | |
640 | void tb_invalidate_page_range(target_ulong start, target_ulong end) | |
641 | { | |
dc5d0b3d FB |
642 | /* XXX: cannot enable it yet because it yields to MMU exception |
643 | where NIP != read address on PowerPC */ | |
644 | #if 0 | |
fbf9eeb3 FB |
645 | target_ulong phys_addr; |
646 | phys_addr = get_phys_addr_code(env, start); | |
647 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); | |
dc5d0b3d | 648 | #endif |
fbf9eeb3 FB |
649 | } |
650 | ||
1a18c71b | 651 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 652 | |
6dbad63e FB |
653 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
654 | { | |
655 | CPUX86State *saved_env; | |
656 | ||
657 | saved_env = env; | |
658 | env = s; | |
a412ac57 | 659 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 660 | selector &= 0xffff; |
2e255c6b | 661 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
c27004ec | 662 | (selector << 4), 0xffff, 0); |
a513fe19 | 663 | } else { |
b453b70b | 664 | load_seg(seg_reg, selector); |
a513fe19 | 665 | } |
6dbad63e FB |
666 | env = saved_env; |
667 | } | |
9de5e440 | 668 | |
d0a1ffc9 FB |
669 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
670 | { | |
671 | CPUX86State *saved_env; | |
672 | ||
673 | saved_env = env; | |
674 | env = s; | |
675 | ||
c27004ec | 676 | helper_fsave((target_ulong)ptr, data32); |
d0a1ffc9 FB |
677 | |
678 | env = saved_env; | |
679 | } | |
680 | ||
681 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) | |
682 | { | |
683 | CPUX86State *saved_env; | |
684 | ||
685 | saved_env = env; | |
686 | env = s; | |
687 | ||
c27004ec | 688 | helper_frstor((target_ulong)ptr, data32); |
d0a1ffc9 FB |
689 | |
690 | env = saved_env; | |
691 | } | |
692 | ||
e4533c7a FB |
693 | #endif /* TARGET_I386 */ |
694 | ||
67b915a5 FB |
695 | #if !defined(CONFIG_SOFTMMU) |
696 | ||
3fb2ded1 FB |
697 | #if defined(TARGET_I386) |
698 | ||
b56dad1c | 699 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
700 | the effective address of the memory exception. 'is_write' is 1 if a |
701 | write caused the exception and otherwise 0'. 'old_set' is the | |
702 | signal set which should be restored */ | |
2b413144 | 703 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
704 | int is_write, sigset_t *old_set, |
705 | void *puc) | |
9de5e440 | 706 | { |
a513fe19 FB |
707 | TranslationBlock *tb; |
708 | int ret; | |
68a79315 | 709 | |
83479e77 FB |
710 | if (cpu_single_env) |
711 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 712 | #if defined(DEBUG_SIGNAL) |
bf3e8bf1 FB |
713 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
714 | pc, address, is_write, *(unsigned long *)old_set); | |
9de5e440 | 715 | #endif |
25eb4484 | 716 | /* XXX: locking issue */ |
fbf9eeb3 | 717 | if (is_write && page_unprotect(address, pc, puc)) { |
fd6ce8f6 FB |
718 | return 1; |
719 | } | |
fbf9eeb3 | 720 | |
3fb2ded1 | 721 | /* see if it is an MMU fault */ |
93a40ea9 FB |
722 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
723 | ((env->hflags & HF_CPL_MASK) == 3), 0); | |
3fb2ded1 FB |
724 | if (ret < 0) |
725 | return 0; /* not an MMU fault */ | |
726 | if (ret == 0) | |
727 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
728 | /* now we have a real cpu fault */ | |
a513fe19 FB |
729 | tb = tb_find_pc(pc); |
730 | if (tb) { | |
9de5e440 FB |
731 | /* the PC is inside the translated code. It means that we have |
732 | a virtual CPU fault */ | |
bf3e8bf1 | 733 | cpu_restore_state(tb, env, pc, puc); |
3fb2ded1 | 734 | } |
4cbf74b6 | 735 | if (ret == 1) { |
3fb2ded1 | 736 | #if 0 |
4cbf74b6 FB |
737 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
738 | env->eip, env->cr[2], env->error_code); | |
3fb2ded1 | 739 | #endif |
4cbf74b6 FB |
740 | /* we restore the process signal mask as the sigreturn should |
741 | do it (XXX: use sigsetjmp) */ | |
742 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
743 | raise_exception_err(EXCP0E_PAGE, env->error_code); | |
744 | } else { | |
745 | /* activate soft MMU for this block */ | |
3f337316 | 746 | env->hflags |= HF_SOFTMMU_MASK; |
fbf9eeb3 | 747 | cpu_resume_from_signal(env, puc); |
4cbf74b6 | 748 | } |
3fb2ded1 FB |
749 | /* never comes here */ |
750 | return 1; | |
751 | } | |
752 | ||
e4533c7a | 753 | #elif defined(TARGET_ARM) |
3fb2ded1 | 754 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
755 | int is_write, sigset_t *old_set, |
756 | void *puc) | |
3fb2ded1 | 757 | { |
68016c62 FB |
758 | TranslationBlock *tb; |
759 | int ret; | |
760 | ||
761 | if (cpu_single_env) | |
762 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
763 | #if defined(DEBUG_SIGNAL) | |
764 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
765 | pc, address, is_write, *(unsigned long *)old_set); | |
766 | #endif | |
9f0777ed FB |
767 | /* XXX: locking issue */ |
768 | if (is_write && page_unprotect(address, pc, puc)) { | |
769 | return 1; | |
770 | } | |
68016c62 FB |
771 | /* see if it is an MMU fault */ |
772 | ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); | |
773 | if (ret < 0) | |
774 | return 0; /* not an MMU fault */ | |
775 | if (ret == 0) | |
776 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
777 | /* now we have a real cpu fault */ | |
778 | tb = tb_find_pc(pc); | |
779 | if (tb) { | |
780 | /* the PC is inside the translated code. It means that we have | |
781 | a virtual CPU fault */ | |
782 | cpu_restore_state(tb, env, pc, puc); | |
783 | } | |
784 | /* we restore the process signal mask as the sigreturn should | |
785 | do it (XXX: use sigsetjmp) */ | |
786 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
787 | cpu_loop_exit(); | |
3fb2ded1 | 788 | } |
93ac68bc FB |
789 | #elif defined(TARGET_SPARC) |
790 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
791 | int is_write, sigset_t *old_set, |
792 | void *puc) | |
93ac68bc | 793 | { |
68016c62 FB |
794 | TranslationBlock *tb; |
795 | int ret; | |
796 | ||
797 | if (cpu_single_env) | |
798 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
799 | #if defined(DEBUG_SIGNAL) | |
800 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
801 | pc, address, is_write, *(unsigned long *)old_set); | |
802 | #endif | |
b453b70b | 803 | /* XXX: locking issue */ |
fbf9eeb3 | 804 | if (is_write && page_unprotect(address, pc, puc)) { |
b453b70b FB |
805 | return 1; |
806 | } | |
68016c62 FB |
807 | /* see if it is an MMU fault */ |
808 | ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); | |
809 | if (ret < 0) | |
810 | return 0; /* not an MMU fault */ | |
811 | if (ret == 0) | |
812 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
813 | /* now we have a real cpu fault */ | |
814 | tb = tb_find_pc(pc); | |
815 | if (tb) { | |
816 | /* the PC is inside the translated code. It means that we have | |
817 | a virtual CPU fault */ | |
818 | cpu_restore_state(tb, env, pc, puc); | |
819 | } | |
820 | /* we restore the process signal mask as the sigreturn should | |
821 | do it (XXX: use sigsetjmp) */ | |
822 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
823 | cpu_loop_exit(); | |
93ac68bc | 824 | } |
67867308 FB |
825 | #elif defined (TARGET_PPC) |
826 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
827 | int is_write, sigset_t *old_set, |
828 | void *puc) | |
67867308 FB |
829 | { |
830 | TranslationBlock *tb; | |
ce09776b | 831 | int ret; |
67867308 | 832 | |
67867308 FB |
833 | if (cpu_single_env) |
834 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
67867308 FB |
835 | #if defined(DEBUG_SIGNAL) |
836 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
837 | pc, address, is_write, *(unsigned long *)old_set); | |
838 | #endif | |
839 | /* XXX: locking issue */ | |
fbf9eeb3 | 840 | if (is_write && page_unprotect(address, pc, puc)) { |
67867308 FB |
841 | return 1; |
842 | } | |
843 | ||
ce09776b | 844 | /* see if it is an MMU fault */ |
7f957d28 | 845 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
ce09776b FB |
846 | if (ret < 0) |
847 | return 0; /* not an MMU fault */ | |
848 | if (ret == 0) | |
849 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
850 | ||
67867308 FB |
851 | /* now we have a real cpu fault */ |
852 | tb = tb_find_pc(pc); | |
853 | if (tb) { | |
854 | /* the PC is inside the translated code. It means that we have | |
855 | a virtual CPU fault */ | |
bf3e8bf1 | 856 | cpu_restore_state(tb, env, pc, puc); |
67867308 | 857 | } |
ce09776b | 858 | if (ret == 1) { |
67867308 | 859 | #if 0 |
ce09776b FB |
860 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
861 | env->nip, env->error_code, tb); | |
67867308 FB |
862 | #endif |
863 | /* we restore the process signal mask as the sigreturn should | |
864 | do it (XXX: use sigsetjmp) */ | |
bf3e8bf1 | 865 | sigprocmask(SIG_SETMASK, old_set, NULL); |
9fddaa0c | 866 | do_raise_exception_err(env->exception_index, env->error_code); |
ce09776b FB |
867 | } else { |
868 | /* activate soft MMU for this block */ | |
fbf9eeb3 | 869 | cpu_resume_from_signal(env, puc); |
ce09776b | 870 | } |
67867308 FB |
871 | /* never comes here */ |
872 | return 1; | |
873 | } | |
e4533c7a FB |
874 | #else |
875 | #error unsupported target CPU | |
876 | #endif | |
9de5e440 | 877 | |
2b413144 FB |
878 | #if defined(__i386__) |
879 | ||
bf3e8bf1 FB |
880 | #if defined(USE_CODE_COPY) |
881 | static void cpu_send_trap(unsigned long pc, int trap, | |
882 | struct ucontext *uc) | |
883 | { | |
884 | TranslationBlock *tb; | |
885 | ||
886 | if (cpu_single_env) | |
887 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
888 | /* now we have a real cpu fault */ | |
889 | tb = tb_find_pc(pc); | |
890 | if (tb) { | |
891 | /* the PC is inside the translated code. It means that we have | |
892 | a virtual CPU fault */ | |
893 | cpu_restore_state(tb, env, pc, uc); | |
894 | } | |
895 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
896 | raise_exception_err(trap, env->error_code); | |
897 | } | |
898 | #endif | |
899 | ||
e4533c7a FB |
900 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
901 | void *puc) | |
9de5e440 | 902 | { |
9de5e440 FB |
903 | struct ucontext *uc = puc; |
904 | unsigned long pc; | |
bf3e8bf1 | 905 | int trapno; |
97eb5b14 | 906 | |
d691f669 FB |
907 | #ifndef REG_EIP |
908 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
909 | #define REG_EIP EIP |
910 | #define REG_ERR ERR | |
911 | #define REG_TRAPNO TRAPNO | |
d691f669 | 912 | #endif |
fc2b4c48 | 913 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bf3e8bf1 FB |
914 | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
915 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) | |
916 | if (trapno == 0x00 || trapno == 0x05) { | |
917 | /* send division by zero or bound exception */ | |
918 | cpu_send_trap(pc, trapno, uc); | |
919 | return 1; | |
920 | } else | |
921 | #endif | |
922 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
923 | trapno == 0xe ? | |
924 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
925 | &uc->uc_sigmask, puc); | |
2b413144 FB |
926 | } |
927 | ||
bc51c5c9 FB |
928 | #elif defined(__x86_64__) |
929 | ||
930 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
931 | void *puc) | |
932 | { | |
933 | struct ucontext *uc = puc; | |
934 | unsigned long pc; | |
935 | ||
936 | pc = uc->uc_mcontext.gregs[REG_RIP]; | |
937 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
938 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
939 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
940 | &uc->uc_sigmask, puc); | |
941 | } | |
942 | ||
83fb7adf | 943 | #elif defined(__powerpc__) |
2b413144 | 944 | |
83fb7adf FB |
945 | /*********************************************************************** |
946 | * signal context platform-specific definitions | |
947 | * From Wine | |
948 | */ | |
949 | #ifdef linux | |
950 | /* All Registers access - only for local access */ | |
951 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) | |
952 | /* Gpr Registers access */ | |
953 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
954 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ | |
955 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ | |
956 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ | |
957 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ | |
958 | # define LR_sig(context) REG_sig(link, context) /* Link register */ | |
959 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ | |
960 | /* Float Registers access */ | |
961 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) | |
962 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) | |
963 | /* Exception Registers access */ | |
964 | # define DAR_sig(context) REG_sig(dar, context) | |
965 | # define DSISR_sig(context) REG_sig(dsisr, context) | |
966 | # define TRAP_sig(context) REG_sig(trap, context) | |
967 | #endif /* linux */ | |
968 | ||
969 | #ifdef __APPLE__ | |
970 | # include <sys/ucontext.h> | |
971 | typedef struct ucontext SIGCONTEXT; | |
972 | /* All Registers access - only for local access */ | |
973 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) | |
974 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) | |
975 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) | |
976 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) | |
977 | /* Gpr Registers access */ | |
978 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) | |
979 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ | |
980 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ | |
981 | # define CTR_sig(context) REG_sig(ctr, context) | |
982 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ | |
983 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ | |
984 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ | |
985 | /* Float Registers access */ | |
986 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) | |
987 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) | |
988 | /* Exception Registers access */ | |
989 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ | |
990 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) | |
991 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ | |
992 | #endif /* __APPLE__ */ | |
993 | ||
d1d9f421 | 994 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
e4533c7a | 995 | void *puc) |
2b413144 | 996 | { |
25eb4484 | 997 | struct ucontext *uc = puc; |
25eb4484 | 998 | unsigned long pc; |
25eb4484 FB |
999 | int is_write; |
1000 | ||
83fb7adf | 1001 | pc = IAR_sig(uc); |
25eb4484 FB |
1002 | is_write = 0; |
1003 | #if 0 | |
1004 | /* ppc 4xx case */ | |
83fb7adf | 1005 | if (DSISR_sig(uc) & 0x00800000) |
25eb4484 FB |
1006 | is_write = 1; |
1007 | #else | |
83fb7adf | 1008 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
25eb4484 FB |
1009 | is_write = 1; |
1010 | #endif | |
1011 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1012 | is_write, &uc->uc_sigmask, puc); |
2b413144 FB |
1013 | } |
1014 | ||
2f87c607 FB |
1015 | #elif defined(__alpha__) |
1016 | ||
e4533c7a | 1017 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
2f87c607 FB |
1018 | void *puc) |
1019 | { | |
1020 | struct ucontext *uc = puc; | |
1021 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
1022 | uint32_t insn = *pc; | |
1023 | int is_write = 0; | |
1024 | ||
8c6939c0 | 1025 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
1026 | switch (insn >> 26) { |
1027 | case 0x0d: // stw | |
1028 | case 0x0e: // stb | |
1029 | case 0x0f: // stq_u | |
1030 | case 0x24: // stf | |
1031 | case 0x25: // stg | |
1032 | case 0x26: // sts | |
1033 | case 0x27: // stt | |
1034 | case 0x2c: // stl | |
1035 | case 0x2d: // stq | |
1036 | case 0x2e: // stl_c | |
1037 | case 0x2f: // stq_c | |
1038 | is_write = 1; | |
1039 | } | |
1040 | ||
1041 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1042 | is_write, &uc->uc_sigmask, puc); |
2f87c607 | 1043 | } |
8c6939c0 FB |
1044 | #elif defined(__sparc__) |
1045 | ||
e4533c7a FB |
1046 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1047 | void *puc) | |
8c6939c0 FB |
1048 | { |
1049 | uint32_t *regs = (uint32_t *)(info + 1); | |
1050 | void *sigmask = (regs + 20); | |
1051 | unsigned long pc; | |
1052 | int is_write; | |
1053 | uint32_t insn; | |
1054 | ||
1055 | /* XXX: is there a standard glibc define ? */ | |
1056 | pc = regs[1]; | |
1057 | /* XXX: need kernel patch to get write flag faster */ | |
1058 | is_write = 0; | |
1059 | insn = *(uint32_t *)pc; | |
1060 | if ((insn >> 30) == 3) { | |
1061 | switch((insn >> 19) & 0x3f) { | |
1062 | case 0x05: // stb | |
1063 | case 0x06: // sth | |
1064 | case 0x04: // st | |
1065 | case 0x07: // std | |
1066 | case 0x24: // stf | |
1067 | case 0x27: // stdf | |
1068 | case 0x25: // stfsr | |
1069 | is_write = 1; | |
1070 | break; | |
1071 | } | |
1072 | } | |
1073 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 1074 | is_write, sigmask, NULL); |
8c6939c0 FB |
1075 | } |
1076 | ||
1077 | #elif defined(__arm__) | |
1078 | ||
e4533c7a FB |
1079 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1080 | void *puc) | |
8c6939c0 FB |
1081 | { |
1082 | struct ucontext *uc = puc; | |
1083 | unsigned long pc; | |
1084 | int is_write; | |
1085 | ||
1086 | pc = uc->uc_mcontext.gregs[R15]; | |
1087 | /* XXX: compute is_write */ | |
1088 | is_write = 0; | |
1089 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1090 | is_write, | |
1091 | &uc->uc_sigmask); | |
1092 | } | |
1093 | ||
38e584a0 FB |
1094 | #elif defined(__mc68000) |
1095 | ||
1096 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
1097 | void *puc) | |
1098 | { | |
1099 | struct ucontext *uc = puc; | |
1100 | unsigned long pc; | |
1101 | int is_write; | |
1102 | ||
1103 | pc = uc->uc_mcontext.gregs[16]; | |
1104 | /* XXX: compute is_write */ | |
1105 | is_write = 0; | |
1106 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1107 | is_write, | |
bf3e8bf1 | 1108 | &uc->uc_sigmask, puc); |
38e584a0 FB |
1109 | } |
1110 | ||
9de5e440 | 1111 | #else |
2b413144 | 1112 | |
3fb2ded1 | 1113 | #error host CPU specific signal handler needed |
2b413144 | 1114 | |
9de5e440 | 1115 | #endif |
67b915a5 FB |
1116 | |
1117 | #endif /* !defined(CONFIG_SOFTMMU) */ |