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7d13299d FB |
1 | /* |
2 | * i386 emulator main execution loop | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
3ef693a0 FB |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
7d13299d | 10 | * |
3ef693a0 FB |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
7d13299d | 15 | * |
3ef693a0 FB |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
7d13299d | 19 | */ |
e4533c7a | 20 | #include "config.h" |
93ac68bc | 21 | #include "exec.h" |
956034d7 | 22 | #include "disas.h" |
7d13299d | 23 | |
fbf9eeb3 FB |
24 | #if !defined(CONFIG_SOFTMMU) |
25 | #undef EAX | |
26 | #undef ECX | |
27 | #undef EDX | |
28 | #undef EBX | |
29 | #undef ESP | |
30 | #undef EBP | |
31 | #undef ESI | |
32 | #undef EDI | |
33 | #undef EIP | |
34 | #include <signal.h> | |
35 | #include <sys/ucontext.h> | |
36 | #endif | |
37 | ||
36bdbe54 FB |
38 | int tb_invalidated_flag; |
39 | ||
dc99065b | 40 | //#define DEBUG_EXEC |
9de5e440 | 41 | //#define DEBUG_SIGNAL |
7d13299d | 42 | |
93ac68bc | 43 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) |
e4533c7a FB |
44 | /* XXX: unify with i386 target */ |
45 | void cpu_loop_exit(void) | |
46 | { | |
47 | longjmp(env->jmp_env, 1); | |
48 | } | |
49 | #endif | |
50 | ||
fbf9eeb3 FB |
51 | /* exit the current TB from a signal handler. The host registers are |
52 | restored in a state compatible with the CPU emulator | |
53 | */ | |
54 | void cpu_resume_from_signal(CPUState *env1, void *puc) | |
55 | { | |
56 | #if !defined(CONFIG_SOFTMMU) | |
57 | struct ucontext *uc = puc; | |
58 | #endif | |
59 | ||
60 | env = env1; | |
61 | ||
62 | /* XXX: restore cpu registers saved in host registers */ | |
63 | ||
64 | #if !defined(CONFIG_SOFTMMU) | |
65 | if (puc) { | |
66 | /* XXX: use siglongjmp ? */ | |
67 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
68 | } | |
69 | #endif | |
70 | longjmp(env->jmp_env, 1); | |
71 | } | |
72 | ||
7d13299d FB |
73 | /* main execution loop */ |
74 | ||
e4533c7a | 75 | int cpu_exec(CPUState *env1) |
7d13299d | 76 | { |
e4533c7a FB |
77 | int saved_T0, saved_T1, saved_T2; |
78 | CPUState *saved_env; | |
04369ff2 FB |
79 | #ifdef reg_EAX |
80 | int saved_EAX; | |
81 | #endif | |
82 | #ifdef reg_ECX | |
83 | int saved_ECX; | |
84 | #endif | |
85 | #ifdef reg_EDX | |
86 | int saved_EDX; | |
87 | #endif | |
88 | #ifdef reg_EBX | |
89 | int saved_EBX; | |
90 | #endif | |
91 | #ifdef reg_ESP | |
92 | int saved_ESP; | |
93 | #endif | |
94 | #ifdef reg_EBP | |
95 | int saved_EBP; | |
96 | #endif | |
97 | #ifdef reg_ESI | |
98 | int saved_ESI; | |
99 | #endif | |
100 | #ifdef reg_EDI | |
101 | int saved_EDI; | |
8c6939c0 FB |
102 | #endif |
103 | #ifdef __sparc__ | |
104 | int saved_i7, tmp_T0; | |
04369ff2 | 105 | #endif |
68a79315 | 106 | int code_gen_size, ret, interrupt_request; |
7d13299d | 107 | void (*gen_func)(void); |
9de5e440 | 108 | TranslationBlock *tb, **ptb; |
dab2ed99 | 109 | uint8_t *tc_ptr, *cs_base, *pc; |
6dbad63e | 110 | unsigned int flags; |
8c6939c0 | 111 | |
7d13299d FB |
112 | /* first we save global registers */ |
113 | saved_T0 = T0; | |
114 | saved_T1 = T1; | |
e4533c7a | 115 | saved_T2 = T2; |
7d13299d FB |
116 | saved_env = env; |
117 | env = env1; | |
e4533c7a FB |
118 | #ifdef __sparc__ |
119 | /* we also save i7 because longjmp may not restore it */ | |
120 | asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); | |
121 | #endif | |
122 | ||
123 | #if defined(TARGET_I386) | |
04369ff2 FB |
124 | #ifdef reg_EAX |
125 | saved_EAX = EAX; | |
126 | EAX = env->regs[R_EAX]; | |
127 | #endif | |
128 | #ifdef reg_ECX | |
129 | saved_ECX = ECX; | |
130 | ECX = env->regs[R_ECX]; | |
131 | #endif | |
132 | #ifdef reg_EDX | |
133 | saved_EDX = EDX; | |
134 | EDX = env->regs[R_EDX]; | |
135 | #endif | |
136 | #ifdef reg_EBX | |
137 | saved_EBX = EBX; | |
138 | EBX = env->regs[R_EBX]; | |
139 | #endif | |
140 | #ifdef reg_ESP | |
141 | saved_ESP = ESP; | |
142 | ESP = env->regs[R_ESP]; | |
143 | #endif | |
144 | #ifdef reg_EBP | |
145 | saved_EBP = EBP; | |
146 | EBP = env->regs[R_EBP]; | |
147 | #endif | |
148 | #ifdef reg_ESI | |
149 | saved_ESI = ESI; | |
150 | ESI = env->regs[R_ESI]; | |
151 | #endif | |
152 | #ifdef reg_EDI | |
153 | saved_EDI = EDI; | |
154 | EDI = env->regs[R_EDI]; | |
155 | #endif | |
7d13299d | 156 | |
9de5e440 | 157 | /* put eflags in CPU temporary format */ |
fc2b4c48 FB |
158 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
159 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); | |
9de5e440 | 160 | CC_OP = CC_OP_EFLAGS; |
fc2b4c48 | 161 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a FB |
162 | #elif defined(TARGET_ARM) |
163 | { | |
164 | unsigned int psr; | |
165 | psr = env->cpsr; | |
166 | env->CF = (psr >> 29) & 1; | |
167 | env->NZF = (psr & 0xc0000000) ^ 0x40000000; | |
168 | env->VF = (psr << 3) & 0x80000000; | |
169 | env->cpsr = psr & ~0xf0000000; | |
170 | } | |
93ac68bc | 171 | #elif defined(TARGET_SPARC) |
67867308 | 172 | #elif defined(TARGET_PPC) |
e4533c7a FB |
173 | #else |
174 | #error unsupported target CPU | |
175 | #endif | |
3fb2ded1 | 176 | env->exception_index = -1; |
9d27abd9 | 177 | |
7d13299d | 178 | /* prepare setjmp context for exception handling */ |
3fb2ded1 FB |
179 | for(;;) { |
180 | if (setjmp(env->jmp_env) == 0) { | |
ee8b7021 | 181 | env->current_tb = NULL; |
3fb2ded1 FB |
182 | /* if an exception is pending, we execute it here */ |
183 | if (env->exception_index >= 0) { | |
184 | if (env->exception_index >= EXCP_INTERRUPT) { | |
185 | /* exit request from the cpu execution loop */ | |
186 | ret = env->exception_index; | |
187 | break; | |
188 | } else if (env->user_mode_only) { | |
189 | /* if user mode only, we simulate a fake exception | |
190 | which will be hanlded outside the cpu execution | |
191 | loop */ | |
83479e77 | 192 | #if defined(TARGET_I386) |
3fb2ded1 FB |
193 | do_interrupt_user(env->exception_index, |
194 | env->exception_is_int, | |
195 | env->error_code, | |
196 | env->exception_next_eip); | |
83479e77 | 197 | #endif |
3fb2ded1 FB |
198 | ret = env->exception_index; |
199 | break; | |
200 | } else { | |
83479e77 | 201 | #if defined(TARGET_I386) |
3fb2ded1 FB |
202 | /* simulate a real cpu exception. On i386, it can |
203 | trigger new exceptions, but we do not handle | |
204 | double or triple faults yet. */ | |
205 | do_interrupt(env->exception_index, | |
206 | env->exception_is_int, | |
207 | env->error_code, | |
d05e66d2 | 208 | env->exception_next_eip, 0); |
ce09776b FB |
209 | #elif defined(TARGET_PPC) |
210 | do_interrupt(env); | |
e95c8d51 FB |
211 | #elif defined(TARGET_SPARC) |
212 | do_interrupt(env->exception_index, | |
213 | 0, | |
214 | env->error_code, | |
215 | env->exception_next_pc, 0); | |
83479e77 | 216 | #endif |
3fb2ded1 FB |
217 | } |
218 | env->exception_index = -1; | |
219 | } | |
3fb2ded1 FB |
220 | T0 = 0; /* force lookup of first TB */ |
221 | for(;;) { | |
8c6939c0 | 222 | #ifdef __sparc__ |
3fb2ded1 FB |
223 | /* g1 can be modified by some libc? functions */ |
224 | tmp_T0 = T0; | |
8c6939c0 | 225 | #endif |
68a79315 | 226 | interrupt_request = env->interrupt_request; |
2e255c6b | 227 | if (__builtin_expect(interrupt_request, 0)) { |
68a79315 FB |
228 | #if defined(TARGET_I386) |
229 | /* if hardware interrupt pending, we execute it */ | |
230 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
3f337316 FB |
231 | (env->eflags & IF_MASK) && |
232 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { | |
68a79315 | 233 | int intno; |
fbf9eeb3 | 234 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
a541f297 | 235 | intno = cpu_get_pic_interrupt(env); |
f193c797 | 236 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
68a79315 FB |
237 | fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); |
238 | } | |
d05e66d2 | 239 | do_interrupt(intno, 0, 0, 0, 1); |
907a5b26 FB |
240 | /* ensure that no TB jump will be modified as |
241 | the program flow was changed */ | |
242 | #ifdef __sparc__ | |
243 | tmp_T0 = 0; | |
244 | #else | |
245 | T0 = 0; | |
246 | #endif | |
68a79315 | 247 | } |
ce09776b | 248 | #elif defined(TARGET_PPC) |
9fddaa0c FB |
249 | #if 0 |
250 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { | |
251 | cpu_ppc_reset(env); | |
252 | } | |
253 | #endif | |
254 | if (msr_ee != 0) { | |
ce09776b | 255 | if ((interrupt_request & CPU_INTERRUPT_HARD)) { |
9fddaa0c FB |
256 | /* Raise it */ |
257 | env->exception_index = EXCP_EXTERNAL; | |
258 | env->error_code = 0; | |
ce09776b FB |
259 | do_interrupt(env); |
260 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
9fddaa0c FB |
261 | } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
262 | /* Raise it */ | |
263 | env->exception_index = EXCP_DECR; | |
264 | env->error_code = 0; | |
265 | do_interrupt(env); | |
266 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
267 | } | |
ce09776b | 268 | } |
e95c8d51 FB |
269 | #elif defined(TARGET_SPARC) |
270 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
271 | do_interrupt(0, 0, 0, 0, 0); | |
272 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
273 | } else if (interrupt_request & CPU_INTERRUPT_TIMER) { | |
274 | //do_interrupt(0, 0, 0, 0, 0); | |
275 | env->interrupt_request &= ~CPU_INTERRUPT_TIMER; | |
276 | } | |
68a79315 | 277 | #endif |
bf3e8bf1 FB |
278 | if (interrupt_request & CPU_INTERRUPT_EXITTB) { |
279 | env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; | |
280 | /* ensure that no TB jump will be modified as | |
281 | the program flow was changed */ | |
282 | #ifdef __sparc__ | |
283 | tmp_T0 = 0; | |
284 | #else | |
285 | T0 = 0; | |
286 | #endif | |
287 | } | |
68a79315 FB |
288 | if (interrupt_request & CPU_INTERRUPT_EXIT) { |
289 | env->interrupt_request &= ~CPU_INTERRUPT_EXIT; | |
290 | env->exception_index = EXCP_INTERRUPT; | |
291 | cpu_loop_exit(); | |
292 | } | |
3fb2ded1 | 293 | } |
7d13299d | 294 | #ifdef DEBUG_EXEC |
f193c797 | 295 | if (loglevel & CPU_LOG_EXEC) { |
e4533c7a | 296 | #if defined(TARGET_I386) |
3fb2ded1 FB |
297 | /* restore flags in standard format */ |
298 | env->regs[R_EAX] = EAX; | |
299 | env->regs[R_EBX] = EBX; | |
300 | env->regs[R_ECX] = ECX; | |
301 | env->regs[R_EDX] = EDX; | |
302 | env->regs[R_ESI] = ESI; | |
303 | env->regs[R_EDI] = EDI; | |
304 | env->regs[R_EBP] = EBP; | |
305 | env->regs[R_ESP] = ESP; | |
306 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
68a79315 | 307 | cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); |
3fb2ded1 | 308 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
e4533c7a | 309 | #elif defined(TARGET_ARM) |
1b21b62a | 310 | env->cpsr = compute_cpsr(); |
3fb2ded1 | 311 | cpu_arm_dump_state(env, logfile, 0); |
1b21b62a | 312 | env->cpsr &= ~0xf0000000; |
93ac68bc | 313 | #elif defined(TARGET_SPARC) |
93a40ea9 | 314 | cpu_sparc_dump_state (env, logfile, 0); |
67867308 FB |
315 | #elif defined(TARGET_PPC) |
316 | cpu_ppc_dump_state(env, logfile, 0); | |
e4533c7a FB |
317 | #else |
318 | #error unsupported target CPU | |
319 | #endif | |
3fb2ded1 | 320 | } |
7d13299d | 321 | #endif |
3f337316 FB |
322 | /* we record a subset of the CPU state. It will |
323 | always be the same before a given translated block | |
324 | is executed. */ | |
e4533c7a | 325 | #if defined(TARGET_I386) |
2e255c6b | 326 | flags = env->hflags; |
3f337316 | 327 | flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
3fb2ded1 FB |
328 | cs_base = env->segs[R_CS].base; |
329 | pc = cs_base + env->eip; | |
e4533c7a | 330 | #elif defined(TARGET_ARM) |
3fb2ded1 FB |
331 | flags = 0; |
332 | cs_base = 0; | |
333 | pc = (uint8_t *)env->regs[15]; | |
93ac68bc | 334 | #elif defined(TARGET_SPARC) |
67867308 | 335 | flags = 0; |
ce09776b | 336 | cs_base = (uint8_t *)env->npc; |
67867308 FB |
337 | pc = (uint8_t *) env->pc; |
338 | #elif defined(TARGET_PPC) | |
339 | flags = 0; | |
340 | cs_base = 0; | |
341 | pc = (uint8_t *)env->nip; | |
e4533c7a FB |
342 | #else |
343 | #error unsupported CPU | |
344 | #endif | |
3fb2ded1 FB |
345 | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
346 | flags); | |
d4e8164f | 347 | if (!tb) { |
1376847f FB |
348 | TranslationBlock **ptb1; |
349 | unsigned int h; | |
350 | target_ulong phys_pc, phys_page1, phys_page2, virt_page2; | |
351 | ||
352 | ||
3fb2ded1 | 353 | spin_lock(&tb_lock); |
1376847f FB |
354 | |
355 | tb_invalidated_flag = 0; | |
356 | ||
357 | /* find translated block using physical mappings */ | |
358 | phys_pc = get_phys_addr_code(env, (unsigned long)pc); | |
359 | phys_page1 = phys_pc & TARGET_PAGE_MASK; | |
360 | phys_page2 = -1; | |
361 | h = tb_phys_hash_func(phys_pc); | |
362 | ptb1 = &tb_phys_hash[h]; | |
363 | for(;;) { | |
364 | tb = *ptb1; | |
365 | if (!tb) | |
366 | goto not_found; | |
367 | if (tb->pc == (unsigned long)pc && | |
368 | tb->page_addr[0] == phys_page1 && | |
369 | tb->cs_base == (unsigned long)cs_base && | |
370 | tb->flags == flags) { | |
371 | /* check next page if needed */ | |
b516f85c FB |
372 | if (tb->page_addr[1] != -1) { |
373 | virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) + | |
374 | TARGET_PAGE_SIZE; | |
1376847f FB |
375 | phys_page2 = get_phys_addr_code(env, virt_page2); |
376 | if (tb->page_addr[1] == phys_page2) | |
377 | goto found; | |
378 | } else { | |
379 | goto found; | |
380 | } | |
381 | } | |
382 | ptb1 = &tb->phys_hash_next; | |
383 | } | |
384 | not_found: | |
3fb2ded1 | 385 | /* if no translated code available, then translate it now */ |
d4e8164f | 386 | tb = tb_alloc((unsigned long)pc); |
3fb2ded1 FB |
387 | if (!tb) { |
388 | /* flush must be done */ | |
b453b70b | 389 | tb_flush(env); |
3fb2ded1 FB |
390 | /* cannot fail at this point */ |
391 | tb = tb_alloc((unsigned long)pc); | |
392 | /* don't forget to invalidate previous TB info */ | |
393 | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; | |
394 | T0 = 0; | |
395 | } | |
396 | tc_ptr = code_gen_ptr; | |
397 | tb->tc_ptr = tc_ptr; | |
398 | tb->cs_base = (unsigned long)cs_base; | |
399 | tb->flags = flags; | |
facc68be | 400 | cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
1376847f FB |
401 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
402 | ||
403 | /* check next page if needed */ | |
404 | virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK; | |
405 | phys_page2 = -1; | |
406 | if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) { | |
407 | phys_page2 = get_phys_addr_code(env, virt_page2); | |
408 | } | |
409 | tb_link_phys(tb, phys_pc, phys_page2); | |
410 | ||
411 | found: | |
36bdbe54 FB |
412 | if (tb_invalidated_flag) { |
413 | /* as some TB could have been invalidated because | |
414 | of memory exceptions while generating the code, we | |
415 | must recompute the hash index here */ | |
416 | ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; | |
417 | while (*ptb != NULL) | |
418 | ptb = &(*ptb)->hash_next; | |
419 | T0 = 0; | |
420 | } | |
1376847f | 421 | /* we add the TB in the virtual pc hash table */ |
3fb2ded1 FB |
422 | *ptb = tb; |
423 | tb->hash_next = NULL; | |
424 | tb_link(tb); | |
25eb4484 | 425 | spin_unlock(&tb_lock); |
9de5e440 | 426 | } |
9d27abd9 | 427 | #ifdef DEBUG_EXEC |
f193c797 | 428 | if (loglevel & CPU_LOG_EXEC) { |
3fb2ded1 FB |
429 | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n", |
430 | (long)tb->tc_ptr, (long)tb->pc, | |
431 | lookup_symbol((void *)tb->pc)); | |
432 | } | |
9d27abd9 | 433 | #endif |
8c6939c0 | 434 | #ifdef __sparc__ |
3fb2ded1 | 435 | T0 = tmp_T0; |
8c6939c0 | 436 | #endif |
facc68be | 437 | /* see if we can patch the calling TB. */ |
bf3e8bf1 FB |
438 | if (T0 != 0 |
439 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) | |
440 | && (tb->cflags & CF_CODE_COPY) == | |
441 | (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) | |
442 | #endif | |
443 | ) { | |
3fb2ded1 FB |
444 | spin_lock(&tb_lock); |
445 | tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); | |
97eb5b14 FB |
446 | #if defined(USE_CODE_COPY) |
447 | /* propagates the FP use info */ | |
448 | ((TranslationBlock *)(T0 & ~3))->cflags |= | |
449 | (tb->cflags & CF_FP_USED); | |
450 | #endif | |
3fb2ded1 FB |
451 | spin_unlock(&tb_lock); |
452 | } | |
3fb2ded1 | 453 | tc_ptr = tb->tc_ptr; |
83479e77 | 454 | env->current_tb = tb; |
3fb2ded1 FB |
455 | /* execute the generated code */ |
456 | gen_func = (void *)tc_ptr; | |
8c6939c0 | 457 | #if defined(__sparc__) |
3fb2ded1 FB |
458 | __asm__ __volatile__("call %0\n\t" |
459 | "mov %%o7,%%i0" | |
460 | : /* no outputs */ | |
461 | : "r" (gen_func) | |
462 | : "i0", "i1", "i2", "i3", "i4", "i5"); | |
8c6939c0 | 463 | #elif defined(__arm__) |
3fb2ded1 FB |
464 | asm volatile ("mov pc, %0\n\t" |
465 | ".global exec_loop\n\t" | |
466 | "exec_loop:\n\t" | |
467 | : /* no outputs */ | |
468 | : "r" (gen_func) | |
469 | : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); | |
bf3e8bf1 FB |
470 | #elif defined(TARGET_I386) && defined(USE_CODE_COPY) |
471 | { | |
472 | if (!(tb->cflags & CF_CODE_COPY)) { | |
97eb5b14 FB |
473 | if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) { |
474 | save_native_fp_state(env); | |
475 | } | |
bf3e8bf1 FB |
476 | gen_func(); |
477 | } else { | |
97eb5b14 FB |
478 | if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) { |
479 | restore_native_fp_state(env); | |
480 | } | |
bf3e8bf1 FB |
481 | /* we work with native eflags */ |
482 | CC_SRC = cc_table[CC_OP].compute_all(); | |
483 | CC_OP = CC_OP_EFLAGS; | |
484 | asm(".globl exec_loop\n" | |
485 | "\n" | |
486 | "debug1:\n" | |
487 | " pushl %%ebp\n" | |
488 | " fs movl %10, %9\n" | |
489 | " fs movl %11, %%eax\n" | |
490 | " andl $0x400, %%eax\n" | |
491 | " fs orl %8, %%eax\n" | |
492 | " pushl %%eax\n" | |
493 | " popf\n" | |
494 | " fs movl %%esp, %12\n" | |
495 | " fs movl %0, %%eax\n" | |
496 | " fs movl %1, %%ecx\n" | |
497 | " fs movl %2, %%edx\n" | |
498 | " fs movl %3, %%ebx\n" | |
499 | " fs movl %4, %%esp\n" | |
500 | " fs movl %5, %%ebp\n" | |
501 | " fs movl %6, %%esi\n" | |
502 | " fs movl %7, %%edi\n" | |
503 | " fs jmp *%9\n" | |
504 | "exec_loop:\n" | |
505 | " fs movl %%esp, %4\n" | |
506 | " fs movl %12, %%esp\n" | |
507 | " fs movl %%eax, %0\n" | |
508 | " fs movl %%ecx, %1\n" | |
509 | " fs movl %%edx, %2\n" | |
510 | " fs movl %%ebx, %3\n" | |
511 | " fs movl %%ebp, %5\n" | |
512 | " fs movl %%esi, %6\n" | |
513 | " fs movl %%edi, %7\n" | |
514 | " pushf\n" | |
515 | " popl %%eax\n" | |
516 | " movl %%eax, %%ecx\n" | |
517 | " andl $0x400, %%ecx\n" | |
518 | " shrl $9, %%ecx\n" | |
519 | " andl $0x8d5, %%eax\n" | |
520 | " fs movl %%eax, %8\n" | |
521 | " movl $1, %%eax\n" | |
522 | " subl %%ecx, %%eax\n" | |
523 | " fs movl %%eax, %11\n" | |
524 | " fs movl %9, %%ebx\n" /* get T0 value */ | |
525 | " popl %%ebp\n" | |
526 | : | |
527 | : "m" (*(uint8_t *)offsetof(CPUState, regs[0])), | |
528 | "m" (*(uint8_t *)offsetof(CPUState, regs[1])), | |
529 | "m" (*(uint8_t *)offsetof(CPUState, regs[2])), | |
530 | "m" (*(uint8_t *)offsetof(CPUState, regs[3])), | |
531 | "m" (*(uint8_t *)offsetof(CPUState, regs[4])), | |
532 | "m" (*(uint8_t *)offsetof(CPUState, regs[5])), | |
533 | "m" (*(uint8_t *)offsetof(CPUState, regs[6])), | |
534 | "m" (*(uint8_t *)offsetof(CPUState, regs[7])), | |
535 | "m" (*(uint8_t *)offsetof(CPUState, cc_src)), | |
536 | "m" (*(uint8_t *)offsetof(CPUState, tmp0)), | |
537 | "a" (gen_func), | |
538 | "m" (*(uint8_t *)offsetof(CPUState, df)), | |
539 | "m" (*(uint8_t *)offsetof(CPUState, saved_esp)) | |
540 | : "%ecx", "%edx" | |
541 | ); | |
542 | } | |
543 | } | |
ae228531 | 544 | #else |
3fb2ded1 | 545 | gen_func(); |
ae228531 | 546 | #endif |
83479e77 | 547 | env->current_tb = NULL; |
4cbf74b6 FB |
548 | /* reset soft MMU for next block (it can currently |
549 | only be set by a memory fault) */ | |
550 | #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) | |
3f337316 FB |
551 | if (env->hflags & HF_SOFTMMU_MASK) { |
552 | env->hflags &= ~HF_SOFTMMU_MASK; | |
4cbf74b6 FB |
553 | /* do not allow linking to another block */ |
554 | T0 = 0; | |
555 | } | |
556 | #endif | |
3fb2ded1 FB |
557 | } |
558 | } else { | |
7d13299d | 559 | } |
3fb2ded1 FB |
560 | } /* for(;;) */ |
561 | ||
7d13299d | 562 | |
e4533c7a | 563 | #if defined(TARGET_I386) |
97eb5b14 FB |
564 | #if defined(USE_CODE_COPY) |
565 | if (env->native_fp_regs) { | |
566 | save_native_fp_state(env); | |
567 | } | |
568 | #endif | |
9de5e440 | 569 | /* restore flags in standard format */ |
fc2b4c48 | 570 | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
9de5e440 | 571 | |
7d13299d | 572 | /* restore global registers */ |
04369ff2 FB |
573 | #ifdef reg_EAX |
574 | EAX = saved_EAX; | |
575 | #endif | |
576 | #ifdef reg_ECX | |
577 | ECX = saved_ECX; | |
578 | #endif | |
579 | #ifdef reg_EDX | |
580 | EDX = saved_EDX; | |
581 | #endif | |
582 | #ifdef reg_EBX | |
583 | EBX = saved_EBX; | |
584 | #endif | |
585 | #ifdef reg_ESP | |
586 | ESP = saved_ESP; | |
587 | #endif | |
588 | #ifdef reg_EBP | |
589 | EBP = saved_EBP; | |
590 | #endif | |
591 | #ifdef reg_ESI | |
592 | ESI = saved_ESI; | |
593 | #endif | |
594 | #ifdef reg_EDI | |
595 | EDI = saved_EDI; | |
8c6939c0 | 596 | #endif |
e4533c7a | 597 | #elif defined(TARGET_ARM) |
1b21b62a | 598 | env->cpsr = compute_cpsr(); |
93ac68bc | 599 | #elif defined(TARGET_SPARC) |
67867308 | 600 | #elif defined(TARGET_PPC) |
e4533c7a FB |
601 | #else |
602 | #error unsupported target CPU | |
603 | #endif | |
8c6939c0 FB |
604 | #ifdef __sparc__ |
605 | asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); | |
04369ff2 | 606 | #endif |
7d13299d FB |
607 | T0 = saved_T0; |
608 | T1 = saved_T1; | |
e4533c7a | 609 | T2 = saved_T2; |
7d13299d FB |
610 | env = saved_env; |
611 | return ret; | |
612 | } | |
6dbad63e | 613 | |
fbf9eeb3 FB |
614 | /* must only be called from the generated code as an exception can be |
615 | generated */ | |
616 | void tb_invalidate_page_range(target_ulong start, target_ulong end) | |
617 | { | |
dc5d0b3d FB |
618 | /* XXX: cannot enable it yet because it yields to MMU exception |
619 | where NIP != read address on PowerPC */ | |
620 | #if 0 | |
fbf9eeb3 FB |
621 | target_ulong phys_addr; |
622 | phys_addr = get_phys_addr_code(env, start); | |
623 | tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0); | |
dc5d0b3d | 624 | #endif |
fbf9eeb3 FB |
625 | } |
626 | ||
1a18c71b | 627 | #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY) |
e4533c7a | 628 | |
6dbad63e FB |
629 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
630 | { | |
631 | CPUX86State *saved_env; | |
632 | ||
633 | saved_env = env; | |
634 | env = s; | |
a412ac57 | 635 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
a513fe19 | 636 | selector &= 0xffff; |
2e255c6b FB |
637 | cpu_x86_load_seg_cache(env, seg_reg, selector, |
638 | (uint8_t *)(selector << 4), 0xffff, 0); | |
a513fe19 | 639 | } else { |
b453b70b | 640 | load_seg(seg_reg, selector); |
a513fe19 | 641 | } |
6dbad63e FB |
642 | env = saved_env; |
643 | } | |
9de5e440 | 644 | |
d0a1ffc9 FB |
645 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
646 | { | |
647 | CPUX86State *saved_env; | |
648 | ||
649 | saved_env = env; | |
650 | env = s; | |
651 | ||
652 | helper_fsave(ptr, data32); | |
653 | ||
654 | env = saved_env; | |
655 | } | |
656 | ||
657 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) | |
658 | { | |
659 | CPUX86State *saved_env; | |
660 | ||
661 | saved_env = env; | |
662 | env = s; | |
663 | ||
664 | helper_frstor(ptr, data32); | |
665 | ||
666 | env = saved_env; | |
667 | } | |
668 | ||
e4533c7a FB |
669 | #endif /* TARGET_I386 */ |
670 | ||
67b915a5 FB |
671 | #if !defined(CONFIG_SOFTMMU) |
672 | ||
3fb2ded1 FB |
673 | #if defined(TARGET_I386) |
674 | ||
b56dad1c | 675 | /* 'pc' is the host PC at which the exception was raised. 'address' is |
fd6ce8f6 FB |
676 | the effective address of the memory exception. 'is_write' is 1 if a |
677 | write caused the exception and otherwise 0'. 'old_set' is the | |
678 | signal set which should be restored */ | |
2b413144 | 679 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
680 | int is_write, sigset_t *old_set, |
681 | void *puc) | |
9de5e440 | 682 | { |
a513fe19 FB |
683 | TranslationBlock *tb; |
684 | int ret; | |
68a79315 | 685 | |
83479e77 FB |
686 | if (cpu_single_env) |
687 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
fd6ce8f6 | 688 | #if defined(DEBUG_SIGNAL) |
bf3e8bf1 FB |
689 | qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
690 | pc, address, is_write, *(unsigned long *)old_set); | |
9de5e440 | 691 | #endif |
25eb4484 | 692 | /* XXX: locking issue */ |
fbf9eeb3 | 693 | if (is_write && page_unprotect(address, pc, puc)) { |
fd6ce8f6 FB |
694 | return 1; |
695 | } | |
fbf9eeb3 | 696 | |
3fb2ded1 | 697 | /* see if it is an MMU fault */ |
93a40ea9 FB |
698 | ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
699 | ((env->hflags & HF_CPL_MASK) == 3), 0); | |
3fb2ded1 FB |
700 | if (ret < 0) |
701 | return 0; /* not an MMU fault */ | |
702 | if (ret == 0) | |
703 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
704 | /* now we have a real cpu fault */ | |
a513fe19 FB |
705 | tb = tb_find_pc(pc); |
706 | if (tb) { | |
9de5e440 FB |
707 | /* the PC is inside the translated code. It means that we have |
708 | a virtual CPU fault */ | |
bf3e8bf1 | 709 | cpu_restore_state(tb, env, pc, puc); |
3fb2ded1 | 710 | } |
4cbf74b6 | 711 | if (ret == 1) { |
3fb2ded1 | 712 | #if 0 |
4cbf74b6 FB |
713 | printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n", |
714 | env->eip, env->cr[2], env->error_code); | |
3fb2ded1 | 715 | #endif |
4cbf74b6 FB |
716 | /* we restore the process signal mask as the sigreturn should |
717 | do it (XXX: use sigsetjmp) */ | |
718 | sigprocmask(SIG_SETMASK, old_set, NULL); | |
719 | raise_exception_err(EXCP0E_PAGE, env->error_code); | |
720 | } else { | |
721 | /* activate soft MMU for this block */ | |
3f337316 | 722 | env->hflags |= HF_SOFTMMU_MASK; |
fbf9eeb3 | 723 | cpu_resume_from_signal(env, puc); |
4cbf74b6 | 724 | } |
3fb2ded1 FB |
725 | /* never comes here */ |
726 | return 1; | |
727 | } | |
728 | ||
e4533c7a | 729 | #elif defined(TARGET_ARM) |
3fb2ded1 | 730 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
bf3e8bf1 FB |
731 | int is_write, sigset_t *old_set, |
732 | void *puc) | |
3fb2ded1 FB |
733 | { |
734 | /* XXX: do more */ | |
735 | return 0; | |
736 | } | |
93ac68bc FB |
737 | #elif defined(TARGET_SPARC) |
738 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
739 | int is_write, sigset_t *old_set, |
740 | void *puc) | |
93ac68bc | 741 | { |
b453b70b | 742 | /* XXX: locking issue */ |
fbf9eeb3 | 743 | if (is_write && page_unprotect(address, pc, puc)) { |
b453b70b FB |
744 | return 1; |
745 | } | |
746 | return 0; | |
93ac68bc | 747 | } |
67867308 FB |
748 | #elif defined (TARGET_PPC) |
749 | static inline int handle_cpu_signal(unsigned long pc, unsigned long address, | |
bf3e8bf1 FB |
750 | int is_write, sigset_t *old_set, |
751 | void *puc) | |
67867308 FB |
752 | { |
753 | TranslationBlock *tb; | |
ce09776b | 754 | int ret; |
67867308 | 755 | |
ce09776b | 756 | #if 1 |
67867308 FB |
757 | if (cpu_single_env) |
758 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
759 | #endif | |
760 | #if defined(DEBUG_SIGNAL) | |
761 | printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", | |
762 | pc, address, is_write, *(unsigned long *)old_set); | |
763 | #endif | |
764 | /* XXX: locking issue */ | |
fbf9eeb3 | 765 | if (is_write && page_unprotect(address, pc, puc)) { |
67867308 FB |
766 | return 1; |
767 | } | |
768 | ||
ce09776b | 769 | /* see if it is an MMU fault */ |
7f957d28 | 770 | ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); |
ce09776b FB |
771 | if (ret < 0) |
772 | return 0; /* not an MMU fault */ | |
773 | if (ret == 0) | |
774 | return 1; /* the MMU fault was handled without causing real CPU fault */ | |
775 | ||
67867308 FB |
776 | /* now we have a real cpu fault */ |
777 | tb = tb_find_pc(pc); | |
778 | if (tb) { | |
779 | /* the PC is inside the translated code. It means that we have | |
780 | a virtual CPU fault */ | |
bf3e8bf1 | 781 | cpu_restore_state(tb, env, pc, puc); |
67867308 | 782 | } |
ce09776b | 783 | if (ret == 1) { |
67867308 | 784 | #if 0 |
ce09776b FB |
785 | printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
786 | env->nip, env->error_code, tb); | |
67867308 FB |
787 | #endif |
788 | /* we restore the process signal mask as the sigreturn should | |
789 | do it (XXX: use sigsetjmp) */ | |
bf3e8bf1 | 790 | sigprocmask(SIG_SETMASK, old_set, NULL); |
9fddaa0c | 791 | do_raise_exception_err(env->exception_index, env->error_code); |
ce09776b FB |
792 | } else { |
793 | /* activate soft MMU for this block */ | |
fbf9eeb3 | 794 | cpu_resume_from_signal(env, puc); |
ce09776b | 795 | } |
67867308 FB |
796 | /* never comes here */ |
797 | return 1; | |
798 | } | |
e4533c7a FB |
799 | #else |
800 | #error unsupported target CPU | |
801 | #endif | |
9de5e440 | 802 | |
2b413144 FB |
803 | #if defined(__i386__) |
804 | ||
bf3e8bf1 FB |
805 | #if defined(USE_CODE_COPY) |
806 | static void cpu_send_trap(unsigned long pc, int trap, | |
807 | struct ucontext *uc) | |
808 | { | |
809 | TranslationBlock *tb; | |
810 | ||
811 | if (cpu_single_env) | |
812 | env = cpu_single_env; /* XXX: find a correct solution for multithread */ | |
813 | /* now we have a real cpu fault */ | |
814 | tb = tb_find_pc(pc); | |
815 | if (tb) { | |
816 | /* the PC is inside the translated code. It means that we have | |
817 | a virtual CPU fault */ | |
818 | cpu_restore_state(tb, env, pc, uc); | |
819 | } | |
820 | sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL); | |
821 | raise_exception_err(trap, env->error_code); | |
822 | } | |
823 | #endif | |
824 | ||
e4533c7a FB |
825 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
826 | void *puc) | |
9de5e440 | 827 | { |
9de5e440 FB |
828 | struct ucontext *uc = puc; |
829 | unsigned long pc; | |
bf3e8bf1 | 830 | int trapno; |
97eb5b14 | 831 | |
d691f669 FB |
832 | #ifndef REG_EIP |
833 | /* for glibc 2.1 */ | |
fd6ce8f6 FB |
834 | #define REG_EIP EIP |
835 | #define REG_ERR ERR | |
836 | #define REG_TRAPNO TRAPNO | |
d691f669 | 837 | #endif |
fc2b4c48 | 838 | pc = uc->uc_mcontext.gregs[REG_EIP]; |
bf3e8bf1 FB |
839 | trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
840 | #if defined(TARGET_I386) && defined(USE_CODE_COPY) | |
841 | if (trapno == 0x00 || trapno == 0x05) { | |
842 | /* send division by zero or bound exception */ | |
843 | cpu_send_trap(pc, trapno, uc); | |
844 | return 1; | |
845 | } else | |
846 | #endif | |
847 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
848 | trapno == 0xe ? | |
849 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
850 | &uc->uc_sigmask, puc); | |
2b413144 FB |
851 | } |
852 | ||
bc51c5c9 FB |
853 | #elif defined(__x86_64__) |
854 | ||
855 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
856 | void *puc) | |
857 | { | |
858 | struct ucontext *uc = puc; | |
859 | unsigned long pc; | |
860 | ||
861 | pc = uc->uc_mcontext.gregs[REG_RIP]; | |
862 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
863 | uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ? | |
864 | (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, | |
865 | &uc->uc_sigmask, puc); | |
866 | } | |
867 | ||
83fb7adf | 868 | #elif defined(__powerpc__) |
2b413144 | 869 | |
83fb7adf FB |
870 | /*********************************************************************** |
871 | * signal context platform-specific definitions | |
872 | * From Wine | |
873 | */ | |
874 | #ifdef linux | |
875 | /* All Registers access - only for local access */ | |
876 | # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name) | |
877 | /* Gpr Registers access */ | |
878 | # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) | |
879 | # define IAR_sig(context) REG_sig(nip, context) /* Program counter */ | |
880 | # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ | |
881 | # define CTR_sig(context) REG_sig(ctr, context) /* Count register */ | |
882 | # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ | |
883 | # define LR_sig(context) REG_sig(link, context) /* Link register */ | |
884 | # define CR_sig(context) REG_sig(ccr, context) /* Condition register */ | |
885 | /* Float Registers access */ | |
886 | # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) | |
887 | # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) | |
888 | /* Exception Registers access */ | |
889 | # define DAR_sig(context) REG_sig(dar, context) | |
890 | # define DSISR_sig(context) REG_sig(dsisr, context) | |
891 | # define TRAP_sig(context) REG_sig(trap, context) | |
892 | #endif /* linux */ | |
893 | ||
894 | #ifdef __APPLE__ | |
895 | # include <sys/ucontext.h> | |
896 | typedef struct ucontext SIGCONTEXT; | |
897 | /* All Registers access - only for local access */ | |
898 | # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name) | |
899 | # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name) | |
900 | # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name) | |
901 | # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name) | |
902 | /* Gpr Registers access */ | |
903 | # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) | |
904 | # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ | |
905 | # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ | |
906 | # define CTR_sig(context) REG_sig(ctr, context) | |
907 | # define XER_sig(context) REG_sig(xer, context) /* Link register */ | |
908 | # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ | |
909 | # define CR_sig(context) REG_sig(cr, context) /* Condition register */ | |
910 | /* Float Registers access */ | |
911 | # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context) | |
912 | # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) | |
913 | /* Exception Registers access */ | |
914 | # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ | |
915 | # define DSISR_sig(context) EXCEPREG_sig(dsisr, context) | |
916 | # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ | |
917 | #endif /* __APPLE__ */ | |
918 | ||
d1d9f421 | 919 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
e4533c7a | 920 | void *puc) |
2b413144 | 921 | { |
25eb4484 | 922 | struct ucontext *uc = puc; |
25eb4484 | 923 | unsigned long pc; |
25eb4484 FB |
924 | int is_write; |
925 | ||
83fb7adf | 926 | pc = IAR_sig(uc); |
25eb4484 FB |
927 | is_write = 0; |
928 | #if 0 | |
929 | /* ppc 4xx case */ | |
83fb7adf | 930 | if (DSISR_sig(uc) & 0x00800000) |
25eb4484 FB |
931 | is_write = 1; |
932 | #else | |
83fb7adf | 933 | if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
25eb4484 FB |
934 | is_write = 1; |
935 | #endif | |
936 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 937 | is_write, &uc->uc_sigmask, puc); |
2b413144 FB |
938 | } |
939 | ||
2f87c607 FB |
940 | #elif defined(__alpha__) |
941 | ||
e4533c7a | 942 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
2f87c607 FB |
943 | void *puc) |
944 | { | |
945 | struct ucontext *uc = puc; | |
946 | uint32_t *pc = uc->uc_mcontext.sc_pc; | |
947 | uint32_t insn = *pc; | |
948 | int is_write = 0; | |
949 | ||
8c6939c0 | 950 | /* XXX: need kernel patch to get write flag faster */ |
2f87c607 FB |
951 | switch (insn >> 26) { |
952 | case 0x0d: // stw | |
953 | case 0x0e: // stb | |
954 | case 0x0f: // stq_u | |
955 | case 0x24: // stf | |
956 | case 0x25: // stg | |
957 | case 0x26: // sts | |
958 | case 0x27: // stt | |
959 | case 0x2c: // stl | |
960 | case 0x2d: // stq | |
961 | case 0x2e: // stl_c | |
962 | case 0x2f: // stq_c | |
963 | is_write = 1; | |
964 | } | |
965 | ||
966 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 967 | is_write, &uc->uc_sigmask, puc); |
2f87c607 | 968 | } |
8c6939c0 FB |
969 | #elif defined(__sparc__) |
970 | ||
e4533c7a FB |
971 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
972 | void *puc) | |
8c6939c0 FB |
973 | { |
974 | uint32_t *regs = (uint32_t *)(info + 1); | |
975 | void *sigmask = (regs + 20); | |
976 | unsigned long pc; | |
977 | int is_write; | |
978 | uint32_t insn; | |
979 | ||
980 | /* XXX: is there a standard glibc define ? */ | |
981 | pc = regs[1]; | |
982 | /* XXX: need kernel patch to get write flag faster */ | |
983 | is_write = 0; | |
984 | insn = *(uint32_t *)pc; | |
985 | if ((insn >> 30) == 3) { | |
986 | switch((insn >> 19) & 0x3f) { | |
987 | case 0x05: // stb | |
988 | case 0x06: // sth | |
989 | case 0x04: // st | |
990 | case 0x07: // std | |
991 | case 0x24: // stf | |
992 | case 0x27: // stdf | |
993 | case 0x25: // stfsr | |
994 | is_write = 1; | |
995 | break; | |
996 | } | |
997 | } | |
998 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
bf3e8bf1 | 999 | is_write, sigmask, NULL); |
8c6939c0 FB |
1000 | } |
1001 | ||
1002 | #elif defined(__arm__) | |
1003 | ||
e4533c7a FB |
1004 | int cpu_signal_handler(int host_signum, struct siginfo *info, |
1005 | void *puc) | |
8c6939c0 FB |
1006 | { |
1007 | struct ucontext *uc = puc; | |
1008 | unsigned long pc; | |
1009 | int is_write; | |
1010 | ||
1011 | pc = uc->uc_mcontext.gregs[R15]; | |
1012 | /* XXX: compute is_write */ | |
1013 | is_write = 0; | |
1014 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1015 | is_write, | |
1016 | &uc->uc_sigmask); | |
1017 | } | |
1018 | ||
38e584a0 FB |
1019 | #elif defined(__mc68000) |
1020 | ||
1021 | int cpu_signal_handler(int host_signum, struct siginfo *info, | |
1022 | void *puc) | |
1023 | { | |
1024 | struct ucontext *uc = puc; | |
1025 | unsigned long pc; | |
1026 | int is_write; | |
1027 | ||
1028 | pc = uc->uc_mcontext.gregs[16]; | |
1029 | /* XXX: compute is_write */ | |
1030 | is_write = 0; | |
1031 | return handle_cpu_signal(pc, (unsigned long)info->si_addr, | |
1032 | is_write, | |
bf3e8bf1 | 1033 | &uc->uc_sigmask, puc); |
38e584a0 FB |
1034 | } |
1035 | ||
9de5e440 | 1036 | #else |
2b413144 | 1037 | |
3fb2ded1 | 1038 | #error host CPU specific signal handler needed |
2b413144 | 1039 | |
9de5e440 | 1040 | #endif |
67b915a5 FB |
1041 | |
1042 | #endif /* !defined(CONFIG_SOFTMMU) */ |