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9be61fa4 OB |
1 | From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 |
2 | From: Robert Hoo <robert.hu@linux.intel.com> | |
3 | Date: Thu, 5 Jul 2018 17:09:54 +0800 | |
4 | Subject: [PATCH 5/9] i386: Add new MSR indices for IA32_PRED_CMD and | |
5 | IA32_ARCH_CAPABILITIES | |
6 | ||
7 | IA32_PRED_CMD MSR gives software a way to issue commands that affect the state | |
8 | of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26]. | |
9 | IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and | |
10 | IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29]. | |
11 | ||
12 | https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf | |
13 | ||
14 | Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> | |
15 | Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com> | |
16 | Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> | |
17 | --- | |
18 | target/i386/cpu.h | 2 ++ | |
19 | 1 file changed, 2 insertions(+) | |
20 | ||
21 | diff --git a/target/i386/cpu.h b/target/i386/cpu.h | |
22 | index 58ae637edc..fb2f5f6ebc 100644 | |
23 | --- a/target/i386/cpu.h | |
24 | +++ b/target/i386/cpu.h | |
25 | @@ -354,6 +354,8 @@ typedef enum X86Seg { | |
26 | #define MSR_TSC_ADJUST 0x0000003b | |
27 | #define MSR_IA32_SPEC_CTRL 0x48 | |
28 | #define MSR_VIRT_SSBD 0xc001011f | |
29 | +#define MSR_IA32_PRED_CMD 0x49 | |
30 | +#define MSR_IA32_ARCH_CAPABILITIES 0x10a | |
31 | #define MSR_IA32_TSCDEADLINE 0x6e0 | |
32 | ||
33 | #define FEATURE_CONTROL_LOCKED (1<<0) | |
34 | -- | |
35 | 2.20.1 | |
36 |