[qemu.git] / dis-asm.h

/* Interface between the opcode library and its callers.
   Written by Cygnus Support, 1993.

   The opcode library (libopcodes.a) provides instruction decoders for
   a large variety of instruction sets, callable with an identical
   interface, for making instruction-processing programs more independent
   of the instruction set being processed.  */

#ifndef DIS_ASM_H
#define DIS_ASM_H

#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

#define PARAMS(x) x
typedef void *PTR;
typedef uint64_t bfd_vma;
typedef int64_t bfd_signed_vma;
typedef uint8_t bfd_byte;
#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)

#define BFD64

enum bfd_flavour {
  bfd_target_unknown_flavour,
  bfd_target_aout_flavour,
  bfd_target_coff_flavour,
  bfd_target_ecoff_flavour,
  bfd_target_elf_flavour,
  bfd_target_ieee_flavour,
  bfd_target_nlm_flavour,
  bfd_target_oasys_flavour,
  bfd_target_tekhex_flavour,
  bfd_target_srec_flavour,
  bfd_target_ihex_flavour,
  bfd_target_som_flavour,
  bfd_target_os9k_flavour,
  bfd_target_versados_flavour,
  bfd_target_msdos_flavour,
  bfd_target_evax_flavour
};

enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };

enum bfd_architecture
{
  bfd_arch_unknown,    /* File arch not known */
  bfd_arch_obscure,    /* Arch known, not one of these */
  bfd_arch_m68k,       /* Motorola 68xxx */
#define bfd_mach_m68000 1
#define bfd_mach_m68008 2
#define bfd_mach_m68010 3
#define bfd_mach_m68020 4
#define bfd_mach_m68030 5
#define bfd_mach_m68040 6
#define bfd_mach_m68060 7
#define bfd_mach_cpu32  8
#define bfd_mach_mcf5200  9
#define bfd_mach_mcf5206e 10
#define bfd_mach_mcf5307  11
#define bfd_mach_mcf5407  12
#define bfd_mach_mcf528x  13
#define bfd_mach_mcfv4e   14
#define bfd_mach_mcf521x   15
#define bfd_mach_mcf5249   16
#define bfd_mach_mcf547x   17
#define bfd_mach_mcf548x   18
  bfd_arch_vax,        /* DEC Vax */
  bfd_arch_i960,       /* Intel 960 */
     /* The order of the following is important.
       lower number indicates a machine type that
       only accepts a subset of the instructions
       available to machines with higher numbers.
       The exception is the "ca", which is
       incompatible with all other machines except
       "core". */

#define bfd_mach_i960_core      1
#define bfd_mach_i960_ka_sa     2
#define bfd_mach_i960_kb_sb     3
#define bfd_mach_i960_mc        4
#define bfd_mach_i960_xa        5
#define bfd_mach_i960_ca        6
#define bfd_mach_i960_jx        7
#define bfd_mach_i960_hx        8

  bfd_arch_a29k,       /* AMD 29000 */
  bfd_arch_sparc,      /* SPARC */
#define bfd_mach_sparc                 1
/* The difference between v8plus and v9 is that v9 is a true 64 bit env.  */
#define bfd_mach_sparc_sparclet        2
#define bfd_mach_sparc_sparclite       3
#define bfd_mach_sparc_v8plus          4
#define bfd_mach_sparc_v8plusa         5 /* with ultrasparc add'ns.  */
#define bfd_mach_sparc_sparclite_le    6
#define bfd_mach_sparc_v9              7
#define bfd_mach_sparc_v9a             8 /* with ultrasparc add'ns.  */
#define bfd_mach_sparc_v8plusb         9 /* with cheetah add'ns.  */
#define bfd_mach_sparc_v9b             10 /* with cheetah add'ns.  */
/* Nonzero if MACH has the v9 instruction set.  */
#define bfd_mach_sparc_v9_p(mach) \
  ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
   && (mach) != bfd_mach_sparc_sparclite_le)
  bfd_arch_mips,       /* MIPS Rxxxx */
#define bfd_mach_mips3000              3000
#define bfd_mach_mips3900              3900
#define bfd_mach_mips4000              4000
#define bfd_mach_mips4010              4010
#define bfd_mach_mips4100              4100
#define bfd_mach_mips4300              4300
#define bfd_mach_mips4400              4400
#define bfd_mach_mips4600              4600
#define bfd_mach_mips4650              4650
#define bfd_mach_mips5000              5000
#define bfd_mach_mips6000              6000
#define bfd_mach_mips8000              8000
#define bfd_mach_mips10000             10000
#define bfd_mach_mips16                16
  bfd_arch_i386,       /* Intel 386 */
#define bfd_mach_i386_i386 0
#define bfd_mach_i386_i8086 1
#define bfd_mach_i386_i386_intel_syntax 2
#define bfd_mach_x86_64 3
#define bfd_mach_x86_64_intel_syntax 4
  bfd_arch_we32k,      /* AT&T WE32xxx */
  bfd_arch_tahoe,      /* CCI/Harris Tahoe */
  bfd_arch_i860,       /* Intel 860 */
  bfd_arch_romp,       /* IBM ROMP PC/RT */
  bfd_arch_alliant,    /* Alliant */
  bfd_arch_convex,     /* Convex */
  bfd_arch_m88k,       /* Motorola 88xxx */
  bfd_arch_pyramid,    /* Pyramid Technology */
  bfd_arch_h8300,      /* Hitachi H8/300 */
#define bfd_mach_h8300   1
#define bfd_mach_h8300h  2
#define bfd_mach_h8300s  3
  bfd_arch_powerpc,    /* PowerPC */
#define bfd_mach_ppc           0
#define bfd_mach_ppc64         1
#define bfd_mach_ppc_403       403
#define bfd_mach_ppc_403gc     4030
#define bfd_mach_ppc_505       505
#define bfd_mach_ppc_601       601
#define bfd_mach_ppc_602       602
#define bfd_mach_ppc_603       603
#define bfd_mach_ppc_ec603e    6031
#define bfd_mach_ppc_604       604
#define bfd_mach_ppc_620       620
#define bfd_mach_ppc_630       630
#define bfd_mach_ppc_750       750
#define bfd_mach_ppc_860       860
#define bfd_mach_ppc_a35       35
#define bfd_mach_ppc_rs64ii    642
#define bfd_mach_ppc_rs64iii   643
#define bfd_mach_ppc_7400      7400
  bfd_arch_rs6000,     /* IBM RS/6000 */
  bfd_arch_hppa,       /* HP PA RISC */
  bfd_arch_d10v,       /* Mitsubishi D10V */
  bfd_arch_z8k,        /* Zilog Z8000 */
#define bfd_mach_z8001         1
#define bfd_mach_z8002         2
  bfd_arch_h8500,      /* Hitachi H8/500 */
  bfd_arch_sh,         /* Hitachi SH */
#define bfd_mach_sh            1
#define bfd_mach_sh2        0x20
#define bfd_mach_sh_dsp     0x2d
#define bfd_mach_sh2a       0x2a
#define bfd_mach_sh2a_nofpu 0x2b
#define bfd_mach_sh2e       0x2e
#define bfd_mach_sh3        0x30
#define bfd_mach_sh3_nommu  0x31
#define bfd_mach_sh3_dsp    0x3d
#define bfd_mach_sh3e       0x3e
#define bfd_mach_sh4        0x40
#define bfd_mach_sh4_nofpu  0x41
#define bfd_mach_sh4_nommu_nofpu  0x42
#define bfd_mach_sh4a       0x4a
#define bfd_mach_sh4a_nofpu 0x4b
#define bfd_mach_sh4al_dsp  0x4d
#define bfd_mach_sh5        0x50
  bfd_arch_alpha,      /* Dec Alpha */
#define bfd_mach_alpha 1
  bfd_arch_arm,        /* Advanced Risc Machines ARM */
#define bfd_mach_arm_unknown	0
#define bfd_mach_arm_2		1
#define bfd_mach_arm_2a		2
#define bfd_mach_arm_3		3
#define bfd_mach_arm_3M 	4
#define bfd_mach_arm_4 		5
#define bfd_mach_arm_4T 	6
#define bfd_mach_arm_5 		7
#define bfd_mach_arm_5T		8
#define bfd_mach_arm_5TE	9
#define bfd_mach_arm_XScale	10
#define bfd_mach_arm_ep9312	11
#define bfd_mach_arm_iWMMXt	12
#define bfd_mach_arm_iWMMXt2	13
  bfd_arch_ns32k,      /* National Semiconductors ns32000 */
  bfd_arch_w65,        /* WDC 65816 */
  bfd_arch_tic30,      /* Texas Instruments TMS320C30 */
  bfd_arch_v850,       /* NEC V850 */
#define bfd_mach_v850          0
  bfd_arch_arc,        /* Argonaut RISC Core */
#define bfd_mach_arc_base 0
  bfd_arch_m32r,       /* Mitsubishi M32R/D */
#define bfd_mach_m32r          0  /* backwards compatibility */
  bfd_arch_mn10200,    /* Matsushita MN10200 */
  bfd_arch_mn10300,    /* Matsushita MN10300 */
  bfd_arch_cris,       /* Axis CRIS */
#define bfd_mach_cris_v0_v10   255
#define bfd_mach_cris_v32      32
#define bfd_mach_cris_v10_v32  1032
  bfd_arch_last
  };
#define bfd_mach_s390_31 31
#define bfd_mach_s390_64 64

typedef struct symbol_cache_entry
{
    const char *name;
    union
    {
        PTR p;
        bfd_vma i;
    } udata;
} asymbol;

typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...));

enum dis_insn_type {
  dis_noninsn,			/* Not a valid instruction */
  dis_nonbranch,		/* Not a branch instruction */
  dis_branch,			/* Unconditional branch */
  dis_condbranch,		/* Conditional branch */
  dis_jsr,			/* Jump to subroutine */
  dis_condjsr,			/* Conditional jump to subroutine */
  dis_dref,			/* Data reference instruction */
  dis_dref2			/* Two data references in instruction */
};

/* This struct is passed into the instruction decoding routine,
   and is passed back out into each callback.  The various fields are used
   for conveying information from your main routine into your callbacks,
   for passing information into the instruction decoders (such as the
   addresses of the callback functions), or for passing information
   back from the instruction decoders to their callers.

   It must be initialized before it is first passed; this can be done
   by hand, or using one of the initialization macros below.  */

typedef struct disassemble_info {
  fprintf_ftype fprintf_func;
  FILE *stream;
  PTR application_data;

  /* Target description.  We could replace this with a pointer to the bfd,
     but that would require one.  There currently isn't any such requirement
     so to avoid introducing one we record these explicitly.  */
  /* The bfd_flavour.  This can be bfd_target_unknown_flavour.  */
  enum bfd_flavour flavour;
  /* The bfd_arch value.  */
  enum bfd_architecture arch;
  /* The bfd_mach value.  */
  unsigned long mach;
  /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
  enum bfd_endian endian;

  /* An array of pointers to symbols either at the location being disassembled
     or at the start of the function being disassembled.  The array is sorted
     so that the first symbol is intended to be the one used.  The others are
     present for any misc. purposes.  This is not set reliably, but if it is
     not NULL, it is correct.  */
  asymbol **symbols;
  /* Number of symbols in array.  */
  int num_symbols;

  /* For use by the disassembler.
     The top 16 bits are reserved for public use (and are documented here).
     The bottom 16 bits are for the internal use of the disassembler.  */
  unsigned long flags;
#define INSN_HAS_RELOC	0x80000000
  PTR private_data;

  /* Function used to get bytes to disassemble.  MEMADDR is the
     address of the stuff to be disassembled, MYADDR is the address to
     put the bytes in, and LENGTH is the number of bytes to read.
     INFO is a pointer to this struct.
     Returns an errno value or 0 for success.  */
  int (*read_memory_func)
    PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length,
	     struct disassemble_info *info));

  /* Function which should be called if we get an error that we can't
     recover from.  STATUS is the errno value from read_memory_func and
     MEMADDR is the address that we were trying to read.  INFO is a
     pointer to this struct.  */
  void (*memory_error_func)
    PARAMS ((int status, bfd_vma memaddr, struct disassemble_info *info));

  /* Function called to print ADDR.  */
  void (*print_address_func)
    PARAMS ((bfd_vma addr, struct disassemble_info *info));

  /* Function called to determine if there is a symbol at the given ADDR.
     If there is, the function returns 1, otherwise it returns 0.
     This is used by ports which support an overlay manager where
     the overlay number is held in the top part of an address.  In
     some circumstances we want to include the overlay number in the
     address, (normally because there is a symbol associated with
     that address), but sometimes we want to mask out the overlay bits.  */
  int (* symbol_at_address_func)
    PARAMS ((bfd_vma addr, struct disassemble_info * info));

  /* These are for buffer_read_memory.  */
  bfd_byte *buffer;
  bfd_vma buffer_vma;
  int buffer_length;

  /* This variable may be set by the instruction decoder.  It suggests
      the number of bytes objdump should display on a single line.  If
      the instruction decoder sets this, it should always set it to
      the same value in order to get reasonable looking output.  */
  int bytes_per_line;

  /* the next two variables control the way objdump displays the raw data */
  /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
  /* output will look like this:
     00:   00000000 00000000
     with the chunks displayed according to "display_endian". */
  int bytes_per_chunk;
  enum bfd_endian display_endian;

  /* Results from instruction decoders.  Not all decoders yet support
     this information.  This info is set each time an instruction is
     decoded, and is only valid for the last such instruction.

     To determine whether this decoder supports this information, set
     insn_info_valid to 0, decode an instruction, then check it.  */

  char insn_info_valid;		/* Branch info has been set. */
  char branch_delay_insns;	/* How many sequential insn's will run before
				   a branch takes effect.  (0 = normal) */
  char data_size;		/* Size of data reference in insn, in bytes */
  enum dis_insn_type insn_type;	/* Type of instruction */
  bfd_vma target;		/* Target address of branch or dref, if known;
				   zero if unknown.  */
  bfd_vma target2;		/* Second target address for dref2 */

  /* Command line options specific to the target disassembler.  */
  char * disassembler_options;

} disassemble_info;

\f
/* Standard disassemblers.  Disassemble one instruction at the given
   target address.  Return number of bytes processed.  */
typedef int (*disassembler_ftype)
     PARAMS((bfd_vma, disassemble_info *));

extern int print_insn_big_mips		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_little_mips	PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m68k		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8001		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8002		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_h8300		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_h8300h		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_h8300s		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_h8500		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_alpha		PARAMS ((bfd_vma, disassemble_info*));
extern disassembler_ftype arc_get_disassembler PARAMS ((int, int));
extern int print_insn_arm		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_sparc		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_big_a29k		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_little_a29k	PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i960		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_sh		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_shl		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_hppa		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m32r		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m88k		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_mn10200		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_mn10300		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_ns32k		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_big_powerpc	PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_little_powerpc	PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_rs6000		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_w65		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_d10v		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_v850		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_tic30		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_ppc		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_alpha             PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_s390		PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_crisv32           PARAMS ((bfd_vma, disassemble_info*));

#if 0
/* Fetch the disassembler for a given BFD, if that support is available.  */
extern disassembler_ftype disassembler	PARAMS ((bfd *));
#endif

\f
/* This block of definitions is for particular callers who read instructions
   into a buffer before calling the instruction decoder.  */

/* Here is a function which callers may wish to use for read_memory_func.
   It gets bytes from a buffer.  */
extern int buffer_read_memory
  PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *));

/* This function goes with buffer_read_memory.
   It prints a message using info->fprintf_func and info->stream.  */
extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *));


/* Just print the address in hex.  This is included for completeness even
   though both GDB and objdump provide their own (to print symbolic
   addresses).  */
extern void generic_print_address
  PARAMS ((bfd_vma, struct disassemble_info *));

/* Always true.  */
extern int generic_symbol_at_address
  PARAMS ((bfd_vma, struct disassemble_info *));

/* Macro to initialize a disassemble_info struct.  This should be called
   by all applications creating such a struct.  */
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
  (INFO).flavour = bfd_target_unknown_flavour, \
  (INFO).arch = bfd_arch_unknown, \
  (INFO).mach = 0, \
  (INFO).endian = BFD_ENDIAN_UNKNOWN, \
  INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)

/* Call this macro to initialize only the internal variables for the
   disassembler.  Architecture dependent things such as byte order, or machine
   variant are not touched by this macro.  This makes things much easier for
   GDB which must initialize these things separately.  */

#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
  (INFO).fprintf_func = (FPRINTF_FUNC), \
  (INFO).stream = (STREAM), \
  (INFO).symbols = NULL, \
  (INFO).num_symbols = 0, \
  (INFO).buffer = NULL, \
  (INFO).buffer_vma = 0, \
  (INFO).buffer_length = 0, \
  (INFO).read_memory_func = buffer_read_memory, \
  (INFO).memory_error_func = perror_memory, \
  (INFO).print_address_func = generic_print_address, \
  (INFO).symbol_at_address_func = generic_symbol_at_address, \
  (INFO).flags = 0, \
  (INFO).bytes_per_line = 0, \
  (INFO).bytes_per_chunk = 0, \
  (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \
  (INFO).disassembler_options = NULL, \
  (INFO).insn_info_valid = 0

#define _(x) x
#define ATTRIBUTE_UNUSED __attribute__((unused))

/* from libbfd */

bfd_vma bfd_getl32 (const bfd_byte *addr);
bfd_vma bfd_getb32 (const bfd_byte *addr);
bfd_vma bfd_getl16 (const bfd_byte *addr);
bfd_vma bfd_getb16 (const bfd_byte *addr);
typedef enum bfd_boolean {false, true} boolean;
typedef boolean bfd_boolean;

#endif /* ! defined (DIS_ASM_H) */
Commit	Line	Data
dc99065b FB	1	/* Interface between the opcode library and its callers.
	2	Written by Cygnus Support, 1993.
	3
	4	The opcode library (libopcodes.a) provides instruction decoders for
	5	a large variety of instruction sets, callable with an identical
	6	interface, for making instruction-processing programs more independent
	7	of the instruction set being processed. */
	8
	9	#ifndef DIS_ASM_H
	10	#define DIS_ASM_H
	11
c27004ec	12	#include <stdlib.h>
dc99065b	13	#include <stdio.h>
04369ff2	14	#include <string.h>
43d4145a FB	15	#include <inttypes.h>
	16
	17	#define PARAMS(x) x
	18	typedef void *PTR;
	19	typedef uint64_t bfd_vma;
bc51c5c9	20	typedef int64_t bfd_signed_vma;
43d4145a	21	typedef uint8_t bfd_byte;
bc51c5c9	22	#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
43d4145a	23
c27004ec FB	24	#define BFD64
c27004ec FB	25
43d4145a FB	26	enum bfd_flavour {
	27	bfd_target_unknown_flavour,
	28	bfd_target_aout_flavour,
	29	bfd_target_coff_flavour,
	30	bfd_target_ecoff_flavour,
	31	bfd_target_elf_flavour,
	32	bfd_target_ieee_flavour,
	33	bfd_target_nlm_flavour,
	34	bfd_target_oasys_flavour,
	35	bfd_target_tekhex_flavour,
	36	bfd_target_srec_flavour,
	37	bfd_target_ihex_flavour,
	38	bfd_target_som_flavour,
	39	bfd_target_os9k_flavour,
	40	bfd_target_versados_flavour,
	41	bfd_target_msdos_flavour,
	42	bfd_target_evax_flavour
	43	};
	44
	45	enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
	46
5fafdf24	47	enum bfd_architecture
43d4145a FB	48	{
	49	bfd_arch_unknown, /* File arch not known */
	50	bfd_arch_obscure, /* Arch known, not one of these */
	51	bfd_arch_m68k, /* Motorola 68xxx */
	52	#define bfd_mach_m68000 1
	53	#define bfd_mach_m68008 2
	54	#define bfd_mach_m68010 3
	55	#define bfd_mach_m68020 4
	56	#define bfd_mach_m68030 5
	57	#define bfd_mach_m68040 6
	58	#define bfd_mach_m68060 7
48024e4a FB	59	#define bfd_mach_cpu32 8
	60	#define bfd_mach_mcf5200 9
	61	#define bfd_mach_mcf5206e 10
	62	#define bfd_mach_mcf5307 11
	63	#define bfd_mach_mcf5407 12
	64	#define bfd_mach_mcf528x 13
	65	#define bfd_mach_mcfv4e 14
	66	#define bfd_mach_mcf521x 15
	67	#define bfd_mach_mcf5249 16
	68	#define bfd_mach_mcf547x 17
	69	#define bfd_mach_mcf548x 18
3b46e624	70	bfd_arch_vax, /* DEC Vax */
43d4145a FB	71	bfd_arch_i960, /* Intel 960 */
43d4145a FB	72	/* The order of the following is important.
5fafdf24	73	lower number indicates a machine type that
43d4145a FB	74	only accepts a subset of the instructions
	75	available to machines with higher numbers.
	76	The exception is the "ca", which is
5fafdf24	77	incompatible with all other machines except
43d4145a FB	78	"core". */
	79
	80	#define bfd_mach_i960_core 1
	81	#define bfd_mach_i960_ka_sa 2
	82	#define bfd_mach_i960_kb_sb 3
	83	#define bfd_mach_i960_mc 4
	84	#define bfd_mach_i960_xa 5
	85	#define bfd_mach_i960_ca 6
	86	#define bfd_mach_i960_jx 7
	87	#define bfd_mach_i960_hx 8
	88
	89	bfd_arch_a29k, /* AMD 29000 */
	90	bfd_arch_sparc, /* SPARC */
	91	#define bfd_mach_sparc 1
aa0aa4fa	92	/* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
43d4145a FB	93	#define bfd_mach_sparc_sparclet 2
	94	#define bfd_mach_sparc_sparclite 3
	95	#define bfd_mach_sparc_v8plus 4
aa0aa4fa FB	96	#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
	97	#define bfd_mach_sparc_sparclite_le 6
	98	#define bfd_mach_sparc_v9 7
	99	#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
	100	#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
	101	#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
	102	/* Nonzero if MACH has the v9 instruction set. */
43d4145a	103	#define bfd_mach_sparc_v9_p(mach) \
aa0aa4fa FB	104	((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
aa0aa4fa FB	105	&& (mach) != bfd_mach_sparc_sparclite_le)
43d4145a FB	106	bfd_arch_mips, /* MIPS Rxxxx */
	107	#define bfd_mach_mips3000 3000
	108	#define bfd_mach_mips3900 3900
	109	#define bfd_mach_mips4000 4000
	110	#define bfd_mach_mips4010 4010
	111	#define bfd_mach_mips4100 4100
	112	#define bfd_mach_mips4300 4300
	113	#define bfd_mach_mips4400 4400
	114	#define bfd_mach_mips4600 4600
	115	#define bfd_mach_mips4650 4650
	116	#define bfd_mach_mips5000 5000
	117	#define bfd_mach_mips6000 6000
	118	#define bfd_mach_mips8000 8000
	119	#define bfd_mach_mips10000 10000
	120	#define bfd_mach_mips16 16
	121	bfd_arch_i386, /* Intel 386 */
	122	#define bfd_mach_i386_i386 0
	123	#define bfd_mach_i386_i8086 1
bc51c5c9 FB	124	#define bfd_mach_i386_i386_intel_syntax 2
	125	#define bfd_mach_x86_64 3
	126	#define bfd_mach_x86_64_intel_syntax 4
43d4145a FB	127	bfd_arch_we32k, /* AT&T WE32xxx */
	128	bfd_arch_tahoe, /* CCI/Harris Tahoe */
	129	bfd_arch_i860, /* Intel 860 */
	130	bfd_arch_romp, /* IBM ROMP PC/RT */
	131	bfd_arch_alliant, /* Alliant */
	132	bfd_arch_convex, /* Convex */
	133	bfd_arch_m88k, /* Motorola 88xxx */
	134	bfd_arch_pyramid, /* Pyramid Technology */
	135	bfd_arch_h8300, /* Hitachi H8/300 */
	136	#define bfd_mach_h8300 1
	137	#define bfd_mach_h8300h 2
	138	#define bfd_mach_h8300s 3
	139	bfd_arch_powerpc, /* PowerPC */
a2458627 FB	140	#define bfd_mach_ppc 0
	141	#define bfd_mach_ppc64 1
	142	#define bfd_mach_ppc_403 403
	143	#define bfd_mach_ppc_403gc 4030
	144	#define bfd_mach_ppc_505 505
	145	#define bfd_mach_ppc_601 601
	146	#define bfd_mach_ppc_602 602
	147	#define bfd_mach_ppc_603 603
	148	#define bfd_mach_ppc_ec603e 6031
	149	#define bfd_mach_ppc_604 604
	150	#define bfd_mach_ppc_620 620
	151	#define bfd_mach_ppc_630 630
	152	#define bfd_mach_ppc_750 750
	153	#define bfd_mach_ppc_860 860
	154	#define bfd_mach_ppc_a35 35
	155	#define bfd_mach_ppc_rs64ii 642
	156	#define bfd_mach_ppc_rs64iii 643
	157	#define bfd_mach_ppc_7400 7400
43d4145a FB	158	bfd_arch_rs6000, /* IBM RS/6000 */
	159	bfd_arch_hppa, /* HP PA RISC */
	160	bfd_arch_d10v, /* Mitsubishi D10V */
	161	bfd_arch_z8k, /* Zilog Z8000 */
	162	#define bfd_mach_z8001 1
	163	#define bfd_mach_z8002 2
	164	bfd_arch_h8500, /* Hitachi H8/500 */
	165	bfd_arch_sh, /* Hitachi SH */
fdf9b3e8 FB	166	#define bfd_mach_sh 1
	167	#define bfd_mach_sh2 0x20
	168	#define bfd_mach_sh_dsp 0x2d
	169	#define bfd_mach_sh2a 0x2a
	170	#define bfd_mach_sh2a_nofpu 0x2b
	171	#define bfd_mach_sh2e 0x2e
43d4145a	172	#define bfd_mach_sh3 0x30
fdf9b3e8 FB	173	#define bfd_mach_sh3_nommu 0x31
fdf9b3e8 FB	174	#define bfd_mach_sh3_dsp 0x3d
43d4145a FB	175	#define bfd_mach_sh3e 0x3e
43d4145a FB	176	#define bfd_mach_sh4 0x40
fdf9b3e8 FB	177	#define bfd_mach_sh4_nofpu 0x41
	178	#define bfd_mach_sh4_nommu_nofpu 0x42
	179	#define bfd_mach_sh4a 0x4a
	180	#define bfd_mach_sh4a_nofpu 0x4b
	181	#define bfd_mach_sh4al_dsp 0x4d
	182	#define bfd_mach_sh5 0x50
43d4145a	183	bfd_arch_alpha, /* Dec Alpha */
eddf68a6	184	#define bfd_mach_alpha 1
43d4145a	185	bfd_arch_arm, /* Advanced Risc Machines ARM */
4b0f1a8b PB	186	#define bfd_mach_arm_unknown 0
	187	#define bfd_mach_arm_2 1
	188	#define bfd_mach_arm_2a 2
	189	#define bfd_mach_arm_3 3
	190	#define bfd_mach_arm_3M 4
	191	#define bfd_mach_arm_4 5
	192	#define bfd_mach_arm_4T 6
	193	#define bfd_mach_arm_5 7
	194	#define bfd_mach_arm_5T 8
	195	#define bfd_mach_arm_5TE 9
	196	#define bfd_mach_arm_XScale 10
	197	#define bfd_mach_arm_ep9312 11
	198	#define bfd_mach_arm_iWMMXt 12
	199	#define bfd_mach_arm_iWMMXt2 13
43d4145a FB	200	bfd_arch_ns32k, /* National Semiconductors ns32000 */
	201	bfd_arch_w65, /* WDC 65816 */
	202	bfd_arch_tic30, /* Texas Instruments TMS320C30 */
	203	bfd_arch_v850, /* NEC V850 */
	204	#define bfd_mach_v850 0
	205	bfd_arch_arc, /* Argonaut RISC Core */
	206	#define bfd_mach_arc_base 0
	207	bfd_arch_m32r, /* Mitsubishi M32R/D */
	208	#define bfd_mach_m32r 0 /* backwards compatibility */
	209	bfd_arch_mn10200, /* Matsushita MN10200 */
	210	bfd_arch_mn10300, /* Matsushita MN10300 */
a25fd137 TS	211	bfd_arch_cris, /* Axis CRIS */
	212	#define bfd_mach_cris_v0_v10 255
	213	#define bfd_mach_cris_v32 32
	214	#define bfd_mach_cris_v10_v32 1032
43d4145a FB	215	bfd_arch_last
43d4145a FB	216	};
8f860bb8 TS	217	#define bfd_mach_s390_31 31
8f860bb8 TS	218	#define bfd_mach_s390_64 64
43d4145a FB	219
	220	typedef struct symbol_cache_entry
	221	{
	222	const char *name;
	223	union
	224	{
	225	PTR p;
	226	bfd_vma i;
	227	} udata;
	228	} asymbol;
dc99065b FB	229
	230	typedef int (fprintf_ftype) PARAMS((FILE, const char*, ...));
	231
	232	enum dis_insn_type {
	233	dis_noninsn, /* Not a valid instruction */
	234	dis_nonbranch, /* Not a branch instruction */
	235	dis_branch, /* Unconditional branch */
	236	dis_condbranch, /* Conditional branch */
	237	dis_jsr, /* Jump to subroutine */
	238	dis_condjsr, /* Conditional jump to subroutine */
	239	dis_dref, /* Data reference instruction */
	240	dis_dref2 /* Two data references in instruction */
	241	};
	242
5fafdf24	243	/* This struct is passed into the instruction decoding routine,
dc99065b FB	244	and is passed back out into each callback. The various fields are used
	245	for conveying information from your main routine into your callbacks,
	246	for passing information into the instruction decoders (such as the
	247	addresses of the callback functions), or for passing information
	248	back from the instruction decoders to their callers.
	249
	250	It must be initialized before it is first passed; this can be done
	251	by hand, or using one of the initialization macros below. */
	252
	253	typedef struct disassemble_info {
	254	fprintf_ftype fprintf_func;
	255	FILE *stream;
	256	PTR application_data;
	257
	258	/* Target description. We could replace this with a pointer to the bfd,
	259	but that would require one. There currently isn't any such requirement
	260	so to avoid introducing one we record these explicitly. */
	261	/* The bfd_flavour. This can be bfd_target_unknown_flavour. */
	262	enum bfd_flavour flavour;
	263	/* The bfd_arch value. */
	264	enum bfd_architecture arch;
	265	/* The bfd_mach value. */
	266	unsigned long mach;
	267	/* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
	268	enum bfd_endian endian;
	269
	270	/* An array of pointers to symbols either at the location being disassembled
	271	or at the start of the function being disassembled. The array is sorted
	272	so that the first symbol is intended to be the one used. The others are
	273	present for any misc. purposes. This is not set reliably, but if it is
	274	not NULL, it is correct. */
	275	asymbol **symbols;
	276	/* Number of symbols in array. */
	277	int num_symbols;
	278
	279	/* For use by the disassembler.
	280	The top 16 bits are reserved for public use (and are documented here).
	281	The bottom 16 bits are for the internal use of the disassembler. */
	282	unsigned long flags;
	283	#define INSN_HAS_RELOC 0x80000000
	284	PTR private_data;
	285
	286	/* Function used to get bytes to disassemble. MEMADDR is the
	287	address of the stuff to be disassembled, MYADDR is the address to
	288	put the bytes in, and LENGTH is the number of bytes to read.
	289	INFO is a pointer to this struct.
	290	Returns an errno value or 0 for success. */
	291	int (*read_memory_func)
	292	PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length,
	293	struct disassemble_info *info));
	294
	295	/* Function which should be called if we get an error that we can't
	296	recover from. STATUS is the errno value from read_memory_func and
	297	MEMADDR is the address that we were trying to read. INFO is a
	298	pointer to this struct. */
	299	void (*memory_error_func)
	300	PARAMS ((int status, bfd_vma memaddr, struct disassemble_info *info));
	301
	302	/* Function called to print ADDR. */
	303	void (*print_address_func)
	304	PARAMS ((bfd_vma addr, struct disassemble_info *info));
	305
	306	/* Function called to determine if there is a symbol at the given ADDR.
	307	If there is, the function returns 1, otherwise it returns 0.
308	This is used by ports which support an overlay manager where
309	the overlay number is held in the top part of an address. In
310	some circumstances we want to include the overlay number in the
311	address, (normally because there is a symbol associated with
312	that address), but sometimes we want to mask out the overlay bits. */
313	int (* symbol_at_address_func)
314	PARAMS ((bfd_vma addr, struct disassemble_info * info));
315
316	/* These are for buffer_read_memory. */
317	bfd_byte *buffer;
318	bfd_vma buffer_vma;
319	int buffer_length;
320
321	/* This variable may be set by the instruction decoder. It suggests
322	the number of bytes objdump should display on a single line. If
323	the instruction decoder sets this, it should always set it to
324	the same value in order to get reasonable looking output. */
325	int bytes_per_line;
326
327	/* the next two variables control the way objdump displays the raw data */
328	/* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
329	/* output will look like this:
330	00: 00000000 00000000
331	with the chunks displayed according to "display_endian". */
332	int bytes_per_chunk;
333	enum bfd_endian display_endian;
334
335	/* Results from instruction decoders. Not all decoders yet support
336	this information. This info is set each time an instruction is
337	decoded, and is only valid for the last such instruction.
338
339	To determine whether this decoder supports this information, set
340	insn_info_valid to 0, decode an instruction, then check it. */
341
342	char insn_info_valid; /* Branch info has been set. */
343	char branch_delay_insns; /* How many sequential insn's will run before
344	a branch takes effect. (0 = normal) */
345	char data_size; /* Size of data reference in insn, in bytes */
346	enum dis_insn_type insn_type; /* Type of instruction */
347	bfd_vma target; /* Target address of branch or dref, if known;
348	zero if unknown. */
349	bfd_vma target2; /* Second target address for dref2 */
350
aa0aa4fa FB	351	/* Command line options specific to the target disassembler. */
	352	char * disassembler_options;
	353
dc99065b FB	354	} disassemble_info;
	355
	356	\f
	357	/* Standard disassemblers. Disassemble one instruction at the given
	358	target address. Return number of bytes processed. */
	359	typedef int (*disassembler_ftype)
	360	PARAMS((bfd_vma, disassemble_info *));
	361
	362	extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*));
	363	extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
	364	extern int print_insn_i386 PARAMS ((bfd_vma, disassemble_info*));
	365	extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
	366	extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
	367	extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*));
	368	extern int print_insn_h8300 PARAMS ((bfd_vma, disassemble_info*));
	369	extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*));
	370	extern int print_insn_h8300s PARAMS ((bfd_vma, disassemble_info*));
	371	extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*));
	372	extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));
	373	extern disassembler_ftype arc_get_disassembler PARAMS ((int, int));
aa0aa4fa	374	extern int print_insn_arm PARAMS ((bfd_vma, disassemble_info*));
dc99065b FB	375	extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*));
	376	extern int print_insn_big_a29k PARAMS ((bfd_vma, disassemble_info*));
	377	extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*));
	378	extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*));
	379	extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*));
	380	extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*));
	381	extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*));
	382	extern int print_insn_m32r PARAMS ((bfd_vma, disassemble_info*));
	383	extern int print_insn_m88k PARAMS ((bfd_vma, disassemble_info*));
	384	extern int print_insn_mn10200 PARAMS ((bfd_vma, disassemble_info*));
	385	extern int print_insn_mn10300 PARAMS ((bfd_vma, disassemble_info*));
	386	extern int print_insn_ns32k PARAMS ((bfd_vma, disassemble_info*));
	387	extern int print_insn_big_powerpc PARAMS ((bfd_vma, disassemble_info*));
	388	extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*));
	389	extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*));
	390	extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*));
	391	extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*));
	392	extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*));
	393	extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*));
b9adb4a6	394	extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*));
eddf68a6	395	extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));
8f860bb8	396	extern int print_insn_s390 PARAMS ((bfd_vma, disassemble_info*));
a25fd137	397	extern int print_insn_crisv32 PARAMS ((bfd_vma, disassemble_info*));
dc99065b	398
43d4145a	399	#if 0
dc99065b FB	400	/* Fetch the disassembler for a given BFD, if that support is available. */
dc99065b FB	401	extern disassembler_ftype disassembler PARAMS ((bfd *));
43d4145a	402	#endif
dc99065b FB	403
	404	\f
	405	/* This block of definitions is for particular callers who read instructions
	406	into a buffer before calling the instruction decoder. */
	407
	408	/* Here is a function which callers may wish to use for read_memory_func.
	409	It gets bytes from a buffer. */
	410	extern int buffer_read_memory
	411	PARAMS ((bfd_vma, bfd_byte , int, struct disassemble_info ));
	412
	413	/* This function goes with buffer_read_memory.
	414	It prints a message using info->fprintf_func and info->stream. */
	415	extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *));
	416
	417
	418	/* Just print the address in hex. This is included for completeness even
	419	though both GDB and objdump provide their own (to print symbolic
	420	addresses). */
	421	extern void generic_print_address
	422	PARAMS ((bfd_vma, struct disassemble_info *));
	423
	424	/* Always true. */
	425	extern int generic_symbol_at_address
	426	PARAMS ((bfd_vma, struct disassemble_info *));
	427
	428	/* Macro to initialize a disassemble_info struct. This should be called
	429	by all applications creating such a struct. */
	430	#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
	431	(INFO).flavour = bfd_target_unknown_flavour, \
	432	(INFO).arch = bfd_arch_unknown, \
	433	(INFO).mach = 0, \
	434	(INFO).endian = BFD_ENDIAN_UNKNOWN, \
	435	INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)
	436
	437	/* Call this macro to initialize only the internal variables for the
	438	disassembler. Architecture dependent things such as byte order, or machine
	439	variant are not touched by this macro. This makes things much easier for
aa1f17c1	440	GDB which must initialize these things separately. */
dc99065b FB	441
	442	#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
	443	(INFO).fprintf_func = (FPRINTF_FUNC), \
	444	(INFO).stream = (STREAM), \
	445	(INFO).symbols = NULL, \
	446	(INFO).num_symbols = 0, \
	447	(INFO).buffer = NULL, \
	448	(INFO).buffer_vma = 0, \
	449	(INFO).buffer_length = 0, \
	450	(INFO).read_memory_func = buffer_read_memory, \
	451	(INFO).memory_error_func = perror_memory, \
	452	(INFO).print_address_func = generic_print_address, \
	453	(INFO).symbol_at_address_func = generic_symbol_at_address, \
	454	(INFO).flags = 0, \
	455	(INFO).bytes_per_line = 0, \
	456	(INFO).bytes_per_chunk = 0, \
	457	(INFO).display_endian = BFD_ENDIAN_UNKNOWN, \
aa0aa4fa	458	(INFO).disassembler_options = NULL, \
dc99065b FB	459	(INFO).insn_info_valid = 0
dc99065b FB	460
aa0aa4fa	461	#define _(x) x
48024e4a	462	#define ATTRIBUTE_UNUSED __attribute__((unused))
aa0aa4fa FB	463
	464	/* from libbfd */
	465
	466	bfd_vma bfd_getl32 (const bfd_byte *addr);
	467	bfd_vma bfd_getb32 (const bfd_byte *addr);
6af0bf9c FB	468	bfd_vma bfd_getl16 (const bfd_byte *addr);
6af0bf9c FB	469	bfd_vma bfd_getb16 (const bfd_byte *addr);
aa0aa4fa	470	typedef enum bfd_boolean {false, true} boolean;
48024e4a	471	typedef boolean bfd_boolean;
aa0aa4fa	472
dc99065b	473	#endif /* ! defined (DIS_ASM_H) */