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b9adb4a6 1/* General "disassemble this chunk" code. Used for debugging. */
5bbe9299 2#include "config.h"
76cad711 3#include "disas/bfd.h"
b9adb4a6 4#include "elf.h"
aa0aa4fa 5#include <errno.h>
b9adb4a6 6
c6105c0a 7#include "cpu.h"
76cad711 8#include "disas/disas.h"
c6105c0a 9
f4359b9f
BS
10typedef struct CPUDebug {
11 struct disassemble_info info;
12 CPUArchState *env;
13} CPUDebug;
14
b9adb4a6 15/* Filled in by elfload.c. Simplistic, but will do for now. */
e80cfcfc 16struct syminfo *syminfos = NULL;
b9adb4a6 17
aa0aa4fa
FB
18/* Get LENGTH bytes from info's buffer, at target address memaddr.
19 Transfer them to myaddr. */
20int
3a742b76
PB
21buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
22 struct disassemble_info *info)
aa0aa4fa 23{
c6105c0a
FB
24 if (memaddr < info->buffer_vma
25 || memaddr + length > info->buffer_vma + info->buffer_length)
26 /* Out of bounds. Use EIO because GDB uses it. */
27 return EIO;
28 memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
29 return 0;
aa0aa4fa
FB
30}
31
c6105c0a
FB
32/* Get LENGTH bytes from info's buffer, at target address memaddr.
33 Transfer them to myaddr. */
34static int
c27004ec
FB
35target_read_memory (bfd_vma memaddr,
36 bfd_byte *myaddr,
37 int length,
38 struct disassemble_info *info)
c6105c0a 39{
f4359b9f
BS
40 CPUDebug *s = container_of(info, CPUDebug, info);
41
f17ec444 42 cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0);
c6105c0a
FB
43 return 0;
44}
c6105c0a 45
aa0aa4fa
FB
46/* Print an error message. We can assume that this is in response to
47 an error return from buffer_read_memory. */
48void
3a742b76 49perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info)
aa0aa4fa
FB
50{
51 if (status != EIO)
52 /* Can't happen. */
53 (*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
54 else
55 /* Actually, address between memaddr and memaddr + len was
56 out of bounds. */
57 (*info->fprintf_func) (info->stream,
26a76461 58 "Address 0x%" PRIx64 " is out of bounds.\n", memaddr);
aa0aa4fa
FB
59}
60
a31f0531 61/* This could be in a separate file, to save minuscule amounts of space
aa0aa4fa
FB
62 in statically linked executables. */
63
64/* Just print the address is hex. This is included for completeness even
65 though both GDB and objdump provide their own (to print symbolic
66 addresses). */
67
68void
3a742b76 69generic_print_address (bfd_vma addr, struct disassemble_info *info)
aa0aa4fa 70{
26a76461 71 (*info->fprintf_func) (info->stream, "0x%" PRIx64, addr);
aa0aa4fa
FB
72}
73
636bd289
PM
74/* Print address in hex, truncated to the width of a target virtual address. */
75static void
76generic_print_target_address(bfd_vma addr, struct disassemble_info *info)
77{
78 uint64_t mask = ~0ULL >> (64 - TARGET_VIRT_ADDR_SPACE_BITS);
79 generic_print_address(addr & mask, info);
80}
81
82/* Print address in hex, truncated to the width of a host virtual address. */
83static void
84generic_print_host_address(bfd_vma addr, struct disassemble_info *info)
85{
86 uint64_t mask = ~0ULL >> (64 - (sizeof(void *) * 8));
87 generic_print_address(addr & mask, info);
88}
89
aa0aa4fa
FB
90/* Just return the given address. */
91
92int
3a742b76 93generic_symbol_at_address (bfd_vma addr, struct disassemble_info *info)
aa0aa4fa
FB
94{
95 return 1;
96}
97
903ec55c
AJ
98bfd_vma bfd_getl64 (const bfd_byte *addr)
99{
100 unsigned long long v;
101
102 v = (unsigned long long) addr[0];
103 v |= (unsigned long long) addr[1] << 8;
104 v |= (unsigned long long) addr[2] << 16;
105 v |= (unsigned long long) addr[3] << 24;
106 v |= (unsigned long long) addr[4] << 32;
107 v |= (unsigned long long) addr[5] << 40;
108 v |= (unsigned long long) addr[6] << 48;
109 v |= (unsigned long long) addr[7] << 56;
110 return (bfd_vma) v;
111}
112
aa0aa4fa
FB
113bfd_vma bfd_getl32 (const bfd_byte *addr)
114{
115 unsigned long v;
116
117 v = (unsigned long) addr[0];
118 v |= (unsigned long) addr[1] << 8;
119 v |= (unsigned long) addr[2] << 16;
120 v |= (unsigned long) addr[3] << 24;
121 return (bfd_vma) v;
122}
123
124bfd_vma bfd_getb32 (const bfd_byte *addr)
125{
126 unsigned long v;
127
128 v = (unsigned long) addr[0] << 24;
129 v |= (unsigned long) addr[1] << 16;
130 v |= (unsigned long) addr[2] << 8;
131 v |= (unsigned long) addr[3];
132 return (bfd_vma) v;
133}
134
6af0bf9c
FB
135bfd_vma bfd_getl16 (const bfd_byte *addr)
136{
137 unsigned long v;
138
139 v = (unsigned long) addr[0];
140 v |= (unsigned long) addr[1] << 8;
141 return (bfd_vma) v;
142}
143
144bfd_vma bfd_getb16 (const bfd_byte *addr)
145{
146 unsigned long v;
147
148 v = (unsigned long) addr[0] << 24;
149 v |= (unsigned long) addr[1] << 16;
150 return (bfd_vma) v;
151}
152
c2d551ff
FB
153#ifdef TARGET_ARM
154static int
155print_insn_thumb1(bfd_vma pc, disassemble_info *info)
156{
157 return print_insn_arm(pc | 1, info);
158}
159#endif
160
c46ffd57
RH
161static int print_insn_objdump(bfd_vma pc, disassemble_info *info,
162 const char *prefix)
163{
164 int i, n = info->buffer_length;
165 uint8_t *buf = g_malloc(n);
166
167 info->read_memory_func(pc, buf, n, info);
168
169 for (i = 0; i < n; ++i) {
170 if (i % 32 == 0) {
171 info->fprintf_func(info->stream, "\n%s: ", prefix);
172 }
173 info->fprintf_func(info->stream, "%02x", buf[i]);
174 }
175
176 g_free(buf);
177 return n;
178}
179
180static int print_insn_od_host(bfd_vma pc, disassemble_info *info)
181{
182 return print_insn_objdump(pc, info, "OBJD-H");
183}
184
185static int print_insn_od_target(bfd_vma pc, disassemble_info *info)
186{
187 return print_insn_objdump(pc, info, "OBJD-T");
188}
189
e91c8a77 190/* Disassemble this for me please... (debugging). 'flags' has the following
c2d551ff 191 values:
e99722f6 192 i386 - 1 means 16 bit code, 2 means 64 bit code
999b53ec 193 arm - bit 0 = thumb, bit 1 = reverse endian, bit 2 = A64
e13951f8
TM
194 ppc - bits 0:15 specify (optionally) the machine instruction set;
195 bit 16 indicates little endian.
c2d551ff
FB
196 other targets - unused
197 */
f4359b9f
BS
198void target_disas(FILE *out, CPUArchState *env, target_ulong code,
199 target_ulong size, int flags)
b9adb4a6 200{
c27004ec 201 target_ulong pc;
b9adb4a6 202 int count;
f4359b9f 203 CPUDebug s;
c46ffd57 204 int (*print_insn)(bfd_vma pc, disassemble_info *info) = NULL;
b9adb4a6 205
f4359b9f 206 INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
b9adb4a6 207
f4359b9f
BS
208 s.env = env;
209 s.info.read_memory_func = target_read_memory;
210 s.info.buffer_vma = code;
211 s.info.buffer_length = size;
212 s.info.print_address_func = generic_print_target_address;
c27004ec
FB
213
214#ifdef TARGET_WORDS_BIGENDIAN
f4359b9f 215 s.info.endian = BFD_ENDIAN_BIG;
c27004ec 216#else
f4359b9f 217 s.info.endian = BFD_ENDIAN_LITTLE;
c27004ec
FB
218#endif
219#if defined(TARGET_I386)
f4359b9f
BS
220 if (flags == 2) {
221 s.info.mach = bfd_mach_x86_64;
222 } else if (flags == 1) {
223 s.info.mach = bfd_mach_i386_i8086;
224 } else {
225 s.info.mach = bfd_mach_i386_i386;
226 }
c27004ec
FB
227 print_insn = print_insn_i386;
228#elif defined(TARGET_ARM)
999b53ec
CF
229 if (flags & 4) {
230 /* We might not be compiled with the A64 disassembler
231 * because it needs a C++ compiler; in that case we will
232 * fall through to the default print_insn_od case.
233 */
234#if defined(CONFIG_ARM_A64_DIS)
235 print_insn = print_insn_arm_a64;
236#endif
237 } else if (flags & 1) {
d8fd2954
PB
238 print_insn = print_insn_thumb1;
239 } else {
240 print_insn = print_insn_arm;
241 }
242 if (flags & 2) {
243#ifdef TARGET_WORDS_BIGENDIAN
f4359b9f 244 s.info.endian = BFD_ENDIAN_LITTLE;
d8fd2954 245#else
f4359b9f 246 s.info.endian = BFD_ENDIAN_BIG;
d8fd2954
PB
247#endif
248 }
c27004ec
FB
249#elif defined(TARGET_SPARC)
250 print_insn = print_insn_sparc;
3475187d 251#ifdef TARGET_SPARC64
f4359b9f 252 s.info.mach = bfd_mach_sparc_v9b;
3b46e624 253#endif
c27004ec 254#elif defined(TARGET_PPC)
e13951f8 255 if ((flags >> 16) & 1) {
f4359b9f
BS
256 s.info.endian = BFD_ENDIAN_LITTLE;
257 }
237c0af0 258 if (flags & 0xFFFF) {
e13951f8 259 /* If we have a precise definition of the instruction set, use it. */
f4359b9f 260 s.info.mach = flags & 0xFFFF;
237c0af0 261 } else {
a2458627 262#ifdef TARGET_PPC64
f4359b9f 263 s.info.mach = bfd_mach_ppc64;
a2458627 264#else
f4359b9f 265 s.info.mach = bfd_mach_ppc;
a2458627 266#endif
237c0af0 267 }
88770fec 268 s.info.disassembler_options = (char *)"any";
c27004ec 269 print_insn = print_insn_ppc;
e6e5906b
PB
270#elif defined(TARGET_M68K)
271 print_insn = print_insn_m68k;
6af0bf9c 272#elif defined(TARGET_MIPS)
76b3030c 273#ifdef TARGET_WORDS_BIGENDIAN
6af0bf9c 274 print_insn = print_insn_big_mips;
76b3030c
FB
275#else
276 print_insn = print_insn_little_mips;
277#endif
fdf9b3e8 278#elif defined(TARGET_SH4)
f4359b9f 279 s.info.mach = bfd_mach_sh4;
fdf9b3e8 280 print_insn = print_insn_sh;
eddf68a6 281#elif defined(TARGET_ALPHA)
f4359b9f 282 s.info.mach = bfd_mach_alpha_ev6;
eddf68a6 283 print_insn = print_insn_alpha;
a25fd137 284#elif defined(TARGET_CRIS)
b09cd072 285 if (flags != 32) {
f4359b9f 286 s.info.mach = bfd_mach_cris_v0_v10;
b09cd072
EI
287 print_insn = print_insn_crisv10;
288 } else {
f4359b9f 289 s.info.mach = bfd_mach_cris_v32;
b09cd072
EI
290 print_insn = print_insn_crisv32;
291 }
db500609 292#elif defined(TARGET_S390X)
f4359b9f 293 s.info.mach = bfd_mach_s390_64;
db500609 294 print_insn = print_insn_s390;
e90e390c 295#elif defined(TARGET_MICROBLAZE)
f4359b9f 296 s.info.mach = bfd_arch_microblaze;
e90e390c 297 print_insn = print_insn_microblaze;
bd86a88e
AG
298#elif defined(TARGET_MOXIE)
299 s.info.mach = bfd_arch_moxie;
300 print_insn = print_insn_moxie;
79368f49 301#elif defined(TARGET_LM32)
f4359b9f 302 s.info.mach = bfd_mach_lm32;
79368f49 303 print_insn = print_insn_lm32;
c6105c0a 304#endif
c46ffd57
RH
305 if (print_insn == NULL) {
306 print_insn = print_insn_od_target;
307 }
c6105c0a 308
7e000c2e 309 for (pc = code; size > 0; pc += count, size -= count) {
fa15e030 310 fprintf(out, "0x" TARGET_FMT_lx ": ", pc);
f4359b9f 311 count = print_insn(pc, &s.info);
c27004ec
FB
312#if 0
313 {
314 int i;
315 uint8_t b;
316 fprintf(out, " {");
317 for(i = 0; i < count; i++) {
f4359b9f 318 target_read_memory(pc + i, &b, 1, &s.info);
c27004ec
FB
319 fprintf(out, " %02x", b);
320 }
321 fprintf(out, " }");
322 }
323#endif
324 fprintf(out, "\n");
325 if (count < 0)
326 break;
754d00ae 327 if (size < count) {
328 fprintf(out,
329 "Disassembler disagrees with translator over instruction "
330 "decoding\n"
331 "Please report this to qemu-devel@nongnu.org\n");
332 break;
333 }
c27004ec
FB
334 }
335}
336
337/* Disassemble this for me please... (debugging). */
338void disas(FILE *out, void *code, unsigned long size)
339{
b0b0f1c9 340 uintptr_t pc;
c27004ec 341 int count;
f4359b9f 342 CPUDebug s;
c46ffd57 343 int (*print_insn)(bfd_vma pc, disassemble_info *info) = NULL;
c27004ec 344
f4359b9f
BS
345 INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
346 s.info.print_address_func = generic_print_host_address;
c27004ec 347
f4359b9f
BS
348 s.info.buffer = code;
349 s.info.buffer_vma = (uintptr_t)code;
350 s.info.buffer_length = size;
b9adb4a6 351
e2542fe2 352#ifdef HOST_WORDS_BIGENDIAN
f4359b9f 353 s.info.endian = BFD_ENDIAN_BIG;
b9adb4a6 354#else
f4359b9f 355 s.info.endian = BFD_ENDIAN_LITTLE;
b9adb4a6 356#endif
5826e519
SW
357#if defined(CONFIG_TCG_INTERPRETER)
358 print_insn = print_insn_tci;
359#elif defined(__i386__)
f4359b9f 360 s.info.mach = bfd_mach_i386_i386;
c27004ec 361 print_insn = print_insn_i386;
bc51c5c9 362#elif defined(__x86_64__)
f4359b9f 363 s.info.mach = bfd_mach_x86_64;
c27004ec 364 print_insn = print_insn_i386;
e58ffeb3 365#elif defined(_ARCH_PPC)
66d4f6a3 366 s.info.disassembler_options = (char *)"any";
c27004ec 367 print_insn = print_insn_ppc;
999b53ec
CF
368#elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
369 print_insn = print_insn_arm_a64;
a993ba85 370#elif defined(__alpha__)
c27004ec 371 print_insn = print_insn_alpha;
aa0aa4fa 372#elif defined(__sparc__)
c27004ec 373 print_insn = print_insn_sparc;
f4359b9f 374 s.info.mach = bfd_mach_sparc_v9b;
5fafdf24 375#elif defined(__arm__)
c27004ec 376 print_insn = print_insn_arm;
6af0bf9c
FB
377#elif defined(__MIPSEB__)
378 print_insn = print_insn_big_mips;
379#elif defined(__MIPSEL__)
380 print_insn = print_insn_little_mips;
48024e4a
FB
381#elif defined(__m68k__)
382 print_insn = print_insn_m68k;
8f860bb8
TS
383#elif defined(__s390__)
384 print_insn = print_insn_s390;
f54b3f92
AJ
385#elif defined(__hppa__)
386 print_insn = print_insn_hppa;
903ec55c
AJ
387#elif defined(__ia64__)
388 print_insn = print_insn_ia64;
b9adb4a6 389#endif
c46ffd57
RH
390 if (print_insn == NULL) {
391 print_insn = print_insn_od_host;
392 }
b0b0f1c9
SW
393 for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
394 fprintf(out, "0x%08" PRIxPTR ": ", pc);
f4359b9f 395 count = print_insn(pc, &s.info);
b9adb4a6
FB
396 fprintf(out, "\n");
397 if (count < 0)
398 break;
399 }
400}
401
402/* Look up symbol for debugging purpose. Returns "" if unknown. */
c27004ec 403const char *lookup_symbol(target_ulong orig_addr)
b9adb4a6 404{
49918a75 405 const char *symbol = "";
e80cfcfc 406 struct syminfo *s;
3b46e624 407
e80cfcfc 408 for (s = syminfos; s; s = s->next) {
49918a75
PB
409 symbol = s->lookup_symbol(s, orig_addr);
410 if (symbol[0] != '\0') {
411 break;
412 }
b9adb4a6 413 }
49918a75
PB
414
415 return symbol;
b9adb4a6 416}
9307c4c1
FB
417
418#if !defined(CONFIG_USER_ONLY)
419
83c9089e 420#include "monitor/monitor.h"
3d2cfdf1 421
9307c4c1
FB
422static int monitor_disas_is_physical;
423
424static int
a5f1b965
BS
425monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
426 struct disassemble_info *info)
9307c4c1 427{
f4359b9f
BS
428 CPUDebug *s = container_of(info, CPUDebug, info);
429
9307c4c1 430 if (monitor_disas_is_physical) {
54f7b4a3 431 cpu_physical_memory_read(memaddr, myaddr, length);
9307c4c1 432 } else {
f17ec444 433 cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0);
9307c4c1
FB
434 }
435 return 0;
436}
437
8b7968f7
SW
438static int GCC_FMT_ATTR(2, 3)
439monitor_fprintf(FILE *stream, const char *fmt, ...)
3d2cfdf1
FB
440{
441 va_list ap;
442 va_start(ap, fmt);
376253ec 443 monitor_vprintf((Monitor *)stream, fmt, ap);
3d2cfdf1
FB
444 va_end(ap);
445 return 0;
446}
447
1c38f843
TM
448/* Disassembler for the monitor.
449 See target_disas for a description of flags. */
9349b4f9 450void monitor_disas(Monitor *mon, CPUArchState *env,
6a00d601 451 target_ulong pc, int nb_insn, int is_physical, int flags)
9307c4c1 452{
9307c4c1 453 int count, i;
f4359b9f 454 CPUDebug s;
9307c4c1
FB
455 int (*print_insn)(bfd_vma pc, disassemble_info *info);
456
f4359b9f 457 INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf);
9307c4c1 458
f4359b9f 459 s.env = env;
9307c4c1 460 monitor_disas_is_physical = is_physical;
f4359b9f
BS
461 s.info.read_memory_func = monitor_read_memory;
462 s.info.print_address_func = generic_print_target_address;
9307c4c1 463
f4359b9f 464 s.info.buffer_vma = pc;
9307c4c1
FB
465
466#ifdef TARGET_WORDS_BIGENDIAN
f4359b9f 467 s.info.endian = BFD_ENDIAN_BIG;
9307c4c1 468#else
f4359b9f 469 s.info.endian = BFD_ENDIAN_LITTLE;
9307c4c1
FB
470#endif
471#if defined(TARGET_I386)
f4359b9f
BS
472 if (flags == 2) {
473 s.info.mach = bfd_mach_x86_64;
474 } else if (flags == 1) {
475 s.info.mach = bfd_mach_i386_i8086;
476 } else {
477 s.info.mach = bfd_mach_i386_i386;
478 }
9307c4c1
FB
479 print_insn = print_insn_i386;
480#elif defined(TARGET_ARM)
481 print_insn = print_insn_arm;
cbd669da
TS
482#elif defined(TARGET_ALPHA)
483 print_insn = print_insn_alpha;
9307c4c1
FB
484#elif defined(TARGET_SPARC)
485 print_insn = print_insn_sparc;
682c4f15 486#ifdef TARGET_SPARC64
f4359b9f 487 s.info.mach = bfd_mach_sparc_v9b;
682c4f15 488#endif
9307c4c1 489#elif defined(TARGET_PPC)
1c38f843
TM
490 if (flags & 0xFFFF) {
491 /* If we have a precise definition of the instruction set, use it. */
492 s.info.mach = flags & 0xFFFF;
493 } else {
a2458627 494#ifdef TARGET_PPC64
1c38f843 495 s.info.mach = bfd_mach_ppc64;
a2458627 496#else
1c38f843 497 s.info.mach = bfd_mach_ppc;
a2458627 498#endif
1c38f843
TM
499 }
500 if ((flags >> 16) & 1) {
501 s.info.endian = BFD_ENDIAN_LITTLE;
502 }
9307c4c1 503 print_insn = print_insn_ppc;
e6e5906b
PB
504#elif defined(TARGET_M68K)
505 print_insn = print_insn_m68k;
6af0bf9c 506#elif defined(TARGET_MIPS)
76b3030c 507#ifdef TARGET_WORDS_BIGENDIAN
6af0bf9c 508 print_insn = print_insn_big_mips;
76b3030c
FB
509#else
510 print_insn = print_insn_little_mips;
511#endif
b4e1f077 512#elif defined(TARGET_SH4)
f4359b9f 513 s.info.mach = bfd_mach_sh4;
b4e1f077 514 print_insn = print_insn_sh;
db500609 515#elif defined(TARGET_S390X)
f4359b9f 516 s.info.mach = bfd_mach_s390_64;
db500609 517 print_insn = print_insn_s390;
bd86a88e
AG
518#elif defined(TARGET_MOXIE)
519 s.info.mach = bfd_arch_moxie;
520 print_insn = print_insn_moxie;
79368f49 521#elif defined(TARGET_LM32)
f4359b9f 522 s.info.mach = bfd_mach_lm32;
79368f49 523 print_insn = print_insn_lm32;
9307c4c1 524#else
376253ec
AL
525 monitor_printf(mon, "0x" TARGET_FMT_lx
526 ": Asm output not supported on this arch\n", pc);
9307c4c1
FB
527 return;
528#endif
529
530 for(i = 0; i < nb_insn; i++) {
376253ec 531 monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
f4359b9f 532 count = print_insn(pc, &s.info);
376253ec 533 monitor_printf(mon, "\n");
9307c4c1
FB
534 if (count < 0)
535 break;
536 pc += count;
537 }
538}
539#endif