[mirror_qemu.git] / disas.c

/* General "disassemble this chunk" code.  Used for debugging. */
#include "config.h"
#include "disas/bfd.h"
#include "elf.h"
#include <errno.h>

#include "cpu.h"
#include "disas/disas.h"

typedef struct CPUDebug {
    struct disassemble_info info;
    CPUState *cpu;
} CPUDebug;

/* Filled in by elfload.c.  Simplistic, but will do for now. */
struct syminfo *syminfos = NULL;

/* Get LENGTH bytes from info's buffer, at target address memaddr.
   Transfer them to myaddr.  */
int
buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
                   struct disassemble_info *info)
{
    if (memaddr < info->buffer_vma
        || memaddr + length > info->buffer_vma + info->buffer_length)
        /* Out of bounds.  Use EIO because GDB uses it.  */
        return EIO;
    memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
    return 0;
}

/* Get LENGTH bytes from info's buffer, at target address memaddr.
   Transfer them to myaddr.  */
static int
target_read_memory (bfd_vma memaddr,
                    bfd_byte *myaddr,
                    int length,
                    struct disassemble_info *info)
{
    CPUDebug *s = container_of(info, CPUDebug, info);

    cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
    return 0;
}

/* Print an error message.  We can assume that this is in response to
   an error return from buffer_read_memory.  */
void
perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info)
{
  if (status != EIO)
    /* Can't happen.  */
    (*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
  else
    /* Actually, address between memaddr and memaddr + len was
       out of bounds.  */
    (*info->fprintf_func) (info->stream,
			   "Address 0x%" PRIx64 " is out of bounds.\n", memaddr);
}

/* This could be in a separate file, to save minuscule amounts of space
   in statically linked executables.  */

/* Just print the address is hex.  This is included for completeness even
   though both GDB and objdump provide their own (to print symbolic
   addresses).  */

void
generic_print_address (bfd_vma addr, struct disassemble_info *info)
{
    (*info->fprintf_func) (info->stream, "0x%" PRIx64, addr);
}

/* Print address in hex, truncated to the width of a target virtual address. */
static void
generic_print_target_address(bfd_vma addr, struct disassemble_info *info)
{
    uint64_t mask = ~0ULL >> (64 - TARGET_VIRT_ADDR_SPACE_BITS);
    generic_print_address(addr & mask, info);
}

/* Print address in hex, truncated to the width of a host virtual address. */
static void
generic_print_host_address(bfd_vma addr, struct disassemble_info *info)
{
    uint64_t mask = ~0ULL >> (64 - (sizeof(void *) * 8));
    generic_print_address(addr & mask, info);
}

/* Just return the given address.  */

int
generic_symbol_at_address (bfd_vma addr, struct disassemble_info *info)
{
  return 1;
}

bfd_vma bfd_getl64 (const bfd_byte *addr)
{
  unsigned long long v;

  v = (unsigned long long) addr[0];
  v |= (unsigned long long) addr[1] << 8;
  v |= (unsigned long long) addr[2] << 16;
  v |= (unsigned long long) addr[3] << 24;
  v |= (unsigned long long) addr[4] << 32;
  v |= (unsigned long long) addr[5] << 40;
  v |= (unsigned long long) addr[6] << 48;
  v |= (unsigned long long) addr[7] << 56;
  return (bfd_vma) v;
}

bfd_vma bfd_getl32 (const bfd_byte *addr)
{
  unsigned long v;

  v = (unsigned long) addr[0];
  v |= (unsigned long) addr[1] << 8;
  v |= (unsigned long) addr[2] << 16;
  v |= (unsigned long) addr[3] << 24;
  return (bfd_vma) v;
}

bfd_vma bfd_getb32 (const bfd_byte *addr)
{
  unsigned long v;

  v = (unsigned long) addr[0] << 24;
  v |= (unsigned long) addr[1] << 16;
  v |= (unsigned long) addr[2] << 8;
  v |= (unsigned long) addr[3];
  return (bfd_vma) v;
}

bfd_vma bfd_getl16 (const bfd_byte *addr)
{
  unsigned long v;

  v = (unsigned long) addr[0];
  v |= (unsigned long) addr[1] << 8;
  return (bfd_vma) v;
}

bfd_vma bfd_getb16 (const bfd_byte *addr)
{
  unsigned long v;

  v = (unsigned long) addr[0] << 24;
  v |= (unsigned long) addr[1] << 16;
  return (bfd_vma) v;
}

#ifdef TARGET_ARM
static int
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
{
  return print_insn_arm(pc | 1, info);
}
#endif

static int print_insn_objdump(bfd_vma pc, disassemble_info *info,
                              const char *prefix)
{
    int i, n = info->buffer_length;
    uint8_t *buf = g_malloc(n);

    info->read_memory_func(pc, buf, n, info);

    for (i = 0; i < n; ++i) {
        if (i % 32 == 0) {
            info->fprintf_func(info->stream, "\n%s: ", prefix);
        }
        info->fprintf_func(info->stream, "%02x", buf[i]);
    }

    g_free(buf);
    return n;
}

static int print_insn_od_host(bfd_vma pc, disassemble_info *info)
{
    return print_insn_objdump(pc, info, "OBJD-H");
}

static int print_insn_od_target(bfd_vma pc, disassemble_info *info)
{
    return print_insn_objdump(pc, info, "OBJD-T");
}

/* Disassemble this for me please... (debugging). 'flags' has the following
   values:
    i386 - 1 means 16 bit code, 2 means 64 bit code
    arm  - bit 0 = thumb, bit 1 = reverse endian, bit 2 = A64
    ppc  - bits 0:15 specify (optionally) the machine instruction set;
           bit 16 indicates little endian.
    other targets - unused
 */
void target_disas(FILE *out, CPUState *cpu, target_ulong code,
                  target_ulong size, int flags)
{
    target_ulong pc;
    int count;
    CPUDebug s;

    INIT_DISASSEMBLE_INFO(s.info, out, fprintf);

    s.cpu = cpu;
    s.info.read_memory_func = target_read_memory;
    s.info.buffer_vma = code;
    s.info.buffer_length = size;
    s.info.print_address_func = generic_print_target_address;

#ifdef TARGET_WORDS_BIGENDIAN
    s.info.endian = BFD_ENDIAN_BIG;
#else
    s.info.endian = BFD_ENDIAN_LITTLE;
#endif
#if defined(TARGET_I386)
    if (flags == 2) {
        s.info.mach = bfd_mach_x86_64;
    } else if (flags == 1) {
        s.info.mach = bfd_mach_i386_i8086;
    } else {
        s.info.mach = bfd_mach_i386_i386;
    }
    s.info.print_insn = print_insn_i386;
#elif defined(TARGET_ARM)
    if (flags & 4) {
        /* We might not be compiled with the A64 disassembler
         * because it needs a C++ compiler; in that case we will
         * fall through to the default print_insn_od case.
         */
#if defined(CONFIG_ARM_A64_DIS)
        s.info.print_insn = print_insn_arm_a64;
#endif
    } else if (flags & 1) {
        s.info.print_insn = print_insn_thumb1;
    } else {
        s.info.print_insn = print_insn_arm;
    }
    if (flags & 2) {
#ifdef TARGET_WORDS_BIGENDIAN
        s.info.endian = BFD_ENDIAN_LITTLE;
#else
        s.info.endian = BFD_ENDIAN_BIG;
#endif
    }
#elif defined(TARGET_SPARC)
    s.info.print_insn = print_insn_sparc;
#ifdef TARGET_SPARC64
    s.info.mach = bfd_mach_sparc_v9b;
#endif
#elif defined(TARGET_PPC)
    if ((flags >> 16) & 1) {
        s.info.endian = BFD_ENDIAN_LITTLE;
    }
    if (flags & 0xFFFF) {
        /* If we have a precise definition of the instruction set, use it. */
        s.info.mach = flags & 0xFFFF;
    } else {
#ifdef TARGET_PPC64
        s.info.mach = bfd_mach_ppc64;
#else
        s.info.mach = bfd_mach_ppc;
#endif
    }
    s.info.disassembler_options = (char *)"any";
    s.info.print_insn = print_insn_ppc;
#elif defined(TARGET_M68K)
    s.info.print_insn = print_insn_m68k;
#elif defined(TARGET_MIPS)
#ifdef TARGET_WORDS_BIGENDIAN
    s.info.print_insn = print_insn_big_mips;
#else
    s.info.print_insn = print_insn_little_mips;
#endif
#elif defined(TARGET_SH4)
    s.info.mach = bfd_mach_sh4;
    s.info.print_insn = print_insn_sh;
#elif defined(TARGET_ALPHA)
    s.info.mach = bfd_mach_alpha_ev6;
    s.info.print_insn = print_insn_alpha;
#elif defined(TARGET_CRIS)
    if (flags != 32) {
        s.info.mach = bfd_mach_cris_v0_v10;
        s.info.print_insn = print_insn_crisv10;
    } else {
        s.info.mach = bfd_mach_cris_v32;
        s.info.print_insn = print_insn_crisv32;
    }
#elif defined(TARGET_S390X)
    s.info.mach = bfd_mach_s390_64;
    s.info.print_insn = print_insn_s390;
#elif defined(TARGET_MICROBLAZE)
    s.info.mach = bfd_arch_microblaze;
    s.info.print_insn = print_insn_microblaze;
#elif defined(TARGET_MOXIE)
    s.info.mach = bfd_arch_moxie;
    s.info.print_insn = print_insn_moxie;
#elif defined(TARGET_LM32)
    s.info.mach = bfd_mach_lm32;
    s.info.print_insn = print_insn_lm32;
#endif
    if (s.info.print_insn == NULL) {
        s.info.print_insn = print_insn_od_target;
    }

    for (pc = code; size > 0; pc += count, size -= count) {
	fprintf(out, "0x" TARGET_FMT_lx ":  ", pc);
	count = s.info.print_insn(pc, &s.info);
#if 0
        {
            int i;
            uint8_t b;
            fprintf(out, " {");
            for(i = 0; i < count; i++) {
                target_read_memory(pc + i, &b, 1, &s.info);
                fprintf(out, " %02x", b);
            }
            fprintf(out, " }");
        }
#endif
	fprintf(out, "\n");
	if (count < 0)
	    break;
        if (size < count) {
            fprintf(out,
                    "Disassembler disagrees with translator over instruction "
                    "decoding\n"
                    "Please report this to qemu-devel@nongnu.org\n");
            break;
        }
    }
}

/* Disassemble this for me please... (debugging). */
void disas(FILE *out, void *code, unsigned long size)
{
    uintptr_t pc;
    int count;
    CPUDebug s;
    int (*print_insn)(bfd_vma pc, disassemble_info *info) = NULL;

    INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
    s.info.print_address_func = generic_print_host_address;

    s.info.buffer = code;
    s.info.buffer_vma = (uintptr_t)code;
    s.info.buffer_length = size;

#ifdef HOST_WORDS_BIGENDIAN
    s.info.endian = BFD_ENDIAN_BIG;
#else
    s.info.endian = BFD_ENDIAN_LITTLE;
#endif
#if defined(CONFIG_TCG_INTERPRETER)
    print_insn = print_insn_tci;
#elif defined(__i386__)
    s.info.mach = bfd_mach_i386_i386;
    print_insn = print_insn_i386;
#elif defined(__x86_64__)
    s.info.mach = bfd_mach_x86_64;
    print_insn = print_insn_i386;
#elif defined(_ARCH_PPC)
    s.info.disassembler_options = (char *)"any";
    print_insn = print_insn_ppc;
#elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
    print_insn = print_insn_arm_a64;
#elif defined(__alpha__)
    print_insn = print_insn_alpha;
#elif defined(__sparc__)
    print_insn = print_insn_sparc;
    s.info.mach = bfd_mach_sparc_v9b;
#elif defined(__arm__)
    print_insn = print_insn_arm;
#elif defined(__MIPSEB__)
    print_insn = print_insn_big_mips;
#elif defined(__MIPSEL__)
    print_insn = print_insn_little_mips;
#elif defined(__m68k__)
    print_insn = print_insn_m68k;
#elif defined(__s390__)
    print_insn = print_insn_s390;
#elif defined(__hppa__)
    print_insn = print_insn_hppa;
#elif defined(__ia64__)
    print_insn = print_insn_ia64;
#endif
    if (print_insn == NULL) {
        print_insn = print_insn_od_host;
    }
    for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
        fprintf(out, "0x%08" PRIxPTR ":  ", pc);
        count = print_insn(pc, &s.info);
	fprintf(out, "\n");
	if (count < 0)
	    break;
    }
}

/* Look up symbol for debugging purpose.  Returns "" if unknown. */
const char *lookup_symbol(target_ulong orig_addr)
{
    const char *symbol = "";
    struct syminfo *s;

    for (s = syminfos; s; s = s->next) {
        symbol = s->lookup_symbol(s, orig_addr);
        if (symbol[0] != '\0') {
            break;
        }
    }

    return symbol;
}

#if !defined(CONFIG_USER_ONLY)

#include "monitor/monitor.h"

static int monitor_disas_is_physical;

static int
monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
                     struct disassemble_info *info)
{
    CPUDebug *s = container_of(info, CPUDebug, info);

    if (monitor_disas_is_physical) {
        cpu_physical_memory_read(memaddr, myaddr, length);
    } else {
        cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
    }
    return 0;
}

static int GCC_FMT_ATTR(2, 3)
monitor_fprintf(FILE *stream, const char *fmt, ...)
{
    va_list ap;
    va_start(ap, fmt);
    monitor_vprintf((Monitor *)stream, fmt, ap);
    va_end(ap);
    return 0;
}

/* Disassembler for the monitor.
   See target_disas for a description of flags. */
void monitor_disas(Monitor *mon, CPUState *cpu,
                   target_ulong pc, int nb_insn, int is_physical, int flags)
{
    int count, i;
    CPUDebug s;

    INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf);

    s.cpu = cpu;
    monitor_disas_is_physical = is_physical;
    s.info.read_memory_func = monitor_read_memory;
    s.info.print_address_func = generic_print_target_address;

    s.info.buffer_vma = pc;

#ifdef TARGET_WORDS_BIGENDIAN
    s.info.endian = BFD_ENDIAN_BIG;
#else
    s.info.endian = BFD_ENDIAN_LITTLE;
#endif
#if defined(TARGET_I386)
    if (flags == 2) {
        s.info.mach = bfd_mach_x86_64;
    } else if (flags == 1) {
        s.info.mach = bfd_mach_i386_i8086;
    } else {
        s.info.mach = bfd_mach_i386_i386;
    }
    s.info.print_insn = print_insn_i386;
#elif defined(TARGET_ARM)
    s.info.print_insn = print_insn_arm;
#elif defined(TARGET_ALPHA)
    s.info.print_insn = print_insn_alpha;
#elif defined(TARGET_SPARC)
    s.info.print_insn = print_insn_sparc;
#ifdef TARGET_SPARC64
    s.info.mach = bfd_mach_sparc_v9b;
#endif
#elif defined(TARGET_PPC)
    if (flags & 0xFFFF) {
        /* If we have a precise definition of the instruction set, use it. */
        s.info.mach = flags & 0xFFFF;
    } else {
#ifdef TARGET_PPC64
        s.info.mach = bfd_mach_ppc64;
#else
        s.info.mach = bfd_mach_ppc;
#endif
    }
    if ((flags >> 16) & 1) {
        s.info.endian = BFD_ENDIAN_LITTLE;
    }
    s.info.print_insn = print_insn_ppc;
#elif defined(TARGET_M68K)
    s.info.print_insn = print_insn_m68k;
#elif defined(TARGET_MIPS)
#ifdef TARGET_WORDS_BIGENDIAN
    s.info.print_insn = print_insn_big_mips;
#else
    s.info.print_insn = print_insn_little_mips;
#endif
#elif defined(TARGET_SH4)
    s.info.mach = bfd_mach_sh4;
    s.info.print_insn = print_insn_sh;
#elif defined(TARGET_S390X)
    s.info.mach = bfd_mach_s390_64;
    s.info.print_insn = print_insn_s390;
#elif defined(TARGET_MOXIE)
    s.info.mach = bfd_arch_moxie;
    s.info.print_insn = print_insn_moxie;
#elif defined(TARGET_LM32)
    s.info.mach = bfd_mach_lm32;
    s.info.print_insn = print_insn_lm32;
#else
    monitor_printf(mon, "0x" TARGET_FMT_lx
                   ": Asm output not supported on this arch\n", pc);
    return;
#endif

    for(i = 0; i < nb_insn; i++) {
	monitor_printf(mon, "0x" TARGET_FMT_lx ":  ", pc);
        count = s.info.print_insn(pc, &s.info);
	monitor_printf(mon, "\n");
	if (count < 0)
	    break;
        pc += count;
    }
}
#endif
Commit	Line	Data
b9adb4a6	1	/* General "disassemble this chunk" code. Used for debugging. */
5bbe9299	2	#include "config.h"
76cad711	3	#include "disas/bfd.h"
b9adb4a6	4	#include "elf.h"
aa0aa4fa	5	#include <errno.h>
b9adb4a6	6
c6105c0a	7	#include "cpu.h"
76cad711	8	#include "disas/disas.h"
c6105c0a	9
f4359b9f BS	10	typedef struct CPUDebug {
f4359b9f BS	11	struct disassemble_info info;
d49190c4	12	CPUState *cpu;
f4359b9f BS	13	} CPUDebug;
f4359b9f BS	14
b9adb4a6	15	/* Filled in by elfload.c. Simplistic, but will do for now. */
e80cfcfc	16	struct syminfo *syminfos = NULL;
b9adb4a6	17
aa0aa4fa FB	18	/* Get LENGTH bytes from info's buffer, at target address memaddr.
	19	Transfer them to myaddr. */
	20	int
3a742b76 PB	21	buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
3a742b76 PB	22	struct disassemble_info *info)
aa0aa4fa	23	{
c6105c0a FB	24	if (memaddr < info->buffer_vma
	25	\|\| memaddr + length > info->buffer_vma + info->buffer_length)
	26	/* Out of bounds. Use EIO because GDB uses it. */
	27	return EIO;
	28	memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
	29	return 0;
aa0aa4fa FB	30	}
aa0aa4fa FB	31
c6105c0a FB	32	/* Get LENGTH bytes from info's buffer, at target address memaddr.
	33	Transfer them to myaddr. */
	34	static int
c27004ec FB	35	target_read_memory (bfd_vma memaddr,
	36	bfd_byte *myaddr,
	37	int length,
	38	struct disassemble_info *info)
c6105c0a	39	{
f4359b9f BS	40	CPUDebug *s = container_of(info, CPUDebug, info);
f4359b9f BS	41
d49190c4	42	cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
c6105c0a FB	43	return 0;
c6105c0a FB	44	}
c6105c0a	45
aa0aa4fa FB	46	/* Print an error message. We can assume that this is in response to
	47	an error return from buffer_read_memory. */
	48	void
3a742b76	49	perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info)
aa0aa4fa FB	50	{
	51	if (status != EIO)
	52	/* Can't happen. */
	53	(*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
	54	else
	55	/* Actually, address between memaddr and memaddr + len was
	56	out of bounds. */
	57	(*info->fprintf_func) (info->stream,
26a76461	58	"Address 0x%" PRIx64 " is out of bounds.\n", memaddr);
aa0aa4fa FB	59	}
aa0aa4fa FB	60
a31f0531	61	/* This could be in a separate file, to save minuscule amounts of space
aa0aa4fa FB	62	in statically linked executables. */
	63
	64	/* Just print the address is hex. This is included for completeness even
	65	though both GDB and objdump provide their own (to print symbolic
	66	addresses). */
	67
	68	void
3a742b76	69	generic_print_address (bfd_vma addr, struct disassemble_info *info)
aa0aa4fa	70	{
26a76461	71	(*info->fprintf_func) (info->stream, "0x%" PRIx64, addr);
aa0aa4fa FB	72	}
aa0aa4fa FB	73
636bd289 PM	74	/* Print address in hex, truncated to the width of a target virtual address. */
	75	static void
	76	generic_print_target_address(bfd_vma addr, struct disassemble_info *info)
	77	{
	78	uint64_t mask = ~0ULL >> (64 - TARGET_VIRT_ADDR_SPACE_BITS);
	79	generic_print_address(addr & mask, info);
	80	}
	81
	82	/* Print address in hex, truncated to the width of a host virtual address. */
	83	static void
	84	generic_print_host_address(bfd_vma addr, struct disassemble_info *info)
	85	{
	86	uint64_t mask = ~0ULL >> (64 - (sizeof(void ) 8));
	87	generic_print_address(addr & mask, info);
	88	}
	89
aa0aa4fa FB	90	/* Just return the given address. */
	91
	92	int
3a742b76	93	generic_symbol_at_address (bfd_vma addr, struct disassemble_info *info)
aa0aa4fa FB	94	{
	95	return 1;
	96	}
	97
903ec55c AJ	98	bfd_vma bfd_getl64 (const bfd_byte *addr)
	99	{
	100	unsigned long long v;
	101
	102	v = (unsigned long long) addr[0];
	103	v \|= (unsigned long long) addr[1] << 8;
	104	v \|= (unsigned long long) addr[2] << 16;
	105	v \|= (unsigned long long) addr[3] << 24;
	106	v \|= (unsigned long long) addr[4] << 32;
	107	v \|= (unsigned long long) addr[5] << 40;
	108	v \|= (unsigned long long) addr[6] << 48;
	109	v \|= (unsigned long long) addr[7] << 56;
	110	return (bfd_vma) v;
	111	}
	112
aa0aa4fa FB	113	bfd_vma bfd_getl32 (const bfd_byte *addr)
	114	{
	115	unsigned long v;
	116
	117	v = (unsigned long) addr[0];
	118	v \|= (unsigned long) addr[1] << 8;
	119	v \|= (unsigned long) addr[2] << 16;
	120	v \|= (unsigned long) addr[3] << 24;
	121	return (bfd_vma) v;
	122	}
	123
	124	bfd_vma bfd_getb32 (const bfd_byte *addr)
	125	{
	126	unsigned long v;
	127
	128	v = (unsigned long) addr[0] << 24;
	129	v \|= (unsigned long) addr[1] << 16;
	130	v \|= (unsigned long) addr[2] << 8;
	131	v \|= (unsigned long) addr[3];
	132	return (bfd_vma) v;
	133	}
	134
6af0bf9c FB	135	bfd_vma bfd_getl16 (const bfd_byte *addr)
	136	{
	137	unsigned long v;
	138
	139	v = (unsigned long) addr[0];
	140	v \|= (unsigned long) addr[1] << 8;
	141	return (bfd_vma) v;
	142	}
	143
	144	bfd_vma bfd_getb16 (const bfd_byte *addr)
	145	{
	146	unsigned long v;
	147
	148	v = (unsigned long) addr[0] << 24;
	149	v \|= (unsigned long) addr[1] << 16;
	150	return (bfd_vma) v;
	151	}
	152
c2d551ff FB	153	#ifdef TARGET_ARM
	154	static int
	155	print_insn_thumb1(bfd_vma pc, disassemble_info *info)
	156	{
	157	return print_insn_arm(pc \| 1, info);
	158	}
	159	#endif
	160
c46ffd57 RH	161	static int print_insn_objdump(bfd_vma pc, disassemble_info *info,
	162	const char *prefix)
	163	{
	164	int i, n = info->buffer_length;
	165	uint8_t *buf = g_malloc(n);
	166
	167	info->read_memory_func(pc, buf, n, info);
	168
	169	for (i = 0; i < n; ++i) {
	170	if (i % 32 == 0) {
	171	info->fprintf_func(info->stream, "\n%s: ", prefix);
	172	}
	173	info->fprintf_func(info->stream, "%02x", buf[i]);
	174	}
	175
	176	g_free(buf);
	177	return n;
	178	}
	179
	180	static int print_insn_od_host(bfd_vma pc, disassemble_info *info)
	181	{
	182	return print_insn_objdump(pc, info, "OBJD-H");
	183	}
	184
	185	static int print_insn_od_target(bfd_vma pc, disassemble_info *info)
	186	{
	187	return print_insn_objdump(pc, info, "OBJD-T");
	188	}
	189
e91c8a77	190	/* Disassemble this for me please... (debugging). 'flags' has the following
c2d551ff	191	values:
e99722f6	192	i386 - 1 means 16 bit code, 2 means 64 bit code
999b53ec	193	arm - bit 0 = thumb, bit 1 = reverse endian, bit 2 = A64
e13951f8 TM	194	ppc - bits 0:15 specify (optionally) the machine instruction set;
e13951f8 TM	195	bit 16 indicates little endian.
c2d551ff FB	196	other targets - unused
c2d551ff FB	197	*/
d49190c4	198	void target_disas(FILE out, CPUState cpu, target_ulong code,
f4359b9f	199	target_ulong size, int flags)
b9adb4a6	200	{
c27004ec	201	target_ulong pc;
b9adb4a6	202	int count;
f4359b9f	203	CPUDebug s;
b9adb4a6	204
f4359b9f	205	INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
b9adb4a6	206
d49190c4	207	s.cpu = cpu;
f4359b9f BS	208	s.info.read_memory_func = target_read_memory;
	209	s.info.buffer_vma = code;
	210	s.info.buffer_length = size;
	211	s.info.print_address_func = generic_print_target_address;
c27004ec FB	212
c27004ec FB	213	#ifdef TARGET_WORDS_BIGENDIAN
f4359b9f	214	s.info.endian = BFD_ENDIAN_BIG;
c27004ec	215	#else
f4359b9f	216	s.info.endian = BFD_ENDIAN_LITTLE;
c27004ec FB	217	#endif
c27004ec FB	218	#if defined(TARGET_I386)
f4359b9f BS	219	if (flags == 2) {
	220	s.info.mach = bfd_mach_x86_64;
	221	} else if (flags == 1) {
	222	s.info.mach = bfd_mach_i386_i8086;
	223	} else {
	224	s.info.mach = bfd_mach_i386_i386;
	225	}
2de295c5	226	s.info.print_insn = print_insn_i386;
c27004ec	227	#elif defined(TARGET_ARM)
999b53ec CF	228	if (flags & 4) {
	229	/* We might not be compiled with the A64 disassembler
	230	* because it needs a C++ compiler; in that case we will
	231	* fall through to the default print_insn_od case.
	232	*/
	233	#if defined(CONFIG_ARM_A64_DIS)
2de295c5	234	s.info.print_insn = print_insn_arm_a64;
999b53ec CF	235	#endif
999b53ec CF	236	} else if (flags & 1) {
2de295c5	237	s.info.print_insn = print_insn_thumb1;
d8fd2954	238	} else {
2de295c5	239	s.info.print_insn = print_insn_arm;
d8fd2954 PB	240	}
	241	if (flags & 2) {
	242	#ifdef TARGET_WORDS_BIGENDIAN
f4359b9f	243	s.info.endian = BFD_ENDIAN_LITTLE;
d8fd2954	244	#else
f4359b9f	245	s.info.endian = BFD_ENDIAN_BIG;
d8fd2954 PB	246	#endif
d8fd2954 PB	247	}
c27004ec	248	#elif defined(TARGET_SPARC)
2de295c5	249	s.info.print_insn = print_insn_sparc;
3475187d	250	#ifdef TARGET_SPARC64
f4359b9f	251	s.info.mach = bfd_mach_sparc_v9b;
3b46e624	252	#endif
c27004ec	253	#elif defined(TARGET_PPC)
e13951f8	254	if ((flags >> 16) & 1) {
f4359b9f BS	255	s.info.endian = BFD_ENDIAN_LITTLE;
f4359b9f BS	256	}
237c0af0	257	if (flags & 0xFFFF) {
e13951f8	258	/* If we have a precise definition of the instruction set, use it. */
f4359b9f	259	s.info.mach = flags & 0xFFFF;
237c0af0	260	} else {
a2458627	261	#ifdef TARGET_PPC64
f4359b9f	262	s.info.mach = bfd_mach_ppc64;
a2458627	263	#else
f4359b9f	264	s.info.mach = bfd_mach_ppc;
a2458627	265	#endif
237c0af0	266	}
88770fec	267	s.info.disassembler_options = (char *)"any";
2de295c5	268	s.info.print_insn = print_insn_ppc;
e6e5906b	269	#elif defined(TARGET_M68K)
2de295c5	270	s.info.print_insn = print_insn_m68k;
6af0bf9c	271	#elif defined(TARGET_MIPS)
76b3030c	272	#ifdef TARGET_WORDS_BIGENDIAN
2de295c5	273	s.info.print_insn = print_insn_big_mips;
76b3030c	274	#else
2de295c5	275	s.info.print_insn = print_insn_little_mips;
76b3030c	276	#endif
fdf9b3e8	277	#elif defined(TARGET_SH4)
f4359b9f	278	s.info.mach = bfd_mach_sh4;
2de295c5	279	s.info.print_insn = print_insn_sh;
eddf68a6	280	#elif defined(TARGET_ALPHA)
f4359b9f	281	s.info.mach = bfd_mach_alpha_ev6;
2de295c5	282	s.info.print_insn = print_insn_alpha;
a25fd137	283	#elif defined(TARGET_CRIS)
b09cd072	284	if (flags != 32) {
f4359b9f	285	s.info.mach = bfd_mach_cris_v0_v10;
2de295c5	286	s.info.print_insn = print_insn_crisv10;
b09cd072	287	} else {
f4359b9f	288	s.info.mach = bfd_mach_cris_v32;
2de295c5	289	s.info.print_insn = print_insn_crisv32;
b09cd072	290	}
db500609	291	#elif defined(TARGET_S390X)
f4359b9f	292	s.info.mach = bfd_mach_s390_64;
2de295c5	293	s.info.print_insn = print_insn_s390;
e90e390c	294	#elif defined(TARGET_MICROBLAZE)
f4359b9f	295	s.info.mach = bfd_arch_microblaze;
2de295c5	296	s.info.print_insn = print_insn_microblaze;
bd86a88e AG	297	#elif defined(TARGET_MOXIE)
bd86a88e AG	298	s.info.mach = bfd_arch_moxie;
2de295c5	299	s.info.print_insn = print_insn_moxie;
79368f49	300	#elif defined(TARGET_LM32)
f4359b9f	301	s.info.mach = bfd_mach_lm32;
2de295c5	302	s.info.print_insn = print_insn_lm32;
c6105c0a	303	#endif
2de295c5 PC	304	if (s.info.print_insn == NULL) {
2de295c5 PC	305	s.info.print_insn = print_insn_od_target;
c46ffd57	306	}
c6105c0a	307
7e000c2e	308	for (pc = code; size > 0; pc += count, size -= count) {
fa15e030	309	fprintf(out, "0x" TARGET_FMT_lx ": ", pc);
2de295c5	310	count = s.info.print_insn(pc, &s.info);
c27004ec FB	311	#if 0
	312	{
	313	int i;
	314	uint8_t b;
	315	fprintf(out, " {");
	316	for(i = 0; i < count; i++) {
f4359b9f	317	target_read_memory(pc + i, &b, 1, &s.info);
c27004ec FB	318	fprintf(out, " %02x", b);
	319	}
	320	fprintf(out, " }");
	321	}
	322	#endif
	323	fprintf(out, "\n");
	324	if (count < 0)
	325	break;
754d00ae	326	if (size < count) {
	327	fprintf(out,
	328	"Disassembler disagrees with translator over instruction "
	329	"decoding\n"
	330	"Please report this to qemu-devel@nongnu.org\n");
	331	break;
	332	}
c27004ec FB	333	}
	334	}
	335
	336	/* Disassemble this for me please... (debugging). */
	337	void disas(FILE out, void code, unsigned long size)
	338	{
b0b0f1c9	339	uintptr_t pc;
c27004ec	340	int count;
f4359b9f	341	CPUDebug s;
c46ffd57	342	int (print_insn)(bfd_vma pc, disassemble_info info) = NULL;
c27004ec	343
f4359b9f BS	344	INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
f4359b9f BS	345	s.info.print_address_func = generic_print_host_address;
c27004ec	346
f4359b9f BS	347	s.info.buffer = code;
	348	s.info.buffer_vma = (uintptr_t)code;
	349	s.info.buffer_length = size;
b9adb4a6	350
e2542fe2	351	#ifdef HOST_WORDS_BIGENDIAN
f4359b9f	352	s.info.endian = BFD_ENDIAN_BIG;
b9adb4a6	353	#else
f4359b9f	354	s.info.endian = BFD_ENDIAN_LITTLE;
b9adb4a6	355	#endif
5826e519 SW	356	#if defined(CONFIG_TCG_INTERPRETER)
	357	print_insn = print_insn_tci;
	358	#elif defined(__i386__)
f4359b9f	359	s.info.mach = bfd_mach_i386_i386;
c27004ec	360	print_insn = print_insn_i386;
bc51c5c9	361	#elif defined(__x86_64__)
f4359b9f	362	s.info.mach = bfd_mach_x86_64;
c27004ec	363	print_insn = print_insn_i386;
e58ffeb3	364	#elif defined(_ARCH_PPC)
66d4f6a3	365	s.info.disassembler_options = (char *)"any";
c27004ec	366	print_insn = print_insn_ppc;
999b53ec CF	367	#elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
999b53ec CF	368	print_insn = print_insn_arm_a64;
a993ba85	369	#elif defined(__alpha__)
c27004ec	370	print_insn = print_insn_alpha;
aa0aa4fa	371	#elif defined(__sparc__)
c27004ec	372	print_insn = print_insn_sparc;
f4359b9f	373	s.info.mach = bfd_mach_sparc_v9b;
5fafdf24	374	#elif defined(__arm__)
c27004ec	375	print_insn = print_insn_arm;
6af0bf9c FB	376	#elif defined(__MIPSEB__)
	377	print_insn = print_insn_big_mips;
	378	#elif defined(__MIPSEL__)
	379	print_insn = print_insn_little_mips;
48024e4a FB	380	#elif defined(__m68k__)
48024e4a FB	381	print_insn = print_insn_m68k;
8f860bb8 TS	382	#elif defined(__s390__)
8f860bb8 TS	383	print_insn = print_insn_s390;
f54b3f92 AJ	384	#elif defined(__hppa__)
f54b3f92 AJ	385	print_insn = print_insn_hppa;
903ec55c AJ	386	#elif defined(__ia64__)
903ec55c AJ	387	print_insn = print_insn_ia64;
b9adb4a6	388	#endif
c46ffd57 RH	389	if (print_insn == NULL) {
	390	print_insn = print_insn_od_host;
	391	}
b0b0f1c9 SW	392	for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
b0b0f1c9 SW	393	fprintf(out, "0x%08" PRIxPTR ": ", pc);
f4359b9f	394	count = print_insn(pc, &s.info);
b9adb4a6 FB	395	fprintf(out, "\n");
	396	if (count < 0)
	397	break;
	398	}
	399	}
	400
	401	/* Look up symbol for debugging purpose. Returns "" if unknown. */
c27004ec	402	const char *lookup_symbol(target_ulong orig_addr)
b9adb4a6	403	{
49918a75	404	const char *symbol = "";
e80cfcfc	405	struct syminfo *s;
3b46e624	406
e80cfcfc	407	for (s = syminfos; s; s = s->next) {
49918a75 PB	408	symbol = s->lookup_symbol(s, orig_addr);
	409	if (symbol[0] != '\0') {
	410	break;
	411	}
b9adb4a6	412	}
49918a75 PB	413
49918a75 PB	414	return symbol;
b9adb4a6	415	}
9307c4c1 FB	416
	417	#if !defined(CONFIG_USER_ONLY)
	418
83c9089e	419	#include "monitor/monitor.h"
3d2cfdf1	420
9307c4c1 FB	421	static int monitor_disas_is_physical;
	422
	423	static int
a5f1b965 BS	424	monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
a5f1b965 BS	425	struct disassemble_info *info)
9307c4c1	426	{
f4359b9f BS	427	CPUDebug *s = container_of(info, CPUDebug, info);
f4359b9f BS	428
9307c4c1	429	if (monitor_disas_is_physical) {
54f7b4a3	430	cpu_physical_memory_read(memaddr, myaddr, length);
9307c4c1	431	} else {
d49190c4	432	cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0);
9307c4c1 FB	433	}
	434	return 0;
	435	}
	436
8b7968f7 SW	437	static int GCC_FMT_ATTR(2, 3)
8b7968f7 SW	438	monitor_fprintf(FILE stream, const char fmt, ...)
3d2cfdf1 FB	439	{
	440	va_list ap;
	441	va_start(ap, fmt);
376253ec	442	monitor_vprintf((Monitor *)stream, fmt, ap);
3d2cfdf1 FB	443	va_end(ap);
	444	return 0;
	445	}
	446
1c38f843 TM	447	/* Disassembler for the monitor.
1c38f843 TM	448	See target_disas for a description of flags. */
d49190c4	449	void monitor_disas(Monitor mon, CPUState cpu,
6a00d601	450	target_ulong pc, int nb_insn, int is_physical, int flags)
9307c4c1	451	{
9307c4c1	452	int count, i;
f4359b9f	453	CPUDebug s;
9307c4c1	454
f4359b9f	455	INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf);
9307c4c1	456
d49190c4	457	s.cpu = cpu;
9307c4c1	458	monitor_disas_is_physical = is_physical;
f4359b9f BS	459	s.info.read_memory_func = monitor_read_memory;
f4359b9f BS	460	s.info.print_address_func = generic_print_target_address;
9307c4c1	461
f4359b9f	462	s.info.buffer_vma = pc;
9307c4c1 FB	463
9307c4c1 FB	464	#ifdef TARGET_WORDS_BIGENDIAN
f4359b9f	465	s.info.endian = BFD_ENDIAN_BIG;
9307c4c1	466	#else
f4359b9f	467	s.info.endian = BFD_ENDIAN_LITTLE;
9307c4c1 FB	468	#endif
9307c4c1 FB	469	#if defined(TARGET_I386)
f4359b9f BS	470	if (flags == 2) {
	471	s.info.mach = bfd_mach_x86_64;
	472	} else if (flags == 1) {
	473	s.info.mach = bfd_mach_i386_i8086;
	474	} else {
	475	s.info.mach = bfd_mach_i386_i386;
	476	}
2de295c5	477	s.info.print_insn = print_insn_i386;
9307c4c1	478	#elif defined(TARGET_ARM)
2de295c5	479	s.info.print_insn = print_insn_arm;
cbd669da	480	#elif defined(TARGET_ALPHA)
2de295c5	481	s.info.print_insn = print_insn_alpha;
9307c4c1	482	#elif defined(TARGET_SPARC)
2de295c5	483	s.info.print_insn = print_insn_sparc;
682c4f15	484	#ifdef TARGET_SPARC64
f4359b9f	485	s.info.mach = bfd_mach_sparc_v9b;
682c4f15	486	#endif
9307c4c1	487	#elif defined(TARGET_PPC)
1c38f843 TM	488	if (flags & 0xFFFF) {
	489	/* If we have a precise definition of the instruction set, use it. */
	490	s.info.mach = flags & 0xFFFF;
	491	} else {
a2458627	492	#ifdef TARGET_PPC64
1c38f843	493	s.info.mach = bfd_mach_ppc64;
a2458627	494	#else
1c38f843	495	s.info.mach = bfd_mach_ppc;
a2458627	496	#endif
1c38f843 TM	497	}
	498	if ((flags >> 16) & 1) {
	499	s.info.endian = BFD_ENDIAN_LITTLE;
	500	}
2de295c5	501	s.info.print_insn = print_insn_ppc;
e6e5906b	502	#elif defined(TARGET_M68K)
2de295c5	503	s.info.print_insn = print_insn_m68k;
6af0bf9c	504	#elif defined(TARGET_MIPS)
76b3030c	505	#ifdef TARGET_WORDS_BIGENDIAN
2de295c5	506	s.info.print_insn = print_insn_big_mips;
76b3030c	507	#else
2de295c5	508	s.info.print_insn = print_insn_little_mips;
76b3030c	509	#endif
b4e1f077	510	#elif defined(TARGET_SH4)
f4359b9f	511	s.info.mach = bfd_mach_sh4;
2de295c5	512	s.info.print_insn = print_insn_sh;
db500609	513	#elif defined(TARGET_S390X)
f4359b9f	514	s.info.mach = bfd_mach_s390_64;
2de295c5	515	s.info.print_insn = print_insn_s390;
bd86a88e AG	516	#elif defined(TARGET_MOXIE)
bd86a88e AG	517	s.info.mach = bfd_arch_moxie;
2de295c5	518	s.info.print_insn = print_insn_moxie;
79368f49	519	#elif defined(TARGET_LM32)
f4359b9f	520	s.info.mach = bfd_mach_lm32;
2de295c5	521	s.info.print_insn = print_insn_lm32;
9307c4c1	522	#else
376253ec AL	523	monitor_printf(mon, "0x" TARGET_FMT_lx
376253ec AL	524	": Asm output not supported on this arch\n", pc);
9307c4c1 FB	525	return;
	526	#endif
	527
	528	for(i = 0; i < nb_insn; i++) {
376253ec	529	monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
2de295c5	530	count = s.info.print_insn(pc, &s.info);
376253ec	531	monitor_printf(mon, "\n");
9307c4c1 FB	532	if (count < 0)
	533	break;
	534	pc += count;
	535	}
	536	}
	537	#endif