projects / mirror_ubuntu-disco-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1b44c5a6 AT |
1 | /* |
| 2 | * Copyright (C) 2017 Marvell | |
| 3 | * | |
| 4 | * Antoine Tenart <antoine.tenart@free-electrons.com> | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public | |
| 7 | * License version 2. This program is licensed "as is" without any | |
| 8 | * warranty of any kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __SAFEXCEL_H__ | |
| 12 | #define __SAFEXCEL_H__ | |
| 13 | ||
| f6beaea3 | 14 | #include <crypto/aead.h> |
| 1b44c5a6 AT |
15 | #include <crypto/algapi.h> |
| 16 | #include <crypto/internal/hash.h> | |
| f6beaea3 | 17 | #include <crypto/sha.h> |
| 1b44c5a6 AT |
18 | #include <crypto/skcipher.h> |
| 19 | ||
| 20 | #define EIP197_HIA_VERSION_LE 0xca35 | |
| 21 | #define EIP197_HIA_VERSION_BE 0x35ca | |
| 22 | ||
| 23 | /* Static configuration */ | |
| fc8c72b2 | 24 | #define EIP197_DEFAULT_RING_SIZE 400 |
| f6beaea3 | 25 | #define EIP197_MAX_TOKENS 8 |
| 1b44c5a6 AT |
26 | #define EIP197_MAX_RINGS 4 |
| 27 | #define EIP197_FETCH_COUNT 1 | |
| fc8c72b2 | 28 | #define EIP197_MAX_BATCH_SZ 64 |
| 1b44c5a6 AT |
29 | |
| 30 | #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \ | |
| 31 | GFP_KERNEL : GFP_ATOMIC) | |
| 32 | ||
| 61824806 AT |
33 | /* Custom on-stack requests (for invalidation) */ |
| 34 | #define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \ | |
| 35 | sizeof(struct safexcel_cipher_req) | |
| 36 | #define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \ | |
| 37 | sizeof(struct safexcel_ahash_req) | |
| f6beaea3 AT |
38 | #define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \ |
| 39 | sizeof(struct safexcel_cipher_req) | |
| 61824806 AT |
40 | #define EIP197_REQUEST_ON_STACK(name, type, size) \ |
| 41 | char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \ | |
| 42 | struct type##_request *name = (void *)__##name##_desc | |
| 43 | ||
| 871df319 AT |
44 | /* Register base offsets */ |
| 45 | #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic) | |
| 46 | #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g) | |
| 47 | #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r) | |
| 48 | #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr) | |
| 49 | #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe) | |
| 50 | #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr) | |
| 51 | #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse) | |
| 52 | #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr) | |
| 53 | #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg) | |
| 54 | #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe) | |
| 55 | ||
| 56 | /* EIP197 base offsets */ | |
| 57 | #define EIP197_HIA_AIC_BASE 0x90000 | |
| 58 | #define EIP197_HIA_AIC_G_BASE 0x90000 | |
| 59 | #define EIP197_HIA_AIC_R_BASE 0x90800 | |
| 60 | #define EIP197_HIA_AIC_xDR_BASE 0x80000 | |
| 61 | #define EIP197_HIA_DFE_BASE 0x8c000 | |
| 62 | #define EIP197_HIA_DFE_THR_BASE 0x8c040 | |
| 63 | #define EIP197_HIA_DSE_BASE 0x8d000 | |
| 64 | #define EIP197_HIA_DSE_THR_BASE 0x8d040 | |
| 65 | #define EIP197_HIA_GEN_CFG_BASE 0xf0000 | |
| 66 | #define EIP197_PE_BASE 0xa0000 | |
| 67 | ||
| 68 | /* EIP97 base offsets */ | |
| 69 | #define EIP97_HIA_AIC_BASE 0x0 | |
| 70 | #define EIP97_HIA_AIC_G_BASE 0x0 | |
| 71 | #define EIP97_HIA_AIC_R_BASE 0x0 | |
| 72 | #define EIP97_HIA_AIC_xDR_BASE 0x0 | |
| 73 | #define EIP97_HIA_DFE_BASE 0xf000 | |
| 74 | #define EIP97_HIA_DFE_THR_BASE 0xf200 | |
| 75 | #define EIP97_HIA_DSE_BASE 0xf400 | |
| 76 | #define EIP97_HIA_DSE_THR_BASE 0xf600 | |
| 77 | #define EIP97_HIA_GEN_CFG_BASE 0x10000 | |
| 78 | #define EIP97_PE_BASE 0x10000 | |
| 79 | ||
| 1b44c5a6 | 80 | /* CDR/RDR register offsets */ |
| 871df319 AT |
81 | #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000) |
| 82 | #define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r)) | |
| 83 | #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800) | |
| 84 | #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000 | |
| 85 | #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004 | |
| 86 | #define EIP197_HIA_xDR_RING_SIZE 0x0018 | |
| 87 | #define EIP197_HIA_xDR_DESC_SIZE 0x001c | |
| 88 | #define EIP197_HIA_xDR_CFG 0x0020 | |
| 89 | #define EIP197_HIA_xDR_DMA_CFG 0x0024 | |
| 90 | #define EIP197_HIA_xDR_THRESH 0x0028 | |
| 91 | #define EIP197_HIA_xDR_PREP_COUNT 0x002c | |
| 92 | #define EIP197_HIA_xDR_PROC_COUNT 0x0030 | |
| 93 | #define EIP197_HIA_xDR_PREP_PNTR 0x0034 | |
| 94 | #define EIP197_HIA_xDR_PROC_PNTR 0x0038 | |
| 95 | #define EIP197_HIA_xDR_STAT 0x003c | |
| 1b44c5a6 AT |
96 | |
| 97 | /* register offsets */ | |
| 871df319 AT |
98 | #define EIP197_HIA_DFE_CFG 0x0000 |
| 99 | #define EIP197_HIA_DFE_THR_CTRL 0x0000 | |
| 100 | #define EIP197_HIA_DFE_THR_STAT 0x0004 | |
| 101 | #define EIP197_HIA_DSE_CFG 0x0000 | |
| 102 | #define EIP197_HIA_DSE_THR_CTRL 0x0000 | |
| 103 | #define EIP197_HIA_DSE_THR_STAT 0x0004 | |
| 104 | #define EIP197_HIA_RA_PE_CTRL 0x0010 | |
| 105 | #define EIP197_HIA_RA_PE_STAT 0x0014 | |
| 1b44c5a6 | 106 | #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000) |
| 871df319 AT |
107 | #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r)) |
| 108 | #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) | |
| 109 | #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) | |
| 110 | #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r)) | |
| 111 | #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808 | |
| 112 | #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810 | |
| 113 | #define EIP197_HIA_AIC_G_ACK 0xf810 | |
| 114 | #define EIP197_HIA_MST_CTRL 0xfff4 | |
| 115 | #define EIP197_HIA_OPTIONS 0xfff8 | |
| 116 | #define EIP197_HIA_VERSION 0xfffc | |
| 117 | #define EIP197_PE_IN_DBUF_THRES 0x0000 | |
| 118 | #define EIP197_PE_IN_TBUF_THRES 0x0100 | |
| 119 | #define EIP197_PE_ICE_SCRATCH_RAM 0x0800 | |
| 120 | #define EIP197_PE_ICE_PUE_CTRL 0x0c80 | |
| 121 | #define EIP197_PE_ICE_SCRATCH_CTRL 0x0d04 | |
| 122 | #define EIP197_PE_ICE_FPP_CTRL 0x0d80 | |
| 123 | #define EIP197_PE_ICE_RAM_CTRL 0x0ff0 | |
| 124 | #define EIP197_PE_EIP96_FUNCTION_EN 0x1004 | |
| 125 | #define EIP197_PE_EIP96_CONTEXT_CTRL 0x1008 | |
| 126 | #define EIP197_PE_EIP96_CONTEXT_STAT 0x100c | |
| 127 | #define EIP197_PE_OUT_DBUF_THRES 0x1c00 | |
| 128 | #define EIP197_PE_OUT_TBUF_THRES 0x1d00 | |
| 129 | #define EIP197_MST_CTRL 0xfff4 | |
| 130 | ||
| 131 | /* EIP197-specific registers, no indirection */ | |
| 1b44c5a6 AT |
132 | #define EIP197_CLASSIFICATION_RAMS 0xe0000 |
| 133 | #define EIP197_TRC_CTRL 0xf0800 | |
| 134 | #define EIP197_TRC_LASTRES 0xf0804 | |
| 135 | #define EIP197_TRC_REGINDEX 0xf0808 | |
| 136 | #define EIP197_TRC_PARAMS 0xf0820 | |
| 137 | #define EIP197_TRC_FREECHAIN 0xf0824 | |
| 138 | #define EIP197_TRC_PARAMS2 0xf0828 | |
| 139 | #define EIP197_TRC_ECCCTRL 0xf0830 | |
| 140 | #define EIP197_TRC_ECCSTAT 0xf0834 | |
| 141 | #define EIP197_TRC_ECCADMINSTAT 0xf0838 | |
| 142 | #define EIP197_TRC_ECCDATASTAT 0xf083c | |
| 143 | #define EIP197_TRC_ECCDATA 0xf0840 | |
| 144 | #define EIP197_CS_RAM_CTRL 0xf7ff0 | |
| 1b44c5a6 AT |
145 | |
| 146 | /* EIP197_HIA_xDR_DESC_SIZE */ | |
| 147 | #define EIP197_xDR_DESC_MODE_64BIT BIT(31) | |
| 148 | ||
| 149 | /* EIP197_HIA_xDR_DMA_CFG */ | |
| 150 | #define EIP197_HIA_xDR_WR_RES_BUF BIT(22) | |
| d9107087 | 151 | #define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23) |
| 1b44c5a6 | 152 | #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24) |
| aefa794e | 153 | #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) |
| 1b44c5a6 AT |
154 | #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) |
| 155 | ||
| 156 | /* EIP197_HIA_CDR_THRESH */ | |
| 157 | #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) | |
| 158 | #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22) | |
| 159 | #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23) | |
| 160 | #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ | |
| 161 | ||
| 162 | /* EIP197_HIA_RDR_THRESH */ | |
| 163 | #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) | |
| 164 | #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23) | |
| 165 | #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ | |
| 166 | ||
| 167 | /* EIP197_HIA_xDR_PREP_COUNT */ | |
| 168 | #define EIP197_xDR_PREP_CLR_COUNT BIT(31) | |
| 169 | ||
| 170 | /* EIP197_HIA_xDR_PROC_COUNT */ | |
| 7f77f5a4 AT |
171 | #define EIP197_xDR_PROC_xD_PKT_OFFSET 24 |
| 172 | #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0) | |
| 1b44c5a6 AT |
173 | #define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2) |
| 174 | #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) | |
| 175 | #define EIP197_xDR_PROC_CLR_COUNT BIT(31) | |
| 176 | ||
| 177 | /* EIP197_HIA_xDR_STAT */ | |
| 178 | #define EIP197_xDR_DMA_ERR BIT(0) | |
| 179 | #define EIP197_xDR_PREP_CMD_THRES BIT(1) | |
| 180 | #define EIP197_xDR_ERR BIT(2) | |
| 181 | #define EIP197_xDR_THRESH BIT(4) | |
| 182 | #define EIP197_xDR_TIMEOUT BIT(5) | |
| 183 | ||
| 184 | #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31) | |
| 185 | #define EIP197_HIA_RA_PE_CTRL_EN BIT(30) | |
| 186 | ||
| 187 | /* EIP197_HIA_AIC_R_ENABLE_CTRL */ | |
| 188 | #define EIP197_CDR_IRQ(n) BIT((n) * 2) | |
| 189 | #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) | |
| 190 | ||
| 191 | /* EIP197_HIA_DFE/DSE_CFG */ | |
| 192 | #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) | |
| 193 | #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) | |
| 194 | #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) | |
| c2c55404 | 195 | #define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14) |
| 1b44c5a6 AT |
196 | #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) |
| 197 | #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) | |
| 198 | #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) | |
| 199 | #define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29)) | |
| c87925bf | 200 | #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) |
| 1b44c5a6 AT |
201 | #define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31) |
| 202 | ||
| 203 | /* EIP197_HIA_DFE/DSE_THR_CTRL */ | |
| 204 | #define EIP197_DxE_THR_CTRL_EN BIT(30) | |
| 205 | #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) | |
| 206 | ||
| 207 | /* EIP197_HIA_AIC_G_ENABLED_STAT */ | |
| 208 | #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) | |
| 209 | #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) | |
| 210 | #define EIP197_G_IRQ_RING BIT(16) | |
| 211 | #define EIP197_G_IRQ_PE(n) BIT((n) + 20) | |
| 212 | ||
| 213 | /* EIP197_HIA_MST_CTRL */ | |
| 214 | #define RD_CACHE_3BITS 0x5 | |
| 215 | #define WR_CACHE_3BITS 0x3 | |
| 216 | #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0)) | |
| 217 | #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0)) | |
| 218 | #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) | |
| 219 | #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) | |
| 220 | #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) | |
| 221 | #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) | |
| 222 | ||
| 223 | /* EIP197_PE_IN_DBUF/TBUF_THRES */ | |
| 224 | #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) | |
| 225 | #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) | |
| 226 | ||
| 227 | /* EIP197_PE_OUT_DBUF_THRES */ | |
| 228 | #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) | |
| 229 | #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) | |
| 230 | ||
| 231 | /* EIP197_PE_ICE_SCRATCH_CTRL */ | |
| 232 | #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2) | |
| 233 | #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3) | |
| 234 | #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24) | |
| 235 | #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25) | |
| 236 | ||
| 237 | /* EIP197_PE_ICE_SCRATCH_RAM */ | |
| 238 | #define EIP197_NUM_OF_SCRATCH_BLOCKS 32 | |
| 239 | ||
| 240 | /* EIP197_PE_ICE_PUE/FPP_CTRL */ | |
| 241 | #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0) | |
| 242 | #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14) | |
| 243 | #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15) | |
| 244 | ||
| 245 | /* EIP197_PE_ICE_RAM_CTRL */ | |
| 246 | #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0) | |
| 247 | #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1) | |
| 248 | ||
| 249 | /* EIP197_PE_EIP96_FUNCTION_EN */ | |
| 250 | #define EIP197_FUNCTION_RSVD (BIT(6) | BIT(15) | BIT(20) | BIT(23)) | |
| 251 | #define EIP197_PROTOCOL_HASH_ONLY BIT(0) | |
| 252 | #define EIP197_PROTOCOL_ENCRYPT_ONLY BIT(1) | |
| 253 | #define EIP197_PROTOCOL_HASH_ENCRYPT BIT(2) | |
| 254 | #define EIP197_PROTOCOL_HASH_DECRYPT BIT(3) | |
| 255 | #define EIP197_PROTOCOL_ENCRYPT_HASH BIT(4) | |
| 256 | #define EIP197_PROTOCOL_DECRYPT_HASH BIT(5) | |
| 257 | #define EIP197_ALG_ARC4 BIT(7) | |
| 258 | #define EIP197_ALG_AES_ECB BIT(8) | |
| 259 | #define EIP197_ALG_AES_CBC BIT(9) | |
| 260 | #define EIP197_ALG_AES_CTR_ICM BIT(10) | |
| 261 | #define EIP197_ALG_AES_OFB BIT(11) | |
| 262 | #define EIP197_ALG_AES_CFB BIT(12) | |
| 263 | #define EIP197_ALG_DES_ECB BIT(13) | |
| 264 | #define EIP197_ALG_DES_CBC BIT(14) | |
| 265 | #define EIP197_ALG_DES_OFB BIT(16) | |
| 266 | #define EIP197_ALG_DES_CFB BIT(17) | |
| 267 | #define EIP197_ALG_3DES_ECB BIT(18) | |
| 268 | #define EIP197_ALG_3DES_CBC BIT(19) | |
| 269 | #define EIP197_ALG_3DES_OFB BIT(21) | |
| 270 | #define EIP197_ALG_3DES_CFB BIT(22) | |
| 271 | #define EIP197_ALG_MD5 BIT(24) | |
| 272 | #define EIP197_ALG_HMAC_MD5 BIT(25) | |
| 273 | #define EIP197_ALG_SHA1 BIT(26) | |
| 274 | #define EIP197_ALG_HMAC_SHA1 BIT(27) | |
| 275 | #define EIP197_ALG_SHA2 BIT(28) | |
| 276 | #define EIP197_ALG_HMAC_SHA2 BIT(29) | |
| 277 | #define EIP197_ALG_AES_XCBC_MAC BIT(30) | |
| 278 | #define EIP197_ALG_GCM_HASH BIT(31) | |
| 279 | ||
| 280 | /* EIP197_PE_EIP96_CONTEXT_CTRL */ | |
| 281 | #define EIP197_CONTEXT_SIZE(n) (n) | |
| 282 | #define EIP197_ADDRESS_MODE BIT(8) | |
| 283 | #define EIP197_CONTROL_MODE BIT(9) | |
| 284 | ||
| 285 | /* Context Control */ | |
| 286 | struct safexcel_context_record { | |
| 287 | u32 control0; | |
| 288 | u32 control1; | |
| 289 | ||
| f6beaea3 | 290 | __le32 data[24]; |
| 1b44c5a6 AT |
291 | } __packed; |
| 292 | ||
| 293 | /* control0 */ | |
| 294 | #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0 | |
| 295 | #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1 | |
| 296 | #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2 | |
| 297 | #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3 | |
| 298 | #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4 | |
| 299 | #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5 | |
| 300 | #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6 | |
| 301 | #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7 | |
| 8a21f067 AT |
302 | #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe |
| 303 | #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf | |
| 1b44c5a6 AT |
304 | #define CONTEXT_CONTROL_RESTART_HASH BIT(4) |
| 305 | #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5) | |
| 306 | #define CONTEXT_CONTROL_SIZE(n) ((n) << 8) | |
| 307 | #define CONTEXT_CONTROL_KEY_EN BIT(16) | |
| 308 | #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17) | |
| 309 | #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17) | |
| 310 | #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17) | |
| 311 | #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21) | |
| 312 | #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21) | |
| 313 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23) | |
| 314 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23) | |
| 315 | #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23) | |
| 316 | #define CONTEXT_CONTROL_INV_FR (0x5 << 24) | |
| 317 | #define CONTEXT_CONTROL_INV_TR (0x6 << 24) | |
| 318 | ||
| 319 | /* control1 */ | |
| 320 | #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0) | |
| 321 | #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0) | |
| 322 | #define CONTEXT_CONTROL_IV0 BIT(5) | |
| 323 | #define CONTEXT_CONTROL_IV1 BIT(6) | |
| 324 | #define CONTEXT_CONTROL_IV2 BIT(7) | |
| 325 | #define CONTEXT_CONTROL_IV3 BIT(8) | |
| 326 | #define CONTEXT_CONTROL_DIGEST_CNT BIT(9) | |
| 327 | #define CONTEXT_CONTROL_COUNTER_MODE BIT(10) | |
| 328 | #define CONTEXT_CONTROL_HASH_STORE BIT(19) | |
| 329 | ||
| 330 | /* EIP197_CS_RAM_CTRL */ | |
| 331 | #define EIP197_TRC_ENABLE_0 BIT(4) | |
| 332 | #define EIP197_TRC_ENABLE_1 BIT(5) | |
| 333 | #define EIP197_TRC_ENABLE_2 BIT(6) | |
| 334 | #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4) | |
| 335 | ||
| 336 | /* EIP197_TRC_PARAMS */ | |
| 337 | #define EIP197_TRC_PARAMS_SW_RESET BIT(0) | |
| 338 | #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2) | |
| 339 | #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4) | |
| 340 | #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10) | |
| 341 | #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18) | |
| 342 | ||
| 343 | /* EIP197_TRC_FREECHAIN */ | |
| 344 | #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p) | |
| 345 | #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16) | |
| 346 | ||
| 347 | /* EIP197_TRC_PARAMS2 */ | |
| 348 | #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p) | |
| 349 | #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18) | |
| 350 | ||
| 351 | /* Cache helpers */ | |
| 352 | #define EIP197_CS_RC_MAX 52 | |
| 353 | #define EIP197_CS_RC_SIZE (4 * sizeof(u32)) | |
| 354 | #define EIP197_CS_RC_NEXT(x) (x) | |
| 355 | #define EIP197_CS_RC_PREV(x) ((x) << 10) | |
| 356 | #define EIP197_RC_NULL 0x3ff | |
| 357 | #define EIP197_CS_TRC_REC_WC 59 | |
| 358 | #define EIP197_CS_TRC_LG_REC_WC 73 | |
| 359 | ||
| 360 | /* Result data */ | |
| 361 | struct result_data_desc { | |
| 362 | u32 packet_length:17; | |
| 363 | u32 error_code:15; | |
| 364 | ||
| 365 | u8 bypass_length:4; | |
| 366 | u8 e15:1; | |
| 367 | u16 rsvd0; | |
| 368 | u8 hash_bytes:1; | |
| 369 | u8 hash_length:6; | |
| 370 | u8 generic_bytes:1; | |
| 371 | u8 checksum:1; | |
| 372 | u8 next_header:1; | |
| 373 | u8 length:1; | |
| 374 | ||
| 375 | u16 application_id; | |
| 376 | u16 rsvd1; | |
| 377 | ||
| 378 | u32 rsvd2; | |
| 379 | } __packed; | |
| 380 | ||
| 381 | ||
| 382 | /* Basic Result Descriptor format */ | |
| 383 | struct safexcel_result_desc { | |
| 384 | u32 particle_size:17; | |
| 385 | u8 rsvd0:3; | |
| 386 | u8 descriptor_overflow:1; | |
| 387 | u8 buffer_overflow:1; | |
| 388 | u8 last_seg:1; | |
| 389 | u8 first_seg:1; | |
| 390 | u16 result_size:8; | |
| 391 | ||
| 392 | u32 rsvd1; | |
| 393 | ||
| 394 | u32 data_lo; | |
| 395 | u32 data_hi; | |
| 396 | ||
| 397 | struct result_data_desc result_data; | |
| 398 | } __packed; | |
| 399 | ||
| 400 | struct safexcel_token { | |
| 401 | u32 packet_length:17; | |
| 402 | u8 stat:2; | |
| 403 | u16 instructions:9; | |
| 404 | u8 opcode:4; | |
| 405 | } __packed; | |
| 406 | ||
| f6beaea3 AT |
407 | #define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16) |
| 408 | ||
| 1b44c5a6 AT |
409 | #define EIP197_TOKEN_STAT_LAST_HASH BIT(0) |
| 410 | #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1) | |
| 411 | #define EIP197_TOKEN_OPCODE_DIRECTION 0x0 | |
| 412 | #define EIP197_TOKEN_OPCODE_INSERT 0x2 | |
| 413 | #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT | |
| f6beaea3 AT |
414 | #define EIP197_TOKEN_OPCODE_RETRIEVE 0x4 |
| 415 | #define EIP197_TOKEN_OPCODE_VERIFY 0xd | |
| 1b44c5a6 AT |
416 | #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0) |
| 417 | ||
| 418 | static inline void eip197_noop_token(struct safexcel_token *token) | |
| 419 | { | |
| 420 | token->opcode = EIP197_TOKEN_OPCODE_NOOP; | |
| 421 | token->packet_length = BIT(2); | |
| 422 | } | |
| 423 | ||
| 424 | /* Instructions */ | |
| 425 | #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c | |
| 426 | #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5) | |
| 427 | #define EIP197_TOKEN_INS_TYPE_HASH BIT(6) | |
| 428 | #define EIP197_TOKEN_INS_TYPE_CRYTO BIT(7) | |
| 429 | #define EIP197_TOKEN_INS_LAST BIT(8) | |
| 430 | ||
| 431 | /* Processing Engine Control Data */ | |
| 432 | struct safexcel_control_data_desc { | |
| 433 | u32 packet_length:17; | |
| 434 | u16 options:13; | |
| 435 | u8 type:2; | |
| 436 | ||
| 437 | u16 application_id; | |
| 438 | u16 rsvd; | |
| 439 | ||
| 440 | u8 refresh:2; | |
| 441 | u32 context_lo:30; | |
| 442 | u32 context_hi; | |
| 443 | ||
| 444 | u32 control0; | |
| 445 | u32 control1; | |
| 446 | ||
| 447 | u32 token[EIP197_MAX_TOKENS]; | |
| 448 | } __packed; | |
| 449 | ||
| 450 | #define EIP197_OPTION_MAGIC_VALUE BIT(0) | |
| 451 | #define EIP197_OPTION_64BIT_CTX BIT(1) | |
| 452 | #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8) | |
| 453 | #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9) | |
| 454 | ||
| 455 | #define EIP197_TYPE_EXTENDED 0x3 | |
| 456 | ||
| 457 | /* Basic Command Descriptor format */ | |
| 458 | struct safexcel_command_desc { | |
| 459 | u32 particle_size:17; | |
| 460 | u8 rsvd0:5; | |
| 461 | u8 last_seg:1; | |
| 462 | u8 first_seg:1; | |
| 463 | u16 additional_cdata_size:8; | |
| 464 | ||
| 465 | u32 rsvd1; | |
| 466 | ||
| 467 | u32 data_lo; | |
| 468 | u32 data_hi; | |
| 469 | ||
| 470 | struct safexcel_control_data_desc control_data; | |
| 471 | } __packed; | |
| 472 | ||
| 473 | /* | |
| 474 | * Internal structures & functions | |
| 475 | */ | |
| 476 | ||
| 477 | enum eip197_fw { | |
| 478 | FW_IFPP = 0, | |
| 479 | FW_IPUE, | |
| 480 | FW_NB | |
| 481 | }; | |
| 482 | ||
| 483 | struct safexcel_ring { | |
| 484 | void *base; | |
| 485 | void *base_end; | |
| 486 | dma_addr_t base_dma; | |
| 487 | ||
| 488 | /* write and read pointers */ | |
| 489 | void *write; | |
| 490 | void *read; | |
| 491 | ||
| 492 | /* number of elements used in the ring */ | |
| 493 | unsigned nr; | |
| 494 | unsigned offset; | |
| 495 | }; | |
| 496 | ||
| 497 | enum safexcel_alg_type { | |
| 498 | SAFEXCEL_ALG_TYPE_SKCIPHER, | |
| f6beaea3 | 499 | SAFEXCEL_ALG_TYPE_AEAD, |
| 1b44c5a6 AT |
500 | SAFEXCEL_ALG_TYPE_AHASH, |
| 501 | }; | |
| 502 | ||
| 503 | struct safexcel_request { | |
| 504 | struct list_head list; | |
| 505 | struct crypto_async_request *req; | |
| 506 | }; | |
| 507 | ||
| 508 | struct safexcel_config { | |
| 509 | u32 rings; | |
| 510 | ||
| 511 | u32 cd_size; | |
| 512 | u32 cd_offset; | |
| 513 | ||
| 514 | u32 rd_size; | |
| 515 | u32 rd_offset; | |
| 516 | }; | |
| 517 | ||
| 518 | struct safexcel_work_data { | |
| 519 | struct work_struct work; | |
| 520 | struct safexcel_crypto_priv *priv; | |
| 521 | int ring; | |
| 522 | }; | |
| 523 | ||
| 871df319 AT |
524 | enum safexcel_eip_version { |
| 525 | EIP97, | |
| 526 | EIP197, | |
| 527 | }; | |
| 528 | ||
| 529 | struct safexcel_register_offsets { | |
| 530 | u32 hia_aic; | |
| 531 | u32 hia_aic_g; | |
| 532 | u32 hia_aic_r; | |
| 533 | u32 hia_aic_xdr; | |
| 534 | u32 hia_dfe; | |
| 535 | u32 hia_dfe_thr; | |
| 536 | u32 hia_dse; | |
| 537 | u32 hia_dse_thr; | |
| 538 | u32 hia_gen_cfg; | |
| 539 | u32 pe; | |
| 540 | }; | |
| 541 | ||
| 1b44c5a6 AT |
542 | struct safexcel_crypto_priv { |
| 543 | void __iomem *base; | |
| 544 | struct device *dev; | |
| 545 | struct clk *clk; | |
| 1d17cbfb | 546 | struct clk *reg_clk; |
| 1b44c5a6 AT |
547 | struct safexcel_config config; |
| 548 | ||
| 871df319 AT |
549 | enum safexcel_eip_version version; |
| 550 | struct safexcel_register_offsets offsets; | |
| 551 | ||
| 1b44c5a6 AT |
552 | /* context DMA pool */ |
| 553 | struct dma_pool *context_pool; | |
| 554 | ||
| 555 | atomic_t ring_used; | |
| 556 | ||
| 557 | struct { | |
| 558 | spinlock_t lock; | |
| 559 | spinlock_t egress_lock; | |
| 560 | ||
| 561 | struct list_head list; | |
| 562 | struct workqueue_struct *workqueue; | |
| 563 | struct safexcel_work_data work_data; | |
| 564 | ||
| 565 | /* command/result rings */ | |
| 566 | struct safexcel_ring cdr; | |
| 567 | struct safexcel_ring rdr; | |
| 86671abb AT |
568 | |
| 569 | /* queue */ | |
| 570 | struct crypto_queue queue; | |
| 571 | spinlock_t queue_lock; | |
| dc7e28a3 | 572 | |
| f7268c53 AT |
573 | /* Number of requests in the engine. */ |
| 574 | int requests; | |
| dc7e28a3 AT |
575 | |
| 576 | /* The ring is currently handling at least one request */ | |
| 577 | bool busy; | |
| 8732b298 AT |
578 | |
| 579 | /* Store for current requests when bailing out of the dequeueing | |
| 580 | * function when no enough resources are available. | |
| 581 | */ | |
| 582 | struct crypto_async_request *req; | |
| 583 | struct crypto_async_request *backlog; | |
| 1b44c5a6 AT |
584 | } ring[EIP197_MAX_RINGS]; |
| 585 | }; | |
| 586 | ||
| 587 | struct safexcel_context { | |
| 588 | int (*send)(struct crypto_async_request *req, int ring, | |
| 589 | struct safexcel_request *request, int *commands, | |
| 590 | int *results); | |
| 591 | int (*handle_result)(struct safexcel_crypto_priv *priv, int ring, | |
| 592 | struct crypto_async_request *req, bool *complete, | |
| 593 | int *ret); | |
| 594 | struct safexcel_context_record *ctxr; | |
| 595 | dma_addr_t ctxr_dma; | |
| 596 | ||
| 597 | int ring; | |
| 598 | bool needs_inv; | |
| 599 | bool exit_inv; | |
| 1b44c5a6 AT |
600 | }; |
| 601 | ||
| f6beaea3 AT |
602 | struct safexcel_ahash_export_state { |
| 603 | u64 len; | |
| 604 | u64 processed; | |
| 605 | ||
| 606 | u32 digest; | |
| 607 | ||
| 608 | u32 state[SHA256_DIGEST_SIZE / sizeof(u32)]; | |
| 609 | u8 cache[SHA256_BLOCK_SIZE]; | |
| 610 | }; | |
| 611 | ||
| 1b44c5a6 AT |
612 | /* |
| 613 | * Template structure to describe the algorithms in order to register them. | |
| 614 | * It also has the purpose to contain our private structure and is actually | |
| 615 | * the only way I know in this framework to avoid having global pointers... | |
| 616 | */ | |
| 617 | struct safexcel_alg_template { | |
| 618 | struct safexcel_crypto_priv *priv; | |
| 619 | enum safexcel_alg_type type; | |
| 620 | union { | |
| 621 | struct skcipher_alg skcipher; | |
| f6beaea3 | 622 | struct aead_alg aead; |
| 1b44c5a6 AT |
623 | struct ahash_alg ahash; |
| 624 | } alg; | |
| 625 | }; | |
| 626 | ||
| 627 | struct safexcel_inv_result { | |
| 628 | struct completion completion; | |
| 629 | int error; | |
| 630 | }; | |
| 631 | ||
| 86671abb | 632 | void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring); |
| bdfd1909 AT |
633 | int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv, |
| 634 | struct safexcel_result_desc *rdesc); | |
| 1b44c5a6 | 635 | void safexcel_complete(struct safexcel_crypto_priv *priv, int ring); |
| 1b44c5a6 | 636 | int safexcel_invalidate_cache(struct crypto_async_request *async, |
| 1b44c5a6 AT |
637 | struct safexcel_crypto_priv *priv, |
| 638 | dma_addr_t ctxr_dma, int ring, | |
| 639 | struct safexcel_request *request); | |
| 640 | int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, | |
| 641 | struct safexcel_ring *cdr, | |
| 642 | struct safexcel_ring *rdr); | |
| 643 | int safexcel_select_ring(struct safexcel_crypto_priv *priv); | |
| 644 | void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv, | |
| 645 | struct safexcel_ring *ring); | |
| 646 | void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv, | |
| 647 | struct safexcel_ring *ring); | |
| 648 | struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv, | |
| 649 | int ring_id, | |
| 650 | bool first, bool last, | |
| 651 | dma_addr_t data, u32 len, | |
| 652 | u32 full_data_len, | |
| 653 | dma_addr_t context); | |
| 654 | struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv, | |
| 655 | int ring_id, | |
| 656 | bool first, bool last, | |
| 657 | dma_addr_t data, u32 len); | |
| 658 | void safexcel_inv_complete(struct crypto_async_request *req, int error); | |
| f6beaea3 AT |
659 | int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen, |
| 660 | void *istate, void *ostate); | |
| 1b44c5a6 AT |
661 | |
| 662 | /* available algorithms */ | |
| 663 | extern struct safexcel_alg_template safexcel_alg_ecb_aes; | |
| 664 | extern struct safexcel_alg_template safexcel_alg_cbc_aes; | |
| 665 | extern struct safexcel_alg_template safexcel_alg_sha1; | |
| 666 | extern struct safexcel_alg_template safexcel_alg_sha224; | |
| 667 | extern struct safexcel_alg_template safexcel_alg_sha256; | |
| 668 | extern struct safexcel_alg_template safexcel_alg_hmac_sha1; | |
| 3ad618d8 | 669 | extern struct safexcel_alg_template safexcel_alg_hmac_sha224; |
| 73f36ea7 | 670 | extern struct safexcel_alg_template safexcel_alg_hmac_sha256; |
| 678b2878 | 671 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes; |
| f6beaea3 | 672 | extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes; |
| 1b44c5a6 AT |
673 | |
| 674 | #endif |