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1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_VM_H__ | |
25 | #define __AMDGPU_VM_H__ | |
26 | ||
27 | #include <linux/rbtree.h> | |
28 | ||
29 | #include "gpu_scheduler.h" | |
30 | #include "amdgpu_sync.h" | |
31 | #include "amdgpu_ring.h" | |
32 | ||
33 | struct amdgpu_bo_va; | |
34 | struct amdgpu_job; | |
35 | struct amdgpu_bo_list_entry; | |
36 | ||
37 | /* | |
38 | * GPUVM handling | |
39 | */ | |
40 | ||
41 | /* maximum number of VMIDs */ | |
42 | #define AMDGPU_NUM_VM 16 | |
43 | ||
44 | /* Maximum number of PTEs the hardware can write with one command */ | |
45 | #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF | |
46 | ||
47 | /* number of entries in page table */ | |
48 | #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) | |
49 | ||
50 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ | |
51 | #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 | |
52 | ||
53 | /* LOG2 number of continuous pages for the fragment field */ | |
54 | #define AMDGPU_LOG2_PAGES_PER_FRAG 4 | |
55 | ||
35ba15f0 CK |
56 | #define AMDGPU_PTE_VALID (1ULL << 0) |
57 | #define AMDGPU_PTE_SYSTEM (1ULL << 1) | |
58 | #define AMDGPU_PTE_SNOOPED (1ULL << 2) | |
073440d2 CK |
59 | |
60 | /* VI only */ | |
35ba15f0 | 61 | #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) |
073440d2 | 62 | |
35ba15f0 CK |
63 | #define AMDGPU_PTE_READABLE (1ULL << 5) |
64 | #define AMDGPU_PTE_WRITEABLE (1ULL << 6) | |
073440d2 | 65 | |
982a1348 | 66 | #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) |
073440d2 | 67 | |
35ba15f0 | 68 | #define AMDGPU_PTE_PRT (1ULL << 63) |
284710fa | 69 | |
073440d2 CK |
70 | /* How to programm VM fault handling */ |
71 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
72 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
73 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
74 | ||
75 | struct amdgpu_vm_pt { | |
76 | struct amdgpu_bo *bo; | |
77 | uint64_t addr; | |
78 | }; | |
79 | ||
80 | struct amdgpu_vm { | |
81 | /* tree of virtual addresses mapped */ | |
82 | struct rb_root va; | |
83 | ||
84 | /* protecting invalidated */ | |
85 | spinlock_t status_lock; | |
86 | ||
87 | /* BOs moved, but not yet updated in the PT */ | |
88 | struct list_head invalidated; | |
89 | ||
90 | /* BOs cleared in the PT because of a move */ | |
91 | struct list_head cleared; | |
92 | ||
93 | /* BO mappings freed, but not yet updated in the PT */ | |
94 | struct list_head freed; | |
95 | ||
96 | /* contains the page directory */ | |
97 | struct amdgpu_bo *page_directory; | |
98 | unsigned max_pde_used; | |
220196b3 | 99 | struct dma_fence *page_directory_fence; |
073440d2 CK |
100 | uint64_t last_eviction_counter; |
101 | ||
102 | /* array of page tables, one for each page directory entry */ | |
103 | struct amdgpu_vm_pt *page_tables; | |
104 | ||
105 | /* for id and flush management per ring */ | |
106 | struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; | |
107 | ||
108 | /* protecting freed */ | |
109 | spinlock_t freed_lock; | |
110 | ||
111 | /* Scheduler entity for page table updates */ | |
112 | struct amd_sched_entity entity; | |
113 | ||
114 | /* client id */ | |
115 | u64 client_id; | |
bd7de27d ML |
116 | /* each VM will map on CSA */ |
117 | struct amdgpu_bo_va *csa_bo_va; | |
073440d2 CK |
118 | }; |
119 | ||
120 | struct amdgpu_vm_id { | |
121 | struct list_head list; | |
220196b3 | 122 | struct dma_fence *first; |
073440d2 | 123 | struct amdgpu_sync active; |
220196b3 | 124 | struct dma_fence *last_flush; |
073440d2 CK |
125 | atomic64_t owner; |
126 | ||
127 | uint64_t pd_gpu_addr; | |
128 | /* last flushed PD/PT update */ | |
220196b3 | 129 | struct dma_fence *flushed_updates; |
073440d2 CK |
130 | |
131 | uint32_t current_gpu_reset_count; | |
132 | ||
133 | uint32_t gds_base; | |
134 | uint32_t gds_size; | |
135 | uint32_t gws_base; | |
136 | uint32_t gws_size; | |
137 | uint32_t oa_base; | |
138 | uint32_t oa_size; | |
139 | }; | |
140 | ||
141 | struct amdgpu_vm_manager { | |
142 | /* Handling of VMIDs */ | |
143 | struct mutex lock; | |
144 | unsigned num_ids; | |
145 | struct list_head ids_lru; | |
146 | struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; | |
147 | ||
148 | /* Handling of VM fences */ | |
149 | u64 fence_context; | |
150 | unsigned seqno[AMDGPU_MAX_RINGS]; | |
151 | ||
152 | uint32_t max_pfn; | |
153 | /* vram base address for page table entry */ | |
154 | u64 vram_base_offset; | |
155 | /* is vm enabled? */ | |
156 | bool enabled; | |
157 | /* vm pte handling */ | |
158 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; | |
159 | struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; | |
160 | unsigned vm_pte_num_rings; | |
161 | atomic_t vm_pte_next_ring; | |
162 | /* client id counter */ | |
163 | atomic64_t client_counter; | |
284710fa CK |
164 | |
165 | /* partial resident texture handling */ | |
166 | spinlock_t prt_lock; | |
451bc8eb | 167 | atomic_t num_prt_users; |
073440d2 CK |
168 | }; |
169 | ||
170 | void amdgpu_vm_manager_init(struct amdgpu_device *adev); | |
171 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); | |
172 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); | |
173 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); | |
174 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, | |
175 | struct list_head *validated, | |
176 | struct amdgpu_bo_list_entry *entry); | |
177 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
178 | int (*callback)(void *p, struct amdgpu_bo *bo), | |
179 | void *param); | |
180 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
181 | struct amdgpu_vm *vm); | |
663e4577 CK |
182 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
183 | struct amdgpu_vm *vm, | |
184 | uint64_t saddr, uint64_t size); | |
073440d2 | 185 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
220196b3 | 186 | struct amdgpu_sync *sync, struct dma_fence *fence, |
073440d2 CK |
187 | struct amdgpu_job *job); |
188 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job); | |
189 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); | |
190 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
191 | struct amdgpu_vm *vm); | |
192 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
193 | struct amdgpu_vm *vm, |
194 | struct dma_fence **fence); | |
073440d2 CK |
195 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
196 | struct amdgpu_sync *sync); | |
197 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
198 | struct amdgpu_bo_va *bo_va, | |
199 | bool clear); | |
200 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
201 | struct amdgpu_bo *bo); | |
202 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
203 | struct amdgpu_bo *bo); | |
204 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
205 | struct amdgpu_vm *vm, | |
206 | struct amdgpu_bo *bo); | |
207 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
208 | struct amdgpu_bo_va *bo_va, | |
209 | uint64_t addr, uint64_t offset, | |
268c3001 | 210 | uint64_t size, uint64_t flags); |
80f95c57 CK |
211 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, |
212 | struct amdgpu_bo_va *bo_va, | |
213 | uint64_t addr, uint64_t offset, | |
214 | uint64_t size, uint64_t flags); | |
073440d2 CK |
215 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, |
216 | struct amdgpu_bo_va *bo_va, | |
217 | uint64_t addr); | |
dc54d3d1 CK |
218 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, |
219 | struct amdgpu_vm *vm, | |
220 | uint64_t saddr, uint64_t size); | |
073440d2 CK |
221 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, |
222 | struct amdgpu_bo_va *bo_va); | |
223 | ||
224 | #endif |