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drm/amd/amdgpu: Make afmt_init() cleanup if alloc fails (DCEv11)
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_11_0_d.h"
36#include "dce/dce_11_0_sh_mask.h"
37#include "dce/dce_11_0_enum.h"
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40#include "gmc/gmc_8_1_d.h"
41#include "gmc/gmc_8_1_sh_mask.h"
42
43static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
45
46static const u32 crtc_offsets[] =
47{
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
54 CRTC6_REGISTER_OFFSET
55};
56
57static const u32 hpd_offsets[] =
58{
59 HPD0_REGISTER_OFFSET,
60 HPD1_REGISTER_OFFSET,
61 HPD2_REGISTER_OFFSET,
62 HPD3_REGISTER_OFFSET,
63 HPD4_REGISTER_OFFSET,
64 HPD5_REGISTER_OFFSET
65};
66
67static const uint32_t dig_offsets[] = {
68 DIG0_REGISTER_OFFSET,
69 DIG1_REGISTER_OFFSET,
70 DIG2_REGISTER_OFFSET,
71 DIG3_REGISTER_OFFSET,
72 DIG4_REGISTER_OFFSET,
73 DIG5_REGISTER_OFFSET,
74 DIG6_REGISTER_OFFSET,
75 DIG7_REGISTER_OFFSET,
76 DIG8_REGISTER_OFFSET
77};
78
79static const struct {
80 uint32_t reg;
81 uint32_t vblank;
82 uint32_t vline;
83 uint32_t hpd;
84
85} interrupt_status_offsets[] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
90}, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
105}, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
110}, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115} };
116
117static const u32 cz_golden_settings_a11[] =
118{
119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120 mmFBC_MISC, 0x1f311fff, 0x14300000,
121};
122
5732a94f
AD		 123static const u32 cz_mgcg_cgcg_init[] =
124{
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
fa2f9bef
SL		 129static const u32 stoney_golden_settings_a11[] =
130{
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14302000,
133};
134
135
aaa36a97
AD		 136static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
137{
138 switch (adev->asic_type) {
139 case CHIP_CARRIZO:
5732a94f
AD		 140 amdgpu_program_register_sequence(adev,
141 cz_mgcg_cgcg_init,
142 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
aaa36a97
AD		 143 amdgpu_program_register_sequence(adev,
144 cz_golden_settings_a11,
145 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
146 break;
fa2f9bef
SL		 147 case CHIP_STONEY:
148 amdgpu_program_register_sequence(adev,
149 stoney_golden_settings_a11,
150 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
151 break;
aaa36a97
AD		 152 default:
153 break;
154 }
155}
156
157static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
158 u32 block_offset, u32 reg)
159{
160 unsigned long flags;
161 u32 r;
162
163 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
164 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
165 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
166 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
167
168 return r;
169}
170
171static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
172 u32 block_offset, u32 reg, u32 v)
173{
174 unsigned long flags;
175
176 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
177 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
178 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
179 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
180}
181
182static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
183{
184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
185 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
186 return true;
187 else
188 return false;
189}
190
191static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
192{
193 u32 pos1, pos2;
194
195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
197
198 if (pos1 != pos2)
199 return true;
200 else
201 return false;
202}
203
204/**
205 * dce_v11_0_vblank_wait - vblank wait asic callback.
206 *
207 * @adev: amdgpu_device pointer
208 * @crtc: crtc to wait for vblank on
209 *
210 * Wait for vblank on the requested crtc (evergreen+).
211 */
212static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
213{
9e4e1ae8 214 unsigned i = 100;
aaa36a97 215
15c3277f 216 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
aaa36a97
AD		 217 return;
218
219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
220 return;
221
222 /* depending on when we hit vblank, we may be close to active; if so,
223 * wait for another frame.
224 */
225 while (dce_v11_0_is_in_vblank(adev, crtc)) {
9e4e1ae8
TSD		 226 if (i++ == 100) {
227 i = 0;
aaa36a97
AD		 228 if (!dce_v11_0_is_counter_moving(adev, crtc))
229 break;
230 }
231 }
232
233 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
9e4e1ae8
TSD		 234 if (i++ == 100) {
235 i = 0;
aaa36a97
AD		 236 if (!dce_v11_0_is_counter_moving(adev, crtc))
237 break;
238 }
239 }
240}
241
242static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
243{
15c3277f 244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
aaa36a97
AD		 245 return 0;
246 else
247 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
248}
249
f6c7aba4
MD		 250static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
251{
252 unsigned i;
253
254 /* Enable pflip interrupts */
255 for (i = 0; i < adev->mode_info.num_crtc; i++)
256 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
257}
258
259static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
260{
261 unsigned i;
262
263 /* Disable pflip interrupts */
264 for (i = 0; i < adev->mode_info.num_crtc; i++)
265 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
266}
267
aaa36a97
AD		 268/**
269 * dce_v11_0_page_flip - pageflip callback.
270 *
271 * @adev: amdgpu_device pointer
272 * @crtc_id: crtc to cleanup pageflip on
273 * @crtc_base: new address of the crtc (GPU MC address)
274 *
ce055fe3
AD		 275 * Triggers the actual pageflip by updating the primary
276 * surface base address.
aaa36a97
AD		 277 */
278static void dce_v11_0_page_flip(struct amdgpu_device *adev,
279 int crtc_id, u64 crtc_base)
280{
281 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
aaa36a97
AD		 282
283 /* update the scanout addresses */
aaa36a97
AD		 284 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
285 upper_32_bits(crtc_base));
ce055fe3 286 /* writing to the low address triggers the update */
aaa36a97
AD		 287 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
288 lower_32_bits(crtc_base));
ce055fe3
AD		 289 /* post the write */
290 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
aaa36a97
AD		 291}
292
293static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
294 u32 *vbl, u32 *position)
295{
296 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
297 return -EINVAL;
298
299 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
300 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
301
302 return 0;
303}
304
305/**
306 * dce_v11_0_hpd_sense - hpd sense callback.
307 *
308 * @adev: amdgpu_device pointer
309 * @hpd: hpd (hotplug detect) pin
310 *
311 * Checks if a digital monitor is connected (evergreen+).
312 * Returns true if connected, false if not connected.
313 */
314static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
315 enum amdgpu_hpd_id hpd)
316{
317 int idx;
318 bool connected = false;
319
320 switch (hpd) {
321 case AMDGPU_HPD_1:
322 idx = 0;
323 break;
324 case AMDGPU_HPD_2:
325 idx = 1;
326 break;
327 case AMDGPU_HPD_3:
328 idx = 2;
329 break;
330 case AMDGPU_HPD_4:
331 idx = 3;
332 break;
333 case AMDGPU_HPD_5:
334 idx = 4;
335 break;
336 case AMDGPU_HPD_6:
337 idx = 5;
338 break;
339 default:
340 return connected;
341 }
342
343 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
344 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
345 connected = true;
346
347 return connected;
348}
349
350/**
351 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
352 *
353 * @adev: amdgpu_device pointer
354 * @hpd: hpd (hotplug detect) pin
355 *
356 * Set the polarity of the hpd pin (evergreen+).
357 */
358static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
359 enum amdgpu_hpd_id hpd)
360{
361 u32 tmp;
362 bool connected = dce_v11_0_hpd_sense(adev, hpd);
363 int idx;
364
365 switch (hpd) {
366 case AMDGPU_HPD_1:
367 idx = 0;
368 break;
369 case AMDGPU_HPD_2:
370 idx = 1;
371 break;
372 case AMDGPU_HPD_3:
373 idx = 2;
374 break;
375 case AMDGPU_HPD_4:
376 idx = 3;
377 break;
378 case AMDGPU_HPD_5:
379 idx = 4;
380 break;
381 case AMDGPU_HPD_6:
382 idx = 5;
383 break;
384 default:
385 return;
386 }
387
388 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
389 if (connected)
390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
391 else
392 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
393 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
394}
395
396/**
397 * dce_v11_0_hpd_init - hpd setup callback.
398 *
399 * @adev: amdgpu_device pointer
400 *
401 * Setup the hpd pins used by the card (evergreen+).
402 * Enable the pin, set the polarity, and enable the hpd interrupts.
403 */
404static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
405{
406 struct drm_device *dev = adev->ddev;
407 struct drm_connector *connector;
408 u32 tmp;
409 int idx;
410
411 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
412 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
413
414 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
415 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
416 /* don't try to enable hpd on eDP or LVDS avoid breaking the
417 * aux dp channel on imac and help (but not completely fix)
418 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
419 * also avoid interrupt storms during dpms.
420 */
421 continue;
422 }
423
424 switch (amdgpu_connector->hpd.hpd) {
425 case AMDGPU_HPD_1:
426 idx = 0;
427 break;
428 case AMDGPU_HPD_2:
429 idx = 1;
430 break;
431 case AMDGPU_HPD_3:
432 idx = 2;
433 break;
434 case AMDGPU_HPD_4:
435 idx = 3;
436 break;
437 case AMDGPU_HPD_5:
438 idx = 4;
439 break;
440 case AMDGPU_HPD_6:
441 idx = 5;
442 break;
443 default:
444 continue;
445 }
446
447 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
448 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
449 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
450
451 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
452 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
453 DC_HPD_CONNECT_INT_DELAY,
454 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
455 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
456 DC_HPD_DISCONNECT_INT_DELAY,
457 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
458 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
459
460 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
461 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
462 }
463}
464
465/**
466 * dce_v11_0_hpd_fini - hpd tear down callback.
467 *
468 * @adev: amdgpu_device pointer
469 *
470 * Tear down the hpd pins used by the card (evergreen+).
471 * Disable the hpd interrupts.
472 */
473static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
474{
475 struct drm_device *dev = adev->ddev;
476 struct drm_connector *connector;
477 u32 tmp;
478 int idx;
479
480 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
481 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
482
483 switch (amdgpu_connector->hpd.hpd) {
484 case AMDGPU_HPD_1:
485 idx = 0;
486 break;
487 case AMDGPU_HPD_2:
488 idx = 1;
489 break;
490 case AMDGPU_HPD_3:
491 idx = 2;
492 break;
493 case AMDGPU_HPD_4:
494 idx = 3;
495 break;
496 case AMDGPU_HPD_5:
497 idx = 4;
498 break;
499 case AMDGPU_HPD_6:
500 idx = 5;
501 break;
502 default:
503 continue;
504 }
505
506 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
507 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
508 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
509
510 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
511 }
512}
513
514static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
515{
516 return mmDC_GPIO_HPD_A;
517}
518
519static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
520{
521 u32 crtc_hung = 0;
522 u32 crtc_status[6];
523 u32 i, j, tmp;
524
525 for (i = 0; i < adev->mode_info.num_crtc; i++) {
526 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
527 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
528 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
529 crtc_hung |= (1 << i);
530 }
531 }
532
533 for (j = 0; j < 10; j++) {
534 for (i = 0; i < adev->mode_info.num_crtc; i++) {
535 if (crtc_hung & (1 << i)) {
536 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
537 if (tmp != crtc_status[i])
538 crtc_hung &= ~(1 << i);
539 }
540 }
541 if (crtc_hung == 0)
542 return false;
543 udelay(100);
544 }
545
546 return true;
547}
548
549static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
550 struct amdgpu_mode_mc_save *save)
551{
552 u32 crtc_enabled, tmp;
553 int i;
554
555 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
556 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
557
558 /* disable VGA render */
559 tmp = RREG32(mmVGA_RENDER_CONTROL);
560 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
561 WREG32(mmVGA_RENDER_CONTROL, tmp);
562
563 /* blank the display controllers */
564 for (i = 0; i < adev->mode_info.num_crtc; i++) {
565 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
566 CRTC_CONTROL, CRTC_MASTER_EN);
567 if (crtc_enabled) {
568#if 0
569 u32 frame_count;
570 int j;
571
572 save->crtc_enabled[i] = true;
573 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
574 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
575 amdgpu_display_vblank_wait(adev, i);
576 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
577 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
578 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
579 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
580 }
581 /* wait for the next frame */
582 frame_count = amdgpu_display_vblank_get_counter(adev, i);
583 for (j = 0; j < adev->usec_timeout; j++) {
584 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
585 break;
586 udelay(1);
587 }
588 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
589 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
590 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
591 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
592 }
593 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
594 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
595 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
596 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
597 }
598#else
599 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
600 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
601 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
602 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
603 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
604 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
605 save->crtc_enabled[i] = false;
606 /* ***** */
607#endif
608 } else {
609 save->crtc_enabled[i] = false;
610 }
611 }
612}
613
614static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
615 struct amdgpu_mode_mc_save *save)
616{
617 u32 tmp, frame_count;
618 int i, j;
619
620 /* update crtc base addresses */
621 for (i = 0; i < adev->mode_info.num_crtc; i++) {
622 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
623 upper_32_bits(adev->mc.vram_start));
624 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
625 upper_32_bits(adev->mc.vram_start));
626 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
627 (u32)adev->mc.vram_start);
628 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
629 (u32)adev->mc.vram_start);
630
631 if (save->crtc_enabled[i]) {
632 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
633 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
634 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
635 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
636 }
637 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
638 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
639 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
640 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
641 }
642 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
643 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
644 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
645 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
646 }
647 for (j = 0; j < adev->usec_timeout; j++) {
648 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
649 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
650 break;
651 udelay(1);
652 }
653 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
654 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
655 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
656 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
657 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
658 /* wait for the next frame */
659 frame_count = amdgpu_display_vblank_get_counter(adev, i);
660 for (j = 0; j < adev->usec_timeout; j++) {
661 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
662 break;
663 udelay(1);
664 }
665 }
666 }
667
668 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
669 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
670
671 /* Unlock vga access */
672 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
673 mdelay(1);
674 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
675}
676
677static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
678 bool render)
679{
680 u32 tmp;
681
682 /* Lockout access through VGA aperture*/
683 tmp = RREG32(mmVGA_HDP_CONTROL);
684 if (render)
685 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
686 else
687 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
688 WREG32(mmVGA_HDP_CONTROL, tmp);
689
690 /* disable VGA render */
691 tmp = RREG32(mmVGA_RENDER_CONTROL);
692 if (render)
693 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
694 else
695 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
696 WREG32(mmVGA_RENDER_CONTROL, tmp);
697}
698
699static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
700{
701 struct drm_device *dev = encoder->dev;
702 struct amdgpu_device *adev = dev->dev_private;
703 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
704 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
705 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
706 int bpc = 0;
707 u32 tmp = 0;
708 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
709
710 if (connector) {
711 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
712 bpc = amdgpu_connector_get_monitor_bpc(connector);
713 dither = amdgpu_connector->dither;
714 }
715
716 /* LVDS/eDP FMT is set up by atom */
717 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
718 return;
719
720 /* not needed for analog */
721 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
722 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
723 return;
724
725 if (bpc == 0)
726 return;
727
728 switch (bpc) {
729 case 6:
730 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
731 /* XXX sort out optimal dither settings */
732 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
733 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
734 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
736 } else {
737 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
739 }
740 break;
741 case 8:
742 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
743 /* XXX sort out optimal dither settings */
744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
746 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
749 } else {
750 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
751 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
752 }
753 break;
754 case 10:
755 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
756 /* XXX sort out optimal dither settings */
757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
762 } else {
763 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
764 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
765 }
766 break;
767 default:
768 /* not needed */
769 break;
770 }
771
772 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
773}
774
775
776/* display watermark setup */
777/**
778 * dce_v11_0_line_buffer_adjust - Set up the line buffer
779 *
780 * @adev: amdgpu_device pointer
781 * @amdgpu_crtc: the selected display controller
782 * @mode: the current display mode on the selected display
783 * controller
784 *
785 * Setup up the line buffer allocation for
786 * the selected display controller (CIK).
787 * Returns the line buffer size in pixels.
788 */
789static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
790 struct amdgpu_crtc *amdgpu_crtc,
791 struct drm_display_mode *mode)
792{
793 u32 tmp, buffer_alloc, i, mem_cfg;
794 u32 pipe_offset = amdgpu_crtc->crtc_id;
795 /*
796 * Line Buffer Setup
797 * There are 6 line buffers, one for each display controllers.
798 * There are 3 partitions per LB. Select the number of partitions
799 * to enable based on the display width. For display widths larger
800 * than 4096, you need use to use 2 display controllers and combine
801 * them using the stereo blender.
802 */
803 if (amdgpu_crtc->base.enabled && mode) {
804 if (mode->crtc_hdisplay < 1920) {
805 mem_cfg = 1;
806 buffer_alloc = 2;
807 } else if (mode->crtc_hdisplay < 2560) {
808 mem_cfg = 2;
809 buffer_alloc = 2;
810 } else if (mode->crtc_hdisplay < 4096) {
811 mem_cfg = 0;
2f7d10b3 812 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 813 } else {
814 DRM_DEBUG_KMS("Mode too big for LB!\n");
815 mem_cfg = 0;
2f7d10b3 816 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 817 }
818 } else {
819 mem_cfg = 1;
820 buffer_alloc = 0;
821 }
822
823 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
824 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
825 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
826
827 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
828 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
829 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
830
831 for (i = 0; i < adev->usec_timeout; i++) {
832 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
833 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
834 break;
835 udelay(1);
836 }
837
838 if (amdgpu_crtc->base.enabled && mode) {
839 switch (mem_cfg) {
840 case 0:
841 default:
842 return 4096 * 2;
843 case 1:
844 return 1920 * 2;
845 case 2:
846 return 2560 * 2;
847 }
848 }
849
850 /* controller not enabled, so no lb used */
851 return 0;
852}
853
854/**
855 * cik_get_number_of_dram_channels - get the number of dram channels
856 *
857 * @adev: amdgpu_device pointer
858 *
859 * Look up the number of video ram channels (CIK).
860 * Used for display watermark bandwidth calculations
861 * Returns the number of dram channels
862 */
863static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
864{
865 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
866
867 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
868 case 0:
869 default:
870 return 1;
871 case 1:
872 return 2;
873 case 2:
874 return 4;
875 case 3:
876 return 8;
877 case 4:
878 return 3;
879 case 5:
880 return 6;
881 case 6:
882 return 10;
883 case 7:
884 return 12;
885 case 8:
886 return 16;
887 }
888}
889
890struct dce10_wm_params {
891 u32 dram_channels; /* number of dram channels */
892 u32 yclk; /* bandwidth per dram data pin in kHz */
893 u32 sclk; /* engine clock in kHz */
894 u32 disp_clk; /* display clock in kHz */
895 u32 src_width; /* viewport width */
896 u32 active_time; /* active display time in ns */
897 u32 blank_time; /* blank time in ns */
898 bool interlaced; /* mode is interlaced */
899 fixed20_12 vsc; /* vertical scale ratio */
900 u32 num_heads; /* number of active crtcs */
901 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
902 u32 lb_size; /* line buffer allocated to pipe */
903 u32 vtaps; /* vertical scaler taps */
904};
905
906/**
907 * dce_v11_0_dram_bandwidth - get the dram bandwidth
908 *
909 * @wm: watermark calculation data
910 *
911 * Calculate the raw dram bandwidth (CIK).
912 * Used for display watermark bandwidth calculations
913 * Returns the dram bandwidth in MBytes/s
914 */
915static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
916{
917 /* Calculate raw DRAM Bandwidth */
918 fixed20_12 dram_efficiency; /* 0.7 */
919 fixed20_12 yclk, dram_channels, bandwidth;
920 fixed20_12 a;
921
922 a.full = dfixed_const(1000);
923 yclk.full = dfixed_const(wm->yclk);
924 yclk.full = dfixed_div(yclk, a);
925 dram_channels.full = dfixed_const(wm->dram_channels * 4);
926 a.full = dfixed_const(10);
927 dram_efficiency.full = dfixed_const(7);
928 dram_efficiency.full = dfixed_div(dram_efficiency, a);
929 bandwidth.full = dfixed_mul(dram_channels, yclk);
930 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
931
932 return dfixed_trunc(bandwidth);
933}
934
935/**
936 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
937 *
938 * @wm: watermark calculation data
939 *
940 * Calculate the dram bandwidth used for display (CIK).
941 * Used for display watermark bandwidth calculations
942 * Returns the dram bandwidth for display in MBytes/s
943 */
944static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
945{
946 /* Calculate DRAM Bandwidth and the part allocated to display. */
947 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
948 fixed20_12 yclk, dram_channels, bandwidth;
949 fixed20_12 a;
950
951 a.full = dfixed_const(1000);
952 yclk.full = dfixed_const(wm->yclk);
953 yclk.full = dfixed_div(yclk, a);
954 dram_channels.full = dfixed_const(wm->dram_channels * 4);
955 a.full = dfixed_const(10);
956 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
957 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
958 bandwidth.full = dfixed_mul(dram_channels, yclk);
959 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
960
961 return dfixed_trunc(bandwidth);
962}
963
964/**
965 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
966 *
967 * @wm: watermark calculation data
968 *
969 * Calculate the data return bandwidth used for display (CIK).
970 * Used for display watermark bandwidth calculations
971 * Returns the data return bandwidth in MBytes/s
972 */
973static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
974{
975 /* Calculate the display Data return Bandwidth */
976 fixed20_12 return_efficiency; /* 0.8 */
977 fixed20_12 sclk, bandwidth;
978 fixed20_12 a;
979
980 a.full = dfixed_const(1000);
981 sclk.full = dfixed_const(wm->sclk);
982 sclk.full = dfixed_div(sclk, a);
983 a.full = dfixed_const(10);
984 return_efficiency.full = dfixed_const(8);
985 return_efficiency.full = dfixed_div(return_efficiency, a);
986 a.full = dfixed_const(32);
987 bandwidth.full = dfixed_mul(a, sclk);
988 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
989
990 return dfixed_trunc(bandwidth);
991}
992
993/**
994 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
995 *
996 * @wm: watermark calculation data
997 *
998 * Calculate the dmif bandwidth used for display (CIK).
999 * Used for display watermark bandwidth calculations
1000 * Returns the dmif bandwidth in MBytes/s
1001 */
1002static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1003{
1004 /* Calculate the DMIF Request Bandwidth */
1005 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1006 fixed20_12 disp_clk, bandwidth;
1007 fixed20_12 a, b;
1008
1009 a.full = dfixed_const(1000);
1010 disp_clk.full = dfixed_const(wm->disp_clk);
1011 disp_clk.full = dfixed_div(disp_clk, a);
1012 a.full = dfixed_const(32);
1013 b.full = dfixed_mul(a, disp_clk);
1014
1015 a.full = dfixed_const(10);
1016 disp_clk_request_efficiency.full = dfixed_const(8);
1017 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1018
1019 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1020
1021 return dfixed_trunc(bandwidth);
1022}
1023
1024/**
1025 * dce_v11_0_available_bandwidth - get the min available bandwidth
1026 *
1027 * @wm: watermark calculation data
1028 *
1029 * Calculate the min available bandwidth used for display (CIK).
1030 * Used for display watermark bandwidth calculations
1031 * Returns the min available bandwidth in MBytes/s
1032 */
1033static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1034{
1035 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1036 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1037 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1038 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1039
1040 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1041}
1042
1043/**
1044 * dce_v11_0_average_bandwidth - get the average available bandwidth
1045 *
1046 * @wm: watermark calculation data
1047 *
1048 * Calculate the average available bandwidth used for display (CIK).
1049 * Used for display watermark bandwidth calculations
1050 * Returns the average available bandwidth in MBytes/s
1051 */
1052static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1053{
1054 /* Calculate the display mode Average Bandwidth
1055 * DisplayMode should contain the source and destination dimensions,
1056 * timing, etc.
1057 */
1058 fixed20_12 bpp;
1059 fixed20_12 line_time;
1060 fixed20_12 src_width;
1061 fixed20_12 bandwidth;
1062 fixed20_12 a;
1063
1064 a.full = dfixed_const(1000);
1065 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1066 line_time.full = dfixed_div(line_time, a);
1067 bpp.full = dfixed_const(wm->bytes_per_pixel);
1068 src_width.full = dfixed_const(wm->src_width);
1069 bandwidth.full = dfixed_mul(src_width, bpp);
1070 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1071 bandwidth.full = dfixed_div(bandwidth, line_time);
1072
1073 return dfixed_trunc(bandwidth);
1074}
1075
1076/**
1077 * dce_v11_0_latency_watermark - get the latency watermark
1078 *
1079 * @wm: watermark calculation data
1080 *
1081 * Calculate the latency watermark (CIK).
1082 * Used for display watermark bandwidth calculations
1083 * Returns the latency watermark in ns
1084 */
1085static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1086{
1087 /* First calculate the latency in ns */
1088 u32 mc_latency = 2000; /* 2000 ns. */
1089 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1090 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1091 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1092 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1093 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1094 (wm->num_heads * cursor_line_pair_return_time);
1095 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1096 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1097 u32 tmp, dmif_size = 12288;
1098 fixed20_12 a, b, c;
1099
1100 if (wm->num_heads == 0)
1101 return 0;
1102
1103 a.full = dfixed_const(2);
1104 b.full = dfixed_const(1);
1105 if ((wm->vsc.full > a.full) ||
1106 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1107 (wm->vtaps >= 5) ||
1108 ((wm->vsc.full >= a.full) && wm->interlaced))
1109 max_src_lines_per_dst_line = 4;
1110 else
1111 max_src_lines_per_dst_line = 2;
1112
1113 a.full = dfixed_const(available_bandwidth);
1114 b.full = dfixed_const(wm->num_heads);
1115 a.full = dfixed_div(a, b);
1116
1117 b.full = dfixed_const(mc_latency + 512);
1118 c.full = dfixed_const(wm->disp_clk);
1119 b.full = dfixed_div(b, c);
1120
1121 c.full = dfixed_const(dmif_size);
1122 b.full = dfixed_div(c, b);
1123
1124 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1125
1126 b.full = dfixed_const(1000);
1127 c.full = dfixed_const(wm->disp_clk);
1128 b.full = dfixed_div(c, b);
1129 c.full = dfixed_const(wm->bytes_per_pixel);
1130 b.full = dfixed_mul(b, c);
1131
1132 lb_fill_bw = min(tmp, dfixed_trunc(b));
1133
1134 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1135 b.full = dfixed_const(1000);
1136 c.full = dfixed_const(lb_fill_bw);
1137 b.full = dfixed_div(c, b);
1138 a.full = dfixed_div(a, b);
1139 line_fill_time = dfixed_trunc(a);
1140
1141 if (line_fill_time < wm->active_time)
1142 return latency;
1143 else
1144 return latency + (line_fill_time - wm->active_time);
1145
1146}
1147
1148/**
1149 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1150 * average and available dram bandwidth
1151 *
1152 * @wm: watermark calculation data
1153 *
1154 * Check if the display average bandwidth fits in the display
1155 * dram bandwidth (CIK).
1156 * Used for display watermark bandwidth calculations
1157 * Returns true if the display fits, false if not.
1158 */
1159static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1160{
1161 if (dce_v11_0_average_bandwidth(wm) <=
1162 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1163 return true;
1164 else
1165 return false;
1166}
1167
1168/**
1169 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1170 * average and available bandwidth
1171 *
1172 * @wm: watermark calculation data
1173 *
1174 * Check if the display average bandwidth fits in the display
1175 * available bandwidth (CIK).
1176 * Used for display watermark bandwidth calculations
1177 * Returns true if the display fits, false if not.
1178 */
1179static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1180{
1181 if (dce_v11_0_average_bandwidth(wm) <=
1182 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1183 return true;
1184 else
1185 return false;
1186}
1187
1188/**
1189 * dce_v11_0_check_latency_hiding - check latency hiding
1190 *
1191 * @wm: watermark calculation data
1192 *
1193 * Check latency hiding (CIK).
1194 * Used for display watermark bandwidth calculations
1195 * Returns true if the display fits, false if not.
1196 */
1197static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1198{
1199 u32 lb_partitions = wm->lb_size / wm->src_width;
1200 u32 line_time = wm->active_time + wm->blank_time;
1201 u32 latency_tolerant_lines;
1202 u32 latency_hiding;
1203 fixed20_12 a;
1204
1205 a.full = dfixed_const(1);
1206 if (wm->vsc.full > a.full)
1207 latency_tolerant_lines = 1;
1208 else {
1209 if (lb_partitions <= (wm->vtaps + 1))
1210 latency_tolerant_lines = 1;
1211 else
1212 latency_tolerant_lines = 2;
1213 }
1214
1215 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1216
1217 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1218 return true;
1219 else
1220 return false;
1221}
1222
1223/**
1224 * dce_v11_0_program_watermarks - program display watermarks
1225 *
1226 * @adev: amdgpu_device pointer
1227 * @amdgpu_crtc: the selected display controller
1228 * @lb_size: line buffer size
1229 * @num_heads: number of display controllers in use
1230 *
1231 * Calculate and program the display watermarks for the
1232 * selected display controller (CIK).
1233 */
1234static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1235 struct amdgpu_crtc *amdgpu_crtc,
1236 u32 lb_size, u32 num_heads)
1237{
1238 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1239 struct dce10_wm_params wm_low, wm_high;
1240 u32 pixel_period;
1241 u32 line_time = 0;
1242 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1243 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
aaa36a97
AD		 1244
1245 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1246 pixel_period = 1000000 / (u32)mode->clock;
1247 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1248
1249 /* watermark for high clocks */
1250 if (adev->pm.dpm_enabled) {
1251 wm_high.yclk =
1252 amdgpu_dpm_get_mclk(adev, false) * 10;
1253 wm_high.sclk =
1254 amdgpu_dpm_get_sclk(adev, false) * 10;
1255 } else {
1256 wm_high.yclk = adev->pm.current_mclk * 10;
1257 wm_high.sclk = adev->pm.current_sclk * 10;
1258 }
1259
1260 wm_high.disp_clk = mode->clock;
1261 wm_high.src_width = mode->crtc_hdisplay;
1262 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1263 wm_high.blank_time = line_time - wm_high.active_time;
1264 wm_high.interlaced = false;
1265 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1266 wm_high.interlaced = true;
1267 wm_high.vsc = amdgpu_crtc->vsc;
1268 wm_high.vtaps = 1;
1269 if (amdgpu_crtc->rmx_type != RMX_OFF)
1270 wm_high.vtaps = 2;
1271 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1272 wm_high.lb_size = lb_size;
1273 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1274 wm_high.num_heads = num_heads;
1275
1276 /* set for high clocks */
1277 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1278
1279 /* possibly force display priority to high */
1280 /* should really do this at mode validation time... */
1281 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1282 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1283 !dce_v11_0_check_latency_hiding(&wm_high) ||
1284 (adev->mode_info.disp_priority == 2)) {
1285 DRM_DEBUG_KMS("force priority to high\n");
1286 }
1287
1288 /* watermark for low clocks */
1289 if (adev->pm.dpm_enabled) {
1290 wm_low.yclk =
1291 amdgpu_dpm_get_mclk(adev, true) * 10;
1292 wm_low.sclk =
1293 amdgpu_dpm_get_sclk(adev, true) * 10;
1294 } else {
1295 wm_low.yclk = adev->pm.current_mclk * 10;
1296 wm_low.sclk = adev->pm.current_sclk * 10;
1297 }
1298
1299 wm_low.disp_clk = mode->clock;
1300 wm_low.src_width = mode->crtc_hdisplay;
1301 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1302 wm_low.blank_time = line_time - wm_low.active_time;
1303 wm_low.interlaced = false;
1304 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1305 wm_low.interlaced = true;
1306 wm_low.vsc = amdgpu_crtc->vsc;
1307 wm_low.vtaps = 1;
1308 if (amdgpu_crtc->rmx_type != RMX_OFF)
1309 wm_low.vtaps = 2;
1310 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1311 wm_low.lb_size = lb_size;
1312 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1313 wm_low.num_heads = num_heads;
1314
1315 /* set for low clocks */
1316 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1317
1318 /* possibly force display priority to high */
1319 /* should really do this at mode validation time... */
1320 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1321 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1322 !dce_v11_0_check_latency_hiding(&wm_low) ||
1323 (adev->mode_info.disp_priority == 2)) {
1324 DRM_DEBUG_KMS("force priority to high\n");
1325 }
8e36f9d3 1326 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
aaa36a97
AD		 1327 }
1328
1329 /* select wm A */
1330 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1331 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1332 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1333 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1334 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1335 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1336 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1337 /* select wm B */
1338 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1339 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1340 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
99a09238 1341 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
aaa36a97
AD		 1342 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1343 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1344 /* restore original selection */
1345 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1346
1347 /* save values for DPM */
1348 amdgpu_crtc->line_time = line_time;
1349 amdgpu_crtc->wm_high = latency_watermark_a;
1350 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1351 /* Save number of lines the linebuffer leads before the scanout */
1352 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
aaa36a97
AD		 1353}
1354
1355/**
1356 * dce_v11_0_bandwidth_update - program display watermarks
1357 *
1358 * @adev: amdgpu_device pointer
1359 *
1360 * Calculate and program the display watermarks and line
1361 * buffer allocation (CIK).
1362 */
1363static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1364{
1365 struct drm_display_mode *mode = NULL;
1366 u32 num_heads = 0, lb_size;
1367 int i;
1368
1369 amdgpu_update_display_priority(adev);
1370
1371 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1372 if (adev->mode_info.crtcs[i]->base.enabled)
1373 num_heads++;
1374 }
1375 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1376 mode = &adev->mode_info.crtcs[i]->base.mode;
1377 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1378 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1379 lb_size, num_heads);
1380 }
1381}
1382
1383static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1384{
1385 int i;
1386 u32 offset, tmp;
1387
1388 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1389 offset = adev->mode_info.audio.pin[i].offset;
1390 tmp = RREG32_AUDIO_ENDPT(offset,
1391 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1392 if (((tmp &
1393 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1394 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1395 adev->mode_info.audio.pin[i].connected = false;
1396 else
1397 adev->mode_info.audio.pin[i].connected = true;
1398 }
1399}
1400
1401static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1402{
1403 int i;
1404
1405 dce_v11_0_audio_get_connected_pins(adev);
1406
1407 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1408 if (adev->mode_info.audio.pin[i].connected)
1409 return &adev->mode_info.audio.pin[i];
1410 }
1411 DRM_ERROR("No connected audio pins found!\n");
1412 return NULL;
1413}
1414
1415static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1416{
1417 struct amdgpu_device *adev = encoder->dev->dev_private;
1418 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1419 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1420 u32 tmp;
1421
1422 if (!dig || !dig->afmt || !dig->afmt->pin)
1423 return;
1424
1425 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1426 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1427 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1428}
1429
1430static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1431 struct drm_display_mode *mode)
1432{
1433 struct amdgpu_device *adev = encoder->dev->dev_private;
1434 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1435 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1436 struct drm_connector *connector;
1437 struct amdgpu_connector *amdgpu_connector = NULL;
1438 u32 tmp;
1439 int interlace = 0;
1440
1441 if (!dig || !dig->afmt || !dig->afmt->pin)
1442 return;
1443
1444 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1445 if (connector->encoder == encoder) {
1446 amdgpu_connector = to_amdgpu_connector(connector);
1447 break;
1448 }
1449 }
1450
1451 if (!amdgpu_connector) {
1452 DRM_ERROR("Couldn't find encoder's connector\n");
1453 return;
1454 }
1455
1456 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1457 interlace = 1;
1458 if (connector->latency_present[interlace]) {
1459 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1460 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1461 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1462 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1463 } else {
1464 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1465 VIDEO_LIPSYNC, 0);
1466 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1467 AUDIO_LIPSYNC, 0);
1468 }
1469 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1470 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1471}
1472
1473static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1474{
1475 struct amdgpu_device *adev = encoder->dev->dev_private;
1476 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1477 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1478 struct drm_connector *connector;
1479 struct amdgpu_connector *amdgpu_connector = NULL;
1480 u32 tmp;
1481 u8 *sadb = NULL;
1482 int sad_count;
1483
1484 if (!dig || !dig->afmt || !dig->afmt->pin)
1485 return;
1486
1487 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1488 if (connector->encoder == encoder) {
1489 amdgpu_connector = to_amdgpu_connector(connector);
1490 break;
1491 }
1492 }
1493
1494 if (!amdgpu_connector) {
1495 DRM_ERROR("Couldn't find encoder's connector\n");
1496 return;
1497 }
1498
1499 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1500 if (sad_count < 0) {
1501 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1502 sad_count = 0;
1503 }
1504
1505 /* program the speaker allocation */
1506 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1507 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1508 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1509 DP_CONNECTION, 0);
1510 /* set HDMI mode */
1511 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1512 HDMI_CONNECTION, 1);
1513 if (sad_count)
1514 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1515 SPEAKER_ALLOCATION, sadb[0]);
1516 else
1517 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1518 SPEAKER_ALLOCATION, 5); /* stereo */
1519 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1520 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1521
1522 kfree(sadb);
1523}
1524
1525static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1526{
1527 struct amdgpu_device *adev = encoder->dev->dev_private;
1528 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1529 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1530 struct drm_connector *connector;
1531 struct amdgpu_connector *amdgpu_connector = NULL;
1532 struct cea_sad *sads;
1533 int i, sad_count;
1534
1535 static const u16 eld_reg_to_type[][2] = {
1536 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1537 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1538 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1539 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1540 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1541 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1542 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1543 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1544 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1545 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1546 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1547 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1548 };
1549
1550 if (!dig || !dig->afmt || !dig->afmt->pin)
1551 return;
1552
1553 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1554 if (connector->encoder == encoder) {
1555 amdgpu_connector = to_amdgpu_connector(connector);
1556 break;
1557 }
1558 }
1559
1560 if (!amdgpu_connector) {
1561 DRM_ERROR("Couldn't find encoder's connector\n");
1562 return;
1563 }
1564
1565 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1566 if (sad_count <= 0) {
1567 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1568 return;
1569 }
1570 BUG_ON(!sads);
1571
1572 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1573 u32 tmp = 0;
1574 u8 stereo_freqs = 0;
1575 int max_channels = -1;
1576 int j;
1577
1578 for (j = 0; j < sad_count; j++) {
1579 struct cea_sad *sad = &sads[j];
1580
1581 if (sad->format == eld_reg_to_type[i][1]) {
1582 if (sad->channels > max_channels) {
1583 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1584 MAX_CHANNELS, sad->channels);
1585 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1586 DESCRIPTOR_BYTE_2, sad->byte2);
1587 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1588 SUPPORTED_FREQUENCIES, sad->freq);
1589 max_channels = sad->channels;
1590 }
1591
1592 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1593 stereo_freqs |= sad->freq;
1594 else
1595 break;
1596 }
1597 }
1598
1599 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1600 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1601 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1602 }
1603
1604 kfree(sads);
1605}
1606
1607static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1608 struct amdgpu_audio_pin *pin,
1609 bool enable)
1610{
1611 if (!pin)
1612 return;
1613
1614 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1615 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1616}
1617
1618static const u32 pin_offsets[] =
1619{
1620 AUD0_REGISTER_OFFSET,
1621 AUD1_REGISTER_OFFSET,
1622 AUD2_REGISTER_OFFSET,
1623 AUD3_REGISTER_OFFSET,
1624 AUD4_REGISTER_OFFSET,
1625 AUD5_REGISTER_OFFSET,
1626 AUD6_REGISTER_OFFSET,
1627};
1628
1629static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1630{
1631 int i;
1632
1633 if (!amdgpu_audio)
1634 return 0;
1635
1636 adev->mode_info.audio.enabled = true;
1637
1638 adev->mode_info.audio.num_pins = 7;
1639
1640 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1641 adev->mode_info.audio.pin[i].channels = -1;
1642 adev->mode_info.audio.pin[i].rate = -1;
1643 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1644 adev->mode_info.audio.pin[i].status_bits = 0;
1645 adev->mode_info.audio.pin[i].category_code = 0;
1646 adev->mode_info.audio.pin[i].connected = false;
1647 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1648 adev->mode_info.audio.pin[i].id = i;
1649 /* disable audio. it will be set up later */
1650 /* XXX remove once we switch to ip funcs */
1651 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1652 }
1653
1654 return 0;
1655}
1656
1657static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1658{
1659 int i;
1660
29f646df
TSD		 1661 if (!amdgpu_audio)
1662 return;
1663
aaa36a97
AD		 1664 if (!adev->mode_info.audio.enabled)
1665 return;
1666
1667 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1668 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1669
1670 adev->mode_info.audio.enabled = false;
1671}
1672
1673/*
1674 * update the N and CTS parameters for a given pixel clock rate
1675 */
1676static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1677{
1678 struct drm_device *dev = encoder->dev;
1679 struct amdgpu_device *adev = dev->dev_private;
1680 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1681 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1682 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1683 u32 tmp;
1684
1685 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1686 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1687 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1688 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1689 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1690 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1691
1692 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1694 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1695 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1696 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1697 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1698
1699 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1700 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1701 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1702 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1703 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1704 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1705
1706}
1707
1708/*
1709 * build a HDMI Video Info Frame
1710 */
1711static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1712 void *buffer, size_t size)
1713{
1714 struct drm_device *dev = encoder->dev;
1715 struct amdgpu_device *adev = dev->dev_private;
1716 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1717 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1718 uint8_t *frame = buffer + 3;
1719 uint8_t *header = buffer;
1720
1721 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1722 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1723 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1724 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1725 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1726 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1727 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1728 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1729}
1730
1731static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1732{
1733 struct drm_device *dev = encoder->dev;
1734 struct amdgpu_device *adev = dev->dev_private;
1735 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1736 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1737 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1738 u32 dto_phase = 24 * 1000;
1739 u32 dto_modulo = clock;
1740 u32 tmp;
1741
1742 if (!dig || !dig->afmt)
1743 return;
1744
1745 /* XXX two dtos; generally use dto0 for hdmi */
1746 /* Express [24MHz / target pixel clock] as an exact rational
1747 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1748 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1749 */
1750 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1751 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1752 amdgpu_crtc->crtc_id);
1753 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1754 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1755 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1756}
1757
1758/*
1759 * update the info frames with the data from the current display mode
1760 */
1761static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1762 struct drm_display_mode *mode)
1763{
1764 struct drm_device *dev = encoder->dev;
1765 struct amdgpu_device *adev = dev->dev_private;
1766 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1767 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1768 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1769 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1770 struct hdmi_avi_infoframe frame;
1771 ssize_t err;
1772 u32 tmp;
1773 int bpc = 8;
1774
1775 if (!dig || !dig->afmt)
1776 return;
1777
1778 /* Silent, r600_hdmi_enable will raise WARN for us */
1779 if (!dig->afmt->enabled)
1780 return;
1781
1782 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1783 if (encoder->crtc) {
1784 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1785 bpc = amdgpu_crtc->bpc;
1786 }
1787
1788 /* disable audio prior to setting up hw */
1789 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1790 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1791
1792 dce_v11_0_audio_set_dto(encoder, mode->clock);
1793
1794 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1795 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1796 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1797
1798 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1799
1800 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1801 switch (bpc) {
1802 case 0:
1803 case 6:
1804 case 8:
1805 case 16:
1806 default:
1807 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1808 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1809 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1810 connector->name, bpc);
1811 break;
1812 case 10:
1813 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1815 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1816 connector->name);
1817 break;
1818 case 12:
1819 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1820 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1821 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1822 connector->name);
1823 break;
1824 }
1825 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1826
1827 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1828 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1829 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1830 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1831 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1832
1833 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1834 /* enable audio info frames (frames won't be set until audio is enabled) */
1835 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1836 /* required for audio info values to be updated */
1837 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1838 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1839
1840 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1841 /* required for audio info values to be updated */
1842 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1843 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1844
1845 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1846 /* anything other than 0 */
1847 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1848 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1849
1850 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1851
1852 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1853 /* set the default audio delay */
1854 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1855 /* should be suffient for all audio modes and small enough for all hblanks */
1856 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1857 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1858
1859 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1860 /* allow 60958 channel status fields to be updated */
1861 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1862 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1863
1864 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1865 if (bpc > 8)
1866 /* clear SW CTS value */
1867 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1868 else
1869 /* select SW CTS value */
1870 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1871 /* allow hw to sent ACR packets when required */
1872 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1873 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1874
1875 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1876
1877 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1878 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1879 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1880
1881 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1883 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1884
1885 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1886 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1887 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1888 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1889 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1890 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1891 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1892 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1893
1894 dce_v11_0_audio_write_speaker_allocation(encoder);
1895
1896 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1897 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1898
1899 dce_v11_0_afmt_audio_select_pin(encoder);
1900 dce_v11_0_audio_write_sad_regs(encoder);
1901 dce_v11_0_audio_write_latency_fields(encoder, mode);
1902
1903 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1904 if (err < 0) {
1905 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1906 return;
1907 }
1908
1909 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1910 if (err < 0) {
1911 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1912 return;
1913 }
1914
1915 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1916
1917 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1918 /* enable AVI info frames */
1919 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1920 /* required for audio info values to be updated */
1921 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1922 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1923
1924 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1925 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1926 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1927
1928 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1929 /* send audio packets */
1930 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1931 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1932
1933 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1934 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1935 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1936 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1937
1938 /* enable audio after to setting up hw */
1939 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1940}
1941
1942static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1943{
1944 struct drm_device *dev = encoder->dev;
1945 struct amdgpu_device *adev = dev->dev_private;
1946 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1947 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1948
1949 if (!dig || !dig->afmt)
1950 return;
1951
1952 /* Silent, r600_hdmi_enable will raise WARN for us */
1953 if (enable && dig->afmt->enabled)
1954 return;
1955 if (!enable && !dig->afmt->enabled)
1956 return;
1957
1958 if (!enable && dig->afmt->pin) {
1959 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1960 dig->afmt->pin = NULL;
1961 }
1962
1963 dig->afmt->enabled = enable;
1964
1965 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1966 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1967}
1968
041ab0a4 1969static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
aaa36a97
AD		 1970{
1971 int i;
1972
1973 for (i = 0; i < adev->mode_info.num_dig; i++)
1974 adev->mode_info.afmt[i] = NULL;
1975
1976 /* DCE11 has audio blocks tied to DIG encoders */
1977 for (i = 0; i < adev->mode_info.num_dig; i++) {
1978 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1979 if (adev->mode_info.afmt[i]) {
1980 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1981 adev->mode_info.afmt[i]->id = i;
041ab0a4
TSD		 1982 } else {
1983 int j;
1984 for (j = 0; j < i; j++) {
1985 kfree(adev->mode_info.afmt[j]);
1986 adev->mode_info.afmt[j] = NULL;
1987 }
1988 return -ENOMEM;
aaa36a97
AD		 1989 }
1990 }
041ab0a4 1991 return 0;
aaa36a97
AD		 1992}
1993
1994static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1995{
1996 int i;
1997
1998 for (i = 0; i < adev->mode_info.num_dig; i++) {
1999 kfree(adev->mode_info.afmt[i]);
2000 adev->mode_info.afmt[i] = NULL;
2001 }
2002}
2003
2004static const u32 vga_control_regs[6] =
2005{
2006 mmD1VGA_CONTROL,
2007 mmD2VGA_CONTROL,
2008 mmD3VGA_CONTROL,
2009 mmD4VGA_CONTROL,
2010 mmD5VGA_CONTROL,
2011 mmD6VGA_CONTROL,
2012};
2013
2014static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2015{
2016 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2017 struct drm_device *dev = crtc->dev;
2018 struct amdgpu_device *adev = dev->dev_private;
2019 u32 vga_control;
2020
2021 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2022 if (enable)
2023 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2024 else
2025 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2026}
2027
2028static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2029{
2030 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2031 struct drm_device *dev = crtc->dev;
2032 struct amdgpu_device *adev = dev->dev_private;
2033
2034 if (enable)
2035 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2036 else
2037 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2038}
2039
aaa36a97
AD		 2040static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2041 struct drm_framebuffer *fb,
2042 int x, int y, int atomic)
2043{
2044 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2045 struct drm_device *dev = crtc->dev;
2046 struct amdgpu_device *adev = dev->dev_private;
2047 struct amdgpu_framebuffer *amdgpu_fb;
2048 struct drm_framebuffer *target_fb;
2049 struct drm_gem_object *obj;
2050 struct amdgpu_bo *rbo;
2051 uint64_t fb_location, tiling_flags;
2052 uint32_t fb_format, fb_pitch_pixels;
aaa36a97 2053 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
fbd76d59 2054 u32 pipe_config;
aaa36a97
AD		 2055 u32 tmp, viewport_w, viewport_h;
2056 int r;
2057 bool bypass_lut = false;
2058
2059 /* no fb bound */
2060 if (!atomic && !crtc->primary->fb) {
2061 DRM_DEBUG_KMS("No FB bound\n");
2062 return 0;
2063 }
2064
2065 if (atomic) {
2066 amdgpu_fb = to_amdgpu_framebuffer(fb);
2067 target_fb = fb;
2068 }
2069 else {
2070 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2071 target_fb = crtc->primary->fb;
2072 }
2073
2074 /* If atomic, assume fb object is pinned & idle & fenced and
2075 * just update base pointers
2076 */
2077 obj = amdgpu_fb->obj;
2078 rbo = gem_to_amdgpu_bo(obj);
2079 r = amdgpu_bo_reserve(rbo, false);
2080 if (unlikely(r != 0))
2081 return r;
2082
2083 if (atomic)
2084 fb_location = amdgpu_bo_gpu_offset(rbo);
2085 else {
2086 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2087 if (unlikely(r != 0)) {
2088 amdgpu_bo_unreserve(rbo);
2089 return -EINVAL;
2090 }
2091 }
2092
2093 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2094 amdgpu_bo_unreserve(rbo);
2095
fbd76d59
MO		 2096 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2097
aaa36a97
AD		 2098 switch (target_fb->pixel_format) {
2099 case DRM_FORMAT_C8:
2100 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2101 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2102 break;
2103 case DRM_FORMAT_XRGB4444:
2104 case DRM_FORMAT_ARGB4444:
2105 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2106 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2107#ifdef __BIG_ENDIAN
2108 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2109 ENDIAN_8IN16);
2110#endif
2111 break;
2112 case DRM_FORMAT_XRGB1555:
2113 case DRM_FORMAT_ARGB1555:
2114 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2115 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2116#ifdef __BIG_ENDIAN
2117 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2118 ENDIAN_8IN16);
2119#endif
2120 break;
2121 case DRM_FORMAT_BGRX5551:
2122 case DRM_FORMAT_BGRA5551:
2123 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2124 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2125#ifdef __BIG_ENDIAN
2126 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2127 ENDIAN_8IN16);
2128#endif
2129 break;
2130 case DRM_FORMAT_RGB565:
2131 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2132 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2133#ifdef __BIG_ENDIAN
2134 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2135 ENDIAN_8IN16);
2136#endif
2137 break;
2138 case DRM_FORMAT_XRGB8888:
2139 case DRM_FORMAT_ARGB8888:
2140 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2142#ifdef __BIG_ENDIAN
2143 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2144 ENDIAN_8IN32);
2145#endif
2146 break;
2147 case DRM_FORMAT_XRGB2101010:
2148 case DRM_FORMAT_ARGB2101010:
2149 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2150 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2151#ifdef __BIG_ENDIAN
2152 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2153 ENDIAN_8IN32);
2154#endif
2155 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2156 bypass_lut = true;
2157 break;
2158 case DRM_FORMAT_BGRX1010102:
2159 case DRM_FORMAT_BGRA1010102:
2160 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2162#ifdef __BIG_ENDIAN
2163 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2164 ENDIAN_8IN32);
2165#endif
2166 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2167 bypass_lut = true;
2168 break;
2169 default:
2170 DRM_ERROR("Unsupported screen format %s\n",
2171 drm_get_format_name(target_fb->pixel_format));
2172 return -EINVAL;
2173 }
2174
fbd76d59
MO		 2175 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2176 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
aaa36a97 2177
fbd76d59
MO		 2178 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2179 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2180 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2181 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2182 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
aaa36a97 2183
aaa36a97
AD		 2184 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2185 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2186 ARRAY_2D_TILED_THIN1);
2187 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2188 tile_split);
2189 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2190 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2191 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2192 mtaspect);
2193 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2194 ADDR_SURF_MICRO_TILING_DISPLAY);
fbd76d59 2195 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
aaa36a97
AD		 2196 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2197 ARRAY_1D_TILED_THIN1);
2198 }
2199
aaa36a97
AD		 2200 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2201 pipe_config);
2202
2203 dce_v11_0_vga_enable(crtc, false);
2204
2205 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2206 upper_32_bits(fb_location));
2207 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2208 upper_32_bits(fb_location));
2209 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2210 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2211 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2212 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2213 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2214 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2215
2216 /*
2217 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2218 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2219 * retain the full precision throughout the pipeline.
2220 */
2221 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2222 if (bypass_lut)
2223 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2224 else
2225 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2226 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2227
2228 if (bypass_lut)
2229 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2230
2231 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2232 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2233 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2234 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2235 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2236 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2237
2238 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2239 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2240
2241 dce_v11_0_grph_enable(crtc, true);
2242
2243 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2244 target_fb->height);
2245
2246 x &= ~3;
2247 y &= ~1;
2248 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2249 (x << 16) | y);
2250 viewport_w = crtc->mode.hdisplay;
2251 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2252 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2253 (viewport_w << 16) | viewport_h);
2254
2255 /* pageflip setup */
2256 /* make sure flip is at vb rather than hb */
2257 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2258 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2259 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2260 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2261
2262 /* set pageflip to happen only at start of vblank interval (front porch) */
2263 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2264
2265 if (!atomic && fb && fb != crtc->primary->fb) {
2266 amdgpu_fb = to_amdgpu_framebuffer(fb);
2267 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2268 r = amdgpu_bo_reserve(rbo, false);
2269 if (unlikely(r != 0))
2270 return r;
2271 amdgpu_bo_unpin(rbo);
2272 amdgpu_bo_unreserve(rbo);
2273 }
2274
2275 /* Bytes per pixel may have changed */
2276 dce_v11_0_bandwidth_update(adev);
2277
2278 return 0;
2279}
2280
2281static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2282 struct drm_display_mode *mode)
2283{
2284 struct drm_device *dev = crtc->dev;
2285 struct amdgpu_device *adev = dev->dev_private;
2286 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2287 u32 tmp;
2288
2289 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2290 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2291 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2292 else
2293 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2294 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2295}
2296
2297static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2298{
2299 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2300 struct drm_device *dev = crtc->dev;
2301 struct amdgpu_device *adev = dev->dev_private;
2302 int i;
2303 u32 tmp;
2304
2305 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2306
2307 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2308 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2309 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2310
2311 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2312 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2313 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2314
2315 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2316 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2317 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2318
2319 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2320
2321 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2322 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2323 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2324
2325 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2326 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2327 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2328
2329 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2330 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2331
2332 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2333 for (i = 0; i < 256; i++) {
2334 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2335 (amdgpu_crtc->lut_r[i] << 20) |
2336 (amdgpu_crtc->lut_g[i] << 10) |
2337 (amdgpu_crtc->lut_b[i] << 0));
2338 }
2339
2340 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2341 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2342 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2343 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2344 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2345
2346 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2347 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2348 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2349
2350 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2351 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2352 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2353
2354 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2355 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2356 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2357
2358 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2359 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2360 /* XXX this only needs to be programmed once per crtc at startup,
2361 * not sure where the best place for it is
2362 */
2363 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2364 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2365 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2366}
2367
2368static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2369{
2370 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2371 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2372
2373 switch (amdgpu_encoder->encoder_id) {
2374 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2375 if (dig->linkb)
2376 return 1;
2377 else
2378 return 0;
2379 break;
2380 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2381 if (dig->linkb)
2382 return 3;
2383 else
2384 return 2;
2385 break;
2386 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2387 if (dig->linkb)
2388 return 5;
2389 else
2390 return 4;
2391 break;
2392 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2393 return 6;
2394 break;
2395 default:
2396 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2397 return 0;
2398 }
2399}
2400
2401/**
2402 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2403 *
2404 * @crtc: drm crtc
2405 *
2406 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2407 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2408 * monitors a dedicated PPLL must be used. If a particular board has
2409 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2410 * as there is no need to program the PLL itself. If we are not able to
2411 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2412 * avoid messing up an existing monitor.
2413 *
2414 * Asic specific PLL information
2415 *
2416 * DCE 10.x
2417 * Tonga
2418 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2419 * CI
2420 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2421 *
2422 */
2423static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2424{
2425 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2426 struct drm_device *dev = crtc->dev;
2427 struct amdgpu_device *adev = dev->dev_private;
2428 u32 pll_in_use;
2429 int pll;
2430
2431 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2432 if (adev->clock.dp_extclk)
2433 /* skip PPLL programming if using ext clock */
2434 return ATOM_PPLL_INVALID;
2435 else {
2436 /* use the same PPLL for all DP monitors */
2437 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2438 if (pll != ATOM_PPLL_INVALID)
2439 return pll;
2440 }
2441 } else {
2442 /* use the same PPLL for all monitors with the same clock */
2443 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2444 if (pll != ATOM_PPLL_INVALID)
2445 return pll;
2446 }
2447
2448 /* XXX need to determine what plls are available on each DCE11 part */
2449 pll_in_use = amdgpu_pll_get_use_mask(crtc);
fa2f9bef 2450 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
aaa36a97
AD		 2451 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2452 return ATOM_PPLL1;
2453 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2454 return ATOM_PPLL0;
2455 DRM_ERROR("unable to allocate a PPLL\n");
2456 return ATOM_PPLL_INVALID;
2457 } else {
2458 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2459 return ATOM_PPLL2;
2460 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2461 return ATOM_PPLL1;
2462 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2463 return ATOM_PPLL0;
2464 DRM_ERROR("unable to allocate a PPLL\n");
2465 return ATOM_PPLL_INVALID;
2466 }
2467 return ATOM_PPLL_INVALID;
2468}
2469
2470static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2471{
2472 struct amdgpu_device *adev = crtc->dev->dev_private;
2473 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2474 uint32_t cur_lock;
2475
2476 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2477 if (lock)
2478 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2479 else
2480 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2481 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2482}
2483
2484static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2485{
2486 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2487 struct amdgpu_device *adev = crtc->dev->dev_private;
2488 u32 tmp;
2489
2490 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2491 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2492 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2493}
2494
2495static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2496{
2497 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2498 struct amdgpu_device *adev = crtc->dev->dev_private;
2499 u32 tmp;
2500
ec9353dc
AD		 2501 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2502 upper_32_bits(amdgpu_crtc->cursor_addr));
2503 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2504 lower_32_bits(amdgpu_crtc->cursor_addr));
2505
aaa36a97
AD		 2506 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2507 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2508 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2509 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2510}
2511
d8ee89c6
AD		 2512static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2513 int x, int y)
aaa36a97
AD		 2514{
2515 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2516 struct amdgpu_device *adev = crtc->dev->dev_private;
2517 int xorigin = 0, yorigin = 0;
2518
2519 /* avivo cursor are offset into the total surface */
2520 x += crtc->x;
2521 y += crtc->y;
2522 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2523
2524 if (x < 0) {
2525 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2526 x = 0;
2527 }
2528 if (y < 0) {
2529 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2530 y = 0;
2531 }
2532
aaa36a97
AD		 2533 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2534 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2535 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2536 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
d8ee89c6
AD		 2537
2538 amdgpu_crtc->cursor_x = x;
2539 amdgpu_crtc->cursor_y = y;
aaa36a97
AD		 2540
2541 return 0;
2542}
2543
d8ee89c6
AD		 2544static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2545 int x, int y)
2546{
2547 int ret;
2548
2549 dce_v11_0_lock_cursor(crtc, true);
2550 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2551 dce_v11_0_lock_cursor(crtc, false);
2552
2553 return ret;
2554}
2555
2556static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2557 struct drm_file *file_priv,
2558 uint32_t handle,
2559 uint32_t width,
2560 uint32_t height,
2561 int32_t hot_x,
2562 int32_t hot_y)
aaa36a97
AD		 2563{
2564 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2565 struct drm_gem_object *obj;
232cc652 2566 struct amdgpu_bo *aobj;
aaa36a97
AD		 2567 int ret;
2568
2569 if (!handle) {
2570 /* turn off cursor */
2571 dce_v11_0_hide_cursor(crtc);
2572 obj = NULL;
2573 goto unpin;
2574 }
2575
2576 if ((width > amdgpu_crtc->max_cursor_width) ||
2577 (height > amdgpu_crtc->max_cursor_height)) {
2578 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2579 return -EINVAL;
2580 }
2581
2582 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2583 if (!obj) {
2584 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2585 return -ENOENT;
2586 }
2587
232cc652
AD		 2588 aobj = gem_to_amdgpu_bo(obj);
2589 ret = amdgpu_bo_reserve(aobj, false);
2590 if (ret != 0) {
2591 drm_gem_object_unreference_unlocked(obj);
2592 return ret;
2593 }
2594
2595 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2596 amdgpu_bo_unreserve(aobj);
2597 if (ret) {
2598 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2599 drm_gem_object_unreference_unlocked(obj);
2600 return ret;
2601 }
aaa36a97
AD		 2602
2603 amdgpu_crtc->cursor_width = width;
2604 amdgpu_crtc->cursor_height = height;
2605
2606 dce_v11_0_lock_cursor(crtc, true);
1996ea09
AD		 2607
2608 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2609 hot_y != amdgpu_crtc->cursor_hot_y) {
2610 int x, y;
2611
2612 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2613 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2614
2615 dce_v11_0_cursor_move_locked(crtc, x, y);
2616
2617 amdgpu_crtc->cursor_hot_x = hot_x;
2618 amdgpu_crtc->cursor_hot_y = hot_y;
2619 }
2620
aaa36a97
AD		 2621 dce_v11_0_show_cursor(crtc);
2622 dce_v11_0_lock_cursor(crtc, false);
2623
2624unpin:
2625 if (amdgpu_crtc->cursor_bo) {
8ddef5a5
AD		 2626 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2627 ret = amdgpu_bo_reserve(aobj, false);
aaa36a97 2628 if (likely(ret == 0)) {
8ddef5a5
AD		 2629 amdgpu_bo_unpin(aobj);
2630 amdgpu_bo_unreserve(aobj);
aaa36a97
AD		 2631 }
2632 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2633 }
2634
2635 amdgpu_crtc->cursor_bo = obj;
2636 return 0;
8ddef5a5 2637}
aaa36a97 2638
8ddef5a5
AD		 2639static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2640{
2641 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
8ddef5a5
AD		 2642
2643 if (amdgpu_crtc->cursor_bo) {
2644 dce_v11_0_lock_cursor(crtc, true);
2645
2646 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2647 amdgpu_crtc->cursor_y);
2648
232cc652 2649 dce_v11_0_show_cursor(crtc);
8ddef5a5
AD		 2650
2651 dce_v11_0_lock_cursor(crtc, false);
2652 }
aaa36a97
AD		 2653}
2654
2655static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2656 u16 *blue, uint32_t start, uint32_t size)
2657{
2658 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2659 int end = (start + size > 256) ? 256 : start + size, i;
2660
2661 /* userspace palettes are always correct as is */
2662 for (i = start; i < end; i++) {
2663 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2664 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2665 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2666 }
2667 dce_v11_0_crtc_load_lut(crtc);
2668}
2669
2670static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2671{
2672 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2673
2674 drm_crtc_cleanup(crtc);
aaa36a97
AD		 2675 kfree(amdgpu_crtc);
2676}
2677
2678static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
d8ee89c6 2679 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
aaa36a97
AD		 2680 .cursor_move = dce_v11_0_crtc_cursor_move,
2681 .gamma_set = dce_v11_0_crtc_gamma_set,
2682 .set_config = amdgpu_crtc_set_config,
2683 .destroy = dce_v11_0_crtc_destroy,
2684 .page_flip = amdgpu_crtc_page_flip,
2685};
2686
2687static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2688{
2689 struct drm_device *dev = crtc->dev;
2690 struct amdgpu_device *adev = dev->dev_private;
2691 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
d84b272a 2692 unsigned type;
aaa36a97
AD		 2693
2694 switch (mode) {
2695 case DRM_MODE_DPMS_ON:
2696 amdgpu_crtc->enabled = true;
2697 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2698 dce_v11_0_vga_enable(crtc, true);
2699 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2700 dce_v11_0_vga_enable(crtc, false);
f6c7aba4 2701 /* Make sure VBLANK and PFLIP interrupts are still enabled */
d84b272a
MD		 2702 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2703 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2704 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
b6bae58d 2705 drm_vblank_on(dev, amdgpu_crtc->crtc_id);
aaa36a97
AD		 2706 dce_v11_0_crtc_load_lut(crtc);
2707 break;
2708 case DRM_MODE_DPMS_STANDBY:
2709 case DRM_MODE_DPMS_SUSPEND:
2710 case DRM_MODE_DPMS_OFF:
b6bae58d 2711 drm_vblank_off(dev, amdgpu_crtc->crtc_id);
aaa36a97
AD		 2712 if (amdgpu_crtc->enabled) {
2713 dce_v11_0_vga_enable(crtc, true);
2714 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2715 dce_v11_0_vga_enable(crtc, false);
2716 }
2717 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2718 amdgpu_crtc->enabled = false;
2719 break;
2720 }
2721 /* adjust pm to dpms */
2722 amdgpu_pm_compute_clocks(adev);
2723}
2724
2725static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2726{
2727 /* disable crtc pair power gating before programming */
2728 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2729 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2730 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2731}
2732
2733static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2734{
2735 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2736 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2737}
2738
2739static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2740{
2741 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2742 struct drm_device *dev = crtc->dev;
2743 struct amdgpu_device *adev = dev->dev_private;
2744 struct amdgpu_atom_ss ss;
2745 int i;
2746
2747 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2748 if (crtc->primary->fb) {
2749 int r;
2750 struct amdgpu_framebuffer *amdgpu_fb;
2751 struct amdgpu_bo *rbo;
2752
2753 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2754 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2755 r = amdgpu_bo_reserve(rbo, false);
2756 if (unlikely(r))
2757 DRM_ERROR("failed to reserve rbo before unpin\n");
2758 else {
2759 amdgpu_bo_unpin(rbo);
2760 amdgpu_bo_unreserve(rbo);
2761 }
2762 }
2763 /* disable the GRPH */
2764 dce_v11_0_grph_enable(crtc, false);
2765
2766 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2767
2768 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2769 if (adev->mode_info.crtcs[i] &&
2770 adev->mode_info.crtcs[i]->enabled &&
2771 i != amdgpu_crtc->crtc_id &&
2772 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2773 /* one other crtc is using this pll don't turn
2774 * off the pll
2775 */
2776 goto done;
2777 }
2778 }
2779
2780 switch (amdgpu_crtc->pll_id) {
2781 case ATOM_PPLL0:
2782 case ATOM_PPLL1:
2783 case ATOM_PPLL2:
2784 /* disable the ppll */
2785 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2786 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2787 break;
2788 default:
2789 break;
2790 }
2791done:
2792 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2793 amdgpu_crtc->adjusted_clock = 0;
2794 amdgpu_crtc->encoder = NULL;
2795 amdgpu_crtc->connector = NULL;
2796}
2797
2798static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2799 struct drm_display_mode *mode,
2800 struct drm_display_mode *adjusted_mode,
2801 int x, int y, struct drm_framebuffer *old_fb)
2802{
2803 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2804
2805 if (!amdgpu_crtc->adjusted_clock)
2806 return -EINVAL;
2807
2808 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2809 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2810 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2811 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2812 amdgpu_atombios_crtc_scaler_setup(crtc);
8ddef5a5 2813 dce_v11_0_cursor_reset(crtc);
aaa36a97
AD		 2814 /* update the hw version fpr dpm */
2815 amdgpu_crtc->hw_mode = *adjusted_mode;
2816
2817 return 0;
2818}
2819
2820static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2821 const struct drm_display_mode *mode,
2822 struct drm_display_mode *adjusted_mode)
2823{
2824 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2825 struct drm_device *dev = crtc->dev;
2826 struct drm_encoder *encoder;
2827
2828 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2829 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2830 if (encoder->crtc == crtc) {
2831 amdgpu_crtc->encoder = encoder;
2832 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2833 break;
2834 }
2835 }
2836 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2837 amdgpu_crtc->encoder = NULL;
2838 amdgpu_crtc->connector = NULL;
2839 return false;
2840 }
2841 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2842 return false;
2843 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2844 return false;
2845 /* pick pll */
2846 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2847 /* if we can't get a PPLL for a non-DP encoder, fail */
2848 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2849 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2850 return false;
2851
2852 return true;
2853}
2854
2855static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2856 struct drm_framebuffer *old_fb)
2857{
2858 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2859}
2860
2861static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2862 struct drm_framebuffer *fb,
2863 int x, int y, enum mode_set_atomic state)
2864{
2865 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2866}
2867
2868static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2869 .dpms = dce_v11_0_crtc_dpms,
2870 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2871 .mode_set = dce_v11_0_crtc_mode_set,
2872 .mode_set_base = dce_v11_0_crtc_set_base,
2873 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2874 .prepare = dce_v11_0_crtc_prepare,
2875 .commit = dce_v11_0_crtc_commit,
2876 .load_lut = dce_v11_0_crtc_load_lut,
2877 .disable = dce_v11_0_crtc_disable,
2878};
2879
2880static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2881{
2882 struct amdgpu_crtc *amdgpu_crtc;
2883 int i;
2884
2885 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2886 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2887 if (amdgpu_crtc == NULL)
2888 return -ENOMEM;
2889
2890 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2891
2892 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2893 amdgpu_crtc->crtc_id = index;
aaa36a97
AD		 2894 adev->mode_info.crtcs[index] = amdgpu_crtc;
2895
2896 amdgpu_crtc->max_cursor_width = 128;
2897 amdgpu_crtc->max_cursor_height = 128;
2898 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2899 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2900
2901 for (i = 0; i < 256; i++) {
2902 amdgpu_crtc->lut_r[i] = i << 2;
2903 amdgpu_crtc->lut_g[i] = i << 2;
2904 amdgpu_crtc->lut_b[i] = i << 2;
2905 }
2906
2907 switch (amdgpu_crtc->crtc_id) {
2908 case 0:
2909 default:
2910 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2911 break;
2912 case 1:
2913 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2914 break;
2915 case 2:
2916 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2917 break;
2918 case 3:
2919 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2920 break;
2921 case 4:
2922 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2923 break;
2924 case 5:
2925 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2926 break;
2927 }
2928
2929 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2930 amdgpu_crtc->adjusted_clock = 0;
2931 amdgpu_crtc->encoder = NULL;
2932 amdgpu_crtc->connector = NULL;
2933 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2934
2935 return 0;
2936}
2937
5fc3aeeb 2938static int dce_v11_0_early_init(void *handle)
aaa36a97 2939{
5fc3aeeb 2940 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2941
aaa36a97
AD		 2942 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2943 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2944
2945 dce_v11_0_set_display_funcs(adev);
2946 dce_v11_0_set_irq_funcs(adev);
2947
2948 switch (adev->asic_type) {
2949 case CHIP_CARRIZO:
26d0c21d 2950 adev->mode_info.num_crtc = 3;
aaa36a97
AD		 2951 adev->mode_info.num_hpd = 6;
2952 adev->mode_info.num_dig = 9;
2953 break;
fa2f9bef
SL		 2954 case CHIP_STONEY:
2955 adev->mode_info.num_crtc = 2;
2956 adev->mode_info.num_hpd = 6;
2957 adev->mode_info.num_dig = 9;
2958 break;
aaa36a97
AD		 2959 default:
2960 /* FIXME: not supported yet */
2961 return -EINVAL;
2962 }
2963
2964 return 0;
2965}
2966
5fc3aeeb 2967static int dce_v11_0_sw_init(void *handle)
aaa36a97
AD		 2968{
2969 int r, i;
5fc3aeeb 2970 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 2971
2972 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2973 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2974 if (r)
bcc71beb 2975 return r;
aaa36a97
AD		 2976 }
2977
2978 for (i = 8; i < 20; i += 2) {
2979 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2980 if (r)
2981 return r;
2982 }
2983
2984 /* HPD hotplug */
2985 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2986 if (r)
bcc71beb 2987 return r;
aaa36a97 2988
aaa36a97
AD		 2989 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2990
2991 adev->ddev->mode_config.max_width = 16384;
2992 adev->ddev->mode_config.max_height = 16384;
2993
2994 adev->ddev->mode_config.preferred_depth = 24;
2995 adev->ddev->mode_config.prefer_shadow = 1;
2996
2997 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2998
2999 r = amdgpu_modeset_create_props(adev);
3000 if (r)
3001 return r;
3002
3003 adev->ddev->mode_config.max_width = 16384;
3004 adev->ddev->mode_config.max_height = 16384;
3005
c437b9d6 3006
aaa36a97
AD		 3007 /* allocate crtcs */
3008 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3009 r = dce_v11_0_crtc_init(adev, i);
3010 if (r)
3011 return r;
3012 }
3013
3014 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3015 amdgpu_print_display_setup(adev->ddev);
3016 else
3017 return -EINVAL;
3018
3019 /* setup afmt */
041ab0a4
TSD		 3020 r = dce_v11_0_afmt_init(adev);
3021 if (r)
3022 return r;
aaa36a97
AD		 3023
3024 r = dce_v11_0_audio_init(adev);
3025 if (r)
3026 return r;
3027
3028 drm_kms_helper_poll_init(adev->ddev);
3029
c437b9d6
TSD		 3030 adev->mode_info.mode_config_initialized = true;
3031 return 0;
aaa36a97
AD		 3032}
3033
5fc3aeeb 3034static int dce_v11_0_sw_fini(void *handle)
aaa36a97 3035{
5fc3aeeb 3036 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3037
aaa36a97
AD		 3038 kfree(adev->mode_info.bios_hardcoded_edid);
3039
3040 drm_kms_helper_poll_fini(adev->ddev);
3041
3042 dce_v11_0_audio_fini(adev);
3043
3044 dce_v11_0_afmt_fini(adev);
3045
3046 adev->mode_info.mode_config_initialized = false;
3047
3048 return 0;
3049}
3050
5fc3aeeb 3051static int dce_v11_0_hw_init(void *handle)
aaa36a97
AD		 3052{
3053 int i;
5fc3aeeb 3054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3055
3056 dce_v11_0_init_golden_registers(adev);
3057
3058 /* init dig PHYs, disp eng pll */
f9fff064 3059 amdgpu_atombios_crtc_powergate_init(adev);
aaa36a97
AD		 3060 amdgpu_atombios_encoder_init_dig(adev);
3061 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3062
3063 /* initialize hpd */
3064 dce_v11_0_hpd_init(adev);
3065
3066 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3067 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3068 }
3069
f6c7aba4
MD		 3070 dce_v11_0_pageflip_interrupt_init(adev);
3071
aaa36a97
AD		 3072 return 0;
3073}
3074
5fc3aeeb 3075static int dce_v11_0_hw_fini(void *handle)
aaa36a97
AD		 3076{
3077 int i;
5fc3aeeb 3078 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3079
3080 dce_v11_0_hpd_fini(adev);
3081
3082 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3083 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3084 }
3085
f6c7aba4
MD		 3086 dce_v11_0_pageflip_interrupt_fini(adev);
3087
aaa36a97
AD		 3088 return 0;
3089}
3090
5fc3aeeb 3091static int dce_v11_0_suspend(void *handle)
aaa36a97 3092{
5fc3aeeb 3093 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 3094
aaa36a97
AD		 3095 amdgpu_atombios_scratch_regs_save(adev);
3096
f9fff064 3097 return dce_v11_0_hw_fini(handle);
aaa36a97
AD		 3098}
3099
5fc3aeeb 3100static int dce_v11_0_resume(void *handle)
aaa36a97 3101{
5fc3aeeb 3102 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064 3103 int ret;
aaa36a97 3104
f9fff064 3105 ret = dce_v11_0_hw_init(handle);
aaa36a97
AD		 3106
3107 amdgpu_atombios_scratch_regs_restore(adev);
3108
aaa36a97
AD		 3109 /* turn on the BL */
3110 if (adev->mode_info.bl_encoder) {
3111 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3112 adev->mode_info.bl_encoder);
3113 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3114 bl_level);
3115 }
3116
f9fff064 3117 return ret;
aaa36a97
AD		 3118}
3119
5fc3aeeb 3120static bool dce_v11_0_is_idle(void *handle)
aaa36a97 3121{
aaa36a97
AD		 3122 return true;
3123}
3124
5fc3aeeb 3125static int dce_v11_0_wait_for_idle(void *handle)
aaa36a97 3126{
aaa36a97
AD		 3127 return 0;
3128}
3129
5fc3aeeb 3130static void dce_v11_0_print_status(void *handle)
aaa36a97 3131{
5fc3aeeb 3132 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3133
aaa36a97
AD		 3134 dev_info(adev->dev, "DCE 10.x registers\n");
3135 /* XXX todo */
3136}
3137
5fc3aeeb 3138static int dce_v11_0_soft_reset(void *handle)
aaa36a97
AD		 3139{
3140 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 3141 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3142
3143 if (dce_v11_0_is_display_hung(adev))
3144 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3145
3146 if (srbm_soft_reset) {
5fc3aeeb 3147 dce_v11_0_print_status((void *)adev);
aaa36a97
AD		 3148
3149 tmp = RREG32(mmSRBM_SOFT_RESET);
3150 tmp |= srbm_soft_reset;
3151 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3152 WREG32(mmSRBM_SOFT_RESET, tmp);
3153 tmp = RREG32(mmSRBM_SOFT_RESET);
3154
3155 udelay(50);
3156
3157 tmp &= ~srbm_soft_reset;
3158 WREG32(mmSRBM_SOFT_RESET, tmp);
3159 tmp = RREG32(mmSRBM_SOFT_RESET);
3160
3161 /* Wait a little for things to settle down */
3162 udelay(50);
5fc3aeeb 3163 dce_v11_0_print_status((void *)adev);
aaa36a97
AD		 3164 }
3165 return 0;
3166}
3167
3168static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3169 int crtc,
3170 enum amdgpu_interrupt_state state)
3171{
3172 u32 lb_interrupt_mask;
3173
3174 if (crtc >= adev->mode_info.num_crtc) {
3175 DRM_DEBUG("invalid crtc %d\n", crtc);
3176 return;
3177 }
3178
3179 switch (state) {
3180 case AMDGPU_IRQ_STATE_DISABLE:
3181 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3182 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3183 VBLANK_INTERRUPT_MASK, 0);
3184 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3185 break;
3186 case AMDGPU_IRQ_STATE_ENABLE:
3187 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3188 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3189 VBLANK_INTERRUPT_MASK, 1);
3190 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3191 break;
3192 default:
3193 break;
3194 }
3195}
3196
3197static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3198 int crtc,
3199 enum amdgpu_interrupt_state state)
3200{
3201 u32 lb_interrupt_mask;
3202
3203 if (crtc >= adev->mode_info.num_crtc) {
3204 DRM_DEBUG("invalid crtc %d\n", crtc);
3205 return;
3206 }
3207
3208 switch (state) {
3209 case AMDGPU_IRQ_STATE_DISABLE:
3210 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3211 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3212 VLINE_INTERRUPT_MASK, 0);
3213 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3214 break;
3215 case AMDGPU_IRQ_STATE_ENABLE:
3216 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3217 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3218 VLINE_INTERRUPT_MASK, 1);
3219 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3220 break;
3221 default:
3222 break;
3223 }
3224}
3225
3226static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3227 struct amdgpu_irq_src *source,
3228 unsigned hpd,
3229 enum amdgpu_interrupt_state state)
3230{
3231 u32 tmp;
3232
3233 if (hpd >= adev->mode_info.num_hpd) {
3234 DRM_DEBUG("invalid hdp %d\n", hpd);
3235 return 0;
3236 }
3237
3238 switch (state) {
3239 case AMDGPU_IRQ_STATE_DISABLE:
3240 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3241 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3242 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3243 break;
3244 case AMDGPU_IRQ_STATE_ENABLE:
3245 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3246 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3247 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3248 break;
3249 default:
3250 break;
3251 }
3252
3253 return 0;
3254}
3255
3256static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3257 struct amdgpu_irq_src *source,
3258 unsigned type,
3259 enum amdgpu_interrupt_state state)
3260{
3261 switch (type) {
3262 case AMDGPU_CRTC_IRQ_VBLANK1:
3263 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3264 break;
3265 case AMDGPU_CRTC_IRQ_VBLANK2:
3266 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3267 break;
3268 case AMDGPU_CRTC_IRQ_VBLANK3:
3269 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3270 break;
3271 case AMDGPU_CRTC_IRQ_VBLANK4:
3272 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3273 break;
3274 case AMDGPU_CRTC_IRQ_VBLANK5:
3275 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3276 break;
3277 case AMDGPU_CRTC_IRQ_VBLANK6:
3278 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3279 break;
3280 case AMDGPU_CRTC_IRQ_VLINE1:
3281 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3282 break;
3283 case AMDGPU_CRTC_IRQ_VLINE2:
3284 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3285 break;
3286 case AMDGPU_CRTC_IRQ_VLINE3:
3287 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3288 break;
3289 case AMDGPU_CRTC_IRQ_VLINE4:
3290 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3291 break;
3292 case AMDGPU_CRTC_IRQ_VLINE5:
3293 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3294 break;
3295 case AMDGPU_CRTC_IRQ_VLINE6:
3296 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3297 break;
3298 default:
3299 break;
3300 }
3301 return 0;
3302}
3303
3304static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3305 struct amdgpu_irq_src *src,
3306 unsigned type,
3307 enum amdgpu_interrupt_state state)
3308{
7dfac896
AD		 3309 u32 reg;
3310
3311 if (type >= adev->mode_info.num_crtc) {
3312 DRM_ERROR("invalid pageflip crtc %d\n", type);
3313 return -EINVAL;
aaa36a97
AD		 3314 }
3315
7dfac896 3316 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
aaa36a97 3317 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3318 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3319 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97 3320 else
7dfac896
AD		 3321 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3322 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97
AD		 3323
3324 return 0;
3325}
3326
3327static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3328 struct amdgpu_irq_src *source,
3329 struct amdgpu_iv_entry *entry)
3330{
aaa36a97
AD		 3331 unsigned long flags;
3332 unsigned crtc_id;
3333 struct amdgpu_crtc *amdgpu_crtc;
3334 struct amdgpu_flip_work *works;
3335
3336 crtc_id = (entry->src_id - 8) >> 1;
3337 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3338
7dfac896
AD		 3339 if (crtc_id >= adev->mode_info.num_crtc) {
3340 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3341 return -EINVAL;
aaa36a97
AD		 3342 }
3343
7dfac896
AD		 3344 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3345 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3346 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3347 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
aaa36a97
AD		 3348
3349 /* IRQ could occur when in initial stage */
3350 if(amdgpu_crtc == NULL)
3351 return 0;
3352
3353 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3354 works = amdgpu_crtc->pflip_works;
3355 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3356 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3357 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3358 amdgpu_crtc->pflip_status,
3359 AMDGPU_FLIP_SUBMITTED);
3360 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3361 return 0;
3362 }
3363
3364 /* page flip completed. clean up */
3365 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3366 amdgpu_crtc->pflip_works = NULL;
3367
3368 /* wakeup usersapce */
3369 if(works->event)
3370 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3371
3372 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3373
3374 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
87d58c11 3375 schedule_work(&works->unpin_work);
aaa36a97
AD		 3376
3377 return 0;
3378}
3379
3380static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3381 int hpd)
3382{
3383 u32 tmp;
3384
3385 if (hpd >= adev->mode_info.num_hpd) {
3386 DRM_DEBUG("invalid hdp %d\n", hpd);
3387 return;
3388 }
3389
3390 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3391 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3392 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3393}
3394
3395static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3396 int crtc)
3397{
3398 u32 tmp;
3399
15c3277f 3400 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
aaa36a97
AD		 3401 DRM_DEBUG("invalid crtc %d\n", crtc);
3402 return;
3403 }
3404
3405 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3406 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3407 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3408}
3409
3410static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3411 int crtc)
3412{
3413 u32 tmp;
3414
15c3277f 3415 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
aaa36a97
AD		 3416 DRM_DEBUG("invalid crtc %d\n", crtc);
3417 return;
3418 }
3419
3420 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3421 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3422 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3423}
3424
3425static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3426 struct amdgpu_irq_src *source,
3427 struct amdgpu_iv_entry *entry)
3428{
3429 unsigned crtc = entry->src_id - 1;
3430 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3431 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3432
3433 switch (entry->src_data) {
3434 case 0: /* vblank */
bd833144 3435 if (disp_int & interrupt_status_offsets[crtc].vblank)
aaa36a97 3436 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
bd833144
MK		 3437 else
3438 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3439
3440 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3441 drm_handle_vblank(adev->ddev, crtc);
aaa36a97 3442 }
bd833144
MK		 3443 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3444
aaa36a97
AD		 3445 break;
3446 case 1: /* vline */
bd833144 3447 if (disp_int & interrupt_status_offsets[crtc].vline)
aaa36a97 3448 dce_v11_0_crtc_vline_int_ack(adev, crtc);
bd833144
MK		 3449 else
3450 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3451
3452 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3453
aaa36a97
AD		 3454 break;
3455 default:
3456 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3457 break;
3458 }
3459
3460 return 0;
3461}
3462
3463static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3464 struct amdgpu_irq_src *source,
3465 struct amdgpu_iv_entry *entry)
3466{
3467 uint32_t disp_int, mask;
3468 unsigned hpd;
3469
3470 if (entry->src_data >= adev->mode_info.num_hpd) {
3471 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3472 return 0;
3473 }
3474
3475 hpd = entry->src_data;
3476 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3477 mask = interrupt_status_offsets[hpd].hpd;
3478
3479 if (disp_int & mask) {
3480 dce_v11_0_hpd_int_ack(adev, hpd);
3481 schedule_work(&adev->hotplug_work);
3482 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3483 }
3484
3485 return 0;
3486}
3487
5fc3aeeb 3488static int dce_v11_0_set_clockgating_state(void *handle,
3489 enum amd_clockgating_state state)
aaa36a97
AD		 3490{
3491 return 0;
3492}
3493
5fc3aeeb 3494static int dce_v11_0_set_powergating_state(void *handle,
3495 enum amd_powergating_state state)
aaa36a97
AD		 3496{
3497 return 0;
3498}
3499
5fc3aeeb 3500const struct amd_ip_funcs dce_v11_0_ip_funcs = {
aaa36a97
AD		 3501 .early_init = dce_v11_0_early_init,
3502 .late_init = NULL,
3503 .sw_init = dce_v11_0_sw_init,
3504 .sw_fini = dce_v11_0_sw_fini,
3505 .hw_init = dce_v11_0_hw_init,
3506 .hw_fini = dce_v11_0_hw_fini,
3507 .suspend = dce_v11_0_suspend,
3508 .resume = dce_v11_0_resume,
3509 .is_idle = dce_v11_0_is_idle,
3510 .wait_for_idle = dce_v11_0_wait_for_idle,
3511 .soft_reset = dce_v11_0_soft_reset,
3512 .print_status = dce_v11_0_print_status,
3513 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3514 .set_powergating_state = dce_v11_0_set_powergating_state,
3515};
3516
3517static void
3518dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3519 struct drm_display_mode *mode,
3520 struct drm_display_mode *adjusted_mode)
3521{
3522 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3523
3524 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3525
3526 /* need to call this here rather than in prepare() since we need some crtc info */
3527 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3528
3529 /* set scaler clears this on some chips */
3530 dce_v11_0_set_interleave(encoder->crtc, mode);
3531
3532 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3533 dce_v11_0_afmt_enable(encoder, true);
3534 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3535 }
3536}
3537
3538static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3539{
3540 struct amdgpu_device *adev = encoder->dev->dev_private;
3541 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3542 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3543
3544 if ((amdgpu_encoder->active_device &
3545 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3546 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3547 ENCODER_OBJECT_ID_NONE)) {
3548 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3549 if (dig) {
3550 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3551 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3552 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3553 }
3554 }
3555
3556 amdgpu_atombios_scratch_regs_lock(adev, true);
3557
3558 if (connector) {
3559 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3560
3561 /* select the clock/data port if it uses a router */
3562 if (amdgpu_connector->router.cd_valid)
3563 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3564
3565 /* turn eDP panel on for mode set */
3566 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3567 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3568 ATOM_TRANSMITTER_ACTION_POWER_ON);
3569 }
3570
3571 /* this is needed for the pll/ss setup to work correctly in some cases */
3572 amdgpu_atombios_encoder_set_crtc_source(encoder);
3573 /* set up the FMT blocks */
3574 dce_v11_0_program_fmt(encoder);
3575}
3576
3577static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3578{
3579 struct drm_device *dev = encoder->dev;
3580 struct amdgpu_device *adev = dev->dev_private;
3581
3582 /* need to call this here as we need the crtc set up */
3583 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3584 amdgpu_atombios_scratch_regs_lock(adev, false);
3585}
3586
3587static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3588{
3589 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3590 struct amdgpu_encoder_atom_dig *dig;
3591
3592 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3593
3594 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3595 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3596 dce_v11_0_afmt_enable(encoder, false);
3597 dig = amdgpu_encoder->enc_priv;
3598 dig->dig_encoder = -1;
3599 }
3600 amdgpu_encoder->active_device = 0;
3601}
3602
3603/* these are handled by the primary encoders */
3604static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3605{
3606
3607}
3608
3609static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3610{
3611
3612}
3613
3614static void
3615dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3616 struct drm_display_mode *mode,
3617 struct drm_display_mode *adjusted_mode)
3618{
3619
3620}
3621
3622static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3623{
3624
3625}
3626
3627static void
3628dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3629{
3630
3631}
3632
aaa36a97
AD		 3633static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3634 .dpms = dce_v11_0_ext_dpms,
aaa36a97
AD		 3635 .prepare = dce_v11_0_ext_prepare,
3636 .mode_set = dce_v11_0_ext_mode_set,
3637 .commit = dce_v11_0_ext_commit,
3638 .disable = dce_v11_0_ext_disable,
3639 /* no detect for TMDS/LVDS yet */
3640};
3641
3642static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3643 .dpms = amdgpu_atombios_encoder_dpms,
3644 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3645 .prepare = dce_v11_0_encoder_prepare,
3646 .mode_set = dce_v11_0_encoder_mode_set,
3647 .commit = dce_v11_0_encoder_commit,
3648 .disable = dce_v11_0_encoder_disable,
3649 .detect = amdgpu_atombios_encoder_dig_detect,
3650};
3651
3652static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3653 .dpms = amdgpu_atombios_encoder_dpms,
3654 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3655 .prepare = dce_v11_0_encoder_prepare,
3656 .mode_set = dce_v11_0_encoder_mode_set,
3657 .commit = dce_v11_0_encoder_commit,
3658 .detect = amdgpu_atombios_encoder_dac_detect,
3659};
3660
3661static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3662{
3663 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3664 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3665 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3666 kfree(amdgpu_encoder->enc_priv);
3667 drm_encoder_cleanup(encoder);
3668 kfree(amdgpu_encoder);
3669}
3670
3671static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3672 .destroy = dce_v11_0_encoder_destroy,
3673};
3674
3675static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3676 uint32_t encoder_enum,
3677 uint32_t supported_device,
3678 u16 caps)
3679{
3680 struct drm_device *dev = adev->ddev;
3681 struct drm_encoder *encoder;
3682 struct amdgpu_encoder *amdgpu_encoder;
3683
3684 /* see if we already added it */
3685 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3686 amdgpu_encoder = to_amdgpu_encoder(encoder);
3687 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3688 amdgpu_encoder->devices |= supported_device;
3689 return;
3690 }
3691
3692 }
3693
3694 /* add a new one */
3695 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3696 if (!amdgpu_encoder)
3697 return;
3698
3699 encoder = &amdgpu_encoder->base;
3700 switch (adev->mode_info.num_crtc) {
3701 case 1:
3702 encoder->possible_crtcs = 0x1;
3703 break;
3704 case 2:
3705 default:
3706 encoder->possible_crtcs = 0x3;
3707 break;
3708 case 4:
3709 encoder->possible_crtcs = 0xf;
3710 break;
3711 case 6:
3712 encoder->possible_crtcs = 0x3f;
3713 break;
3714 }
3715
3716 amdgpu_encoder->enc_priv = NULL;
3717
3718 amdgpu_encoder->encoder_enum = encoder_enum;
3719 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3720 amdgpu_encoder->devices = supported_device;
3721 amdgpu_encoder->rmx_type = RMX_OFF;
3722 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3723 amdgpu_encoder->is_ext_encoder = false;
3724 amdgpu_encoder->caps = caps;
3725
3726 switch (amdgpu_encoder->encoder_id) {
3727 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3728 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3729 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3730 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3731 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3732 break;
3733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3734 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3735 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3736 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3738 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3739 amdgpu_encoder->rmx_type = RMX_FULL;
3740 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3741 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3742 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3743 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3744 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3745 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3746 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3747 } else {
3748 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3749 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3750 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3751 }
3752 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3753 break;
3754 case ENCODER_OBJECT_ID_SI170B:
3755 case ENCODER_OBJECT_ID_CH7303:
3756 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3757 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3758 case ENCODER_OBJECT_ID_TITFP513:
3759 case ENCODER_OBJECT_ID_VT1623:
3760 case ENCODER_OBJECT_ID_HDMI_SI1930:
3761 case ENCODER_OBJECT_ID_TRAVIS:
3762 case ENCODER_OBJECT_ID_NUTMEG:
3763 /* these are handled by the primary encoders */
3764 amdgpu_encoder->is_ext_encoder = true;
3765 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3766 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3767 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3768 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3769 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3770 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3771 else
3772 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3773 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3774 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3775 break;
3776 }
3777}
3778
3779static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3780 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3781 .bandwidth_update = &dce_v11_0_bandwidth_update,
3782 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3783 .vblank_wait = &dce_v11_0_vblank_wait,
3784 .is_display_hung = &dce_v11_0_is_display_hung,
3785 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3786 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3787 .hpd_sense = &dce_v11_0_hpd_sense,
3788 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3789 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3790 .page_flip = &dce_v11_0_page_flip,
3791 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3792 .add_encoder = &dce_v11_0_encoder_add,
3793 .add_connector = &amdgpu_connector_add,
3794 .stop_mc_access = &dce_v11_0_stop_mc_access,
3795 .resume_mc_access = &dce_v11_0_resume_mc_access,
3796};
3797
3798static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3799{
3800 if (adev->mode_info.funcs == NULL)
3801 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3802}
3803
3804static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3805 .set = dce_v11_0_set_crtc_irq_state,
3806 .process = dce_v11_0_crtc_irq,
3807};
3808
3809static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3810 .set = dce_v11_0_set_pageflip_irq_state,
3811 .process = dce_v11_0_pageflip_irq,
3812};
3813
3814static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3815 .set = dce_v11_0_set_hpd_irq_state,
3816 .process = dce_v11_0_hpd_irq,
3817};
3818
3819static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3820{
3821 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3822 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3823
3824 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3825 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3826
3827 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3828 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3829}
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