[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfxhub_v1_0.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "gfxhub_v1_0.h"

#include "vega10/soc15ip.h"
#include "vega10/GC/gc_9_0_offset.h"
#include "vega10/GC/gc_9_0_sh_mask.h"
#include "vega10/GC/gc_9_0_default.h"
#include "vega10/vega10_enum.h"

#include "soc15_common.h"

u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
{
	return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
}

static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
{
	uint64_t value;

	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
	value = adev->gart.table_addr - adev->mc.vram_start
		+ adev->vm_manager.vram_base_offset;
	value &= 0x0000FFFFFFFFF000ULL;
	value |= 0x1; /*valid bit*/

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
	       lower_32_bits(value));

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
	       upper_32_bits(value));
}

static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
{
	gfxhub_v1_0_init_gart_pt_regs(adev);

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
		(u32)(adev->mc.gtt_start >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
		(u32)(adev->mc.gtt_start >> 44));

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
		(u32)(adev->mc.gtt_end >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));
}

static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
{
	uint64_t value;
	uint32_t tmp;

	/* Disable AGP. */
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);

	/* Program the system aperture low logical page number. */
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
		adev->mc.vram_start >> 18);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
		adev->mc.vram_end >> 18);

	/* Set default page address. */
	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
		+ adev->vm_manager.vram_base_offset;
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
	       (u32)(value >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
	       (u32)(value >> 44));

	/* Program "protection fault". */
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
	       (u32)(adev->dummy_page.addr >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
	       (u32)((u64)adev->dummy_page.addr >> 44));

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
}

static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
{
	uint32_t tmp;

	/* Setup TLB control */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
			    MTYPE, MTYPE_UC);/* XXX for emulation. */
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
}

static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
{
	uint32_t tmp;

	/* Setup L2 cache */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
	/* XXX for emulation, Refer to closed source code.*/
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
			    0);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);

	tmp = mmVM_L2_CNTL3_DEFAULT;
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);

	tmp = mmVM_L2_CNTL4_DEFAULT;
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
}

int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{
	u32 tmp;
	u32 i;

	if (amdgpu_sriov_vf(adev)) {
		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
		vbios post doesn't program them, for SRIOV driver need to program them */
		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
				adev->mc.vram_start >> 24);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
				adev->mc.vram_end >> 24);
	}

	/* GART Enable. */
	gfxhub_v1_0_init_gart_aperture_regs(adev);
	gfxhub_v1_0_init_system_aperture_regs(adev);
	gfxhub_v1_0_init_tlb_regs(adev);
	gfxhub_v1_0_init_cache_regs(adev);

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);

	/* Disable identity aperture.*/
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);

	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);

	for (i = 0; i <= 14; i++) {
		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
				    adev->vm_manager.num_level);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				PAGE_TABLE_BLOCK_SIZE,
				adev->vm_manager.block_size - 9);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
			lower_32_bits(adev->vm_manager.max_pfn - 1));
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
			upper_32_bits(adev->vm_manager.max_pfn - 1));
	}


	return 0;
}

void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
{
	u32 tmp;
	u32 i;

	/* Disable all tables */
	for (i = 0; i < 16; i++)
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);

	/* Setup TLB control */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				ENABLE_ADVANCED_DRIVER_MODEL,
				0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);

	/* Setup L2 cache */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
}

/**
 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 *
 * @adev: amdgpu_device pointer
 * @value: true redirects VM faults to the default page
 */
void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
					  bool value)
{
	u32 tmp;
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp,
			VM_L2_PROTECTION_FAULT_CNTL,
			TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
			value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
}

static int gfxhub_v1_0_early_init(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_late_init(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_sw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];

	hub->ctx0_ptb_addr_lo32 =
		SOC15_REG_OFFSET(GC, 0,
				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	hub->ctx0_ptb_addr_hi32 =
		SOC15_REG_OFFSET(GC, 0,
				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	hub->vm_inv_eng0_req =
		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
	hub->vm_inv_eng0_ack =
		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
	hub->vm_context0_cntl =
		SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
	hub->vm_l2_pro_fault_status =
		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
	hub->vm_l2_pro_fault_cntl =
		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

	return 0;
}

static int gfxhub_v1_0_sw_fini(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_hw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	unsigned i;

	for (i = 0 ; i < 18; ++i) {
		WREG32(SOC15_REG_OFFSET(GC, 0,
					mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
		       2 * i, 0xffffffff);
		WREG32(SOC15_REG_OFFSET(GC, 0,
					mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
		       2 * i, 0x1f);
	}

	return 0;
}

static int gfxhub_v1_0_hw_fini(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_suspend(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_resume(void *handle)
{
	return 0;
}

static bool gfxhub_v1_0_is_idle(void *handle)
{
	return true;
}

static int gfxhub_v1_0_wait_for_idle(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_soft_reset(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	return 0;
}

static int gfxhub_v1_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	return 0;
}

const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
	.name = "gfxhub_v1_0",
	.early_init = gfxhub_v1_0_early_init,
	.late_init = gfxhub_v1_0_late_init,
	.sw_init = gfxhub_v1_0_sw_init,
	.sw_fini = gfxhub_v1_0_sw_fini,
	.hw_init = gfxhub_v1_0_hw_init,
	.hw_fini = gfxhub_v1_0_hw_fini,
	.suspend = gfxhub_v1_0_suspend,
	.resume = gfxhub_v1_0_resume,
	.is_idle = gfxhub_v1_0_is_idle,
	.wait_for_idle = gfxhub_v1_0_wait_for_idle,
	.soft_reset = gfxhub_v1_0_soft_reset,
	.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
	.set_powergating_state = gfxhub_v1_0_set_powergating_state,
};

const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_GFXHUB,
	.major = 1,
	.minor = 0,
	.rev = 0,
	.funcs = &gfxhub_v1_0_ip_funcs,
};
Commit	Line	Data
e60f8db5 AX	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "gfxhub_v1_0.h"
	25
	26	#include "vega10/soc15ip.h"
	27	#include "vega10/GC/gc_9_0_offset.h"
	28	#include "vega10/GC/gc_9_0_sh_mask.h"
	29	#include "vega10/GC/gc_9_0_default.h"
	30	#include "vega10/vega10_enum.h"
	31
	32	#include "soc15_common.h"
	33
2d8e898e CZ	34	u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
	35	{
	36	return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
	37	}
	38
a51dca4f HR	39	static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
	40	{
	41	uint64_t value;
	42
	43	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
	44	value = adev->gart.table_addr - adev->mc.vram_start
	45	+ adev->vm_manager.vram_base_offset;
	46	value &= 0x0000FFFFFFFFF000ULL;
	47	value \|= 0x1; /valid bit/
	48
	49	WREG32(SOC15_REG_OFFSET(GC, 0,
	50	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
	51	lower_32_bits(value));
	52
	53	WREG32(SOC15_REG_OFFSET(GC, 0,
	54	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
	55	upper_32_bits(value));
	56	}
	57
9bbad6fd HR	58	static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
	59	{
	60	gfxhub_v1_0_init_gart_pt_regs(adev);
	61
	62	WREG32(SOC15_REG_OFFSET(GC, 0,
	63	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
	64	(u32)(adev->mc.gtt_start >> 12));
	65	WREG32(SOC15_REG_OFFSET(GC, 0,
	66	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
	67	(u32)(adev->mc.gtt_start >> 44));
	68
	69	WREG32(SOC15_REG_OFFSET(GC, 0,
	70	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
	71	(u32)(adev->mc.gtt_end >> 12));
	72	WREG32(SOC15_REG_OFFSET(GC, 0,
	73	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
	74	(u32)(adev->mc.gtt_end >> 44));
	75	}
	76
fc4b884b	77	static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
e60f8db5	78	{
fc4b884b HR	79	uint64_t value;
fc4b884b HR	80	uint32_t tmp;
e60f8db5	81
fc4b884b HR	82	/* Disable AGP. */
	83	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
	84	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
	85	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
a51dca4f	86
fc4b884b	87	/* Program the system aperture low logical page number. */
e60f8db5 AX	88	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
	89	adev->mc.vram_start >> 18);
	90	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
	91	adev->mc.vram_end >> 18);
	92
fc4b884b	93	/* Set default page address. */
e60f8db5 AX	94	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
	95	+ adev->vm_manager.vram_base_offset;
	96	WREG32(SOC15_REG_OFFSET(GC, 0,
	97	mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
fc4b884b	98	(u32)(value >> 12));
e60f8db5 AX	99	WREG32(SOC15_REG_OFFSET(GC, 0,
e60f8db5 AX	100	mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
fc4b884b HR	101	(u32)(value >> 44));
	102
	103	/* Program "protection fault". */
	104	WREG32(SOC15_REG_OFFSET(GC, 0,
	105	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
	106	(u32)(adev->dummy_page.addr >> 12));
	107	WREG32(SOC15_REG_OFFSET(GC, 0,
	108	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
	109	(u32)((u64)adev->dummy_page.addr >> 44));
	110
	111	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
	112	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
	113	ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
	114	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
	115	}
	116
34269839 HR	117	static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
	118	{
	119	uint32_t tmp;
	120
	121	/* Setup TLB control */
	122	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
	123
	124	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	125	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
	126	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
	127	ENABLE_ADVANCED_DRIVER_MODEL, 1);
	128	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
	129	SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
	130	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
	131	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
	132	MTYPE, MTYPE_UC);/* XXX for emulation. */
	133	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
	134
	135	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
	136	}
	137
41f6f311 HR	138	static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
	139	{
	140	uint32_t tmp;
	141
	142	/* Setup L2 cache */
	143	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	144	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
	145	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
	146	/* XXX for emulation, Refer to closed source code.*/
	147	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
	148	0);
	149	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
	150	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
	151	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
	152	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
	153
	154	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
	155	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	156	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	157	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
	158
	159	tmp = mmVM_L2_CNTL3_DEFAULT;
	160	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
	161
	162	tmp = mmVM_L2_CNTL4_DEFAULT;
	163	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
	164	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
	165	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
	166	}
	167
fc4b884b HR	168	int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
	169	{
	170	u32 tmp;
	171	u32 i;
e60f8db5	172
eeb2487d ML	173	if (amdgpu_sriov_vf(adev)) {
	174	/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
	175	vbios post doesn't program them, for SRIOV driver need to program them */
	176	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
	177	adev->mc.vram_start >> 24);
	178	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
	179	adev->mc.vram_end >> 24);
	180	}
	181
e60f8db5	182	/* GART Enable. */
fc4b884b HR	183	gfxhub_v1_0_init_gart_aperture_regs(adev);
fc4b884b HR	184	gfxhub_v1_0_init_system_aperture_regs(adev);
34269839	185	gfxhub_v1_0_init_tlb_regs(adev);
41f6f311	186	gfxhub_v1_0_init_cache_regs(adev);
e60f8db5	187
e60f8db5 AX	188	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
	189	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	190	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
	191	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
	192
	193	/* Disable identity aperture.*/
	194	WREG32(SOC15_REG_OFFSET(GC, 0,
	195	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
	196	WREG32(SOC15_REG_OFFSET(GC, 0,
	197	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
	198
	199	WREG32(SOC15_REG_OFFSET(GC, 0,
	200	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
	201	WREG32(SOC15_REG_OFFSET(GC, 0,
	202	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
	203
	204	WREG32(SOC15_REG_OFFSET(GC, 0,
	205	mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
	206	WREG32(SOC15_REG_OFFSET(GC, 0,
	207	mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
	208
	209	for (i = 0; i <= 14; i++) {
	210	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
	211	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
4fb1cf3a CZ	212	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
4fb1cf3a CZ	213	adev->vm_manager.num_level);
e60f8db5 AX	214	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	215	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	216	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	217	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	218	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	219	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	220	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	221	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	222	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	223	READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	224	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	225	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	226	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	227	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	228	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	229	PAGE_TABLE_BLOCK_SIZE,
36b32a68	230	adev->vm_manager.block_size - 9);
e60f8db5 AX	231	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
	232	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
	233	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
	234	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
22770e5a FK	235	lower_32_bits(adev->vm_manager.max_pfn - 1));
	236	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
	237	upper_32_bits(adev->vm_manager.max_pfn - 1));
e60f8db5 AX	238	}
	239
	240
	241	return 0;
	242	}
	243
	244	void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
	245	{
	246	u32 tmp;
	247	u32 i;
	248
	249	/* Disable all tables */
	250	for (i = 0; i < 16; i++)
	251	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);
	252
	253	/* Setup TLB control */
	254	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
	255	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	256	tmp = REG_SET_FIELD(tmp,
	257	MC_VM_MX_L1_TLB_CNTL,
	258	ENABLE_ADVANCED_DRIVER_MODEL,
	259	0);
	260	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
	261
	262	/* Setup L2 cache */
	263	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	264	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
	265	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
	266	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
	267	}
	268
	269	/**
	270	* gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
	271	*
	272	* @adev: amdgpu_device pointer
	273	* @value: true redirects VM faults to the default page
	274	*/
	275	void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
	276	bool value)
	277	{
	278	u32 tmp;
	279	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
	280	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	281	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	282	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	283	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	284	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	285	PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	286	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	287	PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	288	tmp = REG_SET_FIELD(tmp,
	289	VM_L2_PROTECTION_FAULT_CNTL,
	290	TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
	291	value);
	292	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	293	NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	294	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	295	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	296	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	297	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	298	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	299	READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	300	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	301	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
302	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
303	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
304	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
305	}
306
e60f8db5 AX	307	static int gfxhub_v1_0_early_init(void *handle)
	308	{
	309	return 0;
	310	}
	311
	312	static int gfxhub_v1_0_late_init(void *handle)
	313	{
	314	return 0;
	315	}
	316
	317	static int gfxhub_v1_0_sw_init(void *handle)
	318	{
	319	struct amdgpu_device adev = (struct amdgpu_device )handle;
	320	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
	321
	322	hub->ctx0_ptb_addr_lo32 =
	323	SOC15_REG_OFFSET(GC, 0,
	324	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	325	hub->ctx0_ptb_addr_hi32 =
	326	SOC15_REG_OFFSET(GC, 0,
	327	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	328	hub->vm_inv_eng0_req =
	329	SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
	330	hub->vm_inv_eng0_ack =
	331	SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
	332	hub->vm_context0_cntl =
	333	SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
	334	hub->vm_l2_pro_fault_status =
	335	SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
	336	hub->vm_l2_pro_fault_cntl =
	337	SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
	338
e60f8db5 AX	339	return 0;
	340	}
	341
	342	static int gfxhub_v1_0_sw_fini(void *handle)
	343	{
	344	return 0;
	345	}
	346
	347	static int gfxhub_v1_0_hw_init(void *handle)
	348	{
	349	struct amdgpu_device adev = (struct amdgpu_device )handle;
	350	unsigned i;
	351
	352	for (i = 0 ; i < 18; ++i) {
	353	WREG32(SOC15_REG_OFFSET(GC, 0,
	354	mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
	355	2 * i, 0xffffffff);
	356	WREG32(SOC15_REG_OFFSET(GC, 0,
	357	mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
	358	2 * i, 0x1f);
	359	}
	360
	361	return 0;
	362	}
	363
	364	static int gfxhub_v1_0_hw_fini(void *handle)
	365	{
	366	return 0;
	367	}
	368
	369	static int gfxhub_v1_0_suspend(void *handle)
	370	{
	371	return 0;
	372	}
	373
	374	static int gfxhub_v1_0_resume(void *handle)
	375	{
	376	return 0;
	377	}
	378
	379	static bool gfxhub_v1_0_is_idle(void *handle)
	380	{
	381	return true;
	382	}
	383
	384	static int gfxhub_v1_0_wait_for_idle(void *handle)
	385	{
	386	return 0;
	387	}
	388
	389	static int gfxhub_v1_0_soft_reset(void *handle)
	390	{
	391	return 0;
	392	}
	393
	394	static int gfxhub_v1_0_set_clockgating_state(void *handle,
	395	enum amd_clockgating_state state)
	396	{
	397	return 0;
	398	}
	399
	400	static int gfxhub_v1_0_set_powergating_state(void *handle,
	401	enum amd_powergating_state state)
	402	{
403	return 0;
404	}
405
406	const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
407	.name = "gfxhub_v1_0",
408	.early_init = gfxhub_v1_0_early_init,
409	.late_init = gfxhub_v1_0_late_init,
410	.sw_init = gfxhub_v1_0_sw_init,
411	.sw_fini = gfxhub_v1_0_sw_fini,
412	.hw_init = gfxhub_v1_0_hw_init,
413	.hw_fini = gfxhub_v1_0_hw_fini,
414	.suspend = gfxhub_v1_0_suspend,
415	.resume = gfxhub_v1_0_resume,
416	.is_idle = gfxhub_v1_0_is_idle,
417	.wait_for_idle = gfxhub_v1_0_wait_for_idle,
418	.soft_reset = gfxhub_v1_0_soft_reset,
419	.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
420	.set_powergating_state = gfxhub_v1_0_set_powergating_state,
421	};
422
423	const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
424	{
425	.type = AMD_IP_BLOCK_TYPE_GFXHUB,
426	.major = 1,
427	.minor = 0,
428	.rev = 0,
429	.funcs = &gfxhub_v1_0_ip_funcs,
430	};