[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfxhub_v1_0.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "gfxhub_v1_0.h"

#include "vega10/soc15ip.h"
#include "vega10/GC/gc_9_0_offset.h"
#include "vega10/GC/gc_9_0_sh_mask.h"
#include "vega10/GC/gc_9_0_default.h"
#include "vega10/vega10_enum.h"

#include "soc15_common.h"

u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
{
	return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
}

static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
{
	uint64_t value;

	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
	value = adev->gart.table_addr - adev->mc.vram_start
		+ adev->vm_manager.vram_base_offset;
	value &= 0x0000FFFFFFFFF000ULL;
	value |= 0x1; /*valid bit*/

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
	       lower_32_bits(value));

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
	       upper_32_bits(value));
}

static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
{
	gfxhub_v1_0_init_gart_pt_regs(adev);

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
		(u32)(adev->mc.gtt_start >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
		(u32)(adev->mc.gtt_start >> 44));

	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
		(u32)(adev->mc.gtt_end >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));
}

static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
{
	uint64_t value;
	uint32_t tmp;

	/* Disable AGP. */
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);

	/* Program the system aperture low logical page number. */
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
		adev->mc.vram_start >> 18);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
		adev->mc.vram_end >> 18);

	/* Set default page address. */
	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
		+ adev->vm_manager.vram_base_offset;
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
	       (u32)(value >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
	       (u32)(value >> 44));

	/* Program "protection fault". */
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
	       (u32)(adev->dummy_page.addr >> 12));
	WREG32(SOC15_REG_OFFSET(GC, 0,
				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
	       (u32)((u64)adev->dummy_page.addr >> 44));

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
}

int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{
	u32 tmp;
	u32 i;

	if (amdgpu_sriov_vf(adev)) {
		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
		vbios post doesn't program them, for SRIOV driver need to program them */
		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
				adev->mc.vram_start >> 24);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
				adev->mc.vram_end >> 24);
	}

	/* GART Enable. */
	gfxhub_v1_0_init_gart_aperture_regs(adev);
	gfxhub_v1_0_init_system_aperture_regs(adev);

	/* Setup TLB control */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				SYSTEM_ACCESS_MODE,
				3);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				ENABLE_ADVANCED_DRIVER_MODEL,
				1);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				SYSTEM_APERTURE_UNMAPPED_ACCESS,
				0);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				ECO_BITS,
				0);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				MTYPE,
				MTYPE_UC);/* XXX for emulation. */
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				ATC_EN,
				1);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);

	/* Setup L2 cache */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
	tmp = REG_SET_FIELD(tmp,
				VM_L2_CNTL,
				ENABLE_L2_FRAGMENT_PROCESSING,
				0);
	tmp = REG_SET_FIELD(tmp,
				VM_L2_CNTL,
				L2_PDE0_CACHE_TAG_GENERATION_MODE,
				0);/* XXX for emulation, Refer to closed source code.*/
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
	tmp = REG_SET_FIELD(tmp,
				VM_L2_CNTL,
				CONTEXT1_IDENTITY_ACCESS_MODE,
				1);
	tmp = REG_SET_FIELD(tmp,
				VM_L2_CNTL,
				IDENTITY_MODE_FRAGMENT_SIZE,
				0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);

	tmp = mmVM_L2_CNTL3_DEFAULT;
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));
	tmp = REG_SET_FIELD(tmp,
			    VM_L2_CNTL4,
			    VMC_TAP_PDE_REQUEST_PHYSICAL,
			    0);
	tmp = REG_SET_FIELD(tmp,
			    VM_L2_CNTL4,
			    VMC_TAP_PTE_REQUEST_PHYSICAL,
			    0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);

	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);

	/* Disable identity aperture.*/
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);

	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);

	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
	WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);

	for (i = 0; i <= 14; i++) {
		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
				    adev->vm_manager.num_level);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
				PAGE_TABLE_BLOCK_SIZE,
				adev->vm_manager.block_size - 9);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
			lower_32_bits(adev->vm_manager.max_pfn - 1));
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
			upper_32_bits(adev->vm_manager.max_pfn - 1));
	}


	return 0;
}

void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
{
	u32 tmp;
	u32 i;

	/* Disable all tables */
	for (i = 0; i < 16; i++)
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);

	/* Setup TLB control */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	tmp = REG_SET_FIELD(tmp,
				MC_VM_MX_L1_TLB_CNTL,
				ENABLE_ADVANCED_DRIVER_MODEL,
				0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);

	/* Setup L2 cache */
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
}

/**
 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 *
 * @adev: amdgpu_device pointer
 * @value: true redirects VM faults to the default page
 */
void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
					  bool value)
{
	u32 tmp;
	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp,
			VM_L2_PROTECTION_FAULT_CNTL,
			TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
			value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
}

static int gfxhub_v1_0_early_init(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_late_init(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_sw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];

	hub->ctx0_ptb_addr_lo32 =
		SOC15_REG_OFFSET(GC, 0,
				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	hub->ctx0_ptb_addr_hi32 =
		SOC15_REG_OFFSET(GC, 0,
				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	hub->vm_inv_eng0_req =
		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
	hub->vm_inv_eng0_ack =
		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
	hub->vm_context0_cntl =
		SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
	hub->vm_l2_pro_fault_status =
		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
	hub->vm_l2_pro_fault_cntl =
		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

	return 0;
}

static int gfxhub_v1_0_sw_fini(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_hw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	unsigned i;

	for (i = 0 ; i < 18; ++i) {
		WREG32(SOC15_REG_OFFSET(GC, 0,
					mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
		       2 * i, 0xffffffff);
		WREG32(SOC15_REG_OFFSET(GC, 0,
					mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
		       2 * i, 0x1f);
	}

	return 0;
}

static int gfxhub_v1_0_hw_fini(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_suspend(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_resume(void *handle)
{
	return 0;
}

static bool gfxhub_v1_0_is_idle(void *handle)
{
	return true;
}

static int gfxhub_v1_0_wait_for_idle(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_soft_reset(void *handle)
{
	return 0;
}

static int gfxhub_v1_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	return 0;
}

static int gfxhub_v1_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	return 0;
}

const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
	.name = "gfxhub_v1_0",
	.early_init = gfxhub_v1_0_early_init,
	.late_init = gfxhub_v1_0_late_init,
	.sw_init = gfxhub_v1_0_sw_init,
	.sw_fini = gfxhub_v1_0_sw_fini,
	.hw_init = gfxhub_v1_0_hw_init,
	.hw_fini = gfxhub_v1_0_hw_fini,
	.suspend = gfxhub_v1_0_suspend,
	.resume = gfxhub_v1_0_resume,
	.is_idle = gfxhub_v1_0_is_idle,
	.wait_for_idle = gfxhub_v1_0_wait_for_idle,
	.soft_reset = gfxhub_v1_0_soft_reset,
	.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
	.set_powergating_state = gfxhub_v1_0_set_powergating_state,
};

const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_GFXHUB,
	.major = 1,
	.minor = 0,
	.rev = 0,
	.funcs = &gfxhub_v1_0_ip_funcs,
};
Commit	Line	Data
e60f8db5 AX	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "gfxhub_v1_0.h"
	25
	26	#include "vega10/soc15ip.h"
	27	#include "vega10/GC/gc_9_0_offset.h"
	28	#include "vega10/GC/gc_9_0_sh_mask.h"
	29	#include "vega10/GC/gc_9_0_default.h"
	30	#include "vega10/vega10_enum.h"
	31
	32	#include "soc15_common.h"
	33
2d8e898e CZ	34	u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
	35	{
	36	return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
	37	}
	38
a51dca4f HR	39	static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
	40	{
	41	uint64_t value;
	42
	43	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
	44	value = adev->gart.table_addr - adev->mc.vram_start
	45	+ adev->vm_manager.vram_base_offset;
	46	value &= 0x0000FFFFFFFFF000ULL;
	47	value \|= 0x1; /valid bit/
	48
	49	WREG32(SOC15_REG_OFFSET(GC, 0,
	50	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
	51	lower_32_bits(value));
	52
	53	WREG32(SOC15_REG_OFFSET(GC, 0,
	54	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
	55	upper_32_bits(value));
	56	}
	57
9bbad6fd HR	58	static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
	59	{
	60	gfxhub_v1_0_init_gart_pt_regs(adev);
	61
	62	WREG32(SOC15_REG_OFFSET(GC, 0,
	63	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
	64	(u32)(adev->mc.gtt_start >> 12));
	65	WREG32(SOC15_REG_OFFSET(GC, 0,
	66	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
	67	(u32)(adev->mc.gtt_start >> 44));
	68
	69	WREG32(SOC15_REG_OFFSET(GC, 0,
	70	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
	71	(u32)(adev->mc.gtt_end >> 12));
	72	WREG32(SOC15_REG_OFFSET(GC, 0,
	73	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
	74	(u32)(adev->mc.gtt_end >> 44));
	75	}
	76
fc4b884b	77	static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
e60f8db5	78	{
fc4b884b HR	79	uint64_t value;
fc4b884b HR	80	uint32_t tmp;
e60f8db5	81
fc4b884b HR	82	/* Disable AGP. */
	83	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
	84	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
	85	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
a51dca4f	86
fc4b884b	87	/* Program the system aperture low logical page number. */
e60f8db5 AX	88	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
	89	adev->mc.vram_start >> 18);
	90	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
	91	adev->mc.vram_end >> 18);
	92
fc4b884b	93	/* Set default page address. */
e60f8db5 AX	94	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
	95	+ adev->vm_manager.vram_base_offset;
	96	WREG32(SOC15_REG_OFFSET(GC, 0,
	97	mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
fc4b884b	98	(u32)(value >> 12));
e60f8db5 AX	99	WREG32(SOC15_REG_OFFSET(GC, 0,
e60f8db5 AX	100	mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
fc4b884b HR	101	(u32)(value >> 44));
	102
	103	/* Program "protection fault". */
	104	WREG32(SOC15_REG_OFFSET(GC, 0,
	105	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
	106	(u32)(adev->dummy_page.addr >> 12));
	107	WREG32(SOC15_REG_OFFSET(GC, 0,
	108	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
	109	(u32)((u64)adev->dummy_page.addr >> 44));
	110
	111	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
	112	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
	113	ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
	114	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
	115	}
	116
	117	int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
	118	{
	119	u32 tmp;
	120	u32 i;
e60f8db5	121
eeb2487d ML	122	if (amdgpu_sriov_vf(adev)) {
	123	/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
	124	vbios post doesn't program them, for SRIOV driver need to program them */
	125	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
	126	adev->mc.vram_start >> 24);
	127	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
	128	adev->mc.vram_end >> 24);
	129	}
	130
e60f8db5	131	/* GART Enable. */
fc4b884b HR	132	gfxhub_v1_0_init_gart_aperture_regs(adev);
fc4b884b HR	133	gfxhub_v1_0_init_system_aperture_regs(adev);
e60f8db5 AX	134
	135	/* Setup TLB control */
	136	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
	137	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
	138	tmp = REG_SET_FIELD(tmp,
	139	MC_VM_MX_L1_TLB_CNTL,
	140	SYSTEM_ACCESS_MODE,
	141	3);
	142	tmp = REG_SET_FIELD(tmp,
	143	MC_VM_MX_L1_TLB_CNTL,
	144	ENABLE_ADVANCED_DRIVER_MODEL,
	145	1);
	146	tmp = REG_SET_FIELD(tmp,
	147	MC_VM_MX_L1_TLB_CNTL,
	148	SYSTEM_APERTURE_UNMAPPED_ACCESS,
	149	0);
	150	tmp = REG_SET_FIELD(tmp,
	151	MC_VM_MX_L1_TLB_CNTL,
	152	ECO_BITS,
	153	0);
	154	tmp = REG_SET_FIELD(tmp,
	155	MC_VM_MX_L1_TLB_CNTL,
	156	MTYPE,
	157	MTYPE_UC);/* XXX for emulation. */
	158	tmp = REG_SET_FIELD(tmp,
	159	MC_VM_MX_L1_TLB_CNTL,
	160	ATC_EN,
	161	1);
	162	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
	163
	164	/* Setup L2 cache */
	165	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	166	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
	167	tmp = REG_SET_FIELD(tmp,
	168	VM_L2_CNTL,
	169	ENABLE_L2_FRAGMENT_PROCESSING,
	170	0);
	171	tmp = REG_SET_FIELD(tmp,
	172	VM_L2_CNTL,
	173	L2_PDE0_CACHE_TAG_GENERATION_MODE,
	174	0);/* XXX for emulation, Refer to closed source code.*/
	175	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
	176	tmp = REG_SET_FIELD(tmp,
	177	VM_L2_CNTL,
	178	CONTEXT1_IDENTITY_ACCESS_MODE,
	179	1);
	180	tmp = REG_SET_FIELD(tmp,
	181	VM_L2_CNTL,
	182	IDENTITY_MODE_FRAGMENT_SIZE,
	183	0);
	184	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
	185
	186	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
	187	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
	188	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
	189	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
	190
	191	tmp = mmVM_L2_CNTL3_DEFAULT;
	192	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
	193
	194	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));
	195	tmp = REG_SET_FIELD(tmp,
	196	VM_L2_CNTL4,
	197	VMC_TAP_PDE_REQUEST_PHYSICAL,
198	0);
199	tmp = REG_SET_FIELD(tmp,
200	VM_L2_CNTL4,
201	VMC_TAP_PTE_REQUEST_PHYSICAL,
202	0);
203	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
204
e60f8db5 AX	205	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
	206	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
	207	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
	208	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
	209
	210	/* Disable identity aperture.*/
	211	WREG32(SOC15_REG_OFFSET(GC, 0,
	212	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
	213	WREG32(SOC15_REG_OFFSET(GC, 0,
	214	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
	215
	216	WREG32(SOC15_REG_OFFSET(GC, 0,
	217	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
	218	WREG32(SOC15_REG_OFFSET(GC, 0,
	219	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
	220
	221	WREG32(SOC15_REG_OFFSET(GC, 0,
	222	mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
	223	WREG32(SOC15_REG_OFFSET(GC, 0,
	224	mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
	225
	226	for (i = 0; i <= 14; i++) {
	227	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
	228	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
4fb1cf3a CZ	229	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
4fb1cf3a CZ	230	adev->vm_manager.num_level);
e60f8db5 AX	231	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	232	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	233	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	234	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	235	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	236	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	237	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	238	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	239	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	240	READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	241	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	242	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	243	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	244	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
	245	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
	246	PAGE_TABLE_BLOCK_SIZE,
36b32a68	247	adev->vm_manager.block_size - 9);
e60f8db5 AX	248	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
	249	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
	250	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
	251	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
22770e5a FK	252	lower_32_bits(adev->vm_manager.max_pfn - 1));
	253	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
	254	upper_32_bits(adev->vm_manager.max_pfn - 1));
e60f8db5 AX	255	}
	256
	257
	258	return 0;
	259	}
	260
	261	void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
	262	{
	263	u32 tmp;
	264	u32 i;
	265
	266	/* Disable all tables */
	267	for (i = 0; i < 16; i++)
	268	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);
	269
	270	/* Setup TLB control */
	271	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
	272	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
	273	tmp = REG_SET_FIELD(tmp,
	274	MC_VM_MX_L1_TLB_CNTL,
	275	ENABLE_ADVANCED_DRIVER_MODEL,
	276	0);
	277	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
	278
	279	/* Setup L2 cache */
	280	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
	281	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
	282	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
	283	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
	284	}
	285
	286	/**
	287	* gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
	288	*
	289	* @adev: amdgpu_device pointer
	290	* @value: true redirects VM faults to the default page
	291	*/
	292	void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
	293	bool value)
	294	{
	295	u32 tmp;
	296	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
	297	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	298	RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	299	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	300	PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	301	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	302	PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	303	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	304	PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	305	tmp = REG_SET_FIELD(tmp,
	306	VM_L2_PROTECTION_FAULT_CNTL,
	307	TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
	308	value);
	309	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	310	NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	311	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	312	DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	313	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	314	VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	315	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	316	READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
	317	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
	318	WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
319	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
320	EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
321	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
322	}
323
e60f8db5 AX	324	static int gfxhub_v1_0_early_init(void *handle)
	325	{
	326	return 0;
	327	}
	328
	329	static int gfxhub_v1_0_late_init(void *handle)
	330	{
	331	return 0;
	332	}
	333
	334	static int gfxhub_v1_0_sw_init(void *handle)
	335	{
	336	struct amdgpu_device adev = (struct amdgpu_device )handle;
	337	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
	338
	339	hub->ctx0_ptb_addr_lo32 =
	340	SOC15_REG_OFFSET(GC, 0,
	341	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
	342	hub->ctx0_ptb_addr_hi32 =
	343	SOC15_REG_OFFSET(GC, 0,
	344	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
	345	hub->vm_inv_eng0_req =
	346	SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
	347	hub->vm_inv_eng0_ack =
	348	SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
	349	hub->vm_context0_cntl =
	350	SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
	351	hub->vm_l2_pro_fault_status =
	352	SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
	353	hub->vm_l2_pro_fault_cntl =
	354	SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
	355
e60f8db5 AX	356	return 0;
	357	}
	358
	359	static int gfxhub_v1_0_sw_fini(void *handle)
	360	{
	361	return 0;
	362	}
	363
	364	static int gfxhub_v1_0_hw_init(void *handle)
	365	{
	366	struct amdgpu_device adev = (struct amdgpu_device )handle;
	367	unsigned i;
	368
	369	for (i = 0 ; i < 18; ++i) {
	370	WREG32(SOC15_REG_OFFSET(GC, 0,
	371	mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
	372	2 * i, 0xffffffff);
	373	WREG32(SOC15_REG_OFFSET(GC, 0,
	374	mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
	375	2 * i, 0x1f);
	376	}
	377
	378	return 0;
	379	}
	380
	381	static int gfxhub_v1_0_hw_fini(void *handle)
	382	{
	383	return 0;
	384	}
	385
	386	static int gfxhub_v1_0_suspend(void *handle)
	387	{
	388	return 0;
	389	}
	390
	391	static int gfxhub_v1_0_resume(void *handle)
	392	{
	393	return 0;
	394	}
	395
	396	static bool gfxhub_v1_0_is_idle(void *handle)
	397	{
	398	return true;
	399	}
	400
	401	static int gfxhub_v1_0_wait_for_idle(void *handle)
	402	{
	403	return 0;
	404	}
	405
	406	static int gfxhub_v1_0_soft_reset(void *handle)
	407	{
	408	return 0;
	409	}
	410
	411	static int gfxhub_v1_0_set_clockgating_state(void *handle,
	412	enum amd_clockgating_state state)
	413	{
	414	return 0;
	415	}
	416
	417	static int gfxhub_v1_0_set_powergating_state(void *handle,
	418	enum amd_powergating_state state)
	419	{
420	return 0;
421	}
422
423	const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
424	.name = "gfxhub_v1_0",
425	.early_init = gfxhub_v1_0_early_init,
426	.late_init = gfxhub_v1_0_late_init,
427	.sw_init = gfxhub_v1_0_sw_init,
428	.sw_fini = gfxhub_v1_0_sw_fini,
429	.hw_init = gfxhub_v1_0_hw_init,
430	.hw_fini = gfxhub_v1_0_hw_fini,
431	.suspend = gfxhub_v1_0_suspend,
432	.resume = gfxhub_v1_0_resume,
433	.is_idle = gfxhub_v1_0_is_idle,
434	.wait_for_idle = gfxhub_v1_0_wait_for_idle,
435	.soft_reset = gfxhub_v1_0_soft_reset,
436	.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
437	.set_powergating_state = gfxhub_v1_0_set_powergating_state,
438	};
439
440	const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
441	{
442	.type = AMD_IP_BLOCK_TYPE_GFXHUB,
443	.major = 1,
444	.minor = 0,
445	.rev = 0,
446	.funcs = &gfxhub_v1_0_ip_funcs,
447	};