[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / ast / ast_dp501.c

// SPDX-License-Identifier: GPL-2.0

#include <linux/firmware.h>
#include <drm/drmP.h>
#include "ast_drv.h"
MODULE_FIRMWARE("ast_dp501_fw.bin");

static int ast_load_dp501_microcode(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;

	return request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev);
}

static void send_ack(struct ast_private *ast)
{
	u8 sendack;
	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
	sendack |= 0x80;
	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
}

static void send_nack(struct ast_private *ast)
{
	u8 sendack;
	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
	sendack &= ~0x80;
	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
}

static bool wait_ack(struct ast_private *ast)
{
	u8 waitack;
	u32 retry = 0;
	do {
		waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
		waitack &= 0x80;
		udelay(100);
	} while ((!waitack) && (retry++ < 1000));

	if (retry < 1000)
		return true;
	else
		return false;
}

static bool wait_nack(struct ast_private *ast)
{
	u8 waitack;
	u32 retry = 0;
	do {
		waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
		waitack &= 0x80;
		udelay(100);
	} while ((waitack) && (retry++ < 1000));

	if (retry < 1000)
		return true;
	else
		return false;
}

static void set_cmd_trigger(struct ast_private *ast)
{
	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
}

static void clear_cmd_trigger(struct ast_private *ast)
{
	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
}

#if 0
static bool wait_fw_ready(struct ast_private *ast)
{
	u8 waitready;
	u32 retry = 0;
	do {
		waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
		waitready &= 0x40;
		udelay(100);
	} while ((!waitready) && (retry++ < 1000));

	if (retry < 1000)
		return true;
	else
		return false;
}
#endif

static bool ast_write_cmd(struct drm_device *dev, u8 data)
{
	struct ast_private *ast = dev->dev_private;
	int retry = 0;
	if (wait_nack(ast)) {
		send_nack(ast);
		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
		send_ack(ast);
		set_cmd_trigger(ast);
		do {
			if (wait_ack(ast)) {
				clear_cmd_trigger(ast);
				send_nack(ast);
				return true;
			}
		} while (retry++ < 100);
	}
	clear_cmd_trigger(ast);
	send_nack(ast);
	return false;
}

static bool ast_write_data(struct drm_device *dev, u8 data)
{
	struct ast_private *ast = dev->dev_private;

	if (wait_nack(ast)) {
		send_nack(ast);
		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
		send_ack(ast);
		if (wait_ack(ast)) {
			send_nack(ast);
			return true;
		}
	}
	send_nack(ast);
	return false;
}

#if 0
static bool ast_read_data(struct drm_device *dev, u8 *data)
{
	struct ast_private *ast = dev->dev_private;
	u8 tmp;

	*data = 0;

	if (wait_ack(ast) == false)
		return false;
	tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
	*data = tmp;
	if (wait_nack(ast) == false) {
		send_nack(ast);
		return false;
	}
	send_nack(ast);
	return true;
}

static void clear_cmd(struct ast_private *ast)
{
	send_nack(ast);
	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
}
#endif

void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
{
	ast_write_cmd(dev, 0x40);
	ast_write_data(dev, mode);

	msleep(10);
}

static u32 get_fw_base(struct ast_private *ast)
{
	return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
}

bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
{
	struct ast_private *ast = dev->dev_private;
	u32 i, data;
	u32 boot_address;

	data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
	if (data) {
		boot_address = get_fw_base(ast);
		for (i = 0; i < size; i += 4)
			*(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
		return true;
	}
	return false;
}

static bool ast_launch_m68k(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;
	u32 i, data, len = 0;
	u32 boot_address;
	u8 *fw_addr = NULL;
	u8 jreg;

	data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
	if (!data) {

		if (ast->dp501_fw_addr) {
			fw_addr = ast->dp501_fw_addr;
			len = 32*1024;
		} else {
			if (!ast->dp501_fw &&
			    ast_load_dp501_microcode(dev) < 0)
				return false;

			fw_addr = (u8 *)ast->dp501_fw->data;
			len = ast->dp501_fw->size;
		}
		/* Get BootAddress */
		ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
		data = ast_mindwm(ast, 0x1e6e0004);
		switch (data & 0x03) {
		case 0:
			boot_address = 0x44000000;
			break;
		default:
		case 1:
			boot_address = 0x48000000;
			break;
		case 2:
			boot_address = 0x50000000;
			break;
		case 3:
			boot_address = 0x60000000;
			break;
		}
		boot_address -= 0x200000; /* -2MB */

		/* copy image to buffer */
		for (i = 0; i < len; i += 4) {
			data = *(u32 *)(fw_addr + i);
			ast_moutdwm(ast, boot_address + i, data);
		}

		/* Init SCU */
		ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);

		/* Launch FW */
		ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
		ast_moutdwm(ast, 0x1e6e2100, 1);

		/* Update Scratch */
		data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff;		/* D[11:9] = 100b: UEFI handling */
		data |= 0x800;
		ast_moutdwm(ast, 0x1e6e2040, data);

		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
		jreg |= 0x02;
		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
	}
	return true;
}

u8 ast_get_dp501_max_clk(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;
	u32 boot_address, offset, data;
	u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;

	boot_address = get_fw_base(ast);

	/* validate FW version */
	offset = 0xf000;
	data = ast_mindwm(ast, boot_address + offset);
	if ((data & 0xf0) != 0x10) /* version: 1x */
		return maxclk;

	/* Read Link Capability */
	offset  = 0xf014;
	*(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
	if (linkcap[2] == 0) {
		linkrate = linkcap[0];
		linklanes = linkcap[1];
		data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
		if (data > 0xff)
			data = 0xff;
		maxclk = (u8)data;
	}
	return maxclk;
}

bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
{
	struct ast_private *ast = dev->dev_private;
	u32 i, boot_address, offset, data;

	boot_address = get_fw_base(ast);

	/* validate FW version */
	offset = 0xf000;
	data = ast_mindwm(ast, boot_address + offset);
	if ((data & 0xf0) != 0x10)
		return false;

	/* validate PnP Monitor */
	offset = 0xf010;
	data = ast_mindwm(ast, boot_address + offset);
	if (!(data & 0x01))
		return false;

	/* Read EDID */
	offset = 0xf020;
	for (i = 0; i < 128; i += 4) {
		data = ast_mindwm(ast, boot_address + offset + i);
		*(u32 *)(ediddata + i) = data;
	}

	return true;
}

static bool ast_init_dvo(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;
	u8 jreg;
	u32 data;
	ast_write32(ast, 0xf004, 0x1e6e0000);
	ast_write32(ast, 0xf000, 0x1);
	ast_write32(ast, 0x12000, 0x1688a8a8);

	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
	if (!(jreg & 0x80)) {
		/* Init SCU DVO Settings */
		data = ast_read32(ast, 0x12008);
		/* delay phase */
		data &= 0xfffff8ff;
		data |= 0x00000500;
		ast_write32(ast, 0x12008, data);

		if (ast->chip == AST2300) {
			data = ast_read32(ast, 0x12084);
			/* multi-pins for DVO single-edge */
			data |= 0xfffe0000;
			ast_write32(ast, 0x12084, data);

			data = ast_read32(ast, 0x12088);
			/* multi-pins for DVO single-edge */
			data |= 0x000fffff;
			ast_write32(ast, 0x12088, data);

			data = ast_read32(ast, 0x12090);
			/* multi-pins for DVO single-edge */
			data &= 0xffffffcf;
			data |= 0x00000020;
			ast_write32(ast, 0x12090, data);
		} else { /* AST2400 */
			data = ast_read32(ast, 0x12088);
			/* multi-pins for DVO single-edge */
			data |= 0x30000000;
			ast_write32(ast, 0x12088, data);

			data = ast_read32(ast, 0x1208c);
			/* multi-pins for DVO single-edge */
			data |= 0x000000cf;
			ast_write32(ast, 0x1208c, data);

			data = ast_read32(ast, 0x120a4);
			/* multi-pins for DVO single-edge */
			data |= 0xffff0000;
			ast_write32(ast, 0x120a4, data);

			data = ast_read32(ast, 0x120a8);
			/* multi-pins for DVO single-edge */
			data |= 0x0000000f;
			ast_write32(ast, 0x120a8, data);

			data = ast_read32(ast, 0x12094);
			/* multi-pins for DVO single-edge */
			data |= 0x00000002;
			ast_write32(ast, 0x12094, data);
		}
	}

	/* Force to DVO */
	data = ast_read32(ast, 0x1202c);
	data &= 0xfffbffff;
	ast_write32(ast, 0x1202c, data);

	/* Init VGA DVO Settings */
	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
	return true;
}


static void ast_init_analog(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;
	u32 data;

	/*
	 * Set DAC source to VGA mode in SCU2C via the P2A
	 * bridge. First configure the P2U to target the SCU
	 * in case it isn't at this stage.
	 */
	ast_write32(ast, 0xf004, 0x1e6e0000);
	ast_write32(ast, 0xf000, 0x1);

	/* Then unlock the SCU with the magic password */
	ast_write32(ast, 0x12000, 0x1688a8a8);
	ast_write32(ast, 0x12000, 0x1688a8a8);
	ast_write32(ast, 0x12000, 0x1688a8a8);

	/* Finally, clear bits [17:16] of SCU2c */
	data = ast_read32(ast, 0x1202c);
	data &= 0xfffcffff;
	ast_write32(ast, 0, data);

	/* Disable DVO */
	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
}

void ast_init_3rdtx(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;
	u8 jreg;

	if (ast->chip == AST2300 || ast->chip == AST2400) {
		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
		switch (jreg & 0x0e) {
		case 0x04:
			ast_init_dvo(dev);
			break;
		case 0x08:
			ast_launch_m68k(dev);
			break;
		case 0x0c:
			ast_init_dvo(dev);
			break;
		default:
			if (ast->tx_chip_type == AST_TX_SIL164)
				ast_init_dvo(dev);
			else
				ast_init_analog(dev);
		}
	}
}

void ast_release_firmware(struct drm_device *dev)
{
	struct ast_private *ast = dev->dev_private;

	release_firmware(ast->dp501_fw);
	ast->dp501_fw = NULL;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
83c6620b DA	2
	3	#include <linux/firmware.h>
	4	#include <drm/drmP.h>
	5	#include "ast_drv.h"
	6	MODULE_FIRMWARE("ast_dp501_fw.bin");
	7
12f8030e	8	static int ast_load_dp501_microcode(struct drm_device *dev)
83c6620b DA	9	{
83c6620b DA	10	struct ast_private *ast = dev->dev_private;
83c6620b	11
12f8030e	12	return request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev);
83c6620b DA	13	}
	14
	15	static void send_ack(struct ast_private *ast)
	16	{
	17	u8 sendack;
	18	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
	19	sendack \|= 0x80;
	20	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
	21	}
	22
	23	static void send_nack(struct ast_private *ast)
	24	{
	25	u8 sendack;
	26	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
	27	sendack &= ~0x80;
	28	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
	29	}
	30
	31	static bool wait_ack(struct ast_private *ast)
	32	{
	33	u8 waitack;
	34	u32 retry = 0;
	35	do {
	36	waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
	37	waitack &= 0x80;
	38	udelay(100);
	39	} while ((!waitack) && (retry++ < 1000));
	40
	41	if (retry < 1000)
	42	return true;
	43	else
	44	return false;
	45	}
	46
	47	static bool wait_nack(struct ast_private *ast)
	48	{
	49	u8 waitack;
	50	u32 retry = 0;
	51	do {
	52	waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
	53	waitack &= 0x80;
	54	udelay(100);
	55	} while ((waitack) && (retry++ < 1000));
	56
	57	if (retry < 1000)
	58	return true;
	59	else
	60	return false;
	61	}
	62
	63	static void set_cmd_trigger(struct ast_private *ast)
	64	{
	65	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
	66	}
	67
	68	static void clear_cmd_trigger(struct ast_private *ast)
	69	{
	70	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
	71	}
	72
	73	#if 0
	74	static bool wait_fw_ready(struct ast_private *ast)
	75	{
	76	u8 waitready;
77	u32 retry = 0;
78	do {
79	waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
80	waitready &= 0x40;
81	udelay(100);
82	} while ((!waitready) && (retry++ < 1000));
83
84	if (retry < 1000)
85	return true;
86	else
87	return false;
88	}
89	#endif
90
91	static bool ast_write_cmd(struct drm_device *dev, u8 data)
92	{
93	struct ast_private *ast = dev->dev_private;
94	int retry = 0;
95	if (wait_nack(ast)) {
96	send_nack(ast);
97	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
98	send_ack(ast);
99	set_cmd_trigger(ast);
100	do {
101	if (wait_ack(ast)) {
102	clear_cmd_trigger(ast);
103	send_nack(ast);
104	return true;
105	}
106	} while (retry++ < 100);
107	}
108	clear_cmd_trigger(ast);
109	send_nack(ast);
110	return false;
111	}
112
113	static bool ast_write_data(struct drm_device *dev, u8 data)
114	{
115	struct ast_private *ast = dev->dev_private;
116
117	if (wait_nack(ast)) {
118	send_nack(ast);
119	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
120	send_ack(ast);
121	if (wait_ack(ast)) {
122	send_nack(ast);
123	return true;
124	}
125	}
126	send_nack(ast);
127	return false;
128	}
129
130	#if 0
131	static bool ast_read_data(struct drm_device dev, u8 data)
132	{
133	struct ast_private *ast = dev->dev_private;
134	u8 tmp;
135
136	*data = 0;
137
138	if (wait_ack(ast) == false)
139	return false;
140	tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
141	*data = tmp;
142	if (wait_nack(ast) == false) {
143	send_nack(ast);
144	return false;
145	}
146	send_nack(ast);
147	return true;
148	}
149
150	static void clear_cmd(struct ast_private *ast)
151	{
152	send_nack(ast);
153	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
154	}
155	#endif
156
157	void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
158	{
159	ast_write_cmd(dev, 0x40);
160	ast_write_data(dev, mode);
161
162	msleep(10);
163	}
164
165	static u32 get_fw_base(struct ast_private *ast)
166	{
167	return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
168	}
169
170	bool ast_backup_fw(struct drm_device dev, u8 addr, u32 size)
171	{
172	struct ast_private *ast = dev->dev_private;
173	u32 i, data;
174	u32 boot_address;
175
176	data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
177	if (data) {
178	boot_address = get_fw_base(ast);
179	for (i = 0; i < size; i += 4)
180	(u32 )(addr + i) = ast_mindwm(ast, boot_address + i);
181	return true;
182	}
183	return false;
184	}
185
12f8030e	186	static bool ast_launch_m68k(struct drm_device *dev)
83c6620b DA	187	{
	188	struct ast_private *ast = dev->dev_private;
	189	u32 i, data, len = 0;
	190	u32 boot_address;
	191	u8 *fw_addr = NULL;
	192	u8 jreg;
	193
	194	data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
	195	if (!data) {
	196
	197	if (ast->dp501_fw_addr) {
	198	fw_addr = ast->dp501_fw_addr;
	199	len = 32*1024;
12f8030e EE	200	} else {
	201	if (!ast->dp501_fw &&
	202	ast_load_dp501_microcode(dev) < 0)
	203	return false;
	204
83c6620b DA	205	fw_addr = (u8 *)ast->dp501_fw->data;
	206	len = ast->dp501_fw->size;
	207	}
	208	/* Get BootAddress */
	209	ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
	210	data = ast_mindwm(ast, 0x1e6e0004);
	211	switch (data & 0x03) {
	212	case 0:
	213	boot_address = 0x44000000;
	214	break;
	215	default:
	216	case 1:
	217	boot_address = 0x48000000;
	218	break;
	219	case 2:
	220	boot_address = 0x50000000;
	221	break;
	222	case 3:
	223	boot_address = 0x60000000;
	224	break;
	225	}
	226	boot_address -= 0x200000; /* -2MB */
	227
	228	/* copy image to buffer */
	229	for (i = 0; i < len; i += 4) {
	230	data = (u32 )(fw_addr + i);
	231	ast_moutdwm(ast, boot_address + i, data);
	232	}
	233
	234	/* Init SCU */
	235	ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
	236
	237	/* Launch FW */
	238	ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
	239	ast_moutdwm(ast, 0x1e6e2100, 1);
	240
	241	/* Update Scratch */
	242	data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
	243	data \|= 0x800;
	244	ast_moutdwm(ast, 0x1e6e2040, data);
	245
	246	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
	247	jreg \|= 0x02;
	248	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
	249	}
	250	return true;
	251	}
	252
	253	u8 ast_get_dp501_max_clk(struct drm_device *dev)
	254	{
	255	struct ast_private *ast = dev->dev_private;
	256	u32 boot_address, offset, data;
	257	u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
	258
	259	boot_address = get_fw_base(ast);
	260
	261	/* validate FW version */
	262	offset = 0xf000;
	263	data = ast_mindwm(ast, boot_address + offset);
	264	if ((data & 0xf0) != 0x10) /* version: 1x */
	265	return maxclk;
	266
	267	/* Read Link Capability */
	268	offset = 0xf014;
269	(u32 )linkcap = ast_mindwm(ast, boot_address + offset);
270	if (linkcap[2] == 0) {
271	linkrate = linkcap[0];
272	linklanes = linkcap[1];
273	data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
274	if (data > 0xff)
275	data = 0xff;
276	maxclk = (u8)data;
277	}
278	return maxclk;
279	}
280
281	bool ast_dp501_read_edid(struct drm_device dev, u8 ediddata)
282	{
283	struct ast_private *ast = dev->dev_private;
284	u32 i, boot_address, offset, data;
285
286	boot_address = get_fw_base(ast);
287
288	/* validate FW version */
289	offset = 0xf000;
290	data = ast_mindwm(ast, boot_address + offset);
291	if ((data & 0xf0) != 0x10)
292	return false;
293
294	/* validate PnP Monitor */
295	offset = 0xf010;
296	data = ast_mindwm(ast, boot_address + offset);
297	if (!(data & 0x01))
298	return false;
299
300	/* Read EDID */
301	offset = 0xf020;
302	for (i = 0; i < 128; i += 4) {
303	data = ast_mindwm(ast, boot_address + offset + i);
304	(u32 )(ediddata + i) = data;
305	}
306
307	return true;
308	}
309
310	static bool ast_init_dvo(struct drm_device *dev)
311	{
312	struct ast_private *ast = dev->dev_private;
313	u8 jreg;
314	u32 data;
315	ast_write32(ast, 0xf004, 0x1e6e0000);
316	ast_write32(ast, 0xf000, 0x1);
317	ast_write32(ast, 0x12000, 0x1688a8a8);
318
319	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
320	if (!(jreg & 0x80)) {
321	/* Init SCU DVO Settings */
322	data = ast_read32(ast, 0x12008);
323	/* delay phase */
324	data &= 0xfffff8ff;
325	data \|= 0x00000500;
326	ast_write32(ast, 0x12008, data);
327
328	if (ast->chip == AST2300) {
329	data = ast_read32(ast, 0x12084);
330	/* multi-pins for DVO single-edge */
331	data \|= 0xfffe0000;
332	ast_write32(ast, 0x12084, data);
333
334	data = ast_read32(ast, 0x12088);
335	/* multi-pins for DVO single-edge */
336	data \|= 0x000fffff;
337	ast_write32(ast, 0x12088, data);
338
339	data = ast_read32(ast, 0x12090);
340	/* multi-pins for DVO single-edge */
341	data &= 0xffffffcf;
342	data \|= 0x00000020;
343	ast_write32(ast, 0x12090, data);
344	} else { /* AST2400 */
345	data = ast_read32(ast, 0x12088);
346	/* multi-pins for DVO single-edge */
347	data \|= 0x30000000;
348	ast_write32(ast, 0x12088, data);
349
350	data = ast_read32(ast, 0x1208c);
351	/* multi-pins for DVO single-edge */
352	data \|= 0x000000cf;
353	ast_write32(ast, 0x1208c, data);
354
355	data = ast_read32(ast, 0x120a4);
356	/* multi-pins for DVO single-edge */
357	data \|= 0xffff0000;
358	ast_write32(ast, 0x120a4, data);
359
360	data = ast_read32(ast, 0x120a8);
361	/* multi-pins for DVO single-edge */
362	data \|= 0x0000000f;
363	ast_write32(ast, 0x120a8, data);
364
365	data = ast_read32(ast, 0x12094);
366	/* multi-pins for DVO single-edge */
367	data \|= 0x00000002;
368	ast_write32(ast, 0x12094, data);
369	}
370	}
371
372	/* Force to DVO */
373	data = ast_read32(ast, 0x1202c);
374	data &= 0xfffbffff;
375	ast_write32(ast, 0x1202c, data);
376
377	/* Init VGA DVO Settings */
378	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
379	return true;
380	}
381
37b9b81f BH	382
	383	static void ast_init_analog(struct drm_device *dev)
	384	{
	385	struct ast_private *ast = dev->dev_private;
	386	u32 data;
	387
	388	/*
	389	* Set DAC source to VGA mode in SCU2C via the P2A
	390	* bridge. First configure the P2U to target the SCU
	391	* in case it isn't at this stage.
	392	*/
	393	ast_write32(ast, 0xf004, 0x1e6e0000);
	394	ast_write32(ast, 0xf000, 0x1);
	395
	396	/* Then unlock the SCU with the magic password */
	397	ast_write32(ast, 0x12000, 0x1688a8a8);
	398	ast_write32(ast, 0x12000, 0x1688a8a8);
	399	ast_write32(ast, 0x12000, 0x1688a8a8);
	400
	401	/* Finally, clear bits [17:16] of SCU2c */
	402	data = ast_read32(ast, 0x1202c);
	403	data &= 0xfffcffff;
	404	ast_write32(ast, 0, data);
	405
	406	/* Disable DVO */
	407	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
	408	}
	409
83c6620b DA	410	void ast_init_3rdtx(struct drm_device *dev)
	411	{
	412	struct ast_private *ast = dev->dev_private;
	413	u8 jreg;
37b9b81f	414
83c6620b DA	415	if (ast->chip == AST2300 \|\| ast->chip == AST2400) {
	416	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
	417	switch (jreg & 0x0e) {
	418	case 0x04:
	419	ast_init_dvo(dev);
	420	break;
	421	case 0x08:
	422	ast_launch_m68k(dev);
	423	break;
	424	case 0x0c:
	425	ast_init_dvo(dev);
	426	break;
	427	default:
	428	if (ast->tx_chip_type == AST_TX_SIL164)
	429	ast_init_dvo(dev);
37b9b81f BH	430	else
37b9b81f BH	431	ast_init_analog(dev);
83c6620b DA	432	}
	433	}
	434	}
12f8030e EE	435
	436	void ast_release_firmware(struct drm_device *dev)
	437	{
	438	struct ast_private *ast = dev->dev_private;
	439
	440	release_firmware(ast->dp501_fw);
	441	ast->dp501_fw = NULL;
	442	}