]> git.proxmox.com Git - mirror_ubuntu-disco-kernel.git/blame - drivers/gpu/drm/drm_edid.c
gpu: Add export.h as required to drivers/gpu files.
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA
1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
f453ba04 32#include <linux/i2c.h>
2d1a8a48 33#include <linux/export.h>
f453ba04
DA
34#include "drmP.h"
35#include "drm_edid.h"
38fcbb67 36#include "drm_edid_modes.h"
f453ba04 37
13931579
AJ
38#define version_greater(edid, maj, min) \
39 (((edid)->version > (maj)) || \
40 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 41
d1ff6409
AJ
42#define EDID_EST_TIMINGS 16
43#define EDID_STD_TIMINGS 8
44#define EDID_DETAILED_TIMINGS 4
f453ba04
DA
45
46/*
47 * EDID blocks out in the wild have a variety of bugs, try to collect
48 * them here (note that userspace may work around broken monitors first,
49 * but fixes should make their way here so that the kernel "just works"
50 * on as many displays as possible).
51 */
52
53/* First detailed mode wrong, use largest 60Hz mode */
54#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
55/* Reported 135MHz pixel clock is too high, needs adjustment */
56#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
57/* Prefer the largest mode at 75 Hz */
58#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
59/* Detail timing is in cm not mm */
60#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
61/* Detailed timing descriptors have bogus size values, so just take the
62 * maximum size and use that.
63 */
64#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
65/* Monitor forgot to set the first detailed is preferred bit. */
66#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
67/* use +hsync +vsync for detailed mode */
68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
3c537889 69
13931579
AJ
70struct detailed_mode_closure {
71 struct drm_connector *connector;
72 struct edid *edid;
73 bool preferred;
74 u32 quirks;
75 int modes;
76};
f453ba04 77
5c61259e
ZY
78#define LEVEL_DMT 0
79#define LEVEL_GTF 1
7a374350
AJ
80#define LEVEL_GTF2 2
81#define LEVEL_CVT 3
5c61259e 82
f453ba04
DA
83static struct edid_quirk {
84 char *vendor;
85 int product_id;
86 u32 quirks;
87} edid_quirk_list[] = {
88 /* Acer AL1706 */
89 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
90 /* Acer F51 */
91 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
92 /* Unknown Acer */
93 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
94
95 /* Belinea 10 15 55 */
96 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
97 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
98
99 /* Envision Peripherals, Inc. EN-7100e */
100 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ
101 /* Envision EN2028 */
102 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA
103
104 /* Funai Electronics PM36B */
105 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
106 EDID_QUIRK_DETAILED_IN_CM },
107
108 /* LG Philips LCD LP154W01-A5 */
109 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
110 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
111
112 /* Philips 107p5 CRT */
113 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
114
115 /* Proview AY765C */
116 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
117
118 /* Samsung SyncMaster 205BW. Note: irony */
119 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
120 /* Samsung SyncMaster 22[5-6]BW */
121 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
122 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
123};
124
61e57a8d 125/*** DDC fetch and block validation ***/
f453ba04 126
083ae056
AJ
127static const u8 edid_header[] = {
128 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
129};
f453ba04 130
051963d4
TR
131 /*
132 * Sanity check the header of the base EDID block. Return 8 if the header
133 * is perfect, down to 0 if it's totally wrong.
134 */
135int drm_edid_header_is_valid(const u8 *raw_edid)
136{
137 int i, score = 0;
138
139 for (i = 0; i < sizeof(edid_header); i++)
140 if (raw_edid[i] == edid_header[i])
141 score++;
142
143 return score;
144}
145EXPORT_SYMBOL(drm_edid_header_is_valid);
146
147
61e57a8d
AJ
148/*
149 * Sanity check the EDID block (base or extension). Return 0 if the block
150 * doesn't check out, or 1 if it's valid.
f453ba04 151 */
61e57a8d
AJ
152static bool
153drm_edid_block_valid(u8 *raw_edid)
f453ba04 154{
61e57a8d 155 int i;
f453ba04 156 u8 csum = 0;
61e57a8d 157 struct edid *edid = (struct edid *)raw_edid;
f453ba04 158
61e57a8d 159 if (raw_edid[0] == 0x00) {
051963d4 160 int score = drm_edid_header_is_valid(raw_edid);
61e57a8d
AJ
161 if (score == 8) ;
162 else if (score >= 6) {
163 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
164 memcpy(raw_edid, edid_header, sizeof(edid_header));
165 } else {
166 goto bad;
167 }
168 }
f453ba04
DA
169
170 for (i = 0; i < EDID_LENGTH; i++)
171 csum += raw_edid[i];
172 if (csum) {
173 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
4a638b4e
AJ
174
175 /* allow CEA to slide through, switches mangle this */
176 if (raw_edid[0] != 0x02)
177 goto bad;
f453ba04
DA
178 }
179
61e57a8d
AJ
180 /* per-block-type checks */
181 switch (raw_edid[0]) {
182 case 0: /* base */
183 if (edid->version != 1) {
184 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
185 goto bad;
186 }
862b89c0 187
61e57a8d
AJ
188 if (edid->revision > 4)
189 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
190 break;
862b89c0 191
61e57a8d
AJ
192 default:
193 break;
194 }
47ee4ccf 195
f453ba04
DA
196 return 1;
197
198bad:
199 if (raw_edid) {
f49dadb8 200 printk(KERN_ERR "Raw EDID:\n");
0aff47f2
TV
201 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
202 raw_edid, EDID_LENGTH, false);
f453ba04
DA
203 }
204 return 0;
205}
61e57a8d
AJ
206
207/**
208 * drm_edid_is_valid - sanity check EDID data
209 * @edid: EDID data
210 *
211 * Sanity-check an entire EDID record (including extensions)
212 */
213bool drm_edid_is_valid(struct edid *edid)
214{
215 int i;
216 u8 *raw = (u8 *)edid;
217
218 if (!edid)
219 return false;
220
221 for (i = 0; i <= edid->extensions; i++)
222 if (!drm_edid_block_valid(raw + i * EDID_LENGTH))
223 return false;
224
225 return true;
226}
3c537889 227EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 228
61e57a8d
AJ
229#define DDC_ADDR 0x50
230#define DDC_SEGMENT_ADDR 0x30
231/**
232 * Get EDID information via I2C.
233 *
234 * \param adapter : i2c device adaptor
235 * \param buf : EDID data buffer to be filled
236 * \param len : EDID data buffer length
237 * \return 0 on success or -1 on failure.
238 *
239 * Try to fetch EDID information by calling i2c driver function.
240 */
241static int
242drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
243 int block, int len)
244{
245 unsigned char start = block * EDID_LENGTH;
4819d2e4
CW
246 int ret, retries = 5;
247
248 /* The core i2c driver will automatically retry the transfer if the
249 * adapter reports EAGAIN. However, we find that bit-banging transfers
250 * are susceptible to errors under a heavily loaded machine and
251 * generate spurious NAKs and timeouts. Retrying the transfer
252 * of the individual block a few times seems to overcome this.
253 */
254 do {
255 struct i2c_msg msgs[] = {
256 {
257 .addr = DDC_ADDR,
258 .flags = 0,
259 .len = 1,
260 .buf = &start,
261 }, {
262 .addr = DDC_ADDR,
263 .flags = I2C_M_RD,
264 .len = len,
265 .buf = buf,
266 }
267 };
268 ret = i2c_transfer(adapter, msgs, 2);
269 } while (ret != 2 && --retries);
270
271 return ret == 2 ? 0 : -1;
61e57a8d
AJ
272}
273
4a9a8b71
DA
274static bool drm_edid_is_zero(u8 *in_edid, int length)
275{
276 int i;
277 u32 *raw_edid = (u32 *)in_edid;
278
279 for (i = 0; i < length / 4; i++)
280 if (*(raw_edid + i) != 0)
281 return false;
282 return true;
283}
284
61e57a8d
AJ
285static u8 *
286drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
287{
0ea75e23 288 int i, j = 0, valid_extensions = 0;
61e57a8d
AJ
289 u8 *block, *new;
290
291 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
292 return NULL;
293
294 /* base block fetch */
295 for (i = 0; i < 4; i++) {
296 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
297 goto out;
298 if (drm_edid_block_valid(block))
299 break;
4a9a8b71
DA
300 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
301 connector->null_edid_counter++;
302 goto carp;
303 }
61e57a8d
AJ
304 }
305 if (i == 4)
306 goto carp;
307
308 /* if there's no extensions, we're done */
309 if (block[0x7e] == 0)
310 return block;
311
312 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
313 if (!new)
314 goto out;
315 block = new;
316
317 for (j = 1; j <= block[0x7e]; j++) {
318 for (i = 0; i < 4; i++) {
0ea75e23
ST
319 if (drm_do_probe_ddc_edid(adapter,
320 block + (valid_extensions + 1) * EDID_LENGTH,
321 j, EDID_LENGTH))
61e57a8d 322 goto out;
0ea75e23
ST
323 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH)) {
324 valid_extensions++;
61e57a8d 325 break;
0ea75e23 326 }
61e57a8d
AJ
327 }
328 if (i == 4)
0ea75e23
ST
329 dev_warn(connector->dev->dev,
330 "%s: Ignoring invalid EDID block %d.\n",
331 drm_get_connector_name(connector), j);
332 }
333
334 if (valid_extensions != block[0x7e]) {
335 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
336 block[0x7e] = valid_extensions;
337 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
338 if (!new)
339 goto out;
340 block = new;
61e57a8d
AJ
341 }
342
343 return block;
344
345carp:
dcdb1674 346 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
61e57a8d
AJ
347 drm_get_connector_name(connector), j);
348
349out:
350 kfree(block);
351 return NULL;
352}
353
354/**
355 * Probe DDC presence.
356 *
357 * \param adapter : i2c device adaptor
358 * \return 1 on success
359 */
360static bool
361drm_probe_ddc(struct i2c_adapter *adapter)
362{
363 unsigned char out;
364
365 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
366}
367
368/**
369 * drm_get_edid - get EDID data, if available
370 * @connector: connector we're probing
371 * @adapter: i2c adapter to use for DDC
372 *
373 * Poke the given i2c channel to grab EDID data if possible. If found,
374 * attach it to the connector.
375 *
376 * Return edid data or NULL if we couldn't find any.
377 */
378struct edid *drm_get_edid(struct drm_connector *connector,
379 struct i2c_adapter *adapter)
380{
381 struct edid *edid = NULL;
382
383 if (drm_probe_ddc(adapter))
384 edid = (struct edid *)drm_do_get_edid(connector, adapter);
385
386 connector->display_info.raw_edid = (char *)edid;
387
388 return edid;
389
390}
391EXPORT_SYMBOL(drm_get_edid);
392
393/*** EDID parsing ***/
394
f453ba04
DA
395/**
396 * edid_vendor - match a string against EDID's obfuscated vendor field
397 * @edid: EDID to match
398 * @vendor: vendor string
399 *
400 * Returns true if @vendor is in @edid, false otherwise
401 */
402static bool edid_vendor(struct edid *edid, char *vendor)
403{
404 char edid_vendor[3];
405
406 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
407 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
408 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 409 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA
410
411 return !strncmp(edid_vendor, vendor, 3);
412}
413
414/**
415 * edid_get_quirks - return quirk flags for a given EDID
416 * @edid: EDID to process
417 *
418 * This tells subsequent routines what fixes they need to apply.
419 */
420static u32 edid_get_quirks(struct edid *edid)
421{
422 struct edid_quirk *quirk;
423 int i;
424
425 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
426 quirk = &edid_quirk_list[i];
427
428 if (edid_vendor(edid, quirk->vendor) &&
429 (EDID_PRODUCT_ID(edid) == quirk->product_id))
430 return quirk->quirks;
431 }
432
433 return 0;
434}
435
436#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
437#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
438
f453ba04
DA
439/**
440 * edid_fixup_preferred - set preferred modes based on quirk list
441 * @connector: has mode list to fix up
442 * @quirks: quirks list
443 *
444 * Walk the mode list for @connector, clearing the preferred status
445 * on existing modes and setting it anew for the right mode ala @quirks.
446 */
447static void edid_fixup_preferred(struct drm_connector *connector,
448 u32 quirks)
449{
450 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 451 int target_refresh = 0;
f453ba04
DA
452
453 if (list_empty(&connector->probed_modes))
454 return;
455
456 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
457 target_refresh = 60;
458 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
459 target_refresh = 75;
460
461 preferred_mode = list_first_entry(&connector->probed_modes,
462 struct drm_display_mode, head);
463
464 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
465 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
466
467 if (cur_mode == preferred_mode)
468 continue;
469
470 /* Largest mode is preferred */
471 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
472 preferred_mode = cur_mode;
473
474 /* At a given size, try to get closest to target refresh */
475 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
476 MODE_REFRESH_DIFF(cur_mode, target_refresh) <
477 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) {
478 preferred_mode = cur_mode;
479 }
480 }
481
482 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
483}
484
1d42bbc8
DA
485struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
486 int hsize, int vsize, int fresh)
559ee21d 487{
b1f559ec 488 struct drm_display_mode *mode = NULL;
07a5e632 489 int i;
559ee21d 490
07a5e632 491 for (i = 0; i < drm_num_dmt_modes; i++) {
b1f559ec 492 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
559ee21d
ZY
493 if (hsize == ptr->hdisplay &&
494 vsize == ptr->vdisplay &&
495 fresh == drm_mode_vrefresh(ptr)) {
496 /* get the expected default mode */
497 mode = drm_mode_duplicate(dev, ptr);
498 break;
499 }
500 }
501 return mode;
502}
1d42bbc8 503EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 504
d1ff6409
AJ
505typedef void detailed_cb(struct detailed_timing *timing, void *closure);
506
4d76a221
AJ
507static void
508cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
509{
510 int i, n = 0;
511 u8 rev = ext[0x01], d = ext[0x02];
512 u8 *det_base = ext + d;
513
514 switch (rev) {
515 case 0:
516 /* can't happen */
517 return;
518 case 1:
519 /* have to infer how many blocks we have, check pixel clock */
520 for (i = 0; i < 6; i++)
521 if (det_base[18*i] || det_base[18*i+1])
522 n++;
523 break;
524 default:
525 /* explicit count */
526 n = min(ext[0x03] & 0x0f, 6);
527 break;
528 }
529
530 for (i = 0; i < n; i++)
531 cb((struct detailed_timing *)(det_base + 18 * i), closure);
532}
533
cbba98f8
AJ
534static void
535vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
536{
537 unsigned int i, n = min((int)ext[0x02], 6);
538 u8 *det_base = ext + 5;
539
540 if (ext[0x01] != 1)
541 return; /* unknown version */
542
543 for (i = 0; i < n; i++)
544 cb((struct detailed_timing *)(det_base + 18 * i), closure);
545}
546
d1ff6409
AJ
547static void
548drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
549{
550 int i;
551 struct edid *edid = (struct edid *)raw_edid;
552
553 if (edid == NULL)
554 return;
555
556 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
557 cb(&(edid->detailed_timings[i]), closure);
558
4d76a221
AJ
559 for (i = 1; i <= raw_edid[0x7e]; i++) {
560 u8 *ext = raw_edid + (i * EDID_LENGTH);
561 switch (*ext) {
562 case CEA_EXT:
563 cea_for_each_detailed_block(ext, cb, closure);
564 break;
cbba98f8
AJ
565 case VTB_EXT:
566 vtb_for_each_detailed_block(ext, cb, closure);
567 break;
4d76a221
AJ
568 default:
569 break;
570 }
571 }
d1ff6409
AJ
572}
573
574static void
575is_rb(struct detailed_timing *t, void *data)
576{
577 u8 *r = (u8 *)t;
578 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
579 if (r[15] & 0x10)
580 *(bool *)data = true;
581}
582
583/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
584static bool
585drm_monitor_supports_rb(struct edid *edid)
586{
587 if (edid->revision >= 4) {
588 bool ret;
589 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
590 return ret;
591 }
592
593 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
594}
595
7a374350
AJ
596static void
597find_gtf2(struct detailed_timing *t, void *data)
598{
599 u8 *r = (u8 *)t;
600 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
601 *(u8 **)data = r;
602}
603
604/* Secondary GTF curve kicks in above some break frequency */
605static int
606drm_gtf2_hbreak(struct edid *edid)
607{
608 u8 *r = NULL;
609 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
610 return r ? (r[12] * 2) : 0;
611}
612
613static int
614drm_gtf2_2c(struct edid *edid)
615{
616 u8 *r = NULL;
617 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
618 return r ? r[13] : 0;
619}
620
621static int
622drm_gtf2_m(struct edid *edid)
623{
624 u8 *r = NULL;
625 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
626 return r ? (r[15] << 8) + r[14] : 0;
627}
628
629static int
630drm_gtf2_k(struct edid *edid)
631{
632 u8 *r = NULL;
633 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
634 return r ? r[16] : 0;
635}
636
637static int
638drm_gtf2_2j(struct edid *edid)
639{
640 u8 *r = NULL;
641 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
642 return r ? r[17] : 0;
643}
644
645/**
646 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
647 * @edid: EDID block to scan
648 */
649static int standard_timing_level(struct edid *edid)
650{
651 if (edid->revision >= 2) {
652 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
653 return LEVEL_CVT;
654 if (drm_gtf2_hbreak(edid))
655 return LEVEL_GTF2;
656 return LEVEL_GTF;
657 }
658 return LEVEL_DMT;
659}
660
23425cae
AJ
661/*
662 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
663 * monitors fill with ascii space (0x20) instead.
664 */
665static int
666bad_std_timing(u8 a, u8 b)
667{
668 return (a == 0x00 && b == 0x00) ||
669 (a == 0x01 && b == 0x01) ||
670 (a == 0x20 && b == 0x20);
671}
672
f453ba04
DA
673/**
674 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
675 * @t: standard timing params
5c61259e 676 * @timing_level: standard timing level
f453ba04
DA
677 *
678 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 679 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 680 */
7ca6adb3 681static struct drm_display_mode *
7a374350
AJ
682drm_mode_std(struct drm_connector *connector, struct edid *edid,
683 struct std_timing *t, int revision)
f453ba04 684{
7ca6adb3
AJ
685 struct drm_device *dev = connector->dev;
686 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY
687 int hsize, vsize;
688 int vrefresh_rate;
0454beab
MD
689 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
690 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY
691 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
692 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 693 int timing_level = standard_timing_level(edid);
5c61259e 694
23425cae
AJ
695 if (bad_std_timing(t->hsize, t->vfreq_aspect))
696 return NULL;
697
5c61259e
ZY
698 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
699 hsize = t->hsize * 8 + 248;
700 /* vrefresh_rate = vfreq + 60 */
701 vrefresh_rate = vfreq + 60;
702 /* the vdisplay is calculated based on the aspect ratio */
f066a17d
AJ
703 if (aspect_ratio == 0) {
704 if (revision < 3)
705 vsize = hsize;
706 else
707 vsize = (hsize * 10) / 16;
708 } else if (aspect_ratio == 1)
f453ba04 709 vsize = (hsize * 3) / 4;
0454beab 710 else if (aspect_ratio == 2)
f453ba04
DA
711 vsize = (hsize * 4) / 5;
712 else
713 vsize = (hsize * 9) / 16;
a0910c8e
AJ
714
715 /* HDTV hack, part 1 */
716 if (vrefresh_rate == 60 &&
717 ((hsize == 1360 && vsize == 765) ||
718 (hsize == 1368 && vsize == 769))) {
719 hsize = 1366;
720 vsize = 768;
721 }
722
7ca6adb3
AJ
723 /*
724 * If this connector already has a mode for this size and refresh
725 * rate (because it came from detailed or CVT info), use that
726 * instead. This way we don't have to guess at interlace or
727 * reduced blanking.
728 */
522032da 729 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ
730 if (m->hdisplay == hsize && m->vdisplay == vsize &&
731 drm_mode_vrefresh(m) == vrefresh_rate)
732 return NULL;
733
a0910c8e
AJ
734 /* HDTV hack, part 2 */
735 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
736 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 737 false);
559ee21d 738 mode->hdisplay = 1366;
a4967de6
AJ
739 mode->hsync_start = mode->hsync_start - 1;
740 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY
741 return mode;
742 }
a0910c8e 743
559ee21d 744 /* check whether it can be found in default mode table */
1d42bbc8 745 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate);
559ee21d
ZY
746 if (mode)
747 return mode;
748
5c61259e
ZY
749 switch (timing_level) {
750 case LEVEL_DMT:
5c61259e
ZY
751 break;
752 case LEVEL_GTF:
753 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
754 break;
7a374350
AJ
755 case LEVEL_GTF2:
756 /*
757 * This is potentially wrong if there's ever a monitor with
758 * more than one ranges section, each claiming a different
759 * secondary GTF curve. Please don't do that.
760 */
761 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
762 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
763 kfree(mode);
764 mode = drm_gtf_mode_complex(dev, hsize, vsize,
765 vrefresh_rate, 0, 0,
766 drm_gtf2_m(edid),
767 drm_gtf2_2c(edid),
768 drm_gtf2_k(edid),
769 drm_gtf2_2j(edid));
770 }
771 break;
5c61259e 772 case LEVEL_CVT:
d50ba256
DA
773 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
774 false);
5c61259e
ZY
775 break;
776 }
f453ba04
DA
777 return mode;
778}
779
b58db2c6
AJ
780/*
781 * EDID is delightfully ambiguous about how interlaced modes are to be
782 * encoded. Our internal representation is of frame height, but some
783 * HDTV detailed timings are encoded as field height.
784 *
785 * The format list here is from CEA, in frame size. Technically we
786 * should be checking refresh rate too. Whatever.
787 */
788static void
789drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
790 struct detailed_pixel_timing *pt)
791{
792 int i;
793 static const struct {
794 int w, h;
795 } cea_interlaced[] = {
796 { 1920, 1080 },
797 { 720, 480 },
798 { 1440, 480 },
799 { 2880, 480 },
800 { 720, 576 },
801 { 1440, 576 },
802 { 2880, 576 },
803 };
b58db2c6
AJ
804
805 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
806 return;
807
3c581411 808 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ
809 if ((mode->hdisplay == cea_interlaced[i].w) &&
810 (mode->vdisplay == cea_interlaced[i].h / 2)) {
811 mode->vdisplay *= 2;
812 mode->vsync_start *= 2;
813 mode->vsync_end *= 2;
814 mode->vtotal *= 2;
815 mode->vtotal |= 1;
816 }
817 }
818
819 mode->flags |= DRM_MODE_FLAG_INTERLACE;
820}
821
f453ba04
DA
822/**
823 * drm_mode_detailed - create a new mode from an EDID detailed timing section
824 * @dev: DRM device (needed to create new mode)
825 * @edid: EDID block
826 * @timing: EDID detailed timing info
827 * @quirks: quirks to apply
828 *
829 * An EDID detailed timing block contains enough info for us to create and
830 * return a new struct drm_display_mode.
831 */
832static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
833 struct edid *edid,
834 struct detailed_timing *timing,
835 u32 quirks)
836{
837 struct drm_display_mode *mode;
838 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD
839 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
840 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
841 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
842 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD
843 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
844 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
845 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
846 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 847
fc438966 848 /* ignore tiny modes */
0454beab 849 if (hactive < 64 || vactive < 64)
fc438966
AJ
850 return NULL;
851
0454beab 852 if (pt->misc & DRM_EDID_PT_STEREO) {
f453ba04
DA
853 printk(KERN_WARNING "stereo mode not supported\n");
854 return NULL;
855 }
0454beab 856 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
79b7dcb2 857 printk(KERN_WARNING "composite sync not supported\n");
f453ba04
DA
858 }
859
fcb45611
ZY
860 /* it is incorrect if hsync/vsync width is zero */
861 if (!hsync_pulse_width || !vsync_pulse_width) {
862 DRM_DEBUG_KMS("Incorrect Detailed timing. "
863 "Wrong Hsync/Vsync pulse width\n");
864 return NULL;
865 }
f453ba04
DA
866 mode = drm_mode_create(dev);
867 if (!mode)
868 return NULL;
869
870 mode->type = DRM_MODE_TYPE_DRIVER;
871
872 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD
873 timing->pixel_clock = cpu_to_le16(1088);
874
875 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
876
877 mode->hdisplay = hactive;
878 mode->hsync_start = mode->hdisplay + hsync_offset;
879 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
880 mode->htotal = mode->hdisplay + hblank;
881
882 mode->vdisplay = vactive;
883 mode->vsync_start = mode->vdisplay + vsync_offset;
884 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
885 mode->vtotal = mode->vdisplay + vblank;
f453ba04 886
7064fef5
JB
887 /* Some EDIDs have bogus h/vtotal values */
888 if (mode->hsync_end > mode->htotal)
889 mode->htotal = mode->hsync_end + 1;
890 if (mode->vsync_end > mode->vtotal)
891 mode->vtotal = mode->vsync_end + 1;
892
b58db2c6 893 drm_mode_do_interlace_quirk(mode, pt);
f453ba04 894
171fdd89
AJ
895 drm_mode_set_name(mode);
896
f453ba04 897 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 898 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA
899 }
900
0454beab
MD
901 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
902 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
903 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
904 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 905
e14cbee4
MD
906 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
907 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA
908
909 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
910 mode->width_mm *= 10;
911 mode->height_mm *= 10;
912 }
913
914 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
915 mode->width_mm = edid->width_cm * 10;
916 mode->height_mm = edid->height_cm * 10;
917 }
918
919 return mode;
920}
921
07a5e632 922static bool
b1f559ec 923mode_is_rb(const struct drm_display_mode *mode)
07a5e632 924{
b17e52ef
AJ
925 return (mode->htotal - mode->hdisplay == 160) &&
926 (mode->hsync_end - mode->hdisplay == 80) &&
927 (mode->hsync_end - mode->hsync_start == 32) &&
928 (mode->vsync_start - mode->vdisplay == 3);
929}
07a5e632 930
b17e52ef 931static bool
b1f559ec
CW
932mode_in_hsync_range(const struct drm_display_mode *mode,
933 struct edid *edid, u8 *t)
b17e52ef
AJ
934{
935 int hsync, hmin, hmax;
936
937 hmin = t[7];
938 if (edid->revision >= 4)
939 hmin += ((t[4] & 0x04) ? 255 : 0);
940 hmax = t[8];
941 if (edid->revision >= 4)
942 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 943 hsync = drm_mode_hsync(mode);
07a5e632 944
b17e52ef
AJ
945 return (hsync <= hmax && hsync >= hmin);
946}
947
948static bool
b1f559ec
CW
949mode_in_vsync_range(const struct drm_display_mode *mode,
950 struct edid *edid, u8 *t)
b17e52ef
AJ
951{
952 int vsync, vmin, vmax;
953
954 vmin = t[5];
955 if (edid->revision >= 4)
956 vmin += ((t[4] & 0x01) ? 255 : 0);
957 vmax = t[6];
958 if (edid->revision >= 4)
959 vmax += ((t[4] & 0x02) ? 255 : 0);
960 vsync = drm_mode_vrefresh(mode);
961
962 return (vsync <= vmax && vsync >= vmin);
963}
964
965static u32
966range_pixel_clock(struct edid *edid, u8 *t)
967{
968 /* unspecified */
969 if (t[9] == 0 || t[9] == 255)
970 return 0;
971
972 /* 1.4 with CVT support gives us real precision, yay */
973 if (edid->revision >= 4 && t[10] == 0x04)
974 return (t[9] * 10000) - ((t[12] >> 2) * 250);
975
976 /* 1.3 is pathetic, so fuzz up a bit */
977 return t[9] * 10000 + 5001;
978}
979
b17e52ef 980static bool
b1f559ec 981mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ
982 struct detailed_timing *timing)
983{
984 u32 max_clock;
985 u8 *t = (u8 *)timing;
986
987 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ
988 return false;
989
b17e52ef 990 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ
991 return false;
992
b17e52ef 993 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ
994 if (mode->clock > max_clock)
995 return false;
b17e52ef
AJ
996
997 /* 1.4 max horizontal check */
998 if (edid->revision >= 4 && t[10] == 0x04)
999 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1000 return false;
1001
1002 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1003 return false;
07a5e632
AJ
1004
1005 return true;
1006}
1007
1008/*
1009 * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will
1010 * need to account for them.
1011 */
b17e52ef
AJ
1012static int
1013drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1014 struct detailed_timing *timing)
07a5e632
AJ
1015{
1016 int i, modes = 0;
1017 struct drm_display_mode *newmode;
1018 struct drm_device *dev = connector->dev;
1019
1020 for (i = 0; i < drm_num_dmt_modes; i++) {
b17e52ef 1021 if (mode_in_range(drm_dmt_modes + i, edid, timing)) {
07a5e632
AJ
1022 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1023 if (newmode) {
1024 drm_mode_probed_add(connector, newmode);
1025 modes++;
1026 }
1027 }
1028 }
1029
1030 return modes;
1031}
1032
13931579
AJ
1033static void
1034do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 1035{
13931579
AJ
1036 struct detailed_mode_closure *closure = c;
1037 struct detailed_non_pixel *data = &timing->data.other_data;
1038 int gtf = (closure->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
9340d8cf 1039
13931579
AJ
1040 if (gtf && data->type == EDID_DETAIL_MONITOR_RANGE)
1041 closure->modes += drm_gtf_modes_for_range(closure->connector,
1042 closure->edid,
1043 timing);
1044}
69da3015 1045
13931579
AJ
1046static int
1047add_inferred_modes(struct drm_connector *connector, struct edid *edid)
1048{
1049 struct detailed_mode_closure closure = {
1050 connector, edid, 0, 0, 0
1051 };
9340d8cf 1052
13931579
AJ
1053 if (version_greater(edid, 1, 0))
1054 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
1055 &closure);
9340d8cf 1056
13931579 1057 return closure.modes;
9340d8cf
AJ
1058}
1059
2255be14
AJ
1060static int
1061drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1062{
1063 int i, j, m, modes = 0;
1064 struct drm_display_mode *mode;
1065 u8 *est = ((u8 *)timing) + 5;
1066
1067 for (i = 0; i < 6; i++) {
1068 for (j = 7; j > 0; j--) {
1069 m = (i * 8) + (7 - j);
3c581411 1070 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ
1071 break;
1072 if (est[i] & (1 << j)) {
1d42bbc8
DA
1073 mode = drm_mode_find_dmt(connector->dev,
1074 est3_modes[m].w,
1075 est3_modes[m].h,
1076 est3_modes[m].r
1077 /*, est3_modes[m].rb */);
2255be14
AJ
1078 if (mode) {
1079 drm_mode_probed_add(connector, mode);
1080 modes++;
1081 }
1082 }
1083 }
1084 }
1085
1086 return modes;
1087}
1088
13931579
AJ
1089static void
1090do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 1091{
13931579 1092 struct detailed_mode_closure *closure = c;
9cf00977 1093 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 1094
13931579
AJ
1095 if (data->type == EDID_DETAIL_EST_TIMINGS)
1096 closure->modes += drm_est3_modes(closure->connector, timing);
1097}
9cf00977 1098
13931579
AJ
1099/**
1100 * add_established_modes - get est. modes from EDID and add them
1101 * @edid: EDID block to scan
1102 *
1103 * Each EDID block contains a bitmap of the supported "established modes" list
1104 * (defined above). Tease them out and add them to the global modes list.
1105 */
1106static int
1107add_established_modes(struct drm_connector *connector, struct edid *edid)
1108{
1109 struct drm_device *dev = connector->dev;
1110 unsigned long est_bits = edid->established_timings.t1 |
1111 (edid->established_timings.t2 << 8) |
1112 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1113 int i, modes = 0;
1114 struct detailed_mode_closure closure = {
1115 connector, edid, 0, 0, 0
1116 };
9cf00977 1117
13931579
AJ
1118 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
1119 if (est_bits & (1<<i)) {
1120 struct drm_display_mode *newmode;
1121 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1122 if (newmode) {
1123 drm_mode_probed_add(connector, newmode);
1124 modes++;
1125 }
1126 }
9cf00977
AJ
1127 }
1128
13931579
AJ
1129 if (version_greater(edid, 1, 0))
1130 drm_for_each_detailed_block((u8 *)edid,
1131 do_established_modes, &closure);
1132
1133 return modes + closure.modes;
1134}
1135
1136static void
1137do_standard_modes(struct detailed_timing *timing, void *c)
1138{
1139 struct detailed_mode_closure *closure = c;
1140 struct detailed_non_pixel *data = &timing->data.other_data;
1141 struct drm_connector *connector = closure->connector;
1142 struct edid *edid = closure->edid;
1143
1144 if (data->type == EDID_DETAIL_STD_MODES) {
1145 int i;
9cf00977
AJ
1146 for (i = 0; i < 6; i++) {
1147 struct std_timing *std;
1148 struct drm_display_mode *newmode;
1149
1150 std = &data->data.timings[i];
7a374350
AJ
1151 newmode = drm_mode_std(connector, edid, std,
1152 edid->revision);
9cf00977
AJ
1153 if (newmode) {
1154 drm_mode_probed_add(connector, newmode);
13931579 1155 closure->modes++;
9cf00977
AJ
1156 }
1157 }
9cf00977 1158 }
9cf00977
AJ
1159}
1160
f453ba04 1161/**
13931579 1162 * add_standard_modes - get std. modes from EDID and add them
f453ba04 1163 * @edid: EDID block to scan
f453ba04 1164 *
13931579
AJ
1165 * Standard modes can be calculated using the appropriate standard (DMT,
1166 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 1167 */
13931579
AJ
1168static int
1169add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 1170{
9cf00977 1171 int i, modes = 0;
13931579
AJ
1172 struct detailed_mode_closure closure = {
1173 connector, edid, 0, 0, 0
1174 };
1175
1176 for (i = 0; i < EDID_STD_TIMINGS; i++) {
1177 struct drm_display_mode *newmode;
1178
1179 newmode = drm_mode_std(connector, edid,
1180 &edid->standard_timings[i],
1181 edid->revision);
1182 if (newmode) {
1183 drm_mode_probed_add(connector, newmode);
1184 modes++;
1185 }
1186 }
1187
1188 if (version_greater(edid, 1, 0))
1189 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
1190 &closure);
1191
1192 /* XXX should also look for standard codes in VTB blocks */
1193
1194 return modes + closure.modes;
1195}
f453ba04 1196
13931579
AJ
1197static int drm_cvt_modes(struct drm_connector *connector,
1198 struct detailed_timing *timing)
1199{
1200 int i, j, modes = 0;
1201 struct drm_display_mode *newmode;
1202 struct drm_device *dev = connector->dev;
1203 struct cvt_timing *cvt;
1204 const int rates[] = { 60, 85, 75, 60, 50 };
1205 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 1206
13931579
AJ
1207 for (i = 0; i < 4; i++) {
1208 int uninitialized_var(width), height;
1209 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 1210
13931579 1211 if (!memcmp(cvt->code, empty, 3))
9cf00977 1212 continue;
f453ba04 1213
13931579
AJ
1214 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1215 switch (cvt->code[1] & 0x0c) {
1216 case 0x00:
1217 width = height * 4 / 3;
1218 break;
1219 case 0x04:
1220 width = height * 16 / 9;
1221 break;
1222 case 0x08:
1223 width = height * 16 / 10;
1224 break;
1225 case 0x0c:
1226 width = height * 15 / 9;
1227 break;
1228 }
1229
1230 for (j = 1; j < 5; j++) {
1231 if (cvt->code[2] & (1 << j)) {
1232 newmode = drm_cvt_mode(dev, width, height,
1233 rates[j], j == 0,
1234 false, false);
1235 if (newmode) {
1236 drm_mode_probed_add(connector, newmode);
1237 modes++;
1238 }
1239 }
1240 }
f453ba04
DA
1241 }
1242
1243 return modes;
1244}
9cf00977 1245
13931579
AJ
1246static void
1247do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 1248{
13931579
AJ
1249 struct detailed_mode_closure *closure = c;
1250 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 1251
13931579
AJ
1252 if (data->type == EDID_DETAIL_CVT_3BYTE)
1253 closure->modes += drm_cvt_modes(closure->connector, timing);
1254}
882f0219 1255
13931579
AJ
1256static int
1257add_cvt_modes(struct drm_connector *connector, struct edid *edid)
1258{
1259 struct detailed_mode_closure closure = {
1260 connector, edid, 0, 0, 0
1261 };
882f0219 1262
13931579
AJ
1263 if (version_greater(edid, 1, 2))
1264 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 1265
13931579 1266 /* XXX should also look for CVT codes in VTB blocks */
882f0219 1267
13931579
AJ
1268 return closure.modes;
1269}
1270
1271static void
1272do_detailed_mode(struct detailed_timing *timing, void *c)
1273{
1274 struct detailed_mode_closure *closure = c;
1275 struct drm_display_mode *newmode;
1276
1277 if (timing->pixel_clock) {
1278 newmode = drm_mode_detailed(closure->connector->dev,
1279 closure->edid, timing,
1280 closure->quirks);
1281 if (!newmode)
1282 return;
1283
1284 if (closure->preferred)
1285 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1286
1287 drm_mode_probed_add(closure->connector, newmode);
1288 closure->modes++;
1289 closure->preferred = 0;
882f0219 1290 }
13931579 1291}
882f0219 1292
13931579
AJ
1293/*
1294 * add_detailed_modes - Add modes from detailed timings
1295 * @connector: attached connector
1296 * @edid: EDID block to scan
1297 * @quirks: quirks to apply
1298 */
1299static int
1300add_detailed_modes(struct drm_connector *connector, struct edid *edid,
1301 u32 quirks)
1302{
1303 struct detailed_mode_closure closure = {
1304 connector,
1305 edid,
1306 1,
1307 quirks,
1308 0
1309 };
1310
1311 if (closure.preferred && !version_greater(edid, 1, 3))
1312 closure.preferred =
1313 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
1314
1315 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
1316
1317 return closure.modes;
882f0219 1318}
f453ba04 1319
f23c20c8 1320#define HDMI_IDENTIFIER 0x000C03
8fe9790d 1321#define AUDIO_BLOCK 0x01
f23c20c8 1322#define VENDOR_BLOCK 0x03
76adaa34 1323#define SPEAKER_BLOCK 0x04
8fe9790d
ZW
1324#define EDID_BASIC_AUDIO (1 << 6)
1325
f23c20c8 1326/**
8fe9790d 1327 * Search EDID for CEA extension block.
f23c20c8 1328 */
eccaca28 1329u8 *drm_find_cea_extension(struct edid *edid)
f23c20c8 1330{
8fe9790d
ZW
1331 u8 *edid_ext = NULL;
1332 int i;
f23c20c8
ML
1333
1334 /* No EDID or EDID extensions */
1335 if (edid == NULL || edid->extensions == 0)
8fe9790d 1336 return NULL;
f23c20c8 1337
f23c20c8 1338 /* Find CEA extension */
7466f4cc 1339 for (i = 0; i < edid->extensions; i++) {
8fe9790d
ZW
1340 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
1341 if (edid_ext[0] == CEA_EXT)
f23c20c8
ML
1342 break;
1343 }
1344
7466f4cc 1345 if (i == edid->extensions)
8fe9790d
ZW
1346 return NULL;
1347
1348 return edid_ext;
1349}
eccaca28 1350EXPORT_SYMBOL(drm_find_cea_extension);
8fe9790d 1351
76adaa34
WF
1352static void
1353parse_hdmi_vsdb(struct drm_connector *connector, uint8_t *db)
1354{
1355 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
1356
1357 connector->dvi_dual = db[6] & 1;
1358 connector->max_tmds_clock = db[7] * 5;
1359
1360 connector->latency_present[0] = db[8] >> 7;
1361 connector->latency_present[1] = (db[8] >> 6) & 1;
1362 connector->video_latency[0] = db[9];
1363 connector->audio_latency[0] = db[10];
1364 connector->video_latency[1] = db[11];
1365 connector->audio_latency[1] = db[12];
1366
1367 DRM_LOG_KMS("HDMI: DVI dual %d, "
1368 "max TMDS clock %d, "
1369 "latency present %d %d, "
1370 "video latency %d %d, "
1371 "audio latency %d %d\n",
1372 connector->dvi_dual,
1373 connector->max_tmds_clock,
1374 (int) connector->latency_present[0],
1375 (int) connector->latency_present[1],
1376 connector->video_latency[0],
1377 connector->video_latency[1],
1378 connector->audio_latency[0],
1379 connector->audio_latency[1]);
1380}
1381
1382static void
1383monitor_name(struct detailed_timing *t, void *data)
1384{
1385 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
1386 *(u8 **)data = t->data.other_data.data.str.str;
1387}
1388
1389/**
1390 * drm_edid_to_eld - build ELD from EDID
1391 * @connector: connector corresponding to the HDMI/DP sink
1392 * @edid: EDID to parse
1393 *
1394 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver.
1395 * Some ELD fields are left to the graphics driver caller:
1396 * - Conn_Type
1397 * - HDCP
1398 * - Port_ID
1399 */
1400void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
1401{
1402 uint8_t *eld = connector->eld;
1403 u8 *cea;
1404 u8 *name;
1405 u8 *db;
1406 int sad_count = 0;
1407 int mnl;
1408 int dbl;
1409
1410 memset(eld, 0, sizeof(connector->eld));
1411
1412 cea = drm_find_cea_extension(edid);
1413 if (!cea) {
1414 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
1415 return;
1416 }
1417
1418 name = NULL;
1419 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
1420 for (mnl = 0; name && mnl < 13; mnl++) {
1421 if (name[mnl] == 0x0a)
1422 break;
1423 eld[20 + mnl] = name[mnl];
1424 }
1425 eld[4] = (cea[1] << 5) | mnl;
1426 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
1427
1428 eld[0] = 2 << 3; /* ELD version: 2 */
1429
1430 eld[16] = edid->mfg_id[0];
1431 eld[17] = edid->mfg_id[1];
1432 eld[18] = edid->prod_code[0];
1433 eld[19] = edid->prod_code[1];
1434
1435 for (db = cea + 4; db < cea + cea[2]; db += dbl + 1) {
1436 dbl = db[0] & 0x1f;
1437
1438 switch ((db[0] & 0xe0) >> 5) {
1439 case AUDIO_BLOCK: /* Audio Data Block, contains SADs */
1440 sad_count = dbl / 3;
1441 memcpy(eld + 20 + mnl, &db[1], dbl);
1442 break;
1443 case SPEAKER_BLOCK: /* Speaker Allocation Data Block */
1444 eld[7] = db[1];
1445 break;
1446 case VENDOR_BLOCK:
1447 /* HDMI Vendor-Specific Data Block */
1448 if (db[1] == 0x03 && db[2] == 0x0c && db[3] == 0)
1449 parse_hdmi_vsdb(connector, db);
1450 break;
1451 default:
1452 break;
1453 }
1454 }
1455 eld[5] |= sad_count << 4;
1456 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
1457
1458 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count);
1459}
1460EXPORT_SYMBOL(drm_edid_to_eld);
1461
1462/**
1463 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond
1464 * @connector: connector associated with the HDMI/DP sink
1465 * @mode: the display mode
1466 */
1467int drm_av_sync_delay(struct drm_connector *connector,
1468 struct drm_display_mode *mode)
1469{
1470 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1471 int a, v;
1472
1473 if (!connector->latency_present[0])
1474 return 0;
1475 if (!connector->latency_present[1])
1476 i = 0;
1477
1478 a = connector->audio_latency[i];
1479 v = connector->video_latency[i];
1480
1481 /*
1482 * HDMI/DP sink doesn't support audio or video?
1483 */
1484 if (a == 255 || v == 255)
1485 return 0;
1486
1487 /*
1488 * Convert raw EDID values to millisecond.
1489 * Treat unknown latency as 0ms.
1490 */
1491 if (a)
1492 a = min(2 * (a - 1), 500);
1493 if (v)
1494 v = min(2 * (v - 1), 500);
1495
1496 return max(v - a, 0);
1497}
1498EXPORT_SYMBOL(drm_av_sync_delay);
1499
1500/**
1501 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
1502 * @encoder: the encoder just changed display mode
1503 * @mode: the adjusted display mode
1504 *
1505 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
1506 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
1507 */
1508struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
1509 struct drm_display_mode *mode)
1510{
1511 struct drm_connector *connector;
1512 struct drm_device *dev = encoder->dev;
1513
1514 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
1515 if (connector->encoder == encoder && connector->eld[0])
1516 return connector;
1517
1518 return NULL;
1519}
1520EXPORT_SYMBOL(drm_select_eld);
1521
8fe9790d
ZW
1522/**
1523 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
1524 * @edid: monitor EDID information
1525 *
1526 * Parse the CEA extension according to CEA-861-B.
1527 * Return true if HDMI, false if not or unknown.
1528 */
1529bool drm_detect_hdmi_monitor(struct edid *edid)
1530{
1531 u8 *edid_ext;
1532 int i, hdmi_id;
1533 int start_offset, end_offset;
1534 bool is_hdmi = false;
1535
1536 edid_ext = drm_find_cea_extension(edid);
1537 if (!edid_ext)
f23c20c8
ML
1538 goto end;
1539
1540 /* Data block offset in CEA extension block */
1541 start_offset = 4;
1542 end_offset = edid_ext[2];
1543
1544 /*
1545 * Because HDMI identifier is in Vendor Specific Block,
1546 * search it from all data blocks of CEA extension.
1547 */
1548 for (i = start_offset; i < end_offset;
1549 /* Increased by data block len */
1550 i += ((edid_ext[i] & 0x1f) + 1)) {
1551 /* Find vendor specific block */
1552 if ((edid_ext[i] >> 5) == VENDOR_BLOCK) {
1553 hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) |
1554 edid_ext[i + 3] << 16;
1555 /* Find HDMI identifier */
1556 if (hdmi_id == HDMI_IDENTIFIER)
1557 is_hdmi = true;
1558 break;
1559 }
1560 }
1561
1562end:
1563 return is_hdmi;
1564}
1565EXPORT_SYMBOL(drm_detect_hdmi_monitor);
1566
8fe9790d
ZW
1567/**
1568 * drm_detect_monitor_audio - check monitor audio capability
1569 *
1570 * Monitor should have CEA extension block.
1571 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
1572 * audio' only. If there is any audio extension block and supported
1573 * audio format, assume at least 'basic audio' support, even if 'basic
1574 * audio' is not defined in EDID.
1575 *
1576 */
1577bool drm_detect_monitor_audio(struct edid *edid)
1578{
1579 u8 *edid_ext;
1580 int i, j;
1581 bool has_audio = false;
1582 int start_offset, end_offset;
1583
1584 edid_ext = drm_find_cea_extension(edid);
1585 if (!edid_ext)
1586 goto end;
1587
1588 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
1589
1590 if (has_audio) {
1591 DRM_DEBUG_KMS("Monitor has basic audio support\n");
1592 goto end;
1593 }
1594
1595 /* Data block offset in CEA extension block */
1596 start_offset = 4;
1597 end_offset = edid_ext[2];
1598
1599 for (i = start_offset; i < end_offset;
1600 i += ((edid_ext[i] & 0x1f) + 1)) {
1601 if ((edid_ext[i] >> 5) == AUDIO_BLOCK) {
1602 has_audio = true;
1603 for (j = 1; j < (edid_ext[i] & 0x1f); j += 3)
1604 DRM_DEBUG_KMS("CEA audio format %d\n",
1605 (edid_ext[i + j] >> 3) & 0xf);
1606 goto end;
1607 }
1608 }
1609end:
1610 return has_audio;
1611}
1612EXPORT_SYMBOL(drm_detect_monitor_audio);
1613
3b11228b
JB
1614/**
1615 * drm_add_display_info - pull display info out if present
1616 * @edid: EDID data
1617 * @info: display info (attached to connector)
1618 *
1619 * Grab any available display info and stuff it into the drm_display_info
1620 * structure that's part of the connector. Useful for tracking bpp and
1621 * color spaces.
1622 */
1623static void drm_add_display_info(struct edid *edid,
1624 struct drm_display_info *info)
1625{
ebec9a7b
JB
1626 u8 *edid_ext;
1627
3b11228b
JB
1628 info->width_mm = edid->width_cm * 10;
1629 info->height_mm = edid->height_cm * 10;
1630
1631 /* driver figures it out in this case */
1632 info->bpc = 0;
da05a5a7 1633 info->color_formats = 0;
3b11228b
JB
1634
1635 /* Only defined for 1.4 with digital displays */
1636 if (edid->revision < 4)
1637 return;
1638
1639 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
1640 return;
1641
1642 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
1643 case DRM_EDID_DIGITAL_DEPTH_6:
1644 info->bpc = 6;
1645 break;
1646 case DRM_EDID_DIGITAL_DEPTH_8:
1647 info->bpc = 8;
1648 break;
1649 case DRM_EDID_DIGITAL_DEPTH_10:
1650 info->bpc = 10;
1651 break;
1652 case DRM_EDID_DIGITAL_DEPTH_12:
1653 info->bpc = 12;
1654 break;
1655 case DRM_EDID_DIGITAL_DEPTH_14:
1656 info->bpc = 14;
1657 break;
1658 case DRM_EDID_DIGITAL_DEPTH_16:
1659 info->bpc = 16;
1660 break;
1661 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
1662 default:
1663 info->bpc = 0;
1664 break;
1665 }
da05a5a7
JB
1666
1667 info->color_formats = DRM_COLOR_FORMAT_RGB444;
1668 if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB444)
1669 info->color_formats = DRM_COLOR_FORMAT_YCRCB444;
1670 if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB422)
1671 info->color_formats = DRM_COLOR_FORMAT_YCRCB422;
ebec9a7b
JB
1672
1673 /* Get data from CEA blocks if present */
1674 edid_ext = drm_find_cea_extension(edid);
1675 if (!edid_ext)
1676 return;
1677
1678 info->cea_rev = edid_ext[1];
3b11228b
JB
1679}
1680
f453ba04
DA
1681/**
1682 * drm_add_edid_modes - add modes from EDID data, if available
1683 * @connector: connector we're probing
1684 * @edid: edid data
1685 *
1686 * Add the specified modes to the connector's mode list.
1687 *
1688 * Return number of modes added or 0 if we couldn't find any.
1689 */
1690int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1691{
1692 int num_modes = 0;
1693 u32 quirks;
1694
1695 if (edid == NULL) {
1696 return 0;
1697 }
3c537889 1698 if (!drm_edid_is_valid(edid)) {
dcdb1674 1699 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
f453ba04
DA
1700 drm_get_connector_name(connector));
1701 return 0;
1702 }
1703
1704 quirks = edid_get_quirks(edid);
1705
c867df70
AJ
1706 /*
1707 * EDID spec says modes should be preferred in this order:
1708 * - preferred detailed mode
1709 * - other detailed modes from base block
1710 * - detailed modes from extension blocks
1711 * - CVT 3-byte code modes
1712 * - standard timing codes
1713 * - established timing codes
1714 * - modes inferred from GTF or CVT range information
1715 *
13931579 1716 * We get this pretty much right.
c867df70
AJ
1717 *
1718 * XXX order for additional mode types in extension blocks?
1719 */
13931579
AJ
1720 num_modes += add_detailed_modes(connector, edid, quirks);
1721 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ
1722 num_modes += add_standard_modes(connector, edid);
1723 num_modes += add_established_modes(connector, edid);
13931579 1724 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA
1725
1726 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1727 edid_fixup_preferred(connector, quirks);
1728
3b11228b 1729 drm_add_display_info(edid, &connector->display_info);
f453ba04
DA
1730
1731 return num_modes;
1732}
1733EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY
1734
1735/**
1736 * drm_add_modes_noedid - add modes for the connectors without EDID
1737 * @connector: connector we're probing
1738 * @hdisplay: the horizontal display limit
1739 * @vdisplay: the vertical display limit
1740 *
1741 * Add the specified modes to the connector's mode list. Only when the
1742 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1743 *
1744 * Return number of modes added or 0 if we couldn't find any.
1745 */
1746int drm_add_modes_noedid(struct drm_connector *connector,
1747 int hdisplay, int vdisplay)
1748{
1749 int i, count, num_modes = 0;
b1f559ec 1750 struct drm_display_mode *mode;
f0fda0a4
ZY
1751 struct drm_device *dev = connector->dev;
1752
1753 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1754 if (hdisplay < 0)
1755 hdisplay = 0;
1756 if (vdisplay < 0)
1757 vdisplay = 0;
1758
1759 for (i = 0; i < count; i++) {
b1f559ec 1760 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY
1761 if (hdisplay && vdisplay) {
1762 /*
1763 * Only when two are valid, they will be used to check
1764 * whether the mode should be added to the mode list of
1765 * the connector.
1766 */
1767 if (ptr->hdisplay > hdisplay ||
1768 ptr->vdisplay > vdisplay)
1769 continue;
1770 }
f985dedb
AJ
1771 if (drm_mode_vrefresh(ptr) > 61)
1772 continue;
f0fda0a4
ZY
1773 mode = drm_mode_duplicate(dev, ptr);
1774 if (mode) {
1775 drm_mode_probed_add(connector, mode);
1776 num_modes++;
1777 }
1778 }
1779 return num_modes;
1780}
1781EXPORT_SYMBOL(drm_add_modes_noedid);