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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
a8c21a54 T |
2 | #ifndef STATE_HI_XML |
3 | #define STATE_HI_XML | |
4 | ||
5 | /* Autogenerated file, DO NOT EDIT manually! | |
6 | ||
7 | This file was generated by the rules-ng-ng headergen tool in this git repository: | |
8 | http://0x04.net/cgit/index.cgi/rules-ng-ng | |
9 | git clone git://0x04.net/rules-ng-ng | |
10 | ||
11 | The rules-ng-ng source files this header was generated from are: | |
128a9b1d LS |
12 | - state_hi.xml ( 25620 bytes, from 2016-08-19 22:07:37) |
13 | - common.xml ( 20583 bytes, from 2016-06-07 05:22:38) | |
a8c21a54 | 14 | |
128a9b1d | 15 | Copyright (C) 2016 |
a8c21a54 T |
16 | */ |
17 | ||
18 | ||
19 | #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001 | |
20 | #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002 | |
21 | #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003 | |
22 | #define VIVS_HI 0x00000000 | |
23 | ||
24 | #define VIVS_HI_CLOCK_CONTROL 0x00000000 | |
25 | #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001 | |
26 | #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002 | |
27 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc | |
28 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT 2 | |
29 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK) | |
30 | #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x00000200 | |
31 | #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x00000400 | |
32 | #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x00000800 | |
33 | #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x00001000 | |
34 | #define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x00010000 | |
35 | #define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x00020000 | |
36 | #define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x00040000 | |
37 | #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x00080000 | |
38 | #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f00000 | |
39 | #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT 20 | |
40 | #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK) | |
41 | ||
42 | #define VIVS_HI_IDLE_STATE 0x00000004 | |
43 | #define VIVS_HI_IDLE_STATE_FE 0x00000001 | |
44 | #define VIVS_HI_IDLE_STATE_DE 0x00000002 | |
45 | #define VIVS_HI_IDLE_STATE_PE 0x00000004 | |
46 | #define VIVS_HI_IDLE_STATE_SH 0x00000008 | |
47 | #define VIVS_HI_IDLE_STATE_PA 0x00000010 | |
48 | #define VIVS_HI_IDLE_STATE_SE 0x00000020 | |
49 | #define VIVS_HI_IDLE_STATE_RA 0x00000040 | |
50 | #define VIVS_HI_IDLE_STATE_TX 0x00000080 | |
51 | #define VIVS_HI_IDLE_STATE_VG 0x00000100 | |
52 | #define VIVS_HI_IDLE_STATE_IM 0x00000200 | |
53 | #define VIVS_HI_IDLE_STATE_FP 0x00000400 | |
54 | #define VIVS_HI_IDLE_STATE_TS 0x00000800 | |
55 | #define VIVS_HI_IDLE_STATE_AXI_LP 0x80000000 | |
56 | ||
57 | #define VIVS_HI_AXI_CONFIG 0x00000008 | |
58 | #define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f | |
59 | #define VIVS_HI_AXI_CONFIG_AWID__SHIFT 0 | |
60 | #define VIVS_HI_AXI_CONFIG_AWID(x) (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK) | |
61 | #define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0 | |
62 | #define VIVS_HI_AXI_CONFIG_ARID__SHIFT 4 | |
63 | #define VIVS_HI_AXI_CONFIG_ARID(x) (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK) | |
64 | #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00 | |
65 | #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT 8 | |
66 | #define VIVS_HI_AXI_CONFIG_AWCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK) | |
67 | #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000 | |
68 | #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT 12 | |
69 | #define VIVS_HI_AXI_CONFIG_ARCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK) | |
70 | ||
71 | #define VIVS_HI_AXI_STATUS 0x0000000c | |
72 | #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f | |
73 | #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0 | |
74 | #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK) | |
75 | #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0 | |
76 | #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT 4 | |
77 | #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK) | |
78 | #define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100 | |
79 | #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 | |
80 | ||
81 | #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 | |
128a9b1d | 82 | #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff |
a8c21a54 T |
83 | #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 |
84 | #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) | |
128a9b1d | 85 | #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 |
a8c21a54 T |
86 | #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 |
87 | ||
88 | #define VIVS_HI_INTR_ENBL 0x00000014 | |
89 | #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff | |
90 | #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0 | |
91 | #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK) | |
92 | ||
93 | #define VIVS_HI_CHIP_IDENTITY 0x00000018 | |
94 | #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000 | |
95 | #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT 24 | |
96 | #define VIVS_HI_CHIP_IDENTITY_FAMILY(x) (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK) | |
97 | #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000 | |
98 | #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT 16 | |
99 | #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK) | |
100 | #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000 | |
101 | #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT 12 | |
102 | #define VIVS_HI_CHIP_IDENTITY_REVISION(x) (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK) | |
103 | ||
104 | #define VIVS_HI_CHIP_FEATURE 0x0000001c | |
105 | ||
106 | #define VIVS_HI_CHIP_MODEL 0x00000020 | |
107 | ||
108 | #define VIVS_HI_CHIP_REV 0x00000024 | |
109 | ||
110 | #define VIVS_HI_CHIP_DATE 0x00000028 | |
111 | ||
112 | #define VIVS_HI_CHIP_TIME 0x0000002c | |
113 | ||
114 | #define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034 | |
115 | ||
116 | #define VIVS_HI_CACHE_CONTROL 0x00000038 | |
117 | ||
118 | #define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c | |
119 | ||
120 | #define VIVS_HI_PROFILE_READ_BYTES8 0x00000040 | |
121 | ||
122 | #define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044 | |
123 | ||
124 | #define VIVS_HI_CHIP_SPECS 0x00000048 | |
125 | #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f | |
126 | #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0 | |
127 | #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK) | |
128 | #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0 | |
129 | #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT 4 | |
130 | #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK) | |
131 | #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00 | |
132 | #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT 8 | |
133 | #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK) | |
134 | #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000 | |
135 | #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT 12 | |
136 | #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK) | |
137 | #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000 | |
138 | #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT 20 | |
139 | #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK) | |
140 | #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000 | |
141 | #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT 25 | |
142 | #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK) | |
143 | #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000 | |
144 | #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT 28 | |
145 | #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK) | |
146 | ||
147 | #define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c | |
148 | ||
149 | #define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050 | |
150 | ||
151 | #define VIVS_HI_PROFILE_READ_BURSTS 0x00000058 | |
152 | ||
153 | #define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c | |
154 | ||
155 | #define VIVS_HI_PROFILE_READ_LASTS 0x00000060 | |
156 | ||
157 | #define VIVS_HI_GP_OUT0 0x00000064 | |
158 | ||
159 | #define VIVS_HI_GP_OUT1 0x00000068 | |
160 | ||
161 | #define VIVS_HI_GP_OUT2 0x0000006c | |
162 | ||
163 | #define VIVS_HI_AXI_CONTROL 0x00000070 | |
164 | #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001 | |
165 | ||
166 | #define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074 | |
167 | ||
168 | #define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078 | |
169 | ||
170 | #define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c | |
171 | ||
172 | #define VIVS_HI_CHIP_SPECS_2 0x00000080 | |
173 | #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff | |
174 | #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0 | |
175 | #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK) | |
176 | #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00 | |
177 | #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT 8 | |
178 | #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK) | |
179 | #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000 | |
180 | #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT 16 | |
181 | #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK) | |
182 | ||
183 | #define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084 | |
184 | ||
185 | #define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088 | |
186 | ||
e2a2e263 RK |
187 | #define VIVS_HI_CHIP_SPECS_3 0x0000008c |
188 | #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0 | |
189 | #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4 | |
190 | #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK) | |
191 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007 | |
192 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 | |
193 | #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) | |
194 | ||
a8c21a54 T |
195 | #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 |
196 | ||
e2a2e263 RK |
197 | #define VIVS_HI_CHIP_SPECS_4 0x0000009c |
198 | #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000 | |
199 | #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12 | |
200 | #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK) | |
201 | ||
202 | #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0 | |
203 | ||
204 | #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 | |
205 | ||
a8c21a54 T |
206 | #define VIVS_PM 0x00000000 |
207 | ||
208 | #define VIVS_PM_POWER_CONTROLS 0x00000100 | |
209 | #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001 | |
210 | #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002 | |
211 | #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004 | |
212 | #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0 | |
213 | #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT 4 | |
214 | #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK) | |
215 | #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000 | |
216 | #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT 16 | |
217 | #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK) | |
218 | ||
219 | #define VIVS_PM_MODULE_CONTROLS 0x00000104 | |
220 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001 | |
221 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002 | |
222 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004 | |
7d0c6e71 RK |
223 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008 |
224 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010 | |
225 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020 | |
226 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040 | |
227 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080 | |
228 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000 | |
229 | #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000 | |
a8c21a54 T |
230 | |
231 | #define VIVS_PM_MODULE_STATUS 0x00000108 | |
232 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001 | |
233 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002 | |
234 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004 | |
e2a2e263 RK |
235 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008 |
236 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010 | |
237 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020 | |
238 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040 | |
239 | #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 | |
a8c21a54 T |
240 | |
241 | #define VIVS_PM_PULSE_EATER 0x0000010c | |
242 | ||
243 | #define VIVS_MMUv2 0x00000000 | |
244 | ||
245 | #define VIVS_MMUv2_SAFE_ADDRESS 0x00000180 | |
246 | ||
247 | #define VIVS_MMUv2_CONFIGURATION 0x00000184 | |
248 | #define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001 | |
249 | #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0 | |
250 | #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000 | |
251 | #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001 | |
252 | #define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008 | |
253 | #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010 | |
254 | #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT 4 | |
255 | #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010 | |
256 | #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080 | |
257 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100 | |
258 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00 | |
259 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT 10 | |
260 | #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK) | |
261 | ||
262 | #define VIVS_MMUv2_STATUS 0x00000188 | |
263 | #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x00000003 | |
264 | #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0 | |
265 | #define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK) | |
266 | #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x00000030 | |
267 | #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4 | |
268 | #define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK) | |
269 | #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000300 | |
270 | #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8 | |
271 | #define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK) | |
272 | #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x00003000 | |
273 | #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12 | |
274 | #define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK) | |
275 | ||
276 | #define VIVS_MMUv2_CONTROL 0x0000018c | |
277 | #define VIVS_MMUv2_CONTROL_ENABLE 0x00000001 | |
278 | ||
279 | #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) | |
280 | #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 | |
281 | #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 | |
282 | ||
283 | #define VIVS_MC 0x00000000 | |
284 | ||
285 | #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400 | |
286 | ||
287 | #define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404 | |
288 | ||
289 | #define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408 | |
290 | ||
291 | #define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c | |
292 | ||
293 | #define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410 | |
294 | ||
295 | #define VIVS_MC_DEBUG_MEMORY 0x00000414 | |
296 | #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008 | |
297 | #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000 | |
298 | #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000 | |
299 | ||
300 | #define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418 | |
301 | ||
302 | #define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c | |
303 | ||
304 | #define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420 | |
305 | ||
306 | #define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424 | |
307 | ||
308 | #define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428 | |
309 | ||
310 | #define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c | |
311 | ||
312 | #define VIVS_MC_MEMORY_FLUSH 0x00000430 | |
313 | ||
314 | #define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438 | |
315 | ||
316 | #define VIVS_MC_DEBUG_READ0 0x0000043c | |
317 | ||
318 | #define VIVS_MC_DEBUG_READ1 0x00000440 | |
319 | ||
320 | #define VIVS_MC_DEBUG_WRITE 0x00000444 | |
321 | ||
322 | #define VIVS_MC_PROFILE_RA_READ 0x00000448 | |
323 | ||
324 | #define VIVS_MC_PROFILE_TX_READ 0x0000044c | |
325 | ||
326 | #define VIVS_MC_PROFILE_FE_READ 0x00000450 | |
327 | ||
328 | #define VIVS_MC_PROFILE_PE_READ 0x00000454 | |
329 | ||
330 | #define VIVS_MC_PROFILE_DE_READ 0x00000458 | |
331 | ||
332 | #define VIVS_MC_PROFILE_SH_READ 0x0000045c | |
333 | ||
334 | #define VIVS_MC_PROFILE_PA_READ 0x00000460 | |
335 | ||
336 | #define VIVS_MC_PROFILE_SE_READ 0x00000464 | |
337 | ||
338 | #define VIVS_MC_PROFILE_MC_READ 0x00000468 | |
339 | ||
340 | #define VIVS_MC_PROFILE_HI_READ 0x0000046c | |
341 | ||
342 | #define VIVS_MC_PROFILE_CONFIG0 0x00000470 | |
343 | #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x0000000f | |
344 | #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 | |
345 | #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f | |
346 | #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x00000f00 | |
347 | #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 | |
348 | #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 | |
349 | #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x000f0000 | |
350 | #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 | |
351 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 | |
352 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 | |
353 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000 | |
354 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 | |
355 | #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 | |
356 | #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 | |
357 | #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0x0f000000 | |
358 | #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 | |
359 | #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 | |
360 | #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 | |
361 | #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000 | |
362 | #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000 | |
363 | #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000 | |
364 | #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000 | |
365 | #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000 | |
366 | #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000 | |
367 | #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000 | |
368 | #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 | |
369 | ||
370 | #define VIVS_MC_PROFILE_CONFIG1 0x00000474 | |
371 | #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x0000000f | |
372 | #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 | |
373 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 | |
374 | #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 | |
375 | #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005 | |
376 | #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006 | |
377 | #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 | |
378 | #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 | |
379 | #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f | |
380 | #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x00000f00 | |
381 | #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 | |
382 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 | |
383 | #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 | |
384 | #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 | |
385 | #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x000f0000 | |
386 | #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 | |
387 | #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 | |
388 | #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 | |
389 | #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000 | |
390 | #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000 | |
391 | #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000 | |
392 | #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 | |
393 | #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 | |
394 | #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 | |
395 | #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0x0f000000 | |
396 | #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 | |
397 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 | |
398 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 | |
399 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000 | |
400 | #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000 | |
401 | #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000 | |
402 | #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000 | |
403 | #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000 | |
404 | #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000 | |
405 | #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000 | |
406 | #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000 | |
407 | #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 | |
408 | ||
409 | #define VIVS_MC_PROFILE_CONFIG2 0x00000478 | |
410 | #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x0000000f | |
411 | #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 | |
412 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 | |
413 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 | |
414 | #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 | |
415 | #define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f | |
416 | #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x00000f00 | |
417 | #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 | |
418 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 | |
419 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 | |
420 | #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 | |
421 | #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 | |
422 | ||
423 | #define VIVS_MC_PROFILE_CONFIG3 0x0000047c | |
424 | ||
425 | #define VIVS_MC_BUS_CONFIG 0x00000480 | |
426 | #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f | |
427 | #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0 | |
428 | #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK) | |
429 | #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0 | |
430 | #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT 4 | |
431 | #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK) | |
432 | ||
433 | #define VIVS_MC_START_COMPOSITION 0x00000554 | |
434 | ||
435 | #define VIVS_MC_128B_MERGE 0x00000558 | |
436 | ||
437 | ||
438 | #endif /* STATE_HI_XML */ |