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Commit | Line | Data |
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2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
2017263e BG |
33 | #include "drmP.h" |
34 | #include "drm.h" | |
4e5359cd | 35 | #include "intel_drv.h" |
e5c65260 | 36 | #include "intel_ringbuffer.h" |
2017263e BG |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | ||
40 | #define DRM_I915_RING_DEBUG 1 | |
41 | ||
42 | ||
43 | #if defined(CONFIG_DEBUG_FS) | |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 CW |
47 | FLUSHING_LIST, |
48 | INACTIVE_LIST, | |
d21d5975 CW |
49 | PINNED_LIST, |
50 | DEFERRED_FREE_LIST, | |
f13d3f73 | 51 | }; |
2017263e | 52 | |
70d39fe4 CW |
53 | static const char *yesno(int v) |
54 | { | |
55 | return v ? "yes" : "no"; | |
56 | } | |
57 | ||
58 | static int i915_capabilities(struct seq_file *m, void *data) | |
59 | { | |
60 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
61 | struct drm_device *dev = node->minor->dev; | |
62 | const struct intel_device_info *info = INTEL_INFO(dev); | |
63 | ||
64 | seq_printf(m, "gen: %d\n", info->gen); | |
65 | #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) | |
66 | B(is_mobile); | |
70d39fe4 CW |
67 | B(is_i85x); |
68 | B(is_i915g); | |
70d39fe4 | 69 | B(is_i945gm); |
70d39fe4 CW |
70 | B(is_g33); |
71 | B(need_gfx_hws); | |
72 | B(is_g4x); | |
73 | B(is_pineview); | |
74 | B(is_broadwater); | |
75 | B(is_crestline); | |
70d39fe4 | 76 | B(has_fbc); |
70d39fe4 CW |
77 | B(has_pipe_cxsr); |
78 | B(has_hotplug); | |
79 | B(cursor_needs_physical); | |
80 | B(has_overlay); | |
81 | B(overlay_needs_physical); | |
a6c45cf0 | 82 | B(supports_tv); |
549f7365 CW |
83 | B(has_bsd_ring); |
84 | B(has_blt_ring); | |
70d39fe4 CW |
85 | #undef B |
86 | ||
87 | return 0; | |
88 | } | |
2017263e | 89 | |
05394f39 | 90 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 91 | { |
05394f39 | 92 | if (obj->user_pin_count > 0) |
a6172a80 | 93 | return "P"; |
05394f39 | 94 | else if (obj->pin_count > 0) |
a6172a80 CW |
95 | return "p"; |
96 | else | |
97 | return " "; | |
98 | } | |
99 | ||
05394f39 | 100 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 101 | { |
0206e353 AJ |
102 | switch (obj->tiling_mode) { |
103 | default: | |
104 | case I915_TILING_NONE: return " "; | |
105 | case I915_TILING_X: return "X"; | |
106 | case I915_TILING_Y: return "Y"; | |
107 | } | |
a6172a80 CW |
108 | } |
109 | ||
93dfb40c | 110 | static const char *cache_level_str(int type) |
08c18323 CW |
111 | { |
112 | switch (type) { | |
93dfb40c CW |
113 | case I915_CACHE_NONE: return " uncached"; |
114 | case I915_CACHE_LLC: return " snooped (LLC)"; | |
115 | case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; | |
08c18323 CW |
116 | default: return ""; |
117 | } | |
118 | } | |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
08c18323 | 123 | seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s", |
37811fcc CW |
124 | &obj->base, |
125 | get_pin_flag(obj), | |
126 | get_tiling_flag(obj), | |
127 | obj->base.size, | |
128 | obj->base.read_domains, | |
129 | obj->base.write_domain, | |
130 | obj->last_rendering_seqno, | |
caea7476 | 131 | obj->last_fenced_seqno, |
93dfb40c | 132 | cache_level_str(obj->cache_level), |
37811fcc CW |
133 | obj->dirty ? " dirty" : "", |
134 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
135 | if (obj->base.name) | |
136 | seq_printf(m, " (name: %d)", obj->base.name); | |
137 | if (obj->fence_reg != I915_FENCE_REG_NONE) | |
138 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
139 | if (obj->gtt_space != NULL) | |
a00b10c3 CW |
140 | seq_printf(m, " (gtt offset: %08x, size: %08x)", |
141 | obj->gtt_offset, (unsigned int)obj->gtt_space->size); | |
6299f992 CW |
142 | if (obj->pin_mappable || obj->fault_mappable) { |
143 | char s[3], *t = s; | |
144 | if (obj->pin_mappable) | |
145 | *t++ = 'p'; | |
146 | if (obj->fault_mappable) | |
147 | *t++ = 'f'; | |
148 | *t = '\0'; | |
149 | seq_printf(m, " (%s mappable)", s); | |
150 | } | |
69dc4987 CW |
151 | if (obj->ring != NULL) |
152 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
153 | } |
154 | ||
433e12f7 | 155 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
156 | { |
157 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
158 | uintptr_t list = (uintptr_t) node->info_ent->data; |
159 | struct list_head *head; | |
2017263e BG |
160 | struct drm_device *dev = node->minor->dev; |
161 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 162 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
163 | size_t total_obj_size, total_gtt_size; |
164 | int count, ret; | |
de227ef0 CW |
165 | |
166 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
167 | if (ret) | |
168 | return ret; | |
2017263e | 169 | |
433e12f7 BG |
170 | switch (list) { |
171 | case ACTIVE_LIST: | |
172 | seq_printf(m, "Active:\n"); | |
69dc4987 | 173 | head = &dev_priv->mm.active_list; |
433e12f7 BG |
174 | break; |
175 | case INACTIVE_LIST: | |
a17458fc | 176 | seq_printf(m, "Inactive:\n"); |
433e12f7 BG |
177 | head = &dev_priv->mm.inactive_list; |
178 | break; | |
f13d3f73 CW |
179 | case PINNED_LIST: |
180 | seq_printf(m, "Pinned:\n"); | |
181 | head = &dev_priv->mm.pinned_list; | |
182 | break; | |
433e12f7 BG |
183 | case FLUSHING_LIST: |
184 | seq_printf(m, "Flushing:\n"); | |
185 | head = &dev_priv->mm.flushing_list; | |
186 | break; | |
d21d5975 CW |
187 | case DEFERRED_FREE_LIST: |
188 | seq_printf(m, "Deferred free:\n"); | |
189 | head = &dev_priv->mm.deferred_free_list; | |
190 | break; | |
433e12f7 | 191 | default: |
de227ef0 CW |
192 | mutex_unlock(&dev->struct_mutex); |
193 | return -EINVAL; | |
2017263e | 194 | } |
2017263e | 195 | |
8f2480fb | 196 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 197 | list_for_each_entry(obj, head, mm_list) { |
37811fcc | 198 | seq_printf(m, " "); |
05394f39 | 199 | describe_obj(m, obj); |
f4ceda89 | 200 | seq_printf(m, "\n"); |
05394f39 CW |
201 | total_obj_size += obj->base.size; |
202 | total_gtt_size += obj->gtt_space->size; | |
8f2480fb | 203 | count++; |
2017263e | 204 | } |
de227ef0 | 205 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 206 | |
8f2480fb CW |
207 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
208 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
209 | return 0; |
210 | } | |
211 | ||
6299f992 CW |
212 | #define count_objects(list, member) do { \ |
213 | list_for_each_entry(obj, list, member) { \ | |
214 | size += obj->gtt_space->size; \ | |
215 | ++count; \ | |
216 | if (obj->map_and_fenceable) { \ | |
217 | mappable_size += obj->gtt_space->size; \ | |
218 | ++mappable_count; \ | |
219 | } \ | |
220 | } \ | |
0206e353 | 221 | } while (0) |
6299f992 | 222 | |
73aa808f CW |
223 | static int i915_gem_object_info(struct seq_file *m, void* data) |
224 | { | |
225 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
226 | struct drm_device *dev = node->minor->dev; | |
227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299f992 CW |
228 | u32 count, mappable_count; |
229 | size_t size, mappable_size; | |
230 | struct drm_i915_gem_object *obj; | |
73aa808f CW |
231 | int ret; |
232 | ||
233 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
234 | if (ret) | |
235 | return ret; | |
236 | ||
6299f992 CW |
237 | seq_printf(m, "%u objects, %zu bytes\n", |
238 | dev_priv->mm.object_count, | |
239 | dev_priv->mm.object_memory); | |
240 | ||
241 | size = count = mappable_size = mappable_count = 0; | |
242 | count_objects(&dev_priv->mm.gtt_list, gtt_list); | |
243 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", | |
244 | count, mappable_count, size, mappable_size); | |
245 | ||
246 | size = count = mappable_size = mappable_count = 0; | |
247 | count_objects(&dev_priv->mm.active_list, mm_list); | |
248 | count_objects(&dev_priv->mm.flushing_list, mm_list); | |
249 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", | |
250 | count, mappable_count, size, mappable_size); | |
251 | ||
252 | size = count = mappable_size = mappable_count = 0; | |
253 | count_objects(&dev_priv->mm.pinned_list, mm_list); | |
254 | seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n", | |
255 | count, mappable_count, size, mappable_size); | |
256 | ||
257 | size = count = mappable_size = mappable_count = 0; | |
258 | count_objects(&dev_priv->mm.inactive_list, mm_list); | |
259 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", | |
260 | count, mappable_count, size, mappable_size); | |
261 | ||
262 | size = count = mappable_size = mappable_count = 0; | |
263 | count_objects(&dev_priv->mm.deferred_free_list, mm_list); | |
264 | seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n", | |
265 | count, mappable_count, size, mappable_size); | |
266 | ||
267 | size = count = mappable_size = mappable_count = 0; | |
268 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
269 | if (obj->fault_mappable) { | |
270 | size += obj->gtt_space->size; | |
271 | ++count; | |
272 | } | |
273 | if (obj->pin_mappable) { | |
274 | mappable_size += obj->gtt_space->size; | |
275 | ++mappable_count; | |
276 | } | |
277 | } | |
278 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", | |
279 | mappable_count, mappable_size); | |
280 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
281 | count, size); | |
282 | ||
283 | seq_printf(m, "%zu [%zu] gtt total\n", | |
284 | dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); | |
73aa808f CW |
285 | |
286 | mutex_unlock(&dev->struct_mutex); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
08c18323 CW |
291 | static int i915_gem_gtt_info(struct seq_file *m, void* data) |
292 | { | |
293 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
294 | struct drm_device *dev = node->minor->dev; | |
295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
296 | struct drm_i915_gem_object *obj; | |
297 | size_t total_obj_size, total_gtt_size; | |
298 | int count, ret; | |
299 | ||
300 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
301 | if (ret) | |
302 | return ret; | |
303 | ||
304 | total_obj_size = total_gtt_size = count = 0; | |
305 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
306 | seq_printf(m, " "); | |
307 | describe_obj(m, obj); | |
308 | seq_printf(m, "\n"); | |
309 | total_obj_size += obj->base.size; | |
310 | total_gtt_size += obj->gtt_space->size; | |
311 | count++; | |
312 | } | |
313 | ||
314 | mutex_unlock(&dev->struct_mutex); | |
315 | ||
316 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
317 | count, total_obj_size, total_gtt_size); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
73aa808f | 322 | |
4e5359cd SF |
323 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
324 | { | |
325 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
326 | struct drm_device *dev = node->minor->dev; | |
327 | unsigned long flags; | |
328 | struct intel_crtc *crtc; | |
329 | ||
330 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
331 | const char pipe = pipe_name(crtc->pipe); |
332 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
333 | struct intel_unpin_work *work; |
334 | ||
335 | spin_lock_irqsave(&dev->event_lock, flags); | |
336 | work = crtc->unpin_work; | |
337 | if (work == NULL) { | |
9db4a9c7 | 338 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
339 | pipe, plane); |
340 | } else { | |
341 | if (!work->pending) { | |
9db4a9c7 | 342 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
343 | pipe, plane); |
344 | } else { | |
9db4a9c7 | 345 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
346 | pipe, plane); |
347 | } | |
348 | if (work->enable_stall_check) | |
349 | seq_printf(m, "Stall check enabled, "); | |
350 | else | |
351 | seq_printf(m, "Stall check waiting for page flip ioctl, "); | |
352 | seq_printf(m, "%d prepares\n", work->pending); | |
353 | ||
354 | if (work->old_fb_obj) { | |
05394f39 CW |
355 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
356 | if (obj) | |
357 | seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
358 | } |
359 | if (work->pending_flip_obj) { | |
05394f39 CW |
360 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
361 | if (obj) | |
362 | seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); | |
4e5359cd SF |
363 | } |
364 | } | |
365 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
366 | } | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
2017263e BG |
371 | static int i915_gem_request_info(struct seq_file *m, void *data) |
372 | { | |
373 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
374 | struct drm_device *dev = node->minor->dev; | |
375 | drm_i915_private_t *dev_priv = dev->dev_private; | |
376 | struct drm_i915_gem_request *gem_request; | |
c2c347a9 | 377 | int ret, count; |
de227ef0 CW |
378 | |
379 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
380 | if (ret) | |
381 | return ret; | |
2017263e | 382 | |
c2c347a9 | 383 | count = 0; |
1ec14ad3 | 384 | if (!list_empty(&dev_priv->ring[RCS].request_list)) { |
c2c347a9 CW |
385 | seq_printf(m, "Render requests:\n"); |
386 | list_for_each_entry(gem_request, | |
1ec14ad3 | 387 | &dev_priv->ring[RCS].request_list, |
c2c347a9 CW |
388 | list) { |
389 | seq_printf(m, " %d @ %d\n", | |
390 | gem_request->seqno, | |
391 | (int) (jiffies - gem_request->emitted_jiffies)); | |
392 | } | |
393 | count++; | |
394 | } | |
1ec14ad3 | 395 | if (!list_empty(&dev_priv->ring[VCS].request_list)) { |
c2c347a9 CW |
396 | seq_printf(m, "BSD requests:\n"); |
397 | list_for_each_entry(gem_request, | |
1ec14ad3 | 398 | &dev_priv->ring[VCS].request_list, |
c2c347a9 CW |
399 | list) { |
400 | seq_printf(m, " %d @ %d\n", | |
401 | gem_request->seqno, | |
402 | (int) (jiffies - gem_request->emitted_jiffies)); | |
403 | } | |
404 | count++; | |
405 | } | |
1ec14ad3 | 406 | if (!list_empty(&dev_priv->ring[BCS].request_list)) { |
c2c347a9 CW |
407 | seq_printf(m, "BLT requests:\n"); |
408 | list_for_each_entry(gem_request, | |
1ec14ad3 | 409 | &dev_priv->ring[BCS].request_list, |
c2c347a9 CW |
410 | list) { |
411 | seq_printf(m, " %d @ %d\n", | |
412 | gem_request->seqno, | |
413 | (int) (jiffies - gem_request->emitted_jiffies)); | |
414 | } | |
415 | count++; | |
2017263e | 416 | } |
de227ef0 CW |
417 | mutex_unlock(&dev->struct_mutex); |
418 | ||
c2c347a9 CW |
419 | if (count == 0) |
420 | seq_printf(m, "No requests\n"); | |
421 | ||
2017263e BG |
422 | return 0; |
423 | } | |
424 | ||
b2223497 CW |
425 | static void i915_ring_seqno_info(struct seq_file *m, |
426 | struct intel_ring_buffer *ring) | |
427 | { | |
428 | if (ring->get_seqno) { | |
429 | seq_printf(m, "Current sequence (%s): %d\n", | |
430 | ring->name, ring->get_seqno(ring)); | |
431 | seq_printf(m, "Waiter sequence (%s): %d\n", | |
432 | ring->name, ring->waiting_seqno); | |
433 | seq_printf(m, "IRQ sequence (%s): %d\n", | |
434 | ring->name, ring->irq_seqno); | |
435 | } | |
436 | } | |
437 | ||
2017263e BG |
438 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
439 | { | |
440 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
441 | struct drm_device *dev = node->minor->dev; | |
442 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 443 | int ret, i; |
de227ef0 CW |
444 | |
445 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
446 | if (ret) | |
447 | return ret; | |
2017263e | 448 | |
1ec14ad3 CW |
449 | for (i = 0; i < I915_NUM_RINGS; i++) |
450 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | |
de227ef0 CW |
451 | |
452 | mutex_unlock(&dev->struct_mutex); | |
453 | ||
2017263e BG |
454 | return 0; |
455 | } | |
456 | ||
457 | ||
458 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
459 | { | |
460 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
461 | struct drm_device *dev = node->minor->dev; | |
462 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9db4a9c7 | 463 | int ret, i, pipe; |
de227ef0 CW |
464 | |
465 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
466 | if (ret) | |
467 | return ret; | |
2017263e | 468 | |
bad720ff | 469 | if (!HAS_PCH_SPLIT(dev)) { |
5f6a1695 ZW |
470 | seq_printf(m, "Interrupt enable: %08x\n", |
471 | I915_READ(IER)); | |
472 | seq_printf(m, "Interrupt identity: %08x\n", | |
473 | I915_READ(IIR)); | |
474 | seq_printf(m, "Interrupt mask: %08x\n", | |
475 | I915_READ(IMR)); | |
9db4a9c7 JB |
476 | for_each_pipe(pipe) |
477 | seq_printf(m, "Pipe %c stat: %08x\n", | |
478 | pipe_name(pipe), | |
479 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
480 | } else { |
481 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
482 | I915_READ(DEIER)); | |
483 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
484 | I915_READ(DEIIR)); | |
485 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
486 | I915_READ(DEIMR)); | |
487 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
488 | I915_READ(SDEIER)); | |
489 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
490 | I915_READ(SDEIIR)); | |
491 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
492 | I915_READ(SDEIMR)); | |
493 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
494 | I915_READ(GTIER)); | |
495 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
496 | I915_READ(GTIIR)); | |
497 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
498 | I915_READ(GTIMR)); | |
499 | } | |
2017263e BG |
500 | seq_printf(m, "Interrupts received: %d\n", |
501 | atomic_read(&dev_priv->irq_received)); | |
9862e600 | 502 | for (i = 0; i < I915_NUM_RINGS; i++) { |
da64c6fc | 503 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
9862e600 CW |
504 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", |
505 | dev_priv->ring[i].name, | |
506 | I915_READ_IMR(&dev_priv->ring[i])); | |
507 | } | |
1ec14ad3 | 508 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
9862e600 | 509 | } |
de227ef0 CW |
510 | mutex_unlock(&dev->struct_mutex); |
511 | ||
2017263e BG |
512 | return 0; |
513 | } | |
514 | ||
a6172a80 CW |
515 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
516 | { | |
517 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
518 | struct drm_device *dev = node->minor->dev; | |
519 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
520 | int i, ret; |
521 | ||
522 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
523 | if (ret) | |
524 | return ret; | |
a6172a80 CW |
525 | |
526 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
527 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
528 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 529 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 530 | |
c2c347a9 CW |
531 | seq_printf(m, "Fenced object[%2d] = ", i); |
532 | if (obj == NULL) | |
533 | seq_printf(m, "unused"); | |
534 | else | |
05394f39 | 535 | describe_obj(m, obj); |
c2c347a9 | 536 | seq_printf(m, "\n"); |
a6172a80 CW |
537 | } |
538 | ||
05394f39 | 539 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
540 | return 0; |
541 | } | |
542 | ||
2017263e BG |
543 | static int i915_hws_info(struct seq_file *m, void *data) |
544 | { | |
545 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
546 | struct drm_device *dev = node->minor->dev; | |
547 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 548 | struct intel_ring_buffer *ring; |
311bd68e | 549 | const volatile u32 __iomem *hws; |
4066c0ae CW |
550 | int i; |
551 | ||
1ec14ad3 | 552 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
311bd68e | 553 | hws = (volatile u32 __iomem *)ring->status_page.page_addr; |
2017263e BG |
554 | if (hws == NULL) |
555 | return 0; | |
556 | ||
557 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
558 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
559 | i * 4, | |
560 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
561 | } | |
562 | return 0; | |
563 | } | |
564 | ||
5cdf5881 CW |
565 | static void i915_dump_object(struct seq_file *m, |
566 | struct io_mapping *mapping, | |
05394f39 | 567 | struct drm_i915_gem_object *obj) |
6911a9b8 | 568 | { |
5cdf5881 | 569 | int page, page_count, i; |
6911a9b8 | 570 | |
05394f39 | 571 | page_count = obj->base.size / PAGE_SIZE; |
6911a9b8 | 572 | for (page = 0; page < page_count; page++) { |
5cdf5881 | 573 | u32 *mem = io_mapping_map_wc(mapping, |
05394f39 | 574 | obj->gtt_offset + page * PAGE_SIZE); |
6911a9b8 BG |
575 | for (i = 0; i < PAGE_SIZE; i += 4) |
576 | seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); | |
5cdf5881 | 577 | io_mapping_unmap(mem); |
6911a9b8 BG |
578 | } |
579 | } | |
580 | ||
581 | static int i915_batchbuffer_info(struct seq_file *m, void *data) | |
582 | { | |
583 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
584 | struct drm_device *dev = node->minor->dev; | |
585 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 586 | struct drm_i915_gem_object *obj; |
6911a9b8 BG |
587 | int ret; |
588 | ||
de227ef0 CW |
589 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
590 | if (ret) | |
591 | return ret; | |
6911a9b8 | 592 | |
05394f39 CW |
593 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
594 | if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) { | |
595 | seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset); | |
596 | i915_dump_object(m, dev_priv->mm.gtt_mapping, obj); | |
6911a9b8 BG |
597 | } |
598 | } | |
599 | ||
de227ef0 | 600 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
601 | return 0; |
602 | } | |
603 | ||
604 | static int i915_ringbuffer_data(struct seq_file *m, void *data) | |
605 | { | |
606 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
607 | struct drm_device *dev = node->minor->dev; | |
608 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 | 609 | struct intel_ring_buffer *ring; |
de227ef0 CW |
610 | int ret; |
611 | ||
612 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
613 | if (ret) | |
614 | return ret; | |
6911a9b8 | 615 | |
1ec14ad3 | 616 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
05394f39 | 617 | if (!ring->obj) { |
6911a9b8 | 618 | seq_printf(m, "No ringbuffer setup\n"); |
de227ef0 | 619 | } else { |
311bd68e | 620 | const u8 __iomem *virt = ring->virtual_start; |
de227ef0 | 621 | uint32_t off; |
6911a9b8 | 622 | |
c2c347a9 | 623 | for (off = 0; off < ring->size; off += 4) { |
de227ef0 CW |
624 | uint32_t *ptr = (uint32_t *)(virt + off); |
625 | seq_printf(m, "%08x : %08x\n", off, *ptr); | |
626 | } | |
6911a9b8 | 627 | } |
de227ef0 | 628 | mutex_unlock(&dev->struct_mutex); |
6911a9b8 BG |
629 | |
630 | return 0; | |
631 | } | |
632 | ||
633 | static int i915_ringbuffer_info(struct seq_file *m, void *data) | |
634 | { | |
635 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
636 | struct drm_device *dev = node->minor->dev; | |
637 | drm_i915_private_t *dev_priv = dev->dev_private; | |
c2c347a9 CW |
638 | struct intel_ring_buffer *ring; |
639 | ||
1ec14ad3 | 640 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
c2c347a9 | 641 | if (ring->size == 0) |
1ec14ad3 | 642 | return 0; |
6911a9b8 | 643 | |
c2c347a9 CW |
644 | seq_printf(m, "Ring %s:\n", ring->name); |
645 | seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR); | |
646 | seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR); | |
647 | seq_printf(m, " Size : %08x\n", ring->size); | |
648 | seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring)); | |
1ec14ad3 CW |
649 | seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring)); |
650 | if (IS_GEN6(dev)) { | |
651 | seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring)); | |
652 | seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring)); | |
653 | } | |
c2c347a9 CW |
654 | seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring)); |
655 | seq_printf(m, " Start : %08x\n", I915_READ_START(ring)); | |
6911a9b8 BG |
656 | |
657 | return 0; | |
658 | } | |
659 | ||
e5c65260 CW |
660 | static const char *ring_str(int ring) |
661 | { | |
662 | switch (ring) { | |
3685092b CW |
663 | case RING_RENDER: return " render"; |
664 | case RING_BSD: return " bsd"; | |
665 | case RING_BLT: return " blt"; | |
e5c65260 CW |
666 | default: return ""; |
667 | } | |
668 | } | |
669 | ||
9df30794 CW |
670 | static const char *pin_flag(int pinned) |
671 | { | |
672 | if (pinned > 0) | |
673 | return " P"; | |
674 | else if (pinned < 0) | |
675 | return " p"; | |
676 | else | |
677 | return ""; | |
678 | } | |
679 | ||
680 | static const char *tiling_flag(int tiling) | |
681 | { | |
682 | switch (tiling) { | |
683 | default: | |
684 | case I915_TILING_NONE: return ""; | |
685 | case I915_TILING_X: return " X"; | |
686 | case I915_TILING_Y: return " Y"; | |
687 | } | |
688 | } | |
689 | ||
690 | static const char *dirty_flag(int dirty) | |
691 | { | |
692 | return dirty ? " dirty" : ""; | |
693 | } | |
694 | ||
695 | static const char *purgeable_flag(int purgeable) | |
696 | { | |
697 | return purgeable ? " purgeable" : ""; | |
698 | } | |
699 | ||
c724e8a9 CW |
700 | static void print_error_buffers(struct seq_file *m, |
701 | const char *name, | |
702 | struct drm_i915_error_buffer *err, | |
703 | int count) | |
704 | { | |
705 | seq_printf(m, "%s [%d]:\n", name, count); | |
706 | ||
707 | while (count--) { | |
833bcb00 | 708 | seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s", |
c724e8a9 CW |
709 | err->gtt_offset, |
710 | err->size, | |
711 | err->read_domains, | |
712 | err->write_domain, | |
713 | err->seqno, | |
714 | pin_flag(err->pinned), | |
715 | tiling_flag(err->tiling), | |
716 | dirty_flag(err->dirty), | |
717 | purgeable_flag(err->purgeable), | |
a779e5ab | 718 | ring_str(err->ring), |
93dfb40c | 719 | cache_level_str(err->cache_level)); |
c724e8a9 CW |
720 | |
721 | if (err->name) | |
722 | seq_printf(m, " (name: %d)", err->name); | |
723 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
724 | seq_printf(m, " (fence: %d)", err->fence_reg); | |
725 | ||
726 | seq_printf(m, "\n"); | |
727 | err++; | |
728 | } | |
729 | } | |
730 | ||
63eeaf38 JB |
731 | static int i915_error_state(struct seq_file *m, void *unused) |
732 | { | |
733 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
734 | struct drm_device *dev = node->minor->dev; | |
735 | drm_i915_private_t *dev_priv = dev->dev_private; | |
736 | struct drm_i915_error_state *error; | |
737 | unsigned long flags; | |
9df30794 | 738 | int i, page, offset, elt; |
63eeaf38 JB |
739 | |
740 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
741 | if (!dev_priv->first_error) { | |
742 | seq_printf(m, "no error state collected\n"); | |
743 | goto out; | |
744 | } | |
745 | ||
746 | error = dev_priv->first_error; | |
747 | ||
8a905236 JB |
748 | seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
749 | error->time.tv_usec); | |
9df30794 | 750 | seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); |
1d8f38f4 CW |
751 | seq_printf(m, "EIR: 0x%08x\n", error->eir); |
752 | seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
f406839f CW |
753 | if (INTEL_INFO(dev)->gen >= 6) { |
754 | seq_printf(m, "ERROR: 0x%08x\n", error->error); | |
1d8f38f4 CW |
755 | seq_printf(m, "Blitter command stream:\n"); |
756 | seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd); | |
1d8f38f4 | 757 | seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir); |
e5c65260 | 758 | seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr); |
1d8f38f4 CW |
759 | seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone); |
760 | seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno); | |
add354dd CW |
761 | seq_printf(m, "Video (BSD) command stream:\n"); |
762 | seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd); | |
add354dd | 763 | seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir); |
e5c65260 | 764 | seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr); |
add354dd CW |
765 | seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone); |
766 | seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno); | |
f406839f | 767 | } |
1d8f38f4 CW |
768 | seq_printf(m, "Render command stream:\n"); |
769 | seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); | |
63eeaf38 JB |
770 | seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); |
771 | seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); | |
772 | seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); | |
a6c45cf0 | 773 | if (INTEL_INFO(dev)->gen >= 4) { |
63eeaf38 | 774 | seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); |
1d8f38f4 | 775 | seq_printf(m, " INSTPS: 0x%08x\n", error->instps); |
63eeaf38 | 776 | } |
1d8f38f4 CW |
777 | seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); |
778 | seq_printf(m, " seqno: 0x%08x\n", error->seqno); | |
9df30794 | 779 | |
bf3301ab | 780 | for (i = 0; i < dev_priv->num_fence_regs; i++) |
748ebc60 CW |
781 | seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); |
782 | ||
c724e8a9 CW |
783 | if (error->active_bo) |
784 | print_error_buffers(m, "Active", | |
785 | error->active_bo, | |
786 | error->active_bo_count); | |
787 | ||
788 | if (error->pinned_bo) | |
789 | print_error_buffers(m, "Pinned", | |
790 | error->pinned_bo, | |
791 | error->pinned_bo_count); | |
9df30794 CW |
792 | |
793 | for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) { | |
794 | if (error->batchbuffer[i]) { | |
795 | struct drm_i915_error_object *obj = error->batchbuffer[i]; | |
796 | ||
bcfb2e28 CW |
797 | seq_printf(m, "%s --- gtt_offset = 0x%08x\n", |
798 | dev_priv->ring[i].name, | |
799 | obj->gtt_offset); | |
9df30794 CW |
800 | offset = 0; |
801 | for (page = 0; page < obj->page_count; page++) { | |
802 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
803 | seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); | |
804 | offset += 4; | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
e2f973d5 CW |
810 | for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) { |
811 | if (error->ringbuffer[i]) { | |
812 | struct drm_i915_error_object *obj = error->ringbuffer[i]; | |
813 | seq_printf(m, "%s --- ringbuffer = 0x%08x\n", | |
814 | dev_priv->ring[i].name, | |
815 | obj->gtt_offset); | |
816 | offset = 0; | |
817 | for (page = 0; page < obj->page_count; page++) { | |
818 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
819 | seq_printf(m, "%08x : %08x\n", | |
820 | offset, | |
821 | obj->pages[page][elt]); | |
822 | offset += 4; | |
823 | } | |
9df30794 CW |
824 | } |
825 | } | |
826 | } | |
63eeaf38 | 827 | |
6ef3d427 CW |
828 | if (error->overlay) |
829 | intel_overlay_print_error_state(m, error->overlay); | |
830 | ||
c4a1d9e4 CW |
831 | if (error->display) |
832 | intel_display_print_error_state(m, dev, error->display); | |
833 | ||
63eeaf38 JB |
834 | out: |
835 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
836 | ||
837 | return 0; | |
838 | } | |
6911a9b8 | 839 | |
f97108d1 JB |
840 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
841 | { | |
842 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
843 | struct drm_device *dev = node->minor->dev; | |
844 | drm_i915_private_t *dev_priv = dev->dev_private; | |
845 | u16 crstanddelay = I915_READ16(CRSTANDVID); | |
846 | ||
847 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
852 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
853 | { | |
854 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
855 | struct drm_device *dev = node->minor->dev; | |
856 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 857 | int ret; |
3b8d8d91 JB |
858 | |
859 | if (IS_GEN5(dev)) { | |
860 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
861 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
862 | ||
863 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
864 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
865 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
866 | MEMSTAT_VID_SHIFT); | |
867 | seq_printf(m, "Current P-state: %d\n", | |
868 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
1c70c0ce | 869 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 JB |
870 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
871 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
872 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
ccab5c82 JB |
873 | u32 rpstat; |
874 | u32 rpupei, rpcurup, rpprevup; | |
875 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
876 | int max_freq; |
877 | ||
878 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
879 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
880 | if (ret) | |
881 | return ret; | |
882 | ||
fcca7926 | 883 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 884 | |
ccab5c82 JB |
885 | rpstat = I915_READ(GEN6_RPSTAT1); |
886 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
887 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
888 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
889 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
890 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
891 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
892 | ||
d1ebd816 BW |
893 | gen6_gt_force_wake_put(dev_priv); |
894 | mutex_unlock(&dev->struct_mutex); | |
895 | ||
3b8d8d91 | 896 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 897 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
898 | seq_printf(m, "Render p-state ratio: %d\n", |
899 | (gt_perf_status & 0xff00) >> 8); | |
900 | seq_printf(m, "Render p-state VID: %d\n", | |
901 | gt_perf_status & 0xff); | |
902 | seq_printf(m, "Render p-state limit: %d\n", | |
903 | rp_state_limits & 0xff); | |
ccab5c82 | 904 | seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> |
e281fcaa | 905 | GEN6_CAGF_SHIFT) * 50); |
ccab5c82 JB |
906 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
907 | GEN6_CURICONT_MASK); | |
908 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
909 | GEN6_CURBSYTAVG_MASK); | |
910 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
911 | GEN6_CURBSYTAVG_MASK); | |
912 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
913 | GEN6_CURIAVG_MASK); | |
914 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
915 | GEN6_CURBSYTAVG_MASK); | |
916 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
917 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
918 | |
919 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
920 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
e281fcaa | 921 | max_freq * 50); |
3b8d8d91 JB |
922 | |
923 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
924 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
e281fcaa | 925 | max_freq * 50); |
3b8d8d91 JB |
926 | |
927 | max_freq = rp_state_cap & 0xff; | |
928 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
e281fcaa | 929 | max_freq * 50); |
3b8d8d91 JB |
930 | } else { |
931 | seq_printf(m, "no P-state info available\n"); | |
932 | } | |
f97108d1 JB |
933 | |
934 | return 0; | |
935 | } | |
936 | ||
937 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
938 | { | |
939 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
940 | struct drm_device *dev = node->minor->dev; | |
941 | drm_i915_private_t *dev_priv = dev->dev_private; | |
942 | u32 delayfreq; | |
943 | int i; | |
944 | ||
945 | for (i = 0; i < 16; i++) { | |
946 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
947 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
948 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
949 | } |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
954 | static inline int MAP_TO_MV(int map) | |
955 | { | |
956 | return 1250 - (map * 25); | |
957 | } | |
958 | ||
959 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
960 | { | |
961 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
962 | struct drm_device *dev = node->minor->dev; | |
963 | drm_i915_private_t *dev_priv = dev->dev_private; | |
964 | u32 inttoext; | |
965 | int i; | |
966 | ||
967 | for (i = 1; i <= 32; i++) { | |
968 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
969 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
970 | } | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
975 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
976 | { | |
977 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
978 | struct drm_device *dev = node->minor->dev; | |
979 | drm_i915_private_t *dev_priv = dev->dev_private; | |
980 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
88271da3 | 981 | u32 rstdbyctl = I915_READ(RSTDBYCTL); |
7648fa99 | 982 | u16 crstandvid = I915_READ16(CRSTANDVID); |
f97108d1 JB |
983 | |
984 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
985 | "yes" : "no"); | |
986 | seq_printf(m, "Boost freq: %d\n", | |
987 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
988 | MEMMODE_BOOST_FREQ_SHIFT); | |
989 | seq_printf(m, "HW control enabled: %s\n", | |
990 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
991 | seq_printf(m, "SW control enabled: %s\n", | |
992 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
993 | seq_printf(m, "Gated voltage change: %s\n", | |
994 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
995 | seq_printf(m, "Starting frequency: P%d\n", | |
996 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 997 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 998 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
999 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1000 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1001 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1002 | seq_printf(m, "Render standby enabled: %s\n", | |
1003 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
88271da3 JB |
1004 | seq_printf(m, "Current RS state: "); |
1005 | switch (rstdbyctl & RSX_STATUS_MASK) { | |
1006 | case RSX_STATUS_ON: | |
1007 | seq_printf(m, "on\n"); | |
1008 | break; | |
1009 | case RSX_STATUS_RC1: | |
1010 | seq_printf(m, "RC1\n"); | |
1011 | break; | |
1012 | case RSX_STATUS_RC1E: | |
1013 | seq_printf(m, "RC1E\n"); | |
1014 | break; | |
1015 | case RSX_STATUS_RS1: | |
1016 | seq_printf(m, "RS1\n"); | |
1017 | break; | |
1018 | case RSX_STATUS_RS2: | |
1019 | seq_printf(m, "RS2 (RC6)\n"); | |
1020 | break; | |
1021 | case RSX_STATUS_RS3: | |
1022 | seq_printf(m, "RC3 (RC6+)\n"); | |
1023 | break; | |
1024 | default: | |
1025 | seq_printf(m, "unknown\n"); | |
1026 | break; | |
1027 | } | |
f97108d1 JB |
1028 | |
1029 | return 0; | |
1030 | } | |
1031 | ||
b5e50c3f JB |
1032 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1033 | { | |
1034 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1035 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1036 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1037 | |
ee5382ae | 1038 | if (!I915_HAS_FBC(dev)) { |
b5e50c3f JB |
1039 | seq_printf(m, "FBC unsupported on this chipset\n"); |
1040 | return 0; | |
1041 | } | |
1042 | ||
ee5382ae | 1043 | if (intel_fbc_enabled(dev)) { |
b5e50c3f JB |
1044 | seq_printf(m, "FBC enabled\n"); |
1045 | } else { | |
1046 | seq_printf(m, "FBC disabled: "); | |
1047 | switch (dev_priv->no_fbc_reason) { | |
bed4a673 CW |
1048 | case FBC_NO_OUTPUT: |
1049 | seq_printf(m, "no outputs"); | |
1050 | break; | |
b5e50c3f JB |
1051 | case FBC_STOLEN_TOO_SMALL: |
1052 | seq_printf(m, "not enough stolen memory"); | |
1053 | break; | |
1054 | case FBC_UNSUPPORTED_MODE: | |
1055 | seq_printf(m, "mode not supported"); | |
1056 | break; | |
1057 | case FBC_MODE_TOO_LARGE: | |
1058 | seq_printf(m, "mode too large"); | |
1059 | break; | |
1060 | case FBC_BAD_PLANE: | |
1061 | seq_printf(m, "FBC unsupported on plane"); | |
1062 | break; | |
1063 | case FBC_NOT_TILED: | |
1064 | seq_printf(m, "scanout buffer not tiled"); | |
1065 | break; | |
9c928d16 JB |
1066 | case FBC_MULTIPLE_PIPES: |
1067 | seq_printf(m, "multiple pipes are enabled"); | |
1068 | break; | |
c1a9f047 JB |
1069 | case FBC_MODULE_PARAM: |
1070 | seq_printf(m, "disabled per module param (default off)"); | |
1071 | break; | |
b5e50c3f JB |
1072 | default: |
1073 | seq_printf(m, "unknown reason"); | |
1074 | } | |
1075 | seq_printf(m, "\n"); | |
1076 | } | |
1077 | return 0; | |
1078 | } | |
1079 | ||
4a9bef37 JB |
1080 | static int i915_sr_status(struct seq_file *m, void *unused) |
1081 | { | |
1082 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1083 | struct drm_device *dev = node->minor->dev; | |
1084 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1085 | bool sr_enabled = false; | |
1086 | ||
1398261a | 1087 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1088 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1089 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1090 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1091 | else if (IS_I915GM(dev)) | |
1092 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1093 | else if (IS_PINEVIEW(dev)) | |
1094 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1095 | ||
5ba2aaaa CW |
1096 | seq_printf(m, "self-refresh: %s\n", |
1097 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1098 | |
1099 | return 0; | |
1100 | } | |
1101 | ||
7648fa99 JB |
1102 | static int i915_emon_status(struct seq_file *m, void *unused) |
1103 | { | |
1104 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1105 | struct drm_device *dev = node->minor->dev; | |
1106 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1107 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1108 | int ret; |
1109 | ||
1110 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1111 | if (ret) | |
1112 | return ret; | |
7648fa99 JB |
1113 | |
1114 | temp = i915_mch_val(dev_priv); | |
1115 | chipset = i915_chipset_val(dev_priv); | |
1116 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1117 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1118 | |
1119 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1120 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1121 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1122 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
23b2f8bb JB |
1127 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1128 | { | |
1129 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1130 | struct drm_device *dev = node->minor->dev; | |
1131 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1132 | int ret; | |
1133 | int gpu_freq, ia_freq; | |
1134 | ||
1c70c0ce | 1135 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
23b2f8bb JB |
1136 | seq_printf(m, "unsupported on this chipset\n"); |
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1141 | if (ret) | |
1142 | return ret; | |
1143 | ||
1144 | seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); | |
1145 | ||
1146 | for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; | |
1147 | gpu_freq++) { | |
1148 | I915_WRITE(GEN6_PCODE_DATA, gpu_freq); | |
1149 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
1150 | GEN6_PCODE_READ_MIN_FREQ_TABLE); | |
1151 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
1152 | GEN6_PCODE_READY) == 0, 10)) { | |
1153 | DRM_ERROR("pcode read of freq table timed out\n"); | |
1154 | continue; | |
1155 | } | |
1156 | ia_freq = I915_READ(GEN6_PCODE_DATA); | |
1157 | seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); | |
1158 | } | |
1159 | ||
1160 | mutex_unlock(&dev->struct_mutex); | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
7648fa99 JB |
1165 | static int i915_gfxec(struct seq_file *m, void *unused) |
1166 | { | |
1167 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1168 | struct drm_device *dev = node->minor->dev; | |
1169 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1170 | ||
1171 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1172 | ||
1173 | return 0; | |
1174 | } | |
1175 | ||
44834a67 CW |
1176 | static int i915_opregion(struct seq_file *m, void *unused) |
1177 | { | |
1178 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1179 | struct drm_device *dev = node->minor->dev; | |
1180 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1181 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1182 | int ret; | |
1183 | ||
1184 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1185 | if (ret) | |
1186 | return ret; | |
1187 | ||
1188 | if (opregion->header) | |
1189 | seq_write(m, opregion->header, OPREGION_SIZE); | |
1190 | ||
1191 | mutex_unlock(&dev->struct_mutex); | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
37811fcc CW |
1196 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1197 | { | |
1198 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1199 | struct drm_device *dev = node->minor->dev; | |
1200 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1201 | struct intel_fbdev *ifbdev; | |
1202 | struct intel_framebuffer *fb; | |
1203 | int ret; | |
1204 | ||
1205 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1206 | if (ret) | |
1207 | return ret; | |
1208 | ||
1209 | ifbdev = dev_priv->fbdev; | |
1210 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1211 | ||
1212 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", | |
1213 | fb->base.width, | |
1214 | fb->base.height, | |
1215 | fb->base.depth, | |
1216 | fb->base.bits_per_pixel); | |
05394f39 | 1217 | describe_obj(m, fb->obj); |
37811fcc CW |
1218 | seq_printf(m, "\n"); |
1219 | ||
1220 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { | |
1221 | if (&fb->base == ifbdev->helper.fb) | |
1222 | continue; | |
1223 | ||
1224 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", | |
1225 | fb->base.width, | |
1226 | fb->base.height, | |
1227 | fb->base.depth, | |
1228 | fb->base.bits_per_pixel); | |
05394f39 | 1229 | describe_obj(m, fb->obj); |
37811fcc CW |
1230 | seq_printf(m, "\n"); |
1231 | } | |
1232 | ||
1233 | mutex_unlock(&dev->mode_config.mutex); | |
1234 | ||
1235 | return 0; | |
1236 | } | |
1237 | ||
e76d3630 BW |
1238 | static int i915_context_status(struct seq_file *m, void *unused) |
1239 | { | |
1240 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1241 | struct drm_device *dev = node->minor->dev; | |
1242 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1243 | int ret; | |
1244 | ||
1245 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | ||
dc501fbc BW |
1249 | if (dev_priv->pwrctx) { |
1250 | seq_printf(m, "power context "); | |
1251 | describe_obj(m, dev_priv->pwrctx); | |
1252 | seq_printf(m, "\n"); | |
1253 | } | |
e76d3630 | 1254 | |
dc501fbc BW |
1255 | if (dev_priv->renderctx) { |
1256 | seq_printf(m, "render context "); | |
1257 | describe_obj(m, dev_priv->renderctx); | |
1258 | seq_printf(m, "\n"); | |
1259 | } | |
e76d3630 BW |
1260 | |
1261 | mutex_unlock(&dev->mode_config.mutex); | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
6d794d42 BW |
1266 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1267 | { | |
1268 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1269 | struct drm_device *dev = node->minor->dev; | |
1270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1271 | ||
1272 | seq_printf(m, "forcewake count = %d\n", | |
1273 | atomic_read(&dev_priv->forcewake_count)); | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
f3cd474b CW |
1278 | static int |
1279 | i915_wedged_open(struct inode *inode, | |
1280 | struct file *filp) | |
1281 | { | |
1282 | filp->private_data = inode->i_private; | |
1283 | return 0; | |
1284 | } | |
1285 | ||
1286 | static ssize_t | |
1287 | i915_wedged_read(struct file *filp, | |
1288 | char __user *ubuf, | |
1289 | size_t max, | |
1290 | loff_t *ppos) | |
1291 | { | |
1292 | struct drm_device *dev = filp->private_data; | |
1293 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1294 | char buf[80]; | |
1295 | int len; | |
1296 | ||
0206e353 | 1297 | len = snprintf(buf, sizeof(buf), |
f3cd474b CW |
1298 | "wedged : %d\n", |
1299 | atomic_read(&dev_priv->mm.wedged)); | |
1300 | ||
0206e353 AJ |
1301 | if (len > sizeof(buf)) |
1302 | len = sizeof(buf); | |
f4433a8d | 1303 | |
f3cd474b CW |
1304 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); |
1305 | } | |
1306 | ||
1307 | static ssize_t | |
1308 | i915_wedged_write(struct file *filp, | |
1309 | const char __user *ubuf, | |
1310 | size_t cnt, | |
1311 | loff_t *ppos) | |
1312 | { | |
1313 | struct drm_device *dev = filp->private_data; | |
f3cd474b CW |
1314 | char buf[20]; |
1315 | int val = 1; | |
1316 | ||
1317 | if (cnt > 0) { | |
0206e353 | 1318 | if (cnt > sizeof(buf) - 1) |
f3cd474b CW |
1319 | return -EINVAL; |
1320 | ||
1321 | if (copy_from_user(buf, ubuf, cnt)) | |
1322 | return -EFAULT; | |
1323 | buf[cnt] = 0; | |
1324 | ||
1325 | val = simple_strtoul(buf, NULL, 0); | |
1326 | } | |
1327 | ||
1328 | DRM_INFO("Manually setting wedged to %d\n", val); | |
527f9e90 | 1329 | i915_handle_error(dev, val); |
f3cd474b CW |
1330 | |
1331 | return cnt; | |
1332 | } | |
1333 | ||
1334 | static const struct file_operations i915_wedged_fops = { | |
1335 | .owner = THIS_MODULE, | |
1336 | .open = i915_wedged_open, | |
1337 | .read = i915_wedged_read, | |
1338 | .write = i915_wedged_write, | |
6038f373 | 1339 | .llseek = default_llseek, |
f3cd474b CW |
1340 | }; |
1341 | ||
358733e9 JB |
1342 | static int |
1343 | i915_max_freq_open(struct inode *inode, | |
1344 | struct file *filp) | |
1345 | { | |
1346 | filp->private_data = inode->i_private; | |
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | static ssize_t | |
1351 | i915_max_freq_read(struct file *filp, | |
1352 | char __user *ubuf, | |
1353 | size_t max, | |
1354 | loff_t *ppos) | |
1355 | { | |
1356 | struct drm_device *dev = filp->private_data; | |
1357 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1358 | char buf[80]; | |
1359 | int len; | |
1360 | ||
0206e353 | 1361 | len = snprintf(buf, sizeof(buf), |
358733e9 JB |
1362 | "max freq: %d\n", dev_priv->max_delay * 50); |
1363 | ||
0206e353 AJ |
1364 | if (len > sizeof(buf)) |
1365 | len = sizeof(buf); | |
358733e9 JB |
1366 | |
1367 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1368 | } | |
1369 | ||
1370 | static ssize_t | |
1371 | i915_max_freq_write(struct file *filp, | |
1372 | const char __user *ubuf, | |
1373 | size_t cnt, | |
1374 | loff_t *ppos) | |
1375 | { | |
1376 | struct drm_device *dev = filp->private_data; | |
1377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1378 | char buf[20]; | |
1379 | int val = 1; | |
1380 | ||
1381 | if (cnt > 0) { | |
0206e353 | 1382 | if (cnt > sizeof(buf) - 1) |
358733e9 JB |
1383 | return -EINVAL; |
1384 | ||
1385 | if (copy_from_user(buf, ubuf, cnt)) | |
1386 | return -EFAULT; | |
1387 | buf[cnt] = 0; | |
1388 | ||
1389 | val = simple_strtoul(buf, NULL, 0); | |
1390 | } | |
1391 | ||
1392 | DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); | |
1393 | ||
1394 | /* | |
1395 | * Turbo will still be enabled, but won't go above the set value. | |
1396 | */ | |
1397 | dev_priv->max_delay = val / 50; | |
1398 | ||
1399 | gen6_set_rps(dev, val / 50); | |
1400 | ||
1401 | return cnt; | |
1402 | } | |
1403 | ||
1404 | static const struct file_operations i915_max_freq_fops = { | |
1405 | .owner = THIS_MODULE, | |
1406 | .open = i915_max_freq_open, | |
1407 | .read = i915_max_freq_read, | |
1408 | .write = i915_max_freq_write, | |
1409 | .llseek = default_llseek, | |
1410 | }; | |
1411 | ||
07b7ddd9 JB |
1412 | static int |
1413 | i915_cache_sharing_open(struct inode *inode, | |
1414 | struct file *filp) | |
1415 | { | |
1416 | filp->private_data = inode->i_private; | |
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | static ssize_t | |
1421 | i915_cache_sharing_read(struct file *filp, | |
1422 | char __user *ubuf, | |
1423 | size_t max, | |
1424 | loff_t *ppos) | |
1425 | { | |
1426 | struct drm_device *dev = filp->private_data; | |
1427 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1428 | char buf[80]; | |
1429 | u32 snpcr; | |
1430 | int len; | |
1431 | ||
1432 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1433 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1434 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1435 | ||
0206e353 | 1436 | len = snprintf(buf, sizeof(buf), |
07b7ddd9 JB |
1437 | "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> |
1438 | GEN6_MBC_SNPCR_SHIFT); | |
1439 | ||
0206e353 AJ |
1440 | if (len > sizeof(buf)) |
1441 | len = sizeof(buf); | |
07b7ddd9 JB |
1442 | |
1443 | return simple_read_from_buffer(ubuf, max, ppos, buf, len); | |
1444 | } | |
1445 | ||
1446 | static ssize_t | |
1447 | i915_cache_sharing_write(struct file *filp, | |
1448 | const char __user *ubuf, | |
1449 | size_t cnt, | |
1450 | loff_t *ppos) | |
1451 | { | |
1452 | struct drm_device *dev = filp->private_data; | |
1453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1454 | char buf[20]; | |
1455 | u32 snpcr; | |
1456 | int val = 1; | |
1457 | ||
1458 | if (cnt > 0) { | |
0206e353 | 1459 | if (cnt > sizeof(buf) - 1) |
07b7ddd9 JB |
1460 | return -EINVAL; |
1461 | ||
1462 | if (copy_from_user(buf, ubuf, cnt)) | |
1463 | return -EFAULT; | |
1464 | buf[cnt] = 0; | |
1465 | ||
1466 | val = simple_strtoul(buf, NULL, 0); | |
1467 | } | |
1468 | ||
1469 | if (val < 0 || val > 3) | |
1470 | return -EINVAL; | |
1471 | ||
1472 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); | |
1473 | ||
1474 | /* Update the cache sharing policy here as well */ | |
1475 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1476 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1477 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1478 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1479 | ||
1480 | return cnt; | |
1481 | } | |
1482 | ||
1483 | static const struct file_operations i915_cache_sharing_fops = { | |
1484 | .owner = THIS_MODULE, | |
1485 | .open = i915_cache_sharing_open, | |
1486 | .read = i915_cache_sharing_read, | |
1487 | .write = i915_cache_sharing_write, | |
1488 | .llseek = default_llseek, | |
1489 | }; | |
1490 | ||
f3cd474b CW |
1491 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1492 | * allocated we need to hook into the minor for release. */ | |
1493 | static int | |
1494 | drm_add_fake_info_node(struct drm_minor *minor, | |
1495 | struct dentry *ent, | |
1496 | const void *key) | |
1497 | { | |
1498 | struct drm_info_node *node; | |
1499 | ||
1500 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
1501 | if (node == NULL) { | |
1502 | debugfs_remove(ent); | |
1503 | return -ENOMEM; | |
1504 | } | |
1505 | ||
1506 | node->minor = minor; | |
1507 | node->dent = ent; | |
1508 | node->info_ent = (void *) key; | |
1509 | list_add(&node->list, &minor->debugfs_nodes.list); | |
1510 | ||
1511 | return 0; | |
1512 | } | |
1513 | ||
1514 | static int i915_wedged_create(struct dentry *root, struct drm_minor *minor) | |
1515 | { | |
1516 | struct drm_device *dev = minor->dev; | |
1517 | struct dentry *ent; | |
1518 | ||
1519 | ent = debugfs_create_file("i915_wedged", | |
1520 | S_IRUGO | S_IWUSR, | |
1521 | root, dev, | |
1522 | &i915_wedged_fops); | |
1523 | if (IS_ERR(ent)) | |
1524 | return PTR_ERR(ent); | |
1525 | ||
1526 | return drm_add_fake_info_node(minor, ent, &i915_wedged_fops); | |
1527 | } | |
9e3a6d15 | 1528 | |
6d794d42 BW |
1529 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
1530 | { | |
1531 | struct drm_device *dev = inode->i_private; | |
1532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1533 | int ret; | |
1534 | ||
1535 | if (!IS_GEN6(dev)) | |
1536 | return 0; | |
1537 | ||
1538 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1539 | if (ret) | |
1540 | return ret; | |
1541 | gen6_gt_force_wake_get(dev_priv); | |
1542 | mutex_unlock(&dev->struct_mutex); | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | int i915_forcewake_release(struct inode *inode, struct file *file) | |
1548 | { | |
1549 | struct drm_device *dev = inode->i_private; | |
1550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1551 | ||
1552 | if (!IS_GEN6(dev)) | |
1553 | return 0; | |
1554 | ||
1555 | /* | |
1556 | * It's bad that we can potentially hang userspace if struct_mutex gets | |
1557 | * forever stuck. However, if we cannot acquire this lock it means that | |
1558 | * almost certainly the driver has hung, is not unload-able. Therefore | |
1559 | * hanging here is probably a minor inconvenience not to be seen my | |
1560 | * almost every user. | |
1561 | */ | |
1562 | mutex_lock(&dev->struct_mutex); | |
1563 | gen6_gt_force_wake_put(dev_priv); | |
1564 | mutex_unlock(&dev->struct_mutex); | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | static const struct file_operations i915_forcewake_fops = { | |
1570 | .owner = THIS_MODULE, | |
1571 | .open = i915_forcewake_open, | |
1572 | .release = i915_forcewake_release, | |
1573 | }; | |
1574 | ||
1575 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
1576 | { | |
1577 | struct drm_device *dev = minor->dev; | |
1578 | struct dentry *ent; | |
1579 | ||
1580 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 1581 | S_IRUSR, |
6d794d42 BW |
1582 | root, dev, |
1583 | &i915_forcewake_fops); | |
1584 | if (IS_ERR(ent)) | |
1585 | return PTR_ERR(ent); | |
1586 | ||
8eb57294 | 1587 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
1588 | } |
1589 | ||
358733e9 JB |
1590 | static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor) |
1591 | { | |
1592 | struct drm_device *dev = minor->dev; | |
1593 | struct dentry *ent; | |
1594 | ||
1595 | ent = debugfs_create_file("i915_max_freq", | |
1596 | S_IRUGO | S_IWUSR, | |
1597 | root, dev, | |
1598 | &i915_max_freq_fops); | |
1599 | if (IS_ERR(ent)) | |
1600 | return PTR_ERR(ent); | |
1601 | ||
1602 | return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops); | |
1603 | } | |
1604 | ||
07b7ddd9 JB |
1605 | static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor) |
1606 | { | |
1607 | struct drm_device *dev = minor->dev; | |
1608 | struct dentry *ent; | |
1609 | ||
1610 | ent = debugfs_create_file("i915_cache_sharing", | |
1611 | S_IRUGO | S_IWUSR, | |
1612 | root, dev, | |
1613 | &i915_cache_sharing_fops); | |
1614 | if (IS_ERR(ent)) | |
1615 | return PTR_ERR(ent); | |
1616 | ||
1617 | return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops); | |
1618 | } | |
1619 | ||
27c202ad | 1620 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 1621 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 1622 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 1623 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
433e12f7 BG |
1624 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
1625 | {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, | |
1626 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, | |
f13d3f73 | 1627 | {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST}, |
d21d5975 | 1628 | {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST}, |
4e5359cd | 1629 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
1630 | {"i915_gem_request", i915_gem_request_info, 0}, |
1631 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 1632 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 1633 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
1634 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
1635 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
1636 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
1637 | {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS}, | |
1638 | {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS}, | |
1639 | {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS}, | |
1640 | {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS}, | |
1641 | {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS}, | |
1642 | {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS}, | |
6911a9b8 | 1643 | {"i915_batchbuffers", i915_batchbuffer_info, 0}, |
63eeaf38 | 1644 | {"i915_error_state", i915_error_state, 0}, |
f97108d1 JB |
1645 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
1646 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
1647 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
1648 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
1649 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 1650 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 1651 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 1652 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 1653 | {"i915_fbc_status", i915_fbc_status, 0}, |
4a9bef37 | 1654 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 1655 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 1656 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 1657 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 1658 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
2017263e | 1659 | }; |
27c202ad | 1660 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 1661 | |
27c202ad | 1662 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 1663 | { |
f3cd474b CW |
1664 | int ret; |
1665 | ||
1666 | ret = i915_wedged_create(minor->debugfs_root, minor); | |
1667 | if (ret) | |
1668 | return ret; | |
1669 | ||
6d794d42 | 1670 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
1671 | if (ret) |
1672 | return ret; | |
1673 | ret = i915_max_freq_create(minor->debugfs_root, minor); | |
07b7ddd9 JB |
1674 | if (ret) |
1675 | return ret; | |
1676 | ret = i915_cache_sharing_create(minor->debugfs_root, minor); | |
6d794d42 BW |
1677 | if (ret) |
1678 | return ret; | |
1679 | ||
27c202ad BG |
1680 | return drm_debugfs_create_files(i915_debugfs_list, |
1681 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
1682 | minor->debugfs_root, minor); |
1683 | } | |
1684 | ||
27c202ad | 1685 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 1686 | { |
27c202ad BG |
1687 | drm_debugfs_remove_files(i915_debugfs_list, |
1688 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
1689 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
1690 | 1, minor); | |
33db679b KH |
1691 | drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, |
1692 | 1, minor); | |
358733e9 JB |
1693 | drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, |
1694 | 1, minor); | |
07b7ddd9 JB |
1695 | drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, |
1696 | 1, minor); | |
2017263e BG |
1697 | } |
1698 | ||
1699 | #endif /* CONFIG_DEBUG_FS */ |