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drm/i915: make i915_seqno_passed non-static
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CommitLineData
1da177e4
LT
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
585fb111 33#include "i915_reg.h"
79e53945 34#include "intel_bios.h"
0839ccb8 35#include <linux/io-mapping.h>
585fb111 36
1da177e4
LT
37/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
673a394b 44#define DRIVER_DATE "20080730"
1da177e4 45
317c35d1
JB
46enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
80824003
JB
51enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54};
55
52440211
KP
56#define I915_NUM_PIPE 2
57
1da177e4
LT
58/* Interface history:
59 *
60 * 1.1: Original.
0d6aa60b
DA
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
de227f5f 63 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 64 * 1.5: Add vblank pipe configuration
2228ed67
MD
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
1da177e4
LT
67 */
68#define DRIVER_MAJOR 1
2228ed67 69#define DRIVER_MINOR 6
1da177e4
LT
70#define DRIVER_PATCHLEVEL 0
71
673a394b
EA
72#define WATCH_COHERENCY 0
73#define WATCH_BUF 0
74#define WATCH_EXEC 0
75#define WATCH_LRU 0
76#define WATCH_RELOC 0
77#define WATCH_INACTIVE 0
78#define WATCH_PWRITE 0
79
71acb5eb
DA
80#define I915_GEM_PHYS_CURSOR_0 1
81#define I915_GEM_PHYS_CURSOR_1 2
82#define I915_GEM_PHYS_OVERLAY_REGS 3
83#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90};
91
1da177e4 92typedef struct _drm_i915_ring_buffer {
1da177e4
LT
93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
673a394b 99 struct drm_gem_object *ring_obj;
1da177e4
LT
100} drm_i915_ring_buffer_t;
101
102struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
6c340eac 107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT
108};
109
0a3e67a4
JB
110struct opregion_header;
111struct opregion_acpi;
112struct opregion_swsci;
113struct opregion_asle;
114
8ee1c3db
MG
115struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121};
122
7c1c2871
DA
123struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126};
de151cf6
JB
127#define I915_FENCE_REG_NONE -1
128
129struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131};
7c1c2871 132
9b9d172d 133struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138};
139
63eeaf38
JB
140struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154};
155
1da177e4 156typedef struct drm_i915_private {
673a394b
EA
157 struct drm_device *dev;
158
ac5c4e76
DA
159 int has_gem;
160
3043c60c 161 void __iomem *regs;
1da177e4 162
ec2a4c3f 163 struct pci_dev *bridge_dev;
1da177e4
LT
164 drm_i915_ring_buffer_t ring;
165
9c8da5eb 166 drm_dma_handle_t *status_page_dmah;
1da177e4 167 void *hw_status_page;
1da177e4 168 dma_addr_t dma_status_page;
0a3e67a4 169 uint32_t counter;
dc7a9319
WZ
170 unsigned int status_gfx_addr;
171 drm_local_map_t hws_map;
673a394b 172 struct drm_gem_object *hws_obj;
1da177e4 173
d7658989
JB
174 struct resource mch_res;
175
a6b54f3f 176 unsigned int cpp;
1da177e4
LT
177 int back_offset;
178 int front_offset;
179 int current_page;
180 int page_flipping;
1da177e4
LT
181
182 wait_queue_head_t irq_queue;
183 atomic_t irq_received;
ed4cb414
EA
184 /** Protects user_irq_refcount and irq_mask_reg */
185 spinlock_t user_irq_lock;
186 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
187 int user_irq_refcount;
188 /** Cached value of IMR to avoid reads in updating the bitfield */
189 u32 irq_mask_reg;
7c463586 190 u32 pipestat[2];
036a4a7d
ZW
191 /** splitted irq regs for graphics and display engine on IGDNG,
192 irq_mask_reg is still used for display irq. */
193 u32 gt_irq_mask_reg;
194 u32 gt_irq_enable_reg;
195 u32 de_irq_enable_reg;
1da177e4 196
5ca58282
JB
197 u32 hotplug_supported_mask;
198 struct work_struct hotplug_work;
199
1da177e4
LT
200 int tex_lru_log_granularity;
201 int allow_batchbuffer;
202 struct mem_block *agp_heap;
0d6aa60b 203 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2 204 int vblank_pipe;
a6b54f3f 205
79e53945
JB
206 bool cursor_needs_physical;
207
208 struct drm_mm vram;
209
80824003
JB
210 unsigned long cfb_size;
211 unsigned long cfb_pitch;
212 int cfb_fence;
213 int cfb_plane;
214
79e53945
JB
215 int irq_enabled;
216
8ee1c3db
MG
217 struct intel_opregion opregion;
218
79e53945
JB
219 /* LVDS info */
220 int backlight_duty_cycle; /* restore backlight to this value */
221 bool panel_wants_dither;
222 struct drm_display_mode *panel_fixed_mode;
88631706
ML
223 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
224 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
79e53945
JB
225
226 /* Feature bits from the VBIOS */
95281e35
HE
227 unsigned int int_tv_support:1;
228 unsigned int lvds_dither:1;
229 unsigned int lvds_vbt:1;
230 unsigned int int_crt_support:1;
43565a06 231 unsigned int lvds_use_ssc:1;
32f9d658 232 unsigned int edp_support:1;
43565a06 233 int lvds_ssc_freq;
79e53945 234
c1c7af60
JB
235 struct notifier_block lid_notifier;
236
db545019 237 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
de151cf6
JB
238 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
239 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
240 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
241
7662c8bd
SL
242 unsigned int fsb_freq, mem_freq;
243
63eeaf38
JB
244 spinlock_t error_lock;
245 struct drm_i915_error_state *first_error;
8a905236 246 struct work_struct error_work;
9c9fe1f8 247 struct workqueue_struct *wq;
63eeaf38 248
ba8bbcf6
JB
249 /* Register state */
250 u8 saveLBB;
251 u32 saveDSPACNTR;
252 u32 saveDSPBCNTR;
e948e994 253 u32 saveDSPARB;
881ee988 254 u32 saveRENDERSTANDBY;
461cba2d 255 u32 saveHWS;
ba8bbcf6
JB
256 u32 savePIPEACONF;
257 u32 savePIPEBCONF;
258 u32 savePIPEASRC;
259 u32 savePIPEBSRC;
260 u32 saveFPA0;
261 u32 saveFPA1;
262 u32 saveDPLL_A;
263 u32 saveDPLL_A_MD;
264 u32 saveHTOTAL_A;
265 u32 saveHBLANK_A;
266 u32 saveHSYNC_A;
267 u32 saveVTOTAL_A;
268 u32 saveVBLANK_A;
269 u32 saveVSYNC_A;
270 u32 saveBCLRPAT_A;
0da3ea12 271 u32 savePIPEASTAT;
ba8bbcf6
JB
272 u32 saveDSPASTRIDE;
273 u32 saveDSPASIZE;
274 u32 saveDSPAPOS;
585fb111 275 u32 saveDSPAADDR;
ba8bbcf6
JB
276 u32 saveDSPASURF;
277 u32 saveDSPATILEOFF;
278 u32 savePFIT_PGM_RATIOS;
279 u32 saveBLC_PWM_CTL;
280 u32 saveBLC_PWM_CTL2;
281 u32 saveFPB0;
282 u32 saveFPB1;
283 u32 saveDPLL_B;
284 u32 saveDPLL_B_MD;
285 u32 saveHTOTAL_B;
286 u32 saveHBLANK_B;
287 u32 saveHSYNC_B;
288 u32 saveVTOTAL_B;
289 u32 saveVBLANK_B;
290 u32 saveVSYNC_B;
291 u32 saveBCLRPAT_B;
0da3ea12 292 u32 savePIPEBSTAT;
ba8bbcf6
JB
293 u32 saveDSPBSTRIDE;
294 u32 saveDSPBSIZE;
295 u32 saveDSPBPOS;
585fb111 296 u32 saveDSPBADDR;
ba8bbcf6
JB
297 u32 saveDSPBSURF;
298 u32 saveDSPBTILEOFF;
585fb111
JB
299 u32 saveVGA0;
300 u32 saveVGA1;
301 u32 saveVGA_PD;
ba8bbcf6
JB
302 u32 saveVGACNTRL;
303 u32 saveADPA;
304 u32 saveLVDS;
585fb111
JB
305 u32 savePP_ON_DELAYS;
306 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB
307 u32 saveDVOA;
308 u32 saveDVOB;
309 u32 saveDVOC;
310 u32 savePP_ON;
311 u32 savePP_OFF;
312 u32 savePP_CONTROL;
585fb111 313 u32 savePP_DIVISOR;
ba8bbcf6
JB
314 u32 savePFIT_CONTROL;
315 u32 save_palette_a[256];
316 u32 save_palette_b[256];
317 u32 saveFBC_CFB_BASE;
318 u32 saveFBC_LL_BASE;
319 u32 saveFBC_CONTROL;
320 u32 saveFBC_CONTROL2;
0da3ea12
JB
321 u32 saveIER;
322 u32 saveIIR;
323 u32 saveIMR;
1f84e550 324 u32 saveCACHE_MODE_0;
e948e994 325 u32 saveD_STATE;
652c393a 326 u32 saveDSPCLK_GATE_D;
1f84e550 327 u32 saveMI_ARB_STATE;
ba8bbcf6
JB
328 u32 saveSWF0[16];
329 u32 saveSWF1[16];
330 u32 saveSWF2[3];
331 u8 saveMSR;
332 u8 saveSR[8];
123f794f 333 u8 saveGR[25];
ba8bbcf6 334 u8 saveAR_INDEX;
a59e122a 335 u8 saveAR[21];
ba8bbcf6 336 u8 saveDACMASK;
a59e122a 337 u8 saveCR[37];
79f11c19 338 uint64_t saveFENCE[16];
1fd1c624
EA
339 u32 saveCURACNTR;
340 u32 saveCURAPOS;
341 u32 saveCURABASE;
342 u32 saveCURBCNTR;
343 u32 saveCURBPOS;
344 u32 saveCURBBASE;
345 u32 saveCURSIZE;
a4fc5ed6
KP
346 u32 saveDP_B;
347 u32 saveDP_C;
348 u32 saveDP_D;
349 u32 savePIPEA_GMCH_DATA_M;
350 u32 savePIPEB_GMCH_DATA_M;
351 u32 savePIPEA_GMCH_DATA_N;
352 u32 savePIPEB_GMCH_DATA_N;
353 u32 savePIPEA_DP_LINK_M;
354 u32 savePIPEB_DP_LINK_M;
355 u32 savePIPEA_DP_LINK_N;
356 u32 savePIPEB_DP_LINK_N;
673a394b
EA
357
358 struct {
359 struct drm_mm gtt_space;
360
0839ccb8 361 struct io_mapping *gtt_mapping;
ab657db1 362 int gtt_mtrr;
0839ccb8 363
673a394b
EA
364 /**
365 * List of objects currently involved in rendering from the
366 * ringbuffer.
367 *
ce44b0ea
EA
368 * Includes buffers having the contents of their GPU caches
369 * flushed, not necessarily primitives. last_rendering_seqno
370 * represents when the rendering involved will be completed.
371 *
673a394b
EA
372 * A reference is held on the buffer while on this list.
373 */
5e118f41 374 spinlock_t active_list_lock;
673a394b
EA
375 struct list_head active_list;
376
377 /**
378 * List of objects which are not in the ringbuffer but which
379 * still have a write_domain which needs to be flushed before
380 * unbinding.
381 *
ce44b0ea
EA
382 * last_rendering_seqno is 0 while an object is in this list.
383 *
673a394b
EA
384 * A reference is held on the buffer while on this list.
385 */
386 struct list_head flushing_list;
387
388 /**
389 * LRU list of objects which are not in the ringbuffer and
390 * are ready to unbind, but are still in the GTT.
391 *
ce44b0ea
EA
392 * last_rendering_seqno is 0 while an object is in this list.
393 *
673a394b
EA
394 * A reference is not held on the buffer while on this list,
395 * as merely being GTT-bound shouldn't prevent its being
396 * freed, and we'll pull it off the list in the free path.
397 */
398 struct list_head inactive_list;
399
a09ba7fa
EA
400 /** LRU list of objects with fence regs on them. */
401 struct list_head fence_list;
402
673a394b
EA
403 /**
404 * List of breadcrumbs associated with GPU requests currently
405 * outstanding.
406 */
407 struct list_head request_list;
408
409 /**
410 * We leave the user IRQ off as much as possible,
411 * but this means that requests will finish and never
412 * be retired once the system goes idle. Set a timer to
413 * fire periodically while the ring is running. When it
414 * fires, go retire requests.
415 */
416 struct delayed_work retire_work;
417
418 uint32_t next_gem_seqno;
419
420 /**
421 * Waiting sequence number, if any
422 */
423 uint32_t waiting_gem_seqno;
424
425 /**
426 * Last seq seen at irq time
427 */
428 uint32_t irq_gem_seqno;
429
430 /**
431 * Flag if the X Server, and thus DRM, is not currently in
432 * control of the device.
433 *
434 * This is set between LeaveVT and EnterVT. It needs to be
435 * replaced with a semaphore. It also needs to be
436 * transitioned away from for kernel modesetting.
437 */
438 int suspended;
439
440 /**
441 * Flag if the hardware appears to be wedged.
442 *
443 * This is set when attempts to idle the device timeout.
444 * It prevents command submission from occuring and makes
445 * every pending request fail
446 */
447 int wedged;
448
449 /** Bit 6 swizzling required for X tiling */
450 uint32_t bit_6_swizzle_x;
451 /** Bit 6 swizzling required for Y tiling */
452 uint32_t bit_6_swizzle_y;
71acb5eb
DA
453
454 /* storage for physical objects */
455 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
673a394b 456 } mm;
9b9d172d 457 struct sdvo_device_mapping sdvo_mappings[2];
652c393a
JB
458
459 /* Reclocking support */
460 bool render_reclock_avail;
461 bool lvds_downclock_avail;
462 struct work_struct idle_work;
463 struct timer_list idle_timer;
464 bool busy;
465 u16 orig_clock;
1da177e4
LT
466} drm_i915_private_t;
467
673a394b
EA
468/** driver private structure attached to each drm_gem_object */
469struct drm_i915_gem_object {
470 struct drm_gem_object *obj;
471
472 /** Current space allocated to this object in the GTT, if any. */
473 struct drm_mm_node *gtt_space;
474
475 /** This object's place on the active/flushing/inactive lists */
476 struct list_head list;
477
a09ba7fa
EA
478 /** This object's place on the fenced object LRU */
479 struct list_head fence_list;
480
673a394b
EA
481 /**
482 * This is set if the object is on the active or flushing lists
483 * (has pending rendering), and is not set if it's on inactive (ready
484 * to be unbound).
485 */
486 int active;
487
488 /**
489 * This is set if the object has been written to since last bound
490 * to the GTT
491 */
492 int dirty;
493
494 /** AGP memory structure for our GTT binding. */
495 DRM_AGP_MEM *agp_mem;
496
856fa198
EA
497 struct page **pages;
498 int pages_refcount;
673a394b
EA
499
500 /**
501 * Current offset of the object in GTT space.
502 *
503 * This is the same as gtt_space->start
504 */
505 uint32_t gtt_offset;
de151cf6
JB
506 /**
507 * Required alignment for the object
508 */
509 uint32_t gtt_alignment;
510 /**
511 * Fake offset for use by mmap(2)
512 */
513 uint64_t mmap_offset;
514
515 /**
516 * Fence register bits (if any) for this object. Will be set
517 * as needed when mapped into the GTT.
518 * Protected by dev->struct_mutex.
519 */
520 int fence_reg;
673a394b 521
673a394b
EA
522 /** How many users have pinned this object in GTT space */
523 int pin_count;
524
525 /** Breadcrumb of last rendering to the buffer. */
526 uint32_t last_rendering_seqno;
527
528 /** Current tiling mode for the object. */
529 uint32_t tiling_mode;
de151cf6 530 uint32_t stride;
673a394b 531
280b713b
EA
532 /** Record of address bit 17 of each page at last unbind. */
533 long *bit_17;
534
ba1eb1d8
KP
535 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
536 uint32_t agp_type;
537
673a394b 538 /**
e47c68e9
EA
539 * If present, while GEM_DOMAIN_CPU is in the read domain this array
540 * flags which individual pages are valid.
673a394b
EA
541 */
542 uint8_t *page_cpu_valid;
79e53945
JB
543
544 /** User space pin count and filp owning the pin */
545 uint32_t user_pin_count;
546 struct drm_file *pin_filp;
71acb5eb
DA
547
548 /** for phy allocated objects */
549 struct drm_i915_gem_phys_object *phys_obj;
b70d11da
KH
550
551 /**
552 * Used for checking the object doesn't appear more than once
553 * in an execbuffer object list.
554 */
555 int in_execbuffer;
673a394b
EA
556};
557
558/**
559 * Request queue structure.
560 *
561 * The request queue allows us to note sequence numbers that have been emitted
562 * and may be associated with active buffers to be retired.
563 *
564 * By keeping this list, we can avoid having to do questionable
565 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
566 * an emission time with seqnos for tracking how far ahead of the GPU we are.
567 */
568struct drm_i915_gem_request {
569 /** GEM sequence number associated with this request. */
570 uint32_t seqno;
571
572 /** Time at which this request was emitted, in jiffies. */
573 unsigned long emitted_jiffies;
574
b962442e 575 /** global list entry for this request */
673a394b 576 struct list_head list;
b962442e
EA
577
578 /** file_priv list entry for this request */
579 struct list_head client_list;
673a394b
EA
580};
581
582struct drm_i915_file_private {
583 struct {
b962442e 584 struct list_head request_list;
673a394b
EA
585 } mm;
586};
587
79e53945
JB
588enum intel_chip_family {
589 CHIP_I8XX = 0x01,
590 CHIP_I9XX = 0x02,
591 CHIP_I915 = 0x04,
592 CHIP_I965 = 0x08,
593};
594
c153f45f 595extern struct drm_ioctl_desc i915_ioctls[];
b3a83639 596extern int i915_max_ioctl;
79e53945 597extern unsigned int i915_fbpercrtc;
652c393a 598extern unsigned int i915_powersave;
b3a83639 599
1341d655
BG
600extern void i915_save_display(struct drm_device *dev);
601extern void i915_restore_display(struct drm_device *dev);
7c1c2871
DA
602extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
603extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
604
1da177e4 605 /* i915_dma.c */
84b1fd10 606extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 607extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 608extern int i915_driver_unload(struct drm_device *);
673a394b 609extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
84b1fd10 610extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac
EA
611extern void i915_driver_preclose(struct drm_device *dev,
612 struct drm_file *file_priv);
673a394b
EA
613extern void i915_driver_postclose(struct drm_device *dev,
614 struct drm_file *file_priv);
84b1fd10 615extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b
DA
616extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
617 unsigned long arg);
673a394b 618extern int i915_emit_box(struct drm_device *dev,
201361a5 619 struct drm_clip_rect *boxes,
673a394b 620 int i, int DR1, int DR4);
af6061af 621
1da177e4 622/* i915_irq.c */
c153f45f
EA
623extern int i915_irq_emit(struct drm_device *dev, void *data,
624 struct drm_file *file_priv);
625extern int i915_irq_wait(struct drm_device *dev, void *data,
626 struct drm_file *file_priv);
673a394b
EA
627void i915_user_irq_get(struct drm_device *dev);
628void i915_user_irq_put(struct drm_device *dev);
79e53945 629extern void i915_enable_interrupt (struct drm_device *dev);
1da177e4
LT
630
631extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 632extern void i915_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 633extern int i915_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 634extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f
EA
635extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
636 struct drm_file *file_priv);
637extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
638 struct drm_file *file_priv);
0a3e67a4
JB
639extern int i915_enable_vblank(struct drm_device *dev, int crtc);
640extern void i915_disable_vblank(struct drm_device *dev, int crtc);
641extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
9880b7a5 642extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
c153f45f
EA
643extern int i915_vblank_swap(struct drm_device *dev, void *data,
644 struct drm_file *file_priv);
8ee1c3db 645extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1da177e4 646
7c463586
KP
647void
648i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
649
650void
651i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
652
653
1da177e4 654/* i915_mem.c */
c153f45f
EA
655extern int i915_mem_alloc(struct drm_device *dev, void *data,
656 struct drm_file *file_priv);
657extern int i915_mem_free(struct drm_device *dev, void *data,
658 struct drm_file *file_priv);
659extern int i915_mem_init_heap(struct drm_device *dev, void *data,
660 struct drm_file *file_priv);
661extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
662 struct drm_file *file_priv);
1da177e4 663extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10 664extern void i915_mem_release(struct drm_device * dev,
6c340eac 665 struct drm_file *file_priv, struct mem_block *heap);
673a394b
EA
666/* i915_gem.c */
667int i915_gem_init_ioctl(struct drm_device *dev, void *data,
668 struct drm_file *file_priv);
669int i915_gem_create_ioctl(struct drm_device *dev, void *data,
670 struct drm_file *file_priv);
671int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
672 struct drm_file *file_priv);
673int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
674 struct drm_file *file_priv);
675int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
de151cf6
JB
677int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
673a394b
EA
679int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
680 struct drm_file *file_priv);
681int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
682 struct drm_file *file_priv);
683int i915_gem_execbuffer(struct drm_device *dev, void *data,
684 struct drm_file *file_priv);
685int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
686 struct drm_file *file_priv);
687int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
688 struct drm_file *file_priv);
689int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
690 struct drm_file *file_priv);
691int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
692 struct drm_file *file_priv);
693int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
694 struct drm_file *file_priv);
695int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
696 struct drm_file *file_priv);
697int i915_gem_set_tiling(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699int i915_gem_get_tiling(struct drm_device *dev, void *data,
700 struct drm_file *file_priv);
5a125c3c
EA
701int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
702 struct drm_file *file_priv);
673a394b 703void i915_gem_load(struct drm_device *dev);
673a394b
EA
704int i915_gem_init_object(struct drm_gem_object *obj);
705void i915_gem_free_object(struct drm_gem_object *obj);
706int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
707void i915_gem_object_unpin(struct drm_gem_object *obj);
0f973f27 708int i915_gem_object_unbind(struct drm_gem_object *obj);
d05ca301 709void i915_gem_release_mmap(struct drm_gem_object *obj);
673a394b
EA
710void i915_gem_lastclose(struct drm_device *dev);
711uint32_t i915_get_gem_seqno(struct drm_device *dev);
22be1724 712bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
8c4b8c3f 713int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
52dc7d32 714int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
673a394b
EA
715void i915_gem_retire_requests(struct drm_device *dev);
716void i915_gem_retire_work_handler(struct work_struct *work);
717void i915_gem_clflush_object(struct drm_gem_object *obj);
79e53945
JB
718int i915_gem_object_set_domain(struct drm_gem_object *obj,
719 uint32_t read_domains,
720 uint32_t write_domain);
721int i915_gem_init_ringbuffer(struct drm_device *dev);
722void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
723int i915_gem_do_init(struct drm_device *dev, unsigned long start,
724 unsigned long end);
5669fcac 725int i915_gem_idle(struct drm_device *dev);
de151cf6 726int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
79e53945
JB
727int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
728 int write);
71acb5eb
DA
729int i915_gem_attach_phys_object(struct drm_device *dev,
730 struct drm_gem_object *obj, int id);
731void i915_gem_detach_phys_object(struct drm_device *dev,
732 struct drm_gem_object *obj);
733void i915_gem_free_all_phys_object(struct drm_device *dev);
6911a9b8
BG
734int i915_gem_object_get_pages(struct drm_gem_object *obj);
735void i915_gem_object_put_pages(struct drm_gem_object *obj);
1fd1c624 736void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
673a394b
EA
737
738/* i915_gem_tiling.c */
739void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
280b713b
EA
740void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
741void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
673a394b
EA
742
743/* i915_gem_debug.c */
744void i915_gem_dump_object(struct drm_gem_object *obj, int len,
745 const char *where, uint32_t mark);
746#if WATCH_INACTIVE
747void i915_verify_inactive(struct drm_device *dev, char *file, int line);
748#else
749#define i915_verify_inactive(dev, file, line)
750#endif
751void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
752void i915_gem_dump_object(struct drm_gem_object *obj, int len,
753 const char *where, uint32_t mark);
754void i915_dump_lru(struct drm_device *dev, const char *where);
1da177e4 755
2017263e 756/* i915_debugfs.c */
27c202ad
BG
757int i915_debugfs_init(struct drm_minor *minor);
758void i915_debugfs_cleanup(struct drm_minor *minor);
2017263e 759
317c35d1
JB
760/* i915_suspend.c */
761extern int i915_save_state(struct drm_device *dev);
762extern int i915_restore_state(struct drm_device *dev);
0a3e67a4
JB
763
764/* i915_suspend.c */
765extern int i915_save_state(struct drm_device *dev);
766extern int i915_restore_state(struct drm_device *dev);
317c35d1 767
65e082c9 768#ifdef CONFIG_ACPI
8ee1c3db 769/* i915_opregion.c */
74a365b3 770extern int intel_opregion_init(struct drm_device *dev, int resume);
3b1c1c11 771extern void intel_opregion_free(struct drm_device *dev, int suspend);
8ee1c3db
MG
772extern void opregion_asle_intr(struct drm_device *dev);
773extern void opregion_enable_asle(struct drm_device *dev);
65e082c9 774#else
03ae61dd 775static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
3b1c1c11 776static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
65e082c9
LB
777static inline void opregion_asle_intr(struct drm_device *dev) { return; }
778static inline void opregion_enable_asle(struct drm_device *dev) { return; }
779#endif
8ee1c3db 780
79e53945
JB
781/* modesetting */
782extern void intel_modeset_init(struct drm_device *dev);
783extern void intel_modeset_cleanup(struct drm_device *dev);
80824003 784extern void i8xx_disable_fbc(struct drm_device *dev);
79e53945 785
546b0974
EA
786/**
787 * Lock test for when it's just for synchronization of ring access.
788 *
789 * In that case, we don't need to do it when GEM is initialized as nobody else
790 * has access to the ring.
791 */
792#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
793 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
794 LOCK_TEST_WITH_RETURN(dev, file_priv); \
795} while (0)
796
3043c60c
EA
797#define I915_READ(reg) readl(dev_priv->regs + (reg))
798#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
799#define I915_READ16(reg) readw(dev_priv->regs + (reg))
800#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
801#define I915_READ8(reg) readb(dev_priv->regs + (reg))
802#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
de151cf6 803#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
049ef7e4 804#define I915_READ64(reg) readq(dev_priv->regs + (reg))
7d57382e 805#define POSTING_READ(reg) (void)I915_READ(reg)
1da177e4
LT
806
807#define I915_VERBOSE 0
808
0ef82af7
CW
809#define RING_LOCALS volatile unsigned int *ring_virt__;
810
811#define BEGIN_LP_RING(n) do { \
812 int bytes__ = 4*(n); \
813 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
814 /* a wrap must occur between instructions so pad beforehand */ \
815 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
816 i915_wrap_ring(dev); \
817 if (unlikely (dev_priv->ring.space < bytes__)) \
818 i915_wait_ring(dev, bytes__, __func__); \
819 ring_virt__ = (unsigned int *) \
820 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
821 dev_priv->ring.tail += bytes__; \
822 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
823 dev_priv->ring.space -= bytes__; \
1da177e4
LT
824} while (0)
825
0ef82af7 826#define OUT_RING(n) do { \
1da177e4 827 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
0ef82af7 828 *ring_virt__++ = (n); \
1da177e4
LT
829} while (0)
830
831#define ADVANCE_LP_RING() do { \
0ef82af7
CW
832 if (I915_VERBOSE) \
833 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
834 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1da177e4
LT
835} while(0)
836
ba8bbcf6 837/**
585fb111
JB
838 * Reads a dword out of the status page, which is written to from the command
839 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
840 * MI_STORE_DATA_IMM.
ba8bbcf6 841 *
585fb111 842 * The following dwords have a reserved meaning:
0cdad7e8
KP
843 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
844 * 0x04: ring 0 head pointer
845 * 0x05: ring 1 head pointer (915-class)
846 * 0x06: ring 2 head pointer (915-class)
847 * 0x10-0x1b: Context status DWords (GM45)
848 * 0x1f: Last written status offset. (GM45)
ba8bbcf6 849 *
0cdad7e8 850 * The area from dword 0x20 to 0x3ff is available for driver usage.
ba8bbcf6 851 */
585fb111 852#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
0baf823a 853#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
0cdad7e8 854#define I915_GEM_HWS_INDEX 0x20
0baf823a 855#define I915_BREADCRUMB_INDEX 0x21
ba8bbcf6 856
0ef82af7 857extern int i915_wrap_ring(struct drm_device * dev);
585fb111 858extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6
JB
859
860#define IS_I830(dev) ((dev)->pci_device == 0x3577)
861#define IS_845G(dev) ((dev)->pci_device == 0x2562)
862#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
863#define IS_I855(dev) ((dev)->pci_device == 0x3582)
864#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
865
4d1f7888 866#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
ba8bbcf6
JB
867#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
868#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
3bf48468
JB
869#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
870 (dev)->pci_device == 0x27AE)
ba8bbcf6
JB
871#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
872 (dev)->pci_device == 0x2982 || \
873 (dev)->pci_device == 0x2992 || \
874 (dev)->pci_device == 0x29A2 || \
875 (dev)->pci_device == 0x2A02 || \
5f5f9d4c 876 (dev)->pci_device == 0x2A12 || \
d3adbc0c
ZW
877 (dev)->pci_device == 0x2A42 || \
878 (dev)->pci_device == 0x2E02 || \
879 (dev)->pci_device == 0x2E12 || \
72021788 880 (dev)->pci_device == 0x2E22 || \
280da227 881 (dev)->pci_device == 0x2E32 || \
7839c5d5 882 (dev)->pci_device == 0x2E42 || \
280da227
ZW
883 (dev)->pci_device == 0x0042 || \
884 (dev)->pci_device == 0x0046)
ba8bbcf6 885
c9ed4486
ML
886#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
887 (dev)->pci_device == 0x2A12)
ba8bbcf6 888
b9bfdfe6 889#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
5f5f9d4c 890
d3adbc0c
ZW
891#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
892 (dev)->pci_device == 0x2E12 || \
60fd99e3 893 (dev)->pci_device == 0x2E22 || \
72021788 894 (dev)->pci_device == 0x2E32 || \
7839c5d5 895 (dev)->pci_device == 0x2E42 || \
60fd99e3 896 IS_GM45(dev))
d3adbc0c 897
2177832f
SL
898#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
899#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
900#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
901
ba8bbcf6
JB
902#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
903 (dev)->pci_device == 0x29B2 || \
2177832f
SL
904 (dev)->pci_device == 0x29D2 || \
905 (IS_IGD(dev)))
ba8bbcf6 906
280da227
ZW
907#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
908#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
909#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
910
ba8bbcf6 911#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
280da227
ZW
912 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
913 IS_IGDNG(dev))
ba8bbcf6
JB
914
915#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
2177832f 916 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
280da227 917 IS_IGD(dev) || IS_IGDNG_M(dev))
ba8bbcf6 918
280da227
ZW
919#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
920 IS_IGDNG(dev))
0f973f27
JB
921/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
922 * rows, which changed the alignment requirements and fence programming.
923 */
924#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
925 IS_I915GM(dev)))
280da227 926#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
a4fc5ed6 927#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
32f9d658 928#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
af729a26 929#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
7662c8bd 930/* dsparb controlled by hw only */
22bd50c5 931#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
b39d50e5 932
652c393a
JB
933#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
934#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
80824003 935#define I915_HAS_FBC(dev) (IS_I9XX(dev) || IS_I965G(dev))
652c393a 936
ba8bbcf6 937#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b 938
1da177e4 939#endif