[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h

/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
/*
 *
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _I915_DRV_H_
#define _I915_DRV_H_

#include "i915_reg.h"

/* General customization:
 */

#define DRIVER_AUTHOR		"Tungsten Graphics, Inc."

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
#define DRIVER_DATE		"20060119"

/* Interface history:
 *
 * 1.1: Original.
 * 1.2: Add Power Management
 * 1.3: Add vblank support
 * 1.4: Fix cmdbuffer path, add heap destroy
 * 1.5: Add vblank pipe configuration
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
 */
#define DRIVER_MAJOR		1
#define DRIVER_MINOR		6
#define DRIVER_PATCHLEVEL	0

typedef struct _drm_i915_ring_buffer {
	int tail_mask;
	unsigned long Start;
	unsigned long End;
	unsigned long Size;
	u8 *virtual_start;
	int head;
	int tail;
	int space;
	drm_local_map_t map;
} drm_i915_ring_buffer_t;

struct mem_block {
	struct mem_block *next;
	struct mem_block *prev;
	int start;
	int size;
	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
};

typedef struct _drm_i915_vbl_swap {
	struct list_head head;
	drm_drawable_t drw_id;
	unsigned int pipe;
	unsigned int sequence;
} drm_i915_vbl_swap_t;

typedef struct drm_i915_private {
	drm_local_map_t *sarea;
	drm_local_map_t *mmio_map;

	drm_i915_sarea_t *sarea_priv;
	drm_i915_ring_buffer_t ring;

	drm_dma_handle_t *status_page_dmah;
	void *hw_status_page;
	dma_addr_t dma_status_page;
	unsigned long counter;
	unsigned int status_gfx_addr;
	drm_local_map_t hws_map;

	unsigned int cpp;
	int back_offset;
	int front_offset;
	int current_page;
	int page_flipping;

	wait_queue_head_t irq_queue;
	atomic_t irq_received;
	atomic_t irq_emitted;
	/** Protects user_irq_refcount and irq_mask_reg */
	spinlock_t user_irq_lock;
	/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
	int user_irq_refcount;
	/** Cached value of IMR to avoid reads in updating the bitfield */
	u32 irq_mask_reg;

	int tex_lru_log_granularity;
	int allow_batchbuffer;
	struct mem_block *agp_heap;
	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
	int vblank_pipe;

	spinlock_t swaps_lock;
	drm_i915_vbl_swap_t vbl_swaps;
	unsigned int swaps_pending;

	/* Register state */
	u8 saveLBB;
	u32 saveDSPACNTR;
	u32 saveDSPBCNTR;
	u32 saveDSPARB;
	u32 savePIPEACONF;
	u32 savePIPEBCONF;
	u32 savePIPEASRC;
	u32 savePIPEBSRC;
	u32 saveFPA0;
	u32 saveFPA1;
	u32 saveDPLL_A;
	u32 saveDPLL_A_MD;
	u32 saveHTOTAL_A;
	u32 saveHBLANK_A;
	u32 saveHSYNC_A;
	u32 saveVTOTAL_A;
	u32 saveVBLANK_A;
	u32 saveVSYNC_A;
	u32 saveBCLRPAT_A;
	u32 savePIPEASTAT;
	u32 saveDSPASTRIDE;
	u32 saveDSPASIZE;
	u32 saveDSPAPOS;
	u32 saveDSPAADDR;
	u32 saveDSPASURF;
	u32 saveDSPATILEOFF;
	u32 savePFIT_PGM_RATIOS;
	u32 saveBLC_PWM_CTL;
	u32 saveBLC_PWM_CTL2;
	u32 saveFPB0;
	u32 saveFPB1;
	u32 saveDPLL_B;
	u32 saveDPLL_B_MD;
	u32 saveHTOTAL_B;
	u32 saveHBLANK_B;
	u32 saveHSYNC_B;
	u32 saveVTOTAL_B;
	u32 saveVBLANK_B;
	u32 saveVSYNC_B;
	u32 saveBCLRPAT_B;
	u32 savePIPEBSTAT;
	u32 saveDSPBSTRIDE;
	u32 saveDSPBSIZE;
	u32 saveDSPBPOS;
	u32 saveDSPBADDR;
	u32 saveDSPBSURF;
	u32 saveDSPBTILEOFF;
	u32 saveVGA0;
	u32 saveVGA1;
	u32 saveVGA_PD;
	u32 saveVGACNTRL;
	u32 saveADPA;
	u32 saveLVDS;
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
	u32 saveDVOA;
	u32 saveDVOB;
	u32 saveDVOC;
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
	u32 savePP_DIVISOR;
	u32 savePFIT_CONTROL;
	u32 save_palette_a[256];
	u32 save_palette_b[256];
	u32 saveFBC_CFB_BASE;
	u32 saveFBC_LL_BASE;
	u32 saveFBC_CONTROL;
	u32 saveFBC_CONTROL2;
	u32 saveIER;
	u32 saveIIR;
	u32 saveIMR;
	u32 saveCACHE_MODE_0;
	u32 saveD_STATE;
	u32 saveCG_2D_DIS;
	u32 saveMI_ARB_STATE;
	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
	u8 saveMSR;
	u8 saveSR[8];
	u8 saveGR[25];
	u8 saveAR_INDEX;
	u8 saveAR[21];
	u8 saveDACMASK;
	u8 saveDACDATA[256*3]; /* 256 3-byte colors */
	u8 saveCR[37];
} drm_i915_private_t;

extern struct drm_ioctl_desc i915_ioctls[];
extern int i915_max_ioctl;

				/* i915_dma.c */
extern void i915_kernel_lost_context(struct drm_device * dev);
extern int i915_driver_load(struct drm_device *, unsigned long flags);
extern int i915_driver_unload(struct drm_device *);
extern void i915_driver_lastclose(struct drm_device * dev);
extern void i915_driver_preclose(struct drm_device *dev,
				 struct drm_file *file_priv);
extern int i915_driver_device_is_agp(struct drm_device * dev);
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);

/* i915_irq.c */
extern int i915_irq_emit(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_irq_wait(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);

extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
extern void i915_driver_irq_preinstall(struct drm_device * dev);
extern void i915_driver_irq_postinstall(struct drm_device * dev);
extern void i915_driver_irq_uninstall(struct drm_device * dev);
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);

/* i915_mem.c */
extern int i915_mem_alloc(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
extern int i915_mem_free(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
extern int i915_mem_init_heap(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
				 struct drm_file *file_priv);
extern void i915_mem_takedown(struct mem_block **heap);
extern void i915_mem_release(struct drm_device * dev,
			     struct drm_file *file_priv, struct mem_block *heap);

#define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
#define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
#define I915_READ16(reg)	DRM_READ16(dev_priv->mmio_map, (reg))
#define I915_WRITE16(reg,val)	DRM_WRITE16(dev_priv->mmio_map, (reg), (val))

#define I915_VERBOSE 0

#define RING_LOCALS	unsigned int outring, ringmask, outcount; \
                        volatile char *virt;

#define BEGIN_LP_RING(n) do {				\
	if (I915_VERBOSE)				\
		DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));	\
	if (dev_priv->ring.space < (n)*4)		\
		i915_wait_ring(dev, (n)*4, __func__);		\
	outcount = 0;					\
	outring = dev_priv->ring.tail;			\
	ringmask = dev_priv->ring.tail_mask;		\
	virt = dev_priv->ring.virtual_start;		\
} while (0)

#define OUT_RING(n) do {					\
	if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
	*(volatile unsigned int *)(virt + outring) = (n);	\
        outcount++;						\
	outring += 4;						\
	outring &= ringmask;					\
} while (0)

#define ADVANCE_LP_RING() do {						\
	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
	dev_priv->ring.tail = outring;					\
	dev_priv->ring.space -= outcount * 4;				\
	I915_WRITE(PRB0_TAIL, outring);			\
} while(0)

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 4: ring 0 head pointer
 * 5: ring 1 head pointer (915-class)
 * 6: ring 2 head pointer (915-class)
 *
 * The area from dword 0x10 to 0x3ff is available for driver usage.
 */
#define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)

extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);

#define IS_I830(dev) ((dev)->pci_device == 0x3577)
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
#define IS_I855(dev) ((dev)->pci_device == 0x3582)
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)

#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
		        (dev)->pci_device == 0x27AE)
#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
		       (dev)->pci_device == 0x2982 || \
		       (dev)->pci_device == 0x2992 || \
		       (dev)->pci_device == 0x29A2 || \
		       (dev)->pci_device == 0x2A02 || \
		       (dev)->pci_device == 0x2A12 || \
		       (dev)->pci_device == 0x2A42 || \
		       (dev)->pci_device == 0x2E02 || \
		       (dev)->pci_device == 0x2E12 || \
		       (dev)->pci_device == 0x2E22)

#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)

#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)

#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
		     (dev)->pci_device == 0x2E12 || \
		     (dev)->pci_device == 0x2E22)

#define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||	\
			(dev)->pci_device == 0x29B2 ||	\
			(dev)->pci_device == 0x29D2)

#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
		      IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))

#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
			IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))

#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))

#define PRIMARY_RINGBUFFER_SIZE         (128*1024)

#endif
Commit	Line	Data
1da177e4 LT	1	/* i915_drv.h -- Private header for the I915 driver -- linux-c --
1da177e4 LT	2	*/
0d6aa60b	3	/*
bc54fd1a	4	*
1da177e4 LT	5	* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
1da177e4 LT	6	* All Rights Reserved.
bc54fd1a DA	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the
	10	* "Software"), to deal in the Software without restriction, including
	11	* without limitation the rights to use, copy, modify, merge, publish,
	12	* distribute, sub license, and/or sell copies of the Software, and to
	13	* permit persons to whom the Software is furnished to do so, subject to
	14	* the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the
	17	* next paragraph) shall be included in all copies or substantial portions
	18	* of the Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	21	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	22	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	23	* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
	24	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	25	* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	26	* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	27	*
0d6aa60b	28	*/
1da177e4 LT	29
	30	#ifndef _I915_DRV_H_
	31	#define _I915_DRV_H_
	32
585fb111 JB	33	#include "i915_reg.h"
585fb111 JB	34
1da177e4 LT	35	/* General customization:
	36	*/
	37
	38	#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
	39
	40	#define DRIVER_NAME "i915"
	41	#define DRIVER_DESC "Intel Graphics"
de227f5f	42	#define DRIVER_DATE "20060119"
1da177e4 LT	43
	44	/* Interface history:
	45	*
	46	* 1.1: Original.
0d6aa60b DA	47	* 1.2: Add Power Management
0d6aa60b DA	48	* 1.3: Add vblank support
de227f5f	49	* 1.4: Fix cmdbuffer path, add heap destroy
702880f2	50	* 1.5: Add vblank pipe configuration
2228ed67 MD	51	* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
2228ed67 MD	52	* - Support vertical blank on secondary display pipe
1da177e4 LT	53	*/
1da177e4 LT	54	#define DRIVER_MAJOR 1
2228ed67	55	#define DRIVER_MINOR 6
1da177e4 LT	56	#define DRIVER_PATCHLEVEL 0
1da177e4 LT	57
1da177e4 LT	58	typedef struct _drm_i915_ring_buffer {
	59	int tail_mask;
	60	unsigned long Start;
	61	unsigned long End;
	62	unsigned long Size;
	63	u8 *virtual_start;
	64	int head;
	65	int tail;
	66	int space;
	67	drm_local_map_t map;
	68	} drm_i915_ring_buffer_t;
	69
	70	struct mem_block {
	71	struct mem_block *next;
	72	struct mem_block *prev;
	73	int start;
	74	int size;
6c340eac	75	struct drm_file file_priv; / NULL: free, -1: heap, other: real files */
1da177e4 LT	76	};
1da177e4 LT	77
a6b54f3f MD	78	typedef struct _drm_i915_vbl_swap {
	79	struct list_head head;
	80	drm_drawable_t drw_id;
af6061af	81	unsigned int pipe;
a6b54f3f MD	82	unsigned int sequence;
	83	} drm_i915_vbl_swap_t;
	84
1da177e4 LT	85	typedef struct drm_i915_private {
	86	drm_local_map_t *sarea;
	87	drm_local_map_t *mmio_map;
	88
	89	drm_i915_sarea_t *sarea_priv;
	90	drm_i915_ring_buffer_t ring;
	91
9c8da5eb	92	drm_dma_handle_t *status_page_dmah;
1da177e4	93	void *hw_status_page;
1da177e4	94	dma_addr_t dma_status_page;
af6061af	95	unsigned long counter;
dc7a9319 WZ	96	unsigned int status_gfx_addr;
dc7a9319 WZ	97	drm_local_map_t hws_map;
1da177e4	98
a6b54f3f	99	unsigned int cpp;
1da177e4 LT	100	int back_offset;
	101	int front_offset;
	102	int current_page;
	103	int page_flipping;
1da177e4 LT	104
	105	wait_queue_head_t irq_queue;
	106	atomic_t irq_received;
af6061af	107	atomic_t irq_emitted;
ed4cb414 EA	108	/** Protects user_irq_refcount and irq_mask_reg */
	109	spinlock_t user_irq_lock;
	110	/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
	111	int user_irq_refcount;
	112	/** Cached value of IMR to avoid reads in updating the bitfield */
	113	u32 irq_mask_reg;
1da177e4 LT	114
	115	int tex_lru_log_granularity;
	116	int allow_batchbuffer;
	117	struct mem_block *agp_heap;
0d6aa60b	118	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2	119	int vblank_pipe;
a6b54f3f MD	120
	121	spinlock_t swaps_lock;
	122	drm_i915_vbl_swap_t vbl_swaps;
	123	unsigned int swaps_pending;
ba8bbcf6 JB	124
	125	/* Register state */
	126	u8 saveLBB;
	127	u32 saveDSPACNTR;
	128	u32 saveDSPBCNTR;
e948e994	129	u32 saveDSPARB;
ba8bbcf6 JB	130	u32 savePIPEACONF;
	131	u32 savePIPEBCONF;
	132	u32 savePIPEASRC;
	133	u32 savePIPEBSRC;
	134	u32 saveFPA0;
	135	u32 saveFPA1;
	136	u32 saveDPLL_A;
	137	u32 saveDPLL_A_MD;
	138	u32 saveHTOTAL_A;
	139	u32 saveHBLANK_A;
	140	u32 saveHSYNC_A;
	141	u32 saveVTOTAL_A;
	142	u32 saveVBLANK_A;
	143	u32 saveVSYNC_A;
	144	u32 saveBCLRPAT_A;
0da3ea12	145	u32 savePIPEASTAT;
ba8bbcf6 JB	146	u32 saveDSPASTRIDE;
	147	u32 saveDSPASIZE;
	148	u32 saveDSPAPOS;
585fb111	149	u32 saveDSPAADDR;
ba8bbcf6 JB	150	u32 saveDSPASURF;
	151	u32 saveDSPATILEOFF;
	152	u32 savePFIT_PGM_RATIOS;
	153	u32 saveBLC_PWM_CTL;
	154	u32 saveBLC_PWM_CTL2;
	155	u32 saveFPB0;
	156	u32 saveFPB1;
	157	u32 saveDPLL_B;
	158	u32 saveDPLL_B_MD;
	159	u32 saveHTOTAL_B;
	160	u32 saveHBLANK_B;
	161	u32 saveHSYNC_B;
	162	u32 saveVTOTAL_B;
	163	u32 saveVBLANK_B;
	164	u32 saveVSYNC_B;
	165	u32 saveBCLRPAT_B;
0da3ea12	166	u32 savePIPEBSTAT;
ba8bbcf6 JB	167	u32 saveDSPBSTRIDE;
	168	u32 saveDSPBSIZE;
	169	u32 saveDSPBPOS;
585fb111	170	u32 saveDSPBADDR;
ba8bbcf6 JB	171	u32 saveDSPBSURF;
ba8bbcf6 JB	172	u32 saveDSPBTILEOFF;
585fb111 JB	173	u32 saveVGA0;
	174	u32 saveVGA1;
	175	u32 saveVGA_PD;
ba8bbcf6 JB	176	u32 saveVGACNTRL;
	177	u32 saveADPA;
	178	u32 saveLVDS;
585fb111 JB	179	u32 savePP_ON_DELAYS;
585fb111 JB	180	u32 savePP_OFF_DELAYS;
ba8bbcf6 JB	181	u32 saveDVOA;
	182	u32 saveDVOB;
	183	u32 saveDVOC;
	184	u32 savePP_ON;
	185	u32 savePP_OFF;
	186	u32 savePP_CONTROL;
585fb111	187	u32 savePP_DIVISOR;
ba8bbcf6 JB	188	u32 savePFIT_CONTROL;
	189	u32 save_palette_a[256];
	190	u32 save_palette_b[256];
	191	u32 saveFBC_CFB_BASE;
	192	u32 saveFBC_LL_BASE;
	193	u32 saveFBC_CONTROL;
	194	u32 saveFBC_CONTROL2;
0da3ea12 JB	195	u32 saveIER;
	196	u32 saveIIR;
	197	u32 saveIMR;
1f84e550	198	u32 saveCACHE_MODE_0;
e948e994	199	u32 saveD_STATE;
585fb111	200	u32 saveCG_2D_DIS;
1f84e550	201	u32 saveMI_ARB_STATE;
ba8bbcf6 JB	202	u32 saveSWF0[16];
	203	u32 saveSWF1[16];
	204	u32 saveSWF2[3];
	205	u8 saveMSR;
	206	u8 saveSR[8];
123f794f	207	u8 saveGR[25];
ba8bbcf6	208	u8 saveAR_INDEX;
a59e122a	209	u8 saveAR[21];
ba8bbcf6 JB	210	u8 saveDACMASK;
ba8bbcf6 JB	211	u8 saveDACDATA[2563]; / 256 3-byte colors */
a59e122a	212	u8 saveCR[37];
1da177e4 LT	213	} drm_i915_private_t;
1da177e4 LT	214
c153f45f	215	extern struct drm_ioctl_desc i915_ioctls[];
b3a83639 DA	216	extern int i915_max_ioctl;
b3a83639 DA	217
1da177e4	218	/* i915_dma.c */
84b1fd10	219	extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947	220	extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6	221	extern int i915_driver_unload(struct drm_device *);
84b1fd10	222	extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac EA	223	extern void i915_driver_preclose(struct drm_device *dev,
6c340eac EA	224	struct drm_file *file_priv);
84b1fd10	225	extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b DA	226	extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
0d6aa60b DA	227	unsigned long arg);
af6061af	228
1da177e4	229	/* i915_irq.c */
c153f45f EA	230	extern int i915_irq_emit(struct drm_device dev, void data,
	231	struct drm_file *file_priv);
	232	extern int i915_irq_wait(struct drm_device dev, void data,
	233	struct drm_file *file_priv);
1da177e4	234
84b1fd10 DA	235	extern int i915_driver_vblank_wait(struct drm_device dev, unsigned int sequence);
84b1fd10 DA	236	extern int i915_driver_vblank_wait2(struct drm_device dev, unsigned int sequence);
1da177e4	237	extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10	238	extern void i915_driver_irq_preinstall(struct drm_device * dev);
af6061af	239	extern void i915_driver_irq_postinstall(struct drm_device * dev);
84b1fd10	240	extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f EA	241	extern int i915_vblank_pipe_set(struct drm_device dev, void data,
	242	struct drm_file *file_priv);
	243	extern int i915_vblank_pipe_get(struct drm_device dev, void data,
	244	struct drm_file *file_priv);
	245	extern int i915_vblank_swap(struct drm_device dev, void data,
	246	struct drm_file *file_priv);
1da177e4 LT	247
1da177e4 LT	248	/* i915_mem.c */
c153f45f EA	249	extern int i915_mem_alloc(struct drm_device dev, void data,
	250	struct drm_file *file_priv);
	251	extern int i915_mem_free(struct drm_device dev, void data,
	252	struct drm_file *file_priv);
	253	extern int i915_mem_init_heap(struct drm_device dev, void data,
	254	struct drm_file *file_priv);
	255	extern int i915_mem_destroy_heap(struct drm_device dev, void data,
	256	struct drm_file *file_priv);
1da177e4	257	extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10	258	extern void i915_mem_release(struct drm_device * dev,
6c340eac	259	struct drm_file file_priv, struct mem_block heap);
1da177e4	260
0d6aa60b DA	261	#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
0d6aa60b DA	262	#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
bc5f4523	263	#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
0d6aa60b	264	#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
1da177e4 LT	265
	266	#define I915_VERBOSE 0
	267
	268	#define RING_LOCALS unsigned int outring, ringmask, outcount; \
	269	volatile char *virt;
	270
	271	#define BEGIN_LP_RING(n) do { \
	272	if (I915_VERBOSE) \
3e684eae MN	273	DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
3e684eae MN	274	if (dev_priv->ring.space < (n)*4) \
bf9d8929	275	i915_wait_ring(dev, (n)*4, __func__); \
1da177e4 LT	276	outcount = 0; \
	277	outring = dev_priv->ring.tail; \
	278	ringmask = dev_priv->ring.tail_mask; \
	279	virt = dev_priv->ring.virtual_start; \
	280	} while (0)
	281
	282	#define OUT_RING(n) do { \
	283	if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
c29b669c	284	(volatile unsigned int )(virt + outring) = (n); \
1da177e4 LT	285	outcount++; \
	286	outring += 4; \
	287	outring &= ringmask; \
	288	} while (0)
	289
	290	#define ADVANCE_LP_RING() do { \
	291	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
	292	dev_priv->ring.tail = outring; \
	293	dev_priv->ring.space -= outcount * 4; \
585fb111	294	I915_WRITE(PRB0_TAIL, outring); \
1da177e4 LT	295	} while(0)
1da177e4 LT	296
ba8bbcf6	297	/**
585fb111 JB	298	* Reads a dword out of the status page, which is written to from the command
	299	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	300	* MI_STORE_DATA_IMM.
ba8bbcf6	301	*
585fb111 JB	302	* The following dwords have a reserved meaning:
	303	* 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	304	* 4: ring 0 head pointer
	305	* 5: ring 1 head pointer (915-class)
	306	* 6: ring 2 head pointer (915-class)
ba8bbcf6	307	*
585fb111	308	* The area from dword 0x10 to 0x3ff is available for driver usage.
ba8bbcf6	309	*/
585fb111 JB	310	#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
585fb111 JB	311	#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
ba8bbcf6	312
585fb111	313	extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6 JB	314
	315	#define IS_I830(dev) ((dev)->pci_device == 0x3577)
	316	#define IS_845G(dev) ((dev)->pci_device == 0x2562)
	317	#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
	318	#define IS_I855(dev) ((dev)->pci_device == 0x3582)
	319	#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
	320
4d1f7888	321	#define IS_I915G(dev) ((dev)->pci_device == 0x2582 \|\| (dev)->pci_device == 0x258a)
ba8bbcf6 JB	322	#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
ba8bbcf6 JB	323	#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
3bf48468 JB	324	#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 \|\|\
3bf48468 JB	325	(dev)->pci_device == 0x27AE)
ba8bbcf6 JB	326	#define IS_I965G(dev) ((dev)->pci_device == 0x2972 \|\| \
	327	(dev)->pci_device == 0x2982 \|\| \
	328	(dev)->pci_device == 0x2992 \|\| \
	329	(dev)->pci_device == 0x29A2 \|\| \
	330	(dev)->pci_device == 0x2A02 \|\| \
5f5f9d4c	331	(dev)->pci_device == 0x2A12 \|\| \
d3adbc0c ZW	332	(dev)->pci_device == 0x2A42 \|\| \
	333	(dev)->pci_device == 0x2E02 \|\| \
	334	(dev)->pci_device == 0x2E12 \|\| \
	335	(dev)->pci_device == 0x2E22)
ba8bbcf6 JB	336
	337	#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
	338
5f5f9d4c ZW	339	#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
5f5f9d4c ZW	340
d3adbc0c ZW	341	#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 \|\| \
	342	(dev)->pci_device == 0x2E12 \|\| \
	343	(dev)->pci_device == 0x2E22)
	344
ba8bbcf6 JB	345	#define IS_G33(dev) ((dev)->pci_device == 0x29C2 \|\| \
	346	(dev)->pci_device == 0x29B2 \|\| \
	347	(dev)->pci_device == 0x29D2)
	348
	349	#define IS_I9XX(dev) (IS_I915G(dev) \|\| IS_I915GM(dev) \|\| IS_I945G(dev) \|\| \
	350	IS_I945GM(dev) \|\| IS_I965G(dev) \|\| IS_G33(dev))
	351
	352	#define IS_MOBILE(dev) (IS_I830(dev) \|\| IS_I85X(dev) \|\| IS_I915GM(dev) \|\| \
5f5f9d4c	353	IS_I945GM(dev) \|\| IS_I965GM(dev) \|\| IS_IGD_GM(dev))
ba8bbcf6	354
d3adbc0c	355	#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) \|\| IS_IGD_GM(dev) \|\| IS_G4X(dev))
b39d50e5	356
ba8bbcf6	357	#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b	358
1da177e4	359	#endif