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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
4ff4b44c | 40 | #include <linux/hash.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
52137010 | 43 | #include <linux/mm_types.h> |
b46a33e2 | 44 | #include <linux/perf_event.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
d07f0e59 | 46 | #include <linux/reservation.h> |
e73bdd20 CW |
47 | #include <linux/shmem_fs.h> |
48 | ||
49 | #include <drm/drmP.h> | |
50 | #include <drm/intel-gtt.h> | |
51 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
52 | #include <drm/drm_gem.h> | |
3b96a0b1 | 53 | #include <drm/drm_auth.h> |
f9a87bd7 | 54 | #include <drm/drm_cache.h> |
d78aa650 | 55 | #include <drm/drm_util.h> |
7b610f1f | 56 | #include <drm/drm_dsc.h> |
e73bdd20 | 57 | |
2d332ee1 | 58 | #include "i915_fixed.h" |
e73bdd20 CW |
59 | #include "i915_params.h" |
60 | #include "i915_reg.h" | |
40b326ee | 61 | #include "i915_utils.h" |
e73bdd20 CW |
62 | |
63 | #include "intel_bios.h" | |
b978520d | 64 | #include "intel_device_info.h" |
3846a9b1 | 65 | #include "intel_display.h" |
ac7f11c6 | 66 | #include "intel_dpll_mgr.h" |
e73bdd20 | 67 | #include "intel_lrc.h" |
3846a9b1 | 68 | #include "intel_opregion.h" |
e73bdd20 | 69 | #include "intel_ringbuffer.h" |
3846a9b1 | 70 | #include "intel_uncore.h" |
6b0478fb | 71 | #include "intel_wopcm.h" |
25d140fa | 72 | #include "intel_workarounds.h" |
3846a9b1 | 73 | #include "intel_uc.h" |
e73bdd20 | 74 | |
d501b1d2 | 75 | #include "i915_gem.h" |
6095868a | 76 | #include "i915_gem_context.h" |
b42fe9ca JL |
77 | #include "i915_gem_fence_reg.h" |
78 | #include "i915_gem_object.h" | |
e73bdd20 | 79 | #include "i915_gem_gtt.h" |
d897a111 | 80 | #include "i915_gpu_error.h" |
e61e0f51 | 81 | #include "i915_request.h" |
b7268c5e | 82 | #include "i915_scheduler.h" |
a89d1f92 | 83 | #include "i915_timeline.h" |
b42fe9ca JL |
84 | #include "i915_vma.h" |
85 | ||
0ad35fed ZW |
86 | #include "intel_gvt.h" |
87 | ||
1da177e4 LT |
88 | /* General customization: |
89 | */ | |
90 | ||
1da177e4 LT |
91 | #define DRIVER_NAME "i915" |
92 | #define DRIVER_DESC "Intel Graphics" | |
4377d4e0 JN |
93 | #define DRIVER_DATE "20181204" |
94 | #define DRIVER_TIMESTAMP 1543944377 | |
1da177e4 | 95 | |
e2c719b7 RC |
96 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
97 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
98 | * which may not necessarily be a user visible problem. This will either | |
99 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
100 | * enable distros and users to tailor their preferred amount of i915 abrt | |
101 | * spam. | |
102 | */ | |
103 | #define I915_STATE_WARN(condition, format...) ({ \ | |
104 | int __ret_warn_on = !!(condition); \ | |
32753cb8 | 105 | if (unlikely(__ret_warn_on)) \ |
4f044a88 | 106 | if (!WARN(i915_modparams.verbose_state_checks, format)) \ |
e2c719b7 | 107 | DRM_ERROR(format); \ |
e2c719b7 RC |
108 | unlikely(__ret_warn_on); \ |
109 | }) | |
110 | ||
152b2262 JL |
111 | #define I915_STATE_WARN_ON(x) \ |
112 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 113 | |
fae919f0 | 114 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) |
51c18bf7 | 115 | |
4fec15d1 ID |
116 | bool __i915_inject_load_failure(const char *func, int line); |
117 | #define i915_inject_load_failure() \ | |
118 | __i915_inject_load_failure(__func__, __LINE__) | |
51c18bf7 CW |
119 | |
120 | bool i915_error_injected(void); | |
121 | ||
fae919f0 | 122 | #else |
51c18bf7 | 123 | |
fae919f0 | 124 | #define i915_inject_load_failure() false |
51c18bf7 CW |
125 | #define i915_error_injected() false |
126 | ||
fae919f0 | 127 | #endif |
4fec15d1 | 128 | |
51c18bf7 CW |
129 | #define i915_load_error(i915, fmt, ...) \ |
130 | __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \ | |
131 | fmt, ##__VA_ARGS__) | |
132 | ||
1d843f9d EE |
133 | enum hpd_pin { |
134 | HPD_NONE = 0, | |
1d843f9d EE |
135 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
136 | HPD_CRT, | |
137 | HPD_SDVO_B, | |
138 | HPD_SDVO_C, | |
cc24fcdc | 139 | HPD_PORT_A, |
1d843f9d EE |
140 | HPD_PORT_B, |
141 | HPD_PORT_C, | |
142 | HPD_PORT_D, | |
26951caf | 143 | HPD_PORT_E, |
96ae4831 | 144 | HPD_PORT_F, |
1d843f9d EE |
145 | HPD_NUM_PINS |
146 | }; | |
147 | ||
c91711f9 JN |
148 | #define for_each_hpd_pin(__pin) \ |
149 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
150 | ||
9a64c650 LP |
151 | /* Threshold == 5 for long IRQs, 50 for short */ |
152 | #define HPD_STORM_DEFAULT_THRESHOLD 50 | |
317eaa95 | 153 | |
5fcece80 | 154 | struct i915_hotplug { |
4211bdba | 155 | struct delayed_work hotplug_work; |
5fcece80 JN |
156 | |
157 | struct { | |
158 | unsigned long last_jiffies; | |
159 | int count; | |
160 | enum { | |
161 | HPD_ENABLED = 0, | |
162 | HPD_DISABLED = 1, | |
163 | HPD_MARK_DISABLED = 2 | |
164 | } state; | |
165 | } stats[HPD_NUM_PINS]; | |
166 | u32 event_bits; | |
4211bdba | 167 | u32 retry_bits; |
5fcece80 JN |
168 | struct delayed_work reenable_work; |
169 | ||
5fcece80 JN |
170 | u32 long_port_mask; |
171 | u32 short_port_mask; | |
172 | struct work_struct dig_port_work; | |
173 | ||
19625e85 L |
174 | struct work_struct poll_init_work; |
175 | bool poll_enabled; | |
176 | ||
317eaa95 | 177 | unsigned int hpd_storm_threshold; |
9a64c650 LP |
178 | /* Whether or not to count short HPD IRQs in HPD storms */ |
179 | u8 hpd_short_storm_enabled; | |
317eaa95 | 180 | |
5fcece80 JN |
181 | /* |
182 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
183 | * the non-DP HPD could block the workqueue on a mode config | |
184 | * mutex getting, that userspace may have taken. However | |
185 | * userspace is waiting on the DP workqueue to run which is | |
186 | * blocked behind the non-DP one. | |
187 | */ | |
188 | struct workqueue_struct *dp_wq; | |
189 | }; | |
190 | ||
2a2d5482 CW |
191 | #define I915_GEM_GPU_DOMAINS \ |
192 | (I915_GEM_DOMAIN_RENDER | \ | |
193 | I915_GEM_DOMAIN_SAMPLER | \ | |
194 | I915_GEM_DOMAIN_COMMAND | \ | |
195 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
196 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 197 | |
e7b903d2 | 198 | struct drm_i915_private; |
ad46cb53 | 199 | struct i915_mm_struct; |
5cc9ed4b | 200 | struct i915_mmu_object; |
e7b903d2 | 201 | |
a6f766f3 CW |
202 | struct drm_i915_file_private { |
203 | struct drm_i915_private *dev_priv; | |
204 | struct drm_file *file; | |
205 | ||
206 | struct { | |
207 | spinlock_t lock; | |
208 | struct list_head request_list; | |
d0bc54f2 CW |
209 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
210 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
211 | * (when using lax throttling for the frontbuffer). We also use it to | |
212 | * offer free GPU waitboosts for severely congested workloads. | |
213 | */ | |
214 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
215 | } mm; |
216 | struct idr context_idr; | |
217 | ||
2e1b8730 | 218 | struct intel_rps_client { |
7b92c1bd | 219 | atomic_t boosts; |
562d9bae | 220 | } rps_client; |
a6f766f3 | 221 | |
c80ff16e | 222 | unsigned int bsd_engine; |
b083a087 | 223 | |
14921f3c MK |
224 | /* |
225 | * Every context ban increments per client ban score. Also | |
226 | * hangs in short succession increments ban score. If ban threshold | |
227 | * is reached, client is considered banned and submitting more work | |
228 | * will fail. This is a stop gap measure to limit the badly behaving | |
229 | * clients access to gpu. Note that unbannable contexts never increment | |
230 | * the client ban score. | |
b083a087 | 231 | */ |
14921f3c MK |
232 | #define I915_CLIENT_SCORE_HANG_FAST 1 |
233 | #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) | |
234 | #define I915_CLIENT_SCORE_CONTEXT_BAN 3 | |
235 | #define I915_CLIENT_SCORE_BANNED 9 | |
236 | /** ban_score: Accumulated score of all ctx bans and fast hangs. */ | |
237 | atomic_t ban_score; | |
238 | unsigned long hang_timestamp; | |
a6f766f3 CW |
239 | }; |
240 | ||
1da177e4 LT |
241 | /* Interface history: |
242 | * | |
243 | * 1.1: Original. | |
0d6aa60b DA |
244 | * 1.2: Add Power Management |
245 | * 1.3: Add vblank support | |
de227f5f | 246 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 247 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
248 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
249 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
250 | */ |
251 | #define DRIVER_MAJOR 1 | |
2228ed67 | 252 | #define DRIVER_MINOR 6 |
1da177e4 LT |
253 | #define DRIVER_PATCHLEVEL 0 |
254 | ||
6ef3d427 CW |
255 | struct intel_overlay; |
256 | struct intel_overlay_error_state; | |
257 | ||
9b9d172d | 258 | struct sdvo_device_mapping { |
e957d772 | 259 | u8 initialized; |
9b9d172d | 260 | u8 dvo_port; |
261 | u8 slave_addr; | |
262 | u8 dvo_wiring; | |
e957d772 | 263 | u8 i2c_pin; |
b1083333 | 264 | u8 ddc_pin; |
9b9d172d | 265 | }; |
266 | ||
7bd688cd | 267 | struct intel_connector; |
820d2d77 | 268 | struct intel_encoder; |
ccf010fb | 269 | struct intel_atomic_state; |
5cec258b | 270 | struct intel_crtc_state; |
5724dbd1 | 271 | struct intel_initial_plane_config; |
0e8ffe1b | 272 | struct intel_crtc; |
ee9300bb DV |
273 | struct intel_limit; |
274 | struct dpll; | |
49cd97a3 | 275 | struct intel_cdclk_state; |
b8cecdf5 | 276 | |
e70236a8 | 277 | struct drm_i915_display_funcs { |
49cd97a3 VS |
278 | void (*get_cdclk)(struct drm_i915_private *dev_priv, |
279 | struct intel_cdclk_state *cdclk_state); | |
b0587e4d | 280 | void (*set_cdclk)(struct drm_i915_private *dev_priv, |
90402bab VS |
281 | const struct intel_cdclk_state *cdclk_state, |
282 | enum pipe pipe); | |
bdaf8439 VS |
283 | int (*get_fifo_size)(struct drm_i915_private *dev_priv, |
284 | enum i9xx_plane_id i9xx_plane); | |
e3bddded | 285 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
286 | int (*compute_intermediate_wm)(struct drm_device *dev, |
287 | struct intel_crtc *intel_crtc, | |
288 | struct intel_crtc_state *newstate); | |
ccf010fb ML |
289 | void (*initial_watermarks)(struct intel_atomic_state *state, |
290 | struct intel_crtc_state *cstate); | |
291 | void (*atomic_update_watermarks)(struct intel_atomic_state *state, | |
292 | struct intel_crtc_state *cstate); | |
293 | void (*optimize_watermarks)(struct intel_atomic_state *state, | |
294 | struct intel_crtc_state *cstate); | |
98d39494 | 295 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
432081bc | 296 | void (*update_wm)(struct intel_crtc *crtc); |
27c329ed | 297 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
0e8ffe1b DV |
298 | /* Returns the active state of the crtc, and if the crtc is active, |
299 | * fills out the pipe-config with the hw state. */ | |
300 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 301 | struct intel_crtc_state *); |
5724dbd1 DL |
302 | void (*get_initial_plane_config)(struct intel_crtc *, |
303 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
304 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
305 | struct intel_crtc_state *crtc_state); | |
4a806558 ML |
306 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, |
307 | struct drm_atomic_state *old_state); | |
308 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
309 | struct drm_atomic_state *old_state); | |
b44d5c0c | 310 | void (*update_crtcs)(struct drm_atomic_state *state); |
8ec47de2 VS |
311 | void (*audio_codec_enable)(struct intel_encoder *encoder, |
312 | const struct intel_crtc_state *crtc_state, | |
313 | const struct drm_connector_state *conn_state); | |
314 | void (*audio_codec_disable)(struct intel_encoder *encoder, | |
315 | const struct intel_crtc_state *old_crtc_state, | |
316 | const struct drm_connector_state *old_conn_state); | |
dc4a1094 ACO |
317 | void (*fdi_link_train)(struct intel_crtc *crtc, |
318 | const struct intel_crtc_state *crtc_state); | |
46f16e63 | 319 | void (*init_clock_gating)(struct drm_i915_private *dev_priv); |
91d14251 | 320 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
321 | /* clock updates for mode set */ |
322 | /* cursor updates */ | |
323 | /* render clock increase/decrease */ | |
324 | /* display clock increase/decrease */ | |
325 | /* pll clock increase/decrease */ | |
8563b1e8 | 326 | |
b95c5321 ML |
327 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
328 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
329 | }; |
330 | ||
b6e7d894 DL |
331 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
332 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
333 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
334 | ||
eb805623 | 335 | struct intel_csr { |
8144ac59 | 336 | struct work_struct work; |
eb805623 | 337 | const char *fw_path; |
180e9d23 | 338 | uint32_t required_version; |
d8a5b7d7 | 339 | uint32_t max_fw_size; /* bytes */ |
a7f749f9 | 340 | uint32_t *dmc_payload; |
d8a5b7d7 | 341 | uint32_t dmc_fw_size; /* dwords */ |
b6e7d894 | 342 | uint32_t version; |
eb805623 | 343 | uint32_t mmio_count; |
f0f59a00 | 344 | i915_reg_t mmioaddr[8]; |
eb805623 | 345 | uint32_t mmiodata[8]; |
832dba88 | 346 | uint32_t dc_state; |
a37baf3b | 347 | uint32_t allowed_dc_mask; |
eb805623 DV |
348 | }; |
349 | ||
7faf1ab2 DV |
350 | enum i915_cache_level { |
351 | I915_CACHE_NONE = 0, | |
350ec881 CW |
352 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
353 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
354 | caches, eg sampler/render caches, and the | |
355 | large Last-Level-Cache. LLC is coherent with | |
356 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 357 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
358 | }; |
359 | ||
85fd4f58 CW |
360 | #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ |
361 | ||
a4001f1b PZ |
362 | enum fb_op_origin { |
363 | ORIGIN_GTT, | |
364 | ORIGIN_CPU, | |
365 | ORIGIN_CS, | |
366 | ORIGIN_FLIP, | |
74b4ea1e | 367 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
368 | }; |
369 | ||
ab34a7e8 | 370 | struct intel_fbc { |
25ad93fd PZ |
371 | /* This is always the inner lock when overlapping with struct_mutex and |
372 | * it's the outer lock when overlapping with stolen_lock. */ | |
373 | struct mutex lock; | |
5e59f717 | 374 | unsigned threshold; |
dbef0f15 PZ |
375 | unsigned int possible_framebuffer_bits; |
376 | unsigned int busy_bits; | |
010cf73d | 377 | unsigned int visible_pipes_mask; |
e35fef21 | 378 | struct intel_crtc *crtc; |
5c3fe8b0 | 379 | |
c4213885 | 380 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
381 | struct drm_mm_node *compressed_llb; |
382 | ||
da46f936 RV |
383 | bool false_color; |
384 | ||
d029bcad | 385 | bool enabled; |
0e631adc | 386 | bool active; |
c9855a56 | 387 | bool flip_pending; |
9adccc60 | 388 | |
61a585d6 PZ |
389 | bool underrun_detected; |
390 | struct work_struct underrun_work; | |
391 | ||
525a4f93 PZ |
392 | /* |
393 | * Due to the atomic rules we can't access some structures without the | |
394 | * appropriate locking, so we cache information here in order to avoid | |
395 | * these problems. | |
396 | */ | |
aaf78d27 | 397 | struct intel_fbc_state_cache { |
be1e3415 | 398 | struct i915_vma *vma; |
1c9b6b13 | 399 | unsigned long flags; |
be1e3415 | 400 | |
aaf78d27 PZ |
401 | struct { |
402 | unsigned int mode_flags; | |
403 | uint32_t hsw_bdw_pixel_rate; | |
404 | } crtc; | |
405 | ||
406 | struct { | |
407 | unsigned int rotation; | |
408 | int src_w; | |
409 | int src_h; | |
410 | bool visible; | |
bf0a5d4b JPH |
411 | /* |
412 | * Display surface base address adjustement for | |
413 | * pageflips. Note that on gen4+ this only adjusts up | |
414 | * to a tile, offsets within a tile are handled in | |
415 | * the hw itself (with the TILEOFF register). | |
416 | */ | |
417 | int adjusted_x; | |
418 | int adjusted_y; | |
31d1d3c8 JPH |
419 | |
420 | int y; | |
b2081525 ML |
421 | |
422 | uint16_t pixel_blend_mode; | |
aaf78d27 PZ |
423 | } plane; |
424 | ||
425 | struct { | |
801c8fe8 | 426 | const struct drm_format_info *format; |
aaf78d27 | 427 | unsigned int stride; |
aaf78d27 PZ |
428 | } fb; |
429 | } state_cache; | |
430 | ||
525a4f93 PZ |
431 | /* |
432 | * This structure contains everything that's relevant to program the | |
433 | * hardware registers. When we want to figure out if we need to disable | |
434 | * and re-enable FBC for a new configuration we just check if there's | |
435 | * something different in the struct. The genx_fbc_activate functions | |
436 | * are supposed to read from it in order to program the registers. | |
437 | */ | |
b183b3f1 | 438 | struct intel_fbc_reg_params { |
be1e3415 | 439 | struct i915_vma *vma; |
1c9b6b13 | 440 | unsigned long flags; |
be1e3415 | 441 | |
b183b3f1 PZ |
442 | struct { |
443 | enum pipe pipe; | |
ed15030d | 444 | enum i9xx_plane_id i9xx_plane; |
b183b3f1 PZ |
445 | unsigned int fence_y_offset; |
446 | } crtc; | |
447 | ||
448 | struct { | |
801c8fe8 | 449 | const struct drm_format_info *format; |
b183b3f1 | 450 | unsigned int stride; |
b183b3f1 PZ |
451 | } fb; |
452 | ||
453 | int cfb_size; | |
5654a162 | 454 | unsigned int gen9_wa_cfb_stride; |
b183b3f1 PZ |
455 | } params; |
456 | ||
bf6189c6 | 457 | const char *no_fbc_reason; |
b5e50c3f JB |
458 | }; |
459 | ||
fe88d122 | 460 | /* |
96178eeb VK |
461 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
462 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
463 | * parsing for same resolution. | |
464 | */ | |
465 | enum drrs_refresh_rate_type { | |
466 | DRRS_HIGH_RR, | |
467 | DRRS_LOW_RR, | |
468 | DRRS_MAX_RR, /* RR count */ | |
469 | }; | |
470 | ||
471 | enum drrs_support_type { | |
472 | DRRS_NOT_SUPPORTED = 0, | |
473 | STATIC_DRRS_SUPPORT = 1, | |
474 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
475 | }; |
476 | ||
2807cf69 | 477 | struct intel_dp; |
96178eeb VK |
478 | struct i915_drrs { |
479 | struct mutex mutex; | |
480 | struct delayed_work work; | |
481 | struct intel_dp *dp; | |
482 | unsigned busy_frontbuffer_bits; | |
483 | enum drrs_refresh_rate_type refresh_rate_type; | |
484 | enum drrs_support_type type; | |
485 | }; | |
486 | ||
a031d709 | 487 | struct i915_psr { |
f0355c4a | 488 | struct mutex lock; |
c44301fc ML |
489 | |
490 | #define I915_PSR_DEBUG_MODE_MASK 0x0f | |
491 | #define I915_PSR_DEBUG_DEFAULT 0x00 | |
492 | #define I915_PSR_DEBUG_DISABLE 0x01 | |
493 | #define I915_PSR_DEBUG_ENABLE 0x02 | |
2ac45bdd | 494 | #define I915_PSR_DEBUG_FORCE_PSR1 0x03 |
c44301fc ML |
495 | #define I915_PSR_DEBUG_IRQ 0x10 |
496 | ||
497 | u32 debug; | |
a031d709 | 498 | bool sink_support; |
c44301fc ML |
499 | bool prepared, enabled; |
500 | struct intel_dp *dp; | |
f0ad62a6 | 501 | enum pipe pipe; |
7c8f8a70 | 502 | bool active; |
5422b37c | 503 | struct work_struct work; |
9ca15301 | 504 | unsigned busy_frontbuffer_bits; |
95f28d2e | 505 | bool sink_psr2_support; |
60e5ffe3 | 506 | bool link_standby; |
97da2ef4 | 507 | bool colorimetry_support; |
95f28d2e | 508 | bool psr2_enabled; |
26e5378d | 509 | u8 sink_sync_latency; |
3f983e54 DP |
510 | ktime_t last_entry_attempt; |
511 | ktime_t last_exit; | |
50a12d8f | 512 | bool sink_not_reliable; |
183b8e67 | 513 | bool irq_aux_error; |
3f51e471 | 514 | }; |
5c3fe8b0 | 515 | |
3bad0781 | 516 | enum intel_pch { |
f0350830 | 517 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 | 518 | PCH_IBX, /* Ibexpeak PCH */ |
243dec58 VS |
519 | PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ |
520 | PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ | |
e7e7ea20 | 521 | PCH_SPT, /* Sunrisepoint PCH */ |
23247d71 | 522 | PCH_KBP, /* Kaby Lake PCH */ |
298d6aaf | 523 | PCH_CNP, /* Cannon/Comet Lake PCH */ |
0b58436f | 524 | PCH_ICP, /* Ice Lake PCH */ |
b8bf31d8 | 525 | PCH_NOP, /* PCH without south display */ |
3bad0781 ZW |
526 | }; |
527 | ||
988d6ee8 PZ |
528 | enum intel_sbi_destination { |
529 | SBI_ICLK, | |
530 | SBI_MPHY, | |
531 | }; | |
532 | ||
435793df | 533 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 534 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 535 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
656bfa3a | 536 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
c99a259b | 537 | #define QUIRK_INCREASE_T12_DELAY (1<<6) |
90c3e219 | 538 | #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) |
b690e96c | 539 | |
8be48d92 | 540 | struct intel_fbdev; |
1630fe75 | 541 | struct intel_fbc_work; |
38651674 | 542 | |
c2b9152f DV |
543 | struct intel_gmbus { |
544 | struct i2c_adapter adapter; | |
3e4d44e0 | 545 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 546 | u32 force_bit; |
c2b9152f | 547 | u32 reg0; |
f0f59a00 | 548 | i915_reg_t gpio_reg; |
c167a6fc | 549 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
550 | struct drm_i915_private *dev_priv; |
551 | }; | |
552 | ||
f4c956ad | 553 | struct i915_suspend_saved_registers { |
e948e994 | 554 | u32 saveDSPARB; |
ba8bbcf6 | 555 | u32 saveFBC_CONTROL; |
1f84e550 | 556 | u32 saveCACHE_MODE_0; |
1f84e550 | 557 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
558 | u32 saveSWF0[16]; |
559 | u32 saveSWF1[16]; | |
85fa792b | 560 | u32 saveSWF3[3]; |
4b9de737 | 561 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 562 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 563 | u16 saveGCDGMBUS; |
f4c956ad | 564 | }; |
c85aa885 | 565 | |
ddeea5b0 ID |
566 | struct vlv_s0ix_state { |
567 | /* GAM */ | |
568 | u32 wr_watermark; | |
569 | u32 gfx_prio_ctrl; | |
570 | u32 arb_mode; | |
571 | u32 gfx_pend_tlb0; | |
572 | u32 gfx_pend_tlb1; | |
573 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
574 | u32 media_max_req_count; | |
575 | u32 gfx_max_req_count; | |
576 | u32 render_hwsp; | |
577 | u32 ecochk; | |
578 | u32 bsd_hwsp; | |
579 | u32 blt_hwsp; | |
580 | u32 tlb_rd_addr; | |
581 | ||
582 | /* MBC */ | |
583 | u32 g3dctl; | |
584 | u32 gsckgctl; | |
585 | u32 mbctl; | |
586 | ||
587 | /* GCP */ | |
588 | u32 ucgctl1; | |
589 | u32 ucgctl3; | |
590 | u32 rcgctl1; | |
591 | u32 rcgctl2; | |
592 | u32 rstctl; | |
593 | u32 misccpctl; | |
594 | ||
595 | /* GPM */ | |
596 | u32 gfxpause; | |
597 | u32 rpdeuhwtc; | |
598 | u32 rpdeuc; | |
599 | u32 ecobus; | |
600 | u32 pwrdwnupctl; | |
601 | u32 rp_down_timeout; | |
602 | u32 rp_deucsw; | |
603 | u32 rcubmabdtmr; | |
604 | u32 rcedata; | |
605 | u32 spare2gh; | |
606 | ||
607 | /* Display 1 CZ domain */ | |
608 | u32 gt_imr; | |
609 | u32 gt_ier; | |
610 | u32 pm_imr; | |
611 | u32 pm_ier; | |
612 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
613 | ||
614 | /* GT SA CZ domain */ | |
615 | u32 tilectl; | |
616 | u32 gt_fifoctl; | |
617 | u32 gtlc_wake_ctrl; | |
618 | u32 gtlc_survive; | |
619 | u32 pmwgicz; | |
620 | ||
621 | /* Display 2 CZ domain */ | |
622 | u32 gu_ctl0; | |
623 | u32 gu_ctl1; | |
9c25210f | 624 | u32 pcbr; |
ddeea5b0 ID |
625 | u32 clock_gate_dis2; |
626 | }; | |
627 | ||
bf225f20 | 628 | struct intel_rps_ei { |
679cb6c1 | 629 | ktime_t ktime; |
bf225f20 CW |
630 | u32 render_c0; |
631 | u32 media_c0; | |
31685c25 D |
632 | }; |
633 | ||
562d9bae | 634 | struct intel_rps { |
d4d70aa5 ID |
635 | /* |
636 | * work, interrupts_enabled and pm_iir are protected by | |
637 | * dev_priv->irq_lock | |
638 | */ | |
c85aa885 | 639 | struct work_struct work; |
d4d70aa5 | 640 | bool interrupts_enabled; |
c85aa885 | 641 | u32 pm_iir; |
59cdb63d | 642 | |
b20e3cfe | 643 | /* PM interrupt bits that should never be masked */ |
5dd04556 | 644 | u32 pm_intrmsk_mbz; |
1800ad25 | 645 | |
b39fb297 BW |
646 | /* Frequencies are stored in potentially platform dependent multiples. |
647 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
648 | * Soft limits are those which are used for the dynamic reclocking done | |
649 | * by the driver (raise frequencies under heavy loads, and lower for | |
650 | * lighter loads). Hard limits are those imposed by the hardware. | |
651 | * | |
652 | * A distinction is made for overclocking, which is never enabled by | |
653 | * default, and is considered to be above the hard limit if it's | |
654 | * possible at all. | |
655 | */ | |
656 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
657 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
658 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
659 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
660 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 661 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 662 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
663 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
664 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
665 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 666 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 667 | |
dd75fdc8 | 668 | int last_adj; |
60548c55 CW |
669 | |
670 | struct { | |
671 | struct mutex mutex; | |
672 | ||
673 | enum { LOW_POWER, BETWEEN, HIGH_POWER } mode; | |
674 | unsigned int interactive; | |
675 | ||
676 | u8 up_threshold; /* Current %busy required to uplock */ | |
677 | u8 down_threshold; /* Current %busy required to downclock */ | |
678 | } power; | |
dd75fdc8 | 679 | |
c0951f0c | 680 | bool enabled; |
7b92c1bd CW |
681 | atomic_t num_waiters; |
682 | atomic_t boosts; | |
4fc688ce | 683 | |
bf225f20 | 684 | /* manual wa residency calculations */ |
e0e8c7cb | 685 | struct intel_rps_ei ei; |
c85aa885 DV |
686 | }; |
687 | ||
37d933fc SAK |
688 | struct intel_rc6 { |
689 | bool enabled; | |
817cc079 TU |
690 | u64 prev_hw_residency[4]; |
691 | u64 cur_residency[4]; | |
37d933fc SAK |
692 | }; |
693 | ||
694 | struct intel_llc_pstate { | |
695 | bool enabled; | |
696 | }; | |
697 | ||
562d9bae SAK |
698 | struct intel_gen6_power_mgmt { |
699 | struct intel_rps rps; | |
37d933fc SAK |
700 | struct intel_rc6 rc6; |
701 | struct intel_llc_pstate llc_pstate; | |
562d9bae SAK |
702 | }; |
703 | ||
1a240d4d DV |
704 | /* defined intel_pm.c */ |
705 | extern spinlock_t mchdev_lock; | |
706 | ||
c85aa885 DV |
707 | struct intel_ilk_power_mgmt { |
708 | u8 cur_delay; | |
709 | u8 min_delay; | |
710 | u8 max_delay; | |
711 | u8 fmax; | |
712 | u8 fstart; | |
713 | ||
714 | u64 last_count1; | |
715 | unsigned long last_time1; | |
716 | unsigned long chipset_power; | |
717 | u64 last_count2; | |
5ed0bdf2 | 718 | u64 last_time2; |
c85aa885 DV |
719 | unsigned long gfx_power; |
720 | u8 corr; | |
721 | ||
722 | int c_m; | |
723 | int r_t; | |
724 | }; | |
725 | ||
c6cb582e ID |
726 | struct drm_i915_private; |
727 | struct i915_power_well; | |
728 | ||
729 | struct i915_power_well_ops { | |
730 | /* | |
731 | * Synchronize the well's hw state to match the current sw state, for | |
732 | * example enable/disable it based on the current refcount. Called | |
733 | * during driver init and resume time, possibly after first calling | |
734 | * the enable/disable handlers. | |
735 | */ | |
736 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
737 | struct i915_power_well *power_well); | |
738 | /* | |
739 | * Enable the well and resources that depend on it (for example | |
740 | * interrupts located on the well). Called after the 0->1 refcount | |
741 | * transition. | |
742 | */ | |
743 | void (*enable)(struct drm_i915_private *dev_priv, | |
744 | struct i915_power_well *power_well); | |
745 | /* | |
746 | * Disable the well and resources that depend on it. Called after | |
747 | * the 1->0 refcount transition. | |
748 | */ | |
749 | void (*disable)(struct drm_i915_private *dev_priv, | |
750 | struct i915_power_well *power_well); | |
751 | /* Returns the hw enabled state. */ | |
752 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
753 | struct i915_power_well *power_well); | |
754 | }; | |
755 | ||
75e39688 ID |
756 | struct i915_power_well_regs { |
757 | i915_reg_t bios; | |
758 | i915_reg_t driver; | |
759 | i915_reg_t kvmr; | |
760 | i915_reg_t debug; | |
761 | }; | |
762 | ||
a38911a3 | 763 | /* Power well structure for haswell */ |
f28ec6f4 | 764 | struct i915_power_well_desc { |
c1ca727f | 765 | const char *name; |
6f3ef5dd | 766 | bool always_on; |
d8fc70b7 | 767 | u64 domains; |
01c3faa7 | 768 | /* unique identifier for this power well */ |
438b8dc4 | 769 | enum i915_power_well_id id; |
362624c9 ACO |
770 | /* |
771 | * Arbitraty data associated with this power well. Platform and power | |
772 | * well specific. | |
773 | */ | |
b5565a2e | 774 | union { |
d13dd05a ID |
775 | struct { |
776 | /* | |
777 | * request/status flag index in the PUNIT power well | |
778 | * control/status registers. | |
779 | */ | |
780 | u8 idx; | |
781 | } vlv; | |
b5565a2e ID |
782 | struct { |
783 | enum dpio_phy phy; | |
784 | } bxt; | |
001bd2cb | 785 | struct { |
75e39688 ID |
786 | const struct i915_power_well_regs *regs; |
787 | /* | |
788 | * request/status flag index in the power well | |
789 | * constrol/status registers. | |
790 | */ | |
791 | u8 idx; | |
001bd2cb ID |
792 | /* Mask of pipes whose IRQ logic is backed by the pw */ |
793 | u8 irq_pipe_mask; | |
794 | /* The pw is backing the VGA functionality */ | |
795 | bool has_vga:1; | |
b2891eb2 | 796 | bool has_fuses:1; |
c7375d95 ID |
797 | /* |
798 | * The pw is for an ICL+ TypeC PHY port in | |
799 | * Thunderbolt mode. | |
800 | */ | |
801 | bool is_tc_tbt:1; | |
001bd2cb | 802 | } hsw; |
b5565a2e | 803 | }; |
c6cb582e | 804 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
805 | }; |
806 | ||
f28ec6f4 ID |
807 | struct i915_power_well { |
808 | const struct i915_power_well_desc *desc; | |
809 | /* power well enable/disable usage count */ | |
810 | int count; | |
811 | /* cached hw enabled state */ | |
812 | bool hw_enabled; | |
813 | }; | |
814 | ||
83c00f55 | 815 | struct i915_power_domains { |
baa70707 ID |
816 | /* |
817 | * Power wells needed for initialization at driver init and suspend | |
818 | * time are on. They are kept on until after the first modeset. | |
819 | */ | |
0d116a29 | 820 | bool initializing; |
2cd9a689 | 821 | bool display_core_suspended; |
c1ca727f | 822 | int power_well_count; |
baa70707 | 823 | |
83c00f55 | 824 | struct mutex lock; |
1da51581 | 825 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 826 | struct i915_power_well *power_wells; |
83c00f55 ID |
827 | }; |
828 | ||
35a85ac6 | 829 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 830 | struct intel_l3_parity { |
35a85ac6 | 831 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 832 | struct work_struct error_work; |
35a85ac6 | 833 | int which_slice; |
a4da4fa4 DV |
834 | }; |
835 | ||
4b5aed62 | 836 | struct i915_gem_mm { |
4b5aed62 DV |
837 | /** Memory allocator for GTT stolen memory */ |
838 | struct drm_mm stolen; | |
92e97d2f PZ |
839 | /** Protects the usage of the GTT stolen memory allocator. This is |
840 | * always the inner lock when overlapping with struct_mutex. */ | |
841 | struct mutex stolen_lock; | |
842 | ||
f2123818 CW |
843 | /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ |
844 | spinlock_t obj_lock; | |
845 | ||
4b5aed62 DV |
846 | /** List of all objects in gtt_space. Used to restore gtt |
847 | * mappings on resume */ | |
848 | struct list_head bound_list; | |
849 | /** | |
850 | * List of objects which are not bound to the GTT (thus | |
fbbd37b3 CW |
851 | * are idle and not used by the GPU). These objects may or may |
852 | * not actually have any pages attached. | |
4b5aed62 DV |
853 | */ |
854 | struct list_head unbound_list; | |
855 | ||
275f039d CW |
856 | /** List of all objects in gtt_space, currently mmaped by userspace. |
857 | * All objects within this list must also be on bound_list. | |
858 | */ | |
859 | struct list_head userfault_list; | |
860 | ||
fbbd37b3 CW |
861 | /** |
862 | * List of objects which are pending destruction. | |
863 | */ | |
864 | struct llist_head free_list; | |
865 | struct work_struct free_work; | |
87701b4b | 866 | spinlock_t free_lock; |
c9c70471 CW |
867 | /** |
868 | * Count of objects pending destructions. Used to skip needlessly | |
869 | * waiting on an RCU barrier if no objects are waiting to be freed. | |
870 | */ | |
871 | atomic_t free_count; | |
fbbd37b3 | 872 | |
66df1014 CW |
873 | /** |
874 | * Small stash of WC pages | |
875 | */ | |
63fd659f | 876 | struct pagestash wc_stash; |
66df1014 | 877 | |
465c403c MA |
878 | /** |
879 | * tmpfs instance used for shmem backed objects | |
880 | */ | |
881 | struct vfsmount *gemfs; | |
882 | ||
4b5aed62 DV |
883 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
884 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
885 | ||
2cfcd32a | 886 | struct notifier_block oom_notifier; |
e87666b5 | 887 | struct notifier_block vmap_notifier; |
ceabbba5 | 888 | struct shrinker shrinker; |
4b5aed62 | 889 | |
4b5aed62 DV |
890 | /** LRU list of objects with fence regs on them. */ |
891 | struct list_head fence_list; | |
892 | ||
8a2421bd CW |
893 | /** |
894 | * Workqueue to fault in userptr pages, flushed by the execbuf | |
895 | * when required but otherwise left to userspace to try again | |
896 | * on EAGAIN. | |
897 | */ | |
898 | struct workqueue_struct *userptr_wq; | |
899 | ||
94312828 CW |
900 | u64 unordered_timeline; |
901 | ||
bdf1e7e3 | 902 | /* the indicator for dispatch video commands on two BSD rings */ |
6f633402 | 903 | atomic_t bsd_engine_dispatch_index; |
bdf1e7e3 | 904 | |
4b5aed62 DV |
905 | /** Bit 6 swizzling required for X tiling */ |
906 | uint32_t bit_6_swizzle_x; | |
907 | /** Bit 6 swizzling required for Y tiling */ | |
908 | uint32_t bit_6_swizzle_y; | |
909 | ||
4b5aed62 | 910 | /* accounting, useful for userland debugging */ |
c20e8355 | 911 | spinlock_t object_stat_lock; |
3ef7f228 | 912 | u64 object_memory; |
4b5aed62 DV |
913 | u32 object_count; |
914 | }; | |
915 | ||
ee42c00e CW |
916 | #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ |
917 | ||
b52992c0 CW |
918 | #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ |
919 | #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ | |
920 | ||
3fe3b030 MK |
921 | #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ |
922 | #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ | |
923 | ||
1fd00c0f CW |
924 | #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ |
925 | ||
6acab15a | 926 | struct ddi_vbt_port_info { |
d6038611 VS |
927 | int max_tmds_clock; |
928 | ||
ce4dd49e DL |
929 | /* |
930 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
931 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
932 | * populate this field. | |
933 | */ | |
934 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 935 | uint8_t hdmi_level_shift; |
311a2094 PZ |
936 | |
937 | uint8_t supports_dvi:1; | |
938 | uint8_t supports_hdmi:1; | |
939 | uint8_t supports_dp:1; | |
a98d9c1d | 940 | uint8_t supports_edp:1; |
500ea70d RV |
941 | |
942 | uint8_t alternate_aux_channel; | |
11c1b657 | 943 | uint8_t alternate_ddc_pin; |
75067dde AK |
944 | |
945 | uint8_t dp_boost_level; | |
946 | uint8_t hdmi_boost_level; | |
99b91bda | 947 | int dp_max_link_rate; /* 0 for not limited by VBT */ |
6acab15a PZ |
948 | }; |
949 | ||
bfd7ebda RV |
950 | enum psr_lines_to_wait { |
951 | PSR_0_LINES_TO_WAIT = 0, | |
952 | PSR_1_LINE_TO_WAIT, | |
953 | PSR_4_LINES_TO_WAIT, | |
954 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
955 | }; |
956 | ||
41aa3448 RV |
957 | struct intel_vbt_data { |
958 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
959 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
960 | ||
961 | /* Feature bits */ | |
962 | unsigned int int_tv_support:1; | |
963 | unsigned int lvds_dither:1; | |
41aa3448 RV |
964 | unsigned int int_crt_support:1; |
965 | unsigned int lvds_use_ssc:1; | |
5255e2f8 | 966 | unsigned int int_lvds_support:1; |
41aa3448 RV |
967 | unsigned int display_clock_mode:1; |
968 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 969 | unsigned int panel_type:4; |
41aa3448 RV |
970 | int lvds_ssc_freq; |
971 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
c1cd5b24 | 972 | enum drm_panel_orientation orientation; |
41aa3448 | 973 | |
83a7280e PB |
974 | enum drrs_support_type drrs_type; |
975 | ||
6aa23e65 JN |
976 | struct { |
977 | int rate; | |
978 | int lanes; | |
979 | int preemphasis; | |
980 | int vswing; | |
06411f08 | 981 | bool low_vswing; |
6aa23e65 | 982 | bool initialized; |
6aa23e65 JN |
983 | int bpp; |
984 | struct edp_power_seq pps; | |
985 | } edp; | |
41aa3448 | 986 | |
bfd7ebda | 987 | struct { |
2bdd045e | 988 | bool enable; |
bfd7ebda RV |
989 | bool full_link; |
990 | bool require_aux_wakeup; | |
991 | int idle_frames; | |
992 | enum psr_lines_to_wait lines_to_wait; | |
77312ae8 VN |
993 | int tp1_wakeup_time_us; |
994 | int tp2_tp3_wakeup_time_us; | |
bfd7ebda RV |
995 | } psr; |
996 | ||
f00076d2 JN |
997 | struct { |
998 | u16 pwm_freq_hz; | |
39fbc9c8 | 999 | bool present; |
f00076d2 | 1000 | bool active_low_pwm; |
1de6068e | 1001 | u8 min_brightness; /* min_brightness/255 of max */ |
add03379 | 1002 | u8 controller; /* brightness controller number */ |
9a41e17d | 1003 | enum intel_backlight_type type; |
f00076d2 JN |
1004 | } backlight; |
1005 | ||
d17c5443 SK |
1006 | /* MIPI DSI */ |
1007 | struct { | |
1008 | u16 panel_id; | |
d3b542fc SK |
1009 | struct mipi_config *config; |
1010 | struct mipi_pps_data *pps; | |
46e58320 MC |
1011 | u16 bl_ports; |
1012 | u16 cabc_ports; | |
d3b542fc SK |
1013 | u8 seq_version; |
1014 | u32 size; | |
1015 | u8 *data; | |
8d3ed2f3 | 1016 | const u8 *sequence[MIPI_SEQ_MAX]; |
fb38e7ad | 1017 | u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ |
c1cd5b24 | 1018 | enum drm_panel_orientation orientation; |
d17c5443 SK |
1019 | } dsi; |
1020 | ||
41aa3448 RV |
1021 | int crt_ddc_pin; |
1022 | ||
1023 | int child_dev_num; | |
cc998589 | 1024 | struct child_device_config *child_dev; |
6acab15a PZ |
1025 | |
1026 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1027 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1028 | }; |
1029 | ||
77c122bc VS |
1030 | enum intel_ddb_partitioning { |
1031 | INTEL_DDB_PART_1_2, | |
1032 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1033 | }; | |
1034 | ||
1fd527cc VS |
1035 | struct intel_wm_level { |
1036 | bool enable; | |
1037 | uint32_t pri_val; | |
1038 | uint32_t spr_val; | |
1039 | uint32_t cur_val; | |
1040 | uint32_t fbc_val; | |
1041 | }; | |
1042 | ||
820c1980 | 1043 | struct ilk_wm_values { |
609cedef VS |
1044 | uint32_t wm_pipe[3]; |
1045 | uint32_t wm_lp[3]; | |
1046 | uint32_t wm_lp_spr[3]; | |
1047 | uint32_t wm_linetime[3]; | |
1048 | bool enable_fbc_wm; | |
1049 | enum intel_ddb_partitioning partitioning; | |
1050 | }; | |
1051 | ||
114d7dc0 | 1052 | struct g4x_pipe_wm { |
1b31389c | 1053 | uint16_t plane[I915_MAX_PLANES]; |
04548cba | 1054 | uint16_t fbc; |
262cd2e1 | 1055 | }; |
ae80152d | 1056 | |
114d7dc0 | 1057 | struct g4x_sr_wm { |
262cd2e1 | 1058 | uint16_t plane; |
1b31389c | 1059 | uint16_t cursor; |
04548cba | 1060 | uint16_t fbc; |
1b31389c VS |
1061 | }; |
1062 | ||
1063 | struct vlv_wm_ddl_values { | |
1064 | uint8_t plane[I915_MAX_PLANES]; | |
262cd2e1 | 1065 | }; |
ae80152d | 1066 | |
262cd2e1 | 1067 | struct vlv_wm_values { |
114d7dc0 VS |
1068 | struct g4x_pipe_wm pipe[3]; |
1069 | struct g4x_sr_wm sr; | |
1b31389c | 1070 | struct vlv_wm_ddl_values ddl[3]; |
6eb1a681 VS |
1071 | uint8_t level; |
1072 | bool cxsr; | |
0018fda1 VS |
1073 | }; |
1074 | ||
04548cba VS |
1075 | struct g4x_wm_values { |
1076 | struct g4x_pipe_wm pipe[2]; | |
1077 | struct g4x_sr_wm sr; | |
1078 | struct g4x_sr_wm hpll; | |
1079 | bool cxsr; | |
1080 | bool hpll_en; | |
1081 | bool fbc_en; | |
1082 | }; | |
1083 | ||
c193924e | 1084 | struct skl_ddb_entry { |
16160e3d | 1085 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1086 | }; |
1087 | ||
1088 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1089 | { | |
16160e3d | 1090 | return entry->end - entry->start; |
c193924e DL |
1091 | } |
1092 | ||
08db6652 DL |
1093 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1094 | const struct skl_ddb_entry *e2) | |
1095 | { | |
1096 | if (e1->start == e2->start && e1->end == e2->end) | |
1097 | return true; | |
1098 | ||
1099 | return false; | |
1100 | } | |
1101 | ||
c193924e | 1102 | struct skl_ddb_allocation { |
74bd8004 | 1103 | u8 enabled_slices; /* GEN11 has configurable 2 slices */ |
c193924e DL |
1104 | }; |
1105 | ||
60f8e873 | 1106 | struct skl_ddb_values { |
2b4b9f35 | 1107 | unsigned dirty_pipes; |
c193924e | 1108 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1109 | }; |
1110 | ||
1111 | struct skl_wm_level { | |
a62163e9 L |
1112 | uint16_t plane_res_b; |
1113 | uint8_t plane_res_l; | |
eeba5b5c | 1114 | bool plane_en; |
2ac96d2a PB |
1115 | }; |
1116 | ||
7e452fdb KM |
1117 | /* Stores plane specific WM parameters */ |
1118 | struct skl_wm_params { | |
1119 | bool x_tiled, y_tiled; | |
1120 | bool rc_surface; | |
942aa2d0 | 1121 | bool is_planar; |
7e452fdb KM |
1122 | uint32_t width; |
1123 | uint8_t cpp; | |
1124 | uint32_t plane_pixel_rate; | |
1125 | uint32_t y_min_scanlines; | |
1126 | uint32_t plane_bytes_per_line; | |
1127 | uint_fixed_16_16_t plane_blocks_per_line; | |
1128 | uint_fixed_16_16_t y_tile_minimum; | |
1129 | uint32_t linetime_us; | |
df8ee190 | 1130 | uint32_t dbuf_block_size; |
7e452fdb KM |
1131 | }; |
1132 | ||
c67a470b | 1133 | /* |
765dab67 PZ |
1134 | * This struct helps tracking the state needed for runtime PM, which puts the |
1135 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1136 | * graphics device works, even register access, so we don't get interrupts nor | |
1137 | * anything else. | |
c67a470b | 1138 | * |
765dab67 PZ |
1139 | * Every piece of our code that needs to actually touch the hardware needs to |
1140 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1141 | * appropriate power domain. | |
a8a8bd54 | 1142 | * |
765dab67 PZ |
1143 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1144 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1145 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1146 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1147 | * |
1148 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1149 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1150 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1151 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1152 | * case it happens. |
c67a470b | 1153 | * |
765dab67 | 1154 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1155 | */ |
5d584b2e | 1156 | struct i915_runtime_pm { |
1f814dac | 1157 | atomic_t wakeref_count; |
5d584b2e | 1158 | bool suspended; |
2aeb7d3a | 1159 | bool irqs_enabled; |
c67a470b PZ |
1160 | }; |
1161 | ||
926321d5 DV |
1162 | enum intel_pipe_crc_source { |
1163 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1164 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1165 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1166 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1167 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1168 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1169 | INTEL_PIPE_CRC_SOURCE_TV, | |
1170 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1171 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1172 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1173 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1174 | INTEL_PIPE_CRC_SOURCE_MAX, |
1175 | }; | |
1176 | ||
b2c88f5b | 1177 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1178 | struct intel_pipe_crc { |
d538bbdf | 1179 | spinlock_t lock; |
8c6b709d | 1180 | int skipped; |
6cc42152 | 1181 | enum intel_pipe_crc_source source; |
8bf1e9f1 SH |
1182 | }; |
1183 | ||
f99d7069 | 1184 | struct i915_frontbuffer_tracking { |
b5add959 | 1185 | spinlock_t lock; |
f99d7069 DV |
1186 | |
1187 | /* | |
1188 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1189 | * scheduled flips. | |
1190 | */ | |
1191 | unsigned busy_bits; | |
1192 | unsigned flip_bits; | |
1193 | }; | |
1194 | ||
cf9d2890 YZ |
1195 | struct i915_virtual_gpu { |
1196 | bool active; | |
8a4ab66f | 1197 | u32 caps; |
cf9d2890 YZ |
1198 | }; |
1199 | ||
aa363136 MR |
1200 | /* used in computing the new watermarks state */ |
1201 | struct intel_wm_config { | |
1202 | unsigned int num_pipes_active; | |
1203 | bool sprites_enabled; | |
1204 | bool sprites_scaled; | |
1205 | }; | |
1206 | ||
d7965152 RB |
1207 | struct i915_oa_format { |
1208 | u32 format; | |
1209 | int size; | |
1210 | }; | |
1211 | ||
8a3003dd RB |
1212 | struct i915_oa_reg { |
1213 | i915_reg_t addr; | |
1214 | u32 value; | |
1215 | }; | |
1216 | ||
701f8231 LL |
1217 | struct i915_oa_config { |
1218 | char uuid[UUID_STRING_LEN + 1]; | |
1219 | int id; | |
1220 | ||
1221 | const struct i915_oa_reg *mux_regs; | |
1222 | u32 mux_regs_len; | |
1223 | const struct i915_oa_reg *b_counter_regs; | |
1224 | u32 b_counter_regs_len; | |
1225 | const struct i915_oa_reg *flex_regs; | |
1226 | u32 flex_regs_len; | |
1227 | ||
1228 | struct attribute_group sysfs_metric; | |
1229 | struct attribute *attrs[2]; | |
1230 | struct device_attribute sysfs_metric_id; | |
f89823c2 LL |
1231 | |
1232 | atomic_t ref_count; | |
701f8231 LL |
1233 | }; |
1234 | ||
eec688e1 RB |
1235 | struct i915_perf_stream; |
1236 | ||
16d98b31 RB |
1237 | /** |
1238 | * struct i915_perf_stream_ops - the OPs to support a specific stream type | |
1239 | */ | |
eec688e1 | 1240 | struct i915_perf_stream_ops { |
16d98b31 RB |
1241 | /** |
1242 | * @enable: Enables the collection of HW samples, either in response to | |
1243 | * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened | |
1244 | * without `I915_PERF_FLAG_DISABLED`. | |
eec688e1 RB |
1245 | */ |
1246 | void (*enable)(struct i915_perf_stream *stream); | |
1247 | ||
16d98b31 RB |
1248 | /** |
1249 | * @disable: Disables the collection of HW samples, either in response | |
1250 | * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying | |
1251 | * the stream. | |
eec688e1 RB |
1252 | */ |
1253 | void (*disable)(struct i915_perf_stream *stream); | |
1254 | ||
16d98b31 RB |
1255 | /** |
1256 | * @poll_wait: Call poll_wait, passing a wait queue that will be woken | |
eec688e1 RB |
1257 | * once there is something ready to read() for the stream |
1258 | */ | |
1259 | void (*poll_wait)(struct i915_perf_stream *stream, | |
1260 | struct file *file, | |
1261 | poll_table *wait); | |
1262 | ||
16d98b31 RB |
1263 | /** |
1264 | * @wait_unlocked: For handling a blocking read, wait until there is | |
1265 | * something to ready to read() for the stream. E.g. wait on the same | |
d7965152 | 1266 | * wait queue that would be passed to poll_wait(). |
eec688e1 RB |
1267 | */ |
1268 | int (*wait_unlocked)(struct i915_perf_stream *stream); | |
1269 | ||
16d98b31 RB |
1270 | /** |
1271 | * @read: Copy buffered metrics as records to userspace | |
1272 | * **buf**: the userspace, destination buffer | |
1273 | * **count**: the number of bytes to copy, requested by userspace | |
1274 | * **offset**: zero at the start of the read, updated as the read | |
1275 | * proceeds, it represents how many bytes have been copied so far and | |
1276 | * the buffer offset for copying the next record. | |
eec688e1 | 1277 | * |
16d98b31 RB |
1278 | * Copy as many buffered i915 perf samples and records for this stream |
1279 | * to userspace as will fit in the given buffer. | |
eec688e1 | 1280 | * |
16d98b31 RB |
1281 | * Only write complete records; returning -%ENOSPC if there isn't room |
1282 | * for a complete record. | |
eec688e1 | 1283 | * |
16d98b31 RB |
1284 | * Return any error condition that results in a short read such as |
1285 | * -%ENOSPC or -%EFAULT, even though these may be squashed before | |
1286 | * returning to userspace. | |
eec688e1 RB |
1287 | */ |
1288 | int (*read)(struct i915_perf_stream *stream, | |
1289 | char __user *buf, | |
1290 | size_t count, | |
1291 | size_t *offset); | |
1292 | ||
16d98b31 RB |
1293 | /** |
1294 | * @destroy: Cleanup any stream specific resources. | |
eec688e1 RB |
1295 | * |
1296 | * The stream will always be disabled before this is called. | |
1297 | */ | |
1298 | void (*destroy)(struct i915_perf_stream *stream); | |
1299 | }; | |
1300 | ||
16d98b31 RB |
1301 | /** |
1302 | * struct i915_perf_stream - state for a single open stream FD | |
1303 | */ | |
eec688e1 | 1304 | struct i915_perf_stream { |
16d98b31 RB |
1305 | /** |
1306 | * @dev_priv: i915 drm device | |
1307 | */ | |
eec688e1 RB |
1308 | struct drm_i915_private *dev_priv; |
1309 | ||
16d98b31 RB |
1310 | /** |
1311 | * @link: Links the stream into ``&drm_i915_private->streams`` | |
1312 | */ | |
eec688e1 RB |
1313 | struct list_head link; |
1314 | ||
16d98b31 RB |
1315 | /** |
1316 | * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` | |
1317 | * properties given when opening a stream, representing the contents | |
1318 | * of a single sample as read() by userspace. | |
1319 | */ | |
eec688e1 | 1320 | u32 sample_flags; |
16d98b31 RB |
1321 | |
1322 | /** | |
1323 | * @sample_size: Considering the configured contents of a sample | |
1324 | * combined with the required header size, this is the total size | |
1325 | * of a single sample record. | |
1326 | */ | |
d7965152 | 1327 | int sample_size; |
eec688e1 | 1328 | |
16d98b31 RB |
1329 | /** |
1330 | * @ctx: %NULL if measuring system-wide across all contexts or a | |
1331 | * specific context that is being monitored. | |
1332 | */ | |
eec688e1 | 1333 | struct i915_gem_context *ctx; |
16d98b31 RB |
1334 | |
1335 | /** | |
1336 | * @enabled: Whether the stream is currently enabled, considering | |
1337 | * whether the stream was opened in a disabled state and based | |
1338 | * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. | |
1339 | */ | |
eec688e1 RB |
1340 | bool enabled; |
1341 | ||
16d98b31 RB |
1342 | /** |
1343 | * @ops: The callbacks providing the implementation of this specific | |
1344 | * type of configured stream. | |
1345 | */ | |
d7965152 | 1346 | const struct i915_perf_stream_ops *ops; |
701f8231 LL |
1347 | |
1348 | /** | |
1349 | * @oa_config: The OA configuration used by the stream. | |
1350 | */ | |
1351 | struct i915_oa_config *oa_config; | |
d7965152 RB |
1352 | }; |
1353 | ||
16d98b31 RB |
1354 | /** |
1355 | * struct i915_oa_ops - Gen specific implementation of an OA unit stream | |
1356 | */ | |
d7965152 | 1357 | struct i915_oa_ops { |
f89823c2 LL |
1358 | /** |
1359 | * @is_valid_b_counter_reg: Validates register's address for | |
1360 | * programming boolean counters for a particular platform. | |
1361 | */ | |
1362 | bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, | |
1363 | u32 addr); | |
1364 | ||
1365 | /** | |
1366 | * @is_valid_mux_reg: Validates register's address for programming mux | |
1367 | * for a particular platform. | |
1368 | */ | |
1369 | bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
1370 | ||
1371 | /** | |
1372 | * @is_valid_flex_reg: Validates register's address for programming | |
1373 | * flex EU filtering for a particular platform. | |
1374 | */ | |
1375 | bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
1376 | ||
19f81df2 RB |
1377 | /** |
1378 | * @enable_metric_set: Selects and applies any MUX configuration to set | |
1379 | * up the Boolean and Custom (B/C) counters that are part of the | |
1380 | * counter reports being sampled. May apply system constraints such as | |
16d98b31 RB |
1381 | * disabling EU clock gating as required. |
1382 | */ | |
5728de2f | 1383 | int (*enable_metric_set)(struct i915_perf_stream *stream); |
16d98b31 RB |
1384 | |
1385 | /** | |
1386 | * @disable_metric_set: Remove system constraints associated with using | |
1387 | * the OA unit. | |
1388 | */ | |
d7965152 | 1389 | void (*disable_metric_set)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
1390 | |
1391 | /** | |
1392 | * @oa_enable: Enable periodic sampling | |
1393 | */ | |
5728de2f | 1394 | void (*oa_enable)(struct i915_perf_stream *stream); |
16d98b31 RB |
1395 | |
1396 | /** | |
1397 | * @oa_disable: Disable periodic sampling | |
1398 | */ | |
5728de2f | 1399 | void (*oa_disable)(struct i915_perf_stream *stream); |
16d98b31 RB |
1400 | |
1401 | /** | |
1402 | * @read: Copy data from the circular OA buffer into a given userspace | |
1403 | * buffer. | |
1404 | */ | |
d7965152 RB |
1405 | int (*read)(struct i915_perf_stream *stream, |
1406 | char __user *buf, | |
1407 | size_t count, | |
1408 | size_t *offset); | |
16d98b31 RB |
1409 | |
1410 | /** | |
19f81df2 | 1411 | * @oa_hw_tail_read: read the OA tail pointer register |
16d98b31 | 1412 | * |
19f81df2 RB |
1413 | * In particular this enables us to share all the fiddly code for |
1414 | * handling the OA unit tail pointer race that affects multiple | |
1415 | * generations. | |
16d98b31 | 1416 | */ |
19f81df2 | 1417 | u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv); |
eec688e1 RB |
1418 | }; |
1419 | ||
49cd97a3 | 1420 | struct intel_cdclk_state { |
b6c51c3e | 1421 | unsigned int cdclk, vco, ref, bypass; |
64600bd5 | 1422 | u8 voltage_level; |
49cd97a3 VS |
1423 | }; |
1424 | ||
77fec556 | 1425 | struct drm_i915_private { |
8f460e2c CW |
1426 | struct drm_device drm; |
1427 | ||
efab6d8d | 1428 | struct kmem_cache *objects; |
e20d2ab7 | 1429 | struct kmem_cache *vmas; |
d1b48c1e | 1430 | struct kmem_cache *luts; |
efab6d8d | 1431 | struct kmem_cache *requests; |
52e54209 | 1432 | struct kmem_cache *dependencies; |
c5cf9a91 | 1433 | struct kmem_cache *priorities; |
f4c956ad | 1434 | |
5c969aa7 | 1435 | const struct intel_device_info info; |
3fed1808 | 1436 | struct intel_driver_caps caps; |
f4c956ad | 1437 | |
77894226 MA |
1438 | /** |
1439 | * Data Stolen Memory - aka "i915 stolen memory" gives us the start and | |
1440 | * end of stolen which we can optionally use to create GEM objects | |
b1ace601 | 1441 | * backed by stolen memory. Note that stolen_usable_size tells us |
77894226 MA |
1442 | * exactly how much of this we are actually allowed to use, given that |
1443 | * some portion of it is in fact reserved for use by hardware functions. | |
1444 | */ | |
1445 | struct resource dsm; | |
17a05345 MA |
1446 | /** |
1447 | * Reseved portion of Data Stolen Memory | |
1448 | */ | |
1449 | struct resource dsm_reserved; | |
77894226 | 1450 | |
b1ace601 MA |
1451 | /* |
1452 | * Stolen memory is segmented in hardware with different portions | |
1453 | * offlimits to certain functions. | |
1454 | * | |
1455 | * The drm_mm is initialised to the total accessible range, as found | |
1456 | * from the PCI config. On Broadwell+, this is further restricted to | |
1457 | * avoid the first page! The upper end of stolen memory is reserved for | |
1458 | * hardware functions and similarly removed from the accessible range. | |
1459 | */ | |
b7128ef1 | 1460 | resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ |
b1ace601 | 1461 | |
f4c956ad DV |
1462 | void __iomem *regs; |
1463 | ||
907b28c5 | 1464 | struct intel_uncore uncore; |
f4c956ad | 1465 | |
cf9d2890 YZ |
1466 | struct i915_virtual_gpu vgpu; |
1467 | ||
feddf6e8 | 1468 | struct intel_gvt *gvt; |
0ad35fed | 1469 | |
6b0478fb JL |
1470 | struct intel_wopcm wopcm; |
1471 | ||
bd132858 | 1472 | struct intel_huc huc; |
33a732f4 AD |
1473 | struct intel_guc guc; |
1474 | ||
eb805623 DV |
1475 | struct intel_csr csr; |
1476 | ||
5ea6e5e3 | 1477 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1478 | |
f4c956ad DV |
1479 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1480 | * controller on different i2c buses. */ | |
1481 | struct mutex gmbus_mutex; | |
1482 | ||
1483 | /** | |
dce88879 LDM |
1484 | * Base address of where the gmbus and gpio blocks are located (either |
1485 | * on PCH or on SoC for platforms without PCH). | |
f4c956ad DV |
1486 | */ |
1487 | uint32_t gpio_mmio_base; | |
1488 | ||
b6fdd0f2 SS |
1489 | /* MMIO base address for MIPI regs */ |
1490 | uint32_t mipi_mmio_base; | |
1491 | ||
443a389f VS |
1492 | uint32_t psr_mmio_base; |
1493 | ||
44cb734c ID |
1494 | uint32_t pps_mmio_base; |
1495 | ||
28c70f16 DV |
1496 | wait_queue_head_t gmbus_wait_queue; |
1497 | ||
f4c956ad | 1498 | struct pci_dev *bridge_dev; |
3b3f1650 | 1499 | struct intel_engine_cs *engine[I915_NUM_ENGINES]; |
e7af3116 CW |
1500 | /* Context used internally to idle the GPU and setup initial state */ |
1501 | struct i915_gem_context *kernel_context; | |
1502 | /* Context only to be used for injecting preemption commands */ | |
1503 | struct i915_gem_context *preempt_context; | |
b46a33e2 TU |
1504 | struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] |
1505 | [MAX_ENGINE_INSTANCE + 1]; | |
f4c956ad | 1506 | |
f4c956ad DV |
1507 | struct resource mch_res; |
1508 | ||
f4c956ad DV |
1509 | /* protects the irq masks */ |
1510 | spinlock_t irq_lock; | |
1511 | ||
f8b79e58 ID |
1512 | bool display_irqs_enabled; |
1513 | ||
9ee32fea DV |
1514 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1515 | struct pm_qos_request pm_qos; | |
1516 | ||
a580516d VS |
1517 | /* Sideband mailbox protection */ |
1518 | struct mutex sb_lock; | |
f4c956ad DV |
1519 | |
1520 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1521 | union { |
1522 | u32 irq_mask; | |
1523 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1524 | }; | |
f4c956ad | 1525 | u32 gt_irq_mask; |
f4e9af4f AG |
1526 | u32 pm_imr; |
1527 | u32 pm_ier; | |
a6706b45 | 1528 | u32 pm_rps_events; |
26705e20 | 1529 | u32 pm_guc_events; |
91d181dd | 1530 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1531 | |
5fcece80 | 1532 | struct i915_hotplug hotplug; |
ab34a7e8 | 1533 | struct intel_fbc fbc; |
439d7ac0 | 1534 | struct i915_drrs drrs; |
f4c956ad | 1535 | struct intel_opregion opregion; |
41aa3448 | 1536 | struct intel_vbt_data vbt; |
f4c956ad | 1537 | |
d9ceb816 JB |
1538 | bool preserve_bios_swizzle; |
1539 | ||
f4c956ad DV |
1540 | /* overlay */ |
1541 | struct intel_overlay *overlay; | |
f4c956ad | 1542 | |
58c68779 | 1543 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1544 | struct mutex backlight_lock; |
31ad8ec6 | 1545 | |
f4c956ad | 1546 | /* LVDS info */ |
f4c956ad DV |
1547 | bool no_aux_handshake; |
1548 | ||
e39b999a VS |
1549 | /* protects panel power sequencer state */ |
1550 | struct mutex pps_mutex; | |
1551 | ||
f4c956ad | 1552 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1553 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1554 | ||
1555 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 1556 | unsigned int skl_preferred_vco_freq; |
49cd97a3 | 1557 | unsigned int max_cdclk_freq; |
8d96561a | 1558 | |
adafdc6f | 1559 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1560 | unsigned int rawclk_freq; |
6bcda4f0 | 1561 | unsigned int hpll_freq; |
58ecd9d5 | 1562 | unsigned int fdi_pll_freq; |
bfa7df01 | 1563 | unsigned int czclk_freq; |
f4c956ad | 1564 | |
63911d72 | 1565 | struct { |
bb0f4aab VS |
1566 | /* |
1567 | * The current logical cdclk state. | |
1568 | * See intel_atomic_state.cdclk.logical | |
1569 | * | |
1570 | * For reading holding any crtc lock is sufficient, | |
1571 | * for writing must hold all of them. | |
1572 | */ | |
1573 | struct intel_cdclk_state logical; | |
1574 | /* | |
1575 | * The current actual cdclk state. | |
1576 | * See intel_atomic_state.cdclk.actual | |
1577 | */ | |
1578 | struct intel_cdclk_state actual; | |
1579 | /* The current hardware cdclk state */ | |
49cd97a3 | 1580 | struct intel_cdclk_state hw; |
385e40fe VS |
1581 | |
1582 | int force_min_cdclk; | |
49cd97a3 | 1583 | } cdclk; |
63911d72 | 1584 | |
645416f5 DV |
1585 | /** |
1586 | * wq - Driver workqueue for GEM. | |
1587 | * | |
1588 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1589 | * locks, for otherwise the flushing done in the pageflip code will | |
1590 | * result in deadlocks. | |
1591 | */ | |
f4c956ad DV |
1592 | struct workqueue_struct *wq; |
1593 | ||
757fffcf VS |
1594 | /* ordered wq for modesets */ |
1595 | struct workqueue_struct *modeset_wq; | |
1596 | ||
f4c956ad DV |
1597 | /* Display functions */ |
1598 | struct drm_i915_display_funcs display; | |
1599 | ||
1600 | /* PCH chipset type */ | |
1601 | enum intel_pch pch_type; | |
17a303ec | 1602 | unsigned short pch_id; |
f4c956ad DV |
1603 | |
1604 | unsigned long quirks; | |
1605 | ||
e2c8b870 | 1606 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 1607 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 1608 | |
62106b4f | 1609 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 1610 | |
4b5aed62 | 1611 | struct i915_gem_mm mm; |
ad46cb53 CW |
1612 | DECLARE_HASHTABLE(mm_structs, 7); |
1613 | struct mutex mm_lock; | |
8781342d | 1614 | |
4395890a ZW |
1615 | struct intel_ppat ppat; |
1616 | ||
8781342d DV |
1617 | /* Kernel Modesetting */ |
1618 | ||
e2af48c6 VS |
1619 | struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1620 | struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 | 1621 | |
c4597872 DV |
1622 | #ifdef CONFIG_DEBUG_FS |
1623 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1624 | #endif | |
1625 | ||
565602d7 | 1626 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1627 | int num_shared_dpll; |
1628 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1629 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 1630 | |
fbf6d879 ML |
1631 | /* |
1632 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1633 | * Must be global rather than per dpll, because on some platforms | |
1634 | * plls share registers. | |
1635 | */ | |
1636 | struct mutex dpll_lock; | |
1637 | ||
565602d7 | 1638 | unsigned int active_crtcs; |
d305e061 VS |
1639 | /* minimum acceptable cdclk for each pipe */ |
1640 | int min_cdclk[I915_MAX_PIPES]; | |
53e9bf5e VS |
1641 | /* minimum acceptable voltage level for each pipe */ |
1642 | u8 min_voltage_level[I915_MAX_PIPES]; | |
565602d7 | 1643 | |
e4607fcf | 1644 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1645 | |
25d140fa | 1646 | struct i915_wa_list gt_wa_list; |
888b5995 | 1647 | |
f99d7069 DV |
1648 | struct i915_frontbuffer_tracking fb_tracking; |
1649 | ||
eb955eee CW |
1650 | struct intel_atomic_helper { |
1651 | struct llist_head free_list; | |
1652 | struct work_struct free_work; | |
1653 | } atomic_helper; | |
1654 | ||
652c393a | 1655 | u16 orig_clock; |
f97108d1 | 1656 | |
c4804411 | 1657 | bool mchbar_need_disable; |
f97108d1 | 1658 | |
a4da4fa4 DV |
1659 | struct intel_l3_parity l3_parity; |
1660 | ||
59124506 | 1661 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 1662 | u32 edram_cap; |
59124506 | 1663 | |
9f817501 SAK |
1664 | /* |
1665 | * Protects RPS/RC6 register access and PCU communication. | |
1666 | * Must be taken after struct_mutex if nested. Note that | |
1667 | * this lock may be held for long periods of time when | |
1668 | * talking to hw - so only take it when talking to hw! | |
1669 | */ | |
1670 | struct mutex pcu_lock; | |
1671 | ||
562d9bae SAK |
1672 | /* gen6+ GT PM state */ |
1673 | struct intel_gen6_power_mgmt gt_pm; | |
c6a828d3 | 1674 | |
20e4d407 DV |
1675 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1676 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1677 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1678 | |
83c00f55 | 1679 | struct i915_power_domains power_domains; |
a38911a3 | 1680 | |
a031d709 | 1681 | struct i915_psr psr; |
3f51e471 | 1682 | |
99584db3 | 1683 | struct i915_gpu_error gpu_error; |
ae681d96 | 1684 | |
c9cddffc JB |
1685 | struct drm_i915_gem_object *vlv_pctx; |
1686 | ||
8be48d92 DA |
1687 | /* list of fbdev register on this device */ |
1688 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1689 | struct work_struct fbdev_suspend_work; |
e953fd7b CW |
1690 | |
1691 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1692 | struct drm_property *force_audio_property; |
e3689190 | 1693 | |
58fddc28 | 1694 | /* hda/i915 audio component */ |
51e1d83c | 1695 | struct i915_audio_component *audio_component; |
58fddc28 | 1696 | bool audio_component_registered; |
4a21ef7d LY |
1697 | /** |
1698 | * av_mutex - mutex for audio/video sync | |
1699 | * | |
1700 | */ | |
1701 | struct mutex av_mutex; | |
385e40fe | 1702 | int audio_power_refcount; |
58fddc28 | 1703 | |
829a0af2 | 1704 | struct { |
288f1ced | 1705 | struct mutex mutex; |
829a0af2 | 1706 | struct list_head list; |
5f09a9c8 CW |
1707 | struct llist_head free_list; |
1708 | struct work_struct free_work; | |
829a0af2 CW |
1709 | |
1710 | /* The hw wants to have a stable context identifier for the | |
1711 | * lifetime of the context (for OA, PASID, faults, etc). | |
1712 | * This is limited in execlists to 21 bits. | |
1713 | */ | |
1714 | struct ida hw_ida; | |
1715 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
218b5000 | 1716 | #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ |
ac52da6a | 1717 | #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ |
288f1ced | 1718 | struct list_head hw_id_list; |
829a0af2 | 1719 | } contexts; |
f4c956ad | 1720 | |
3e68320e | 1721 | u32 fdi_rx_config; |
68d18ad7 | 1722 | |
c231775c | 1723 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 1724 | u32 chv_phy_control; |
c231775c VS |
1725 | /* |
1726 | * Shadows for CHV DPLL_MD regs to keep the state | |
1727 | * checker somewhat working in the presence hardware | |
1728 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1729 | */ | |
1730 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 1731 | u32 bxt_phy_grc; |
70722468 | 1732 | |
842f1c8b | 1733 | u32 suspend_count; |
0f90603c | 1734 | bool power_domains_suspended; |
f4c956ad | 1735 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1736 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1737 | |
656d1b89 | 1738 | enum { |
16dcdc4e PZ |
1739 | I915_SAGV_UNKNOWN = 0, |
1740 | I915_SAGV_DISABLED, | |
1741 | I915_SAGV_ENABLED, | |
1742 | I915_SAGV_NOT_CONTROLLED | |
1743 | } sagv_status; | |
656d1b89 | 1744 | |
53615a5e VS |
1745 | struct { |
1746 | /* | |
1747 | * Raw watermark latency values: | |
1748 | * in 0.1us units for WM0, | |
1749 | * in 0.5us units for WM1+. | |
1750 | */ | |
1751 | /* primary */ | |
1752 | uint16_t pri_latency[5]; | |
1753 | /* sprite */ | |
1754 | uint16_t spr_latency[5]; | |
1755 | /* cursor */ | |
1756 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1757 | /* |
1758 | * Raw watermark memory latency values | |
1759 | * for SKL for all 8 levels | |
1760 | * in 1us units. | |
1761 | */ | |
1762 | uint16_t skl_latency[8]; | |
609cedef VS |
1763 | |
1764 | /* current hardware state */ | |
2d41c0b5 PB |
1765 | union { |
1766 | struct ilk_wm_values hw; | |
60f8e873 | 1767 | struct skl_ddb_values skl_hw; |
0018fda1 | 1768 | struct vlv_wm_values vlv; |
04548cba | 1769 | struct g4x_wm_values g4x; |
2d41c0b5 | 1770 | }; |
58590c14 VS |
1771 | |
1772 | uint8_t max_level; | |
ed4a6a7c MR |
1773 | |
1774 | /* | |
1775 | * Should be held around atomic WM register writing; also | |
1776 | * protects * intel_crtc->wm.active and | |
1777 | * cstate->wm.need_postvbl_update. | |
1778 | */ | |
1779 | struct mutex wm_mutex; | |
279e99d7 MR |
1780 | |
1781 | /* | |
1782 | * Set during HW readout of watermarks/DDB. Some platforms | |
1783 | * need to know when we're still using BIOS-provided values | |
1784 | * (which we don't fully trust). | |
1785 | */ | |
1786 | bool distrust_bios_wm; | |
53615a5e VS |
1787 | } wm; |
1788 | ||
cbfa59d4 MK |
1789 | struct dram_info { |
1790 | bool valid; | |
86b59287 | 1791 | bool is_16gb_dimm; |
cbfa59d4 MK |
1792 | u8 num_channels; |
1793 | enum dram_rank { | |
1794 | I915_DRAM_RANK_INVALID = 0, | |
1795 | I915_DRAM_RANK_SINGLE, | |
1796 | I915_DRAM_RANK_DUAL | |
1797 | } rank; | |
1798 | u32 bandwidth_kbps; | |
8a6c5447 | 1799 | bool symmetric_memory; |
cbfa59d4 MK |
1800 | } dram_info; |
1801 | ||
ad1443f0 | 1802 | struct i915_runtime_pm runtime_pm; |
8a187455 | 1803 | |
eec688e1 RB |
1804 | struct { |
1805 | bool initialized; | |
d7965152 | 1806 | |
442b8c06 | 1807 | struct kobject *metrics_kobj; |
ccdf6341 | 1808 | struct ctl_table_header *sysctl_header; |
442b8c06 | 1809 | |
f89823c2 LL |
1810 | /* |
1811 | * Lock associated with adding/modifying/removing OA configs | |
1812 | * in dev_priv->perf.metrics_idr. | |
1813 | */ | |
1814 | struct mutex metrics_lock; | |
1815 | ||
1816 | /* | |
1817 | * List of dynamic configurations, you need to hold | |
1818 | * dev_priv->perf.metrics_lock to access it. | |
1819 | */ | |
1820 | struct idr metrics_idr; | |
1821 | ||
1822 | /* | |
1823 | * Lock associated with anything below within this structure | |
1824 | * except exclusive_stream. | |
1825 | */ | |
eec688e1 RB |
1826 | struct mutex lock; |
1827 | struct list_head streams; | |
8a3003dd RB |
1828 | |
1829 | struct { | |
f89823c2 LL |
1830 | /* |
1831 | * The stream currently using the OA unit. If accessed | |
1832 | * outside a syscall associated to its file | |
1833 | * descriptor, you need to hold | |
1834 | * dev_priv->drm.struct_mutex. | |
1835 | */ | |
d7965152 RB |
1836 | struct i915_perf_stream *exclusive_stream; |
1837 | ||
1fc44d9b | 1838 | struct intel_context *pinned_ctx; |
d7965152 | 1839 | u32 specific_ctx_id; |
61d5676b | 1840 | u32 specific_ctx_id_mask; |
d7965152 RB |
1841 | |
1842 | struct hrtimer poll_check_timer; | |
1843 | wait_queue_head_t poll_wq; | |
1844 | bool pollin; | |
1845 | ||
712122ea RB |
1846 | /** |
1847 | * For rate limiting any notifications of spurious | |
1848 | * invalid OA reports | |
1849 | */ | |
1850 | struct ratelimit_state spurious_report_rs; | |
1851 | ||
d7965152 RB |
1852 | bool periodic; |
1853 | int period_exponent; | |
d7965152 | 1854 | |
701f8231 | 1855 | struct i915_oa_config test_config; |
d7965152 RB |
1856 | |
1857 | struct { | |
1858 | struct i915_vma *vma; | |
1859 | u8 *vaddr; | |
19f81df2 | 1860 | u32 last_ctx_id; |
d7965152 RB |
1861 | int format; |
1862 | int format_size; | |
f279020a | 1863 | |
0dd860cf RB |
1864 | /** |
1865 | * Locks reads and writes to all head/tail state | |
1866 | * | |
1867 | * Consider: the head and tail pointer state | |
1868 | * needs to be read consistently from a hrtimer | |
1869 | * callback (atomic context) and read() fop | |
1870 | * (user context) with tail pointer updates | |
1871 | * happening in atomic context and head updates | |
1872 | * in user context and the (unlikely) | |
1873 | * possibility of read() errors needing to | |
1874 | * reset all head/tail state. | |
1875 | * | |
1876 | * Note: Contention or performance aren't | |
1877 | * currently a significant concern here | |
1878 | * considering the relatively low frequency of | |
1879 | * hrtimer callbacks (5ms period) and that | |
1880 | * reads typically only happen in response to a | |
1881 | * hrtimer event and likely complete before the | |
1882 | * next callback. | |
1883 | * | |
1884 | * Note: This lock is not held *while* reading | |
1885 | * and copying data to userspace so the value | |
1886 | * of head observed in htrimer callbacks won't | |
1887 | * represent any partial consumption of data. | |
1888 | */ | |
1889 | spinlock_t ptr_lock; | |
1890 | ||
1891 | /** | |
1892 | * One 'aging' tail pointer and one 'aged' | |
1893 | * tail pointer ready to used for reading. | |
1894 | * | |
1895 | * Initial values of 0xffffffff are invalid | |
1896 | * and imply that an update is required | |
1897 | * (and should be ignored by an attempted | |
1898 | * read) | |
1899 | */ | |
1900 | struct { | |
1901 | u32 offset; | |
1902 | } tails[2]; | |
1903 | ||
1904 | /** | |
1905 | * Index for the aged tail ready to read() | |
1906 | * data up to. | |
1907 | */ | |
1908 | unsigned int aged_tail_idx; | |
1909 | ||
1910 | /** | |
1911 | * A monotonic timestamp for when the current | |
1912 | * aging tail pointer was read; used to | |
1913 | * determine when it is old enough to trust. | |
1914 | */ | |
1915 | u64 aging_timestamp; | |
1916 | ||
f279020a RB |
1917 | /** |
1918 | * Although we can always read back the head | |
1919 | * pointer register, we prefer to avoid | |
1920 | * trusting the HW state, just to avoid any | |
1921 | * risk that some hardware condition could | |
1922 | * somehow bump the head pointer unpredictably | |
1923 | * and cause us to forward the wrong OA buffer | |
1924 | * data to userspace. | |
1925 | */ | |
1926 | u32 head; | |
d7965152 RB |
1927 | } oa_buffer; |
1928 | ||
1929 | u32 gen7_latched_oastatus1; | |
19f81df2 RB |
1930 | u32 ctx_oactxctrl_offset; |
1931 | u32 ctx_flexeu0_offset; | |
1932 | ||
1933 | /** | |
1934 | * The RPT_ID/reason field for Gen8+ includes a bit | |
1935 | * to determine if the CTX ID in the report is valid | |
1936 | * but the specific bit differs between Gen 8 and 9 | |
1937 | */ | |
1938 | u32 gen8_valid_ctx_bit; | |
d7965152 RB |
1939 | |
1940 | struct i915_oa_ops ops; | |
1941 | const struct i915_oa_format *oa_formats; | |
8a3003dd | 1942 | } oa; |
eec688e1 RB |
1943 | } perf; |
1944 | ||
a83014d3 OM |
1945 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1946 | struct { | |
821ed7df | 1947 | void (*resume)(struct drm_i915_private *); |
117897f4 | 1948 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 | 1949 | |
b887d615 | 1950 | struct list_head timelines; |
643b450a CW |
1951 | |
1952 | struct list_head active_rings; | |
3365e226 | 1953 | struct list_head closed_vma; |
28176ef4 | 1954 | u32 active_requests; |
52d7f16e | 1955 | u32 request_serial; |
73cb9701 | 1956 | |
67d97da3 CW |
1957 | /** |
1958 | * Is the GPU currently considered idle, or busy executing | |
1959 | * userspace requests? Whilst idle, we allow runtime power | |
1960 | * management to power down the hardware and display clocks. | |
1961 | * In order to reduce the effect on performance, there | |
1962 | * is a slight delay before we do so. | |
1963 | */ | |
67d97da3 CW |
1964 | bool awake; |
1965 | ||
6f56103d CW |
1966 | /** |
1967 | * The number of times we have woken up. | |
1968 | */ | |
1969 | unsigned int epoch; | |
1970 | #define I915_EPOCH_INVALID 0 | |
1971 | ||
67d97da3 CW |
1972 | /** |
1973 | * We leave the user IRQ off as much as possible, | |
1974 | * but this means that requests will finish and never | |
1975 | * be retired once the system goes idle. Set a timer to | |
1976 | * fire periodically while the ring is running. When it | |
1977 | * fires, go retire requests. | |
1978 | */ | |
1979 | struct delayed_work retire_work; | |
1980 | ||
1981 | /** | |
1982 | * When we detect an idle GPU, we want to turn on | |
1983 | * powersaving features. So once we see that there | |
1984 | * are no more requests outstanding and no more | |
1985 | * arrive within a small period of time, we fire | |
1986 | * off the idle_work. | |
1987 | */ | |
1988 | struct delayed_work idle_work; | |
de867c20 CW |
1989 | |
1990 | ktime_t last_init_time; | |
51797499 CW |
1991 | |
1992 | struct i915_vma *scratch; | |
a83014d3 OM |
1993 | } gt; |
1994 | ||
3be60de9 VS |
1995 | /* perform PHY state sanity checks? */ |
1996 | bool chv_phy_assert[2]; | |
1997 | ||
a3a8986c MK |
1998 | bool ipc_enabled; |
1999 | ||
863e97a2 AM |
2000 | /* Hack to bypass TMDS_OE write on DP->HDMI dongle */ |
2001 | bool bypass_tmds_oe; | |
2002 | ||
f9318941 PD |
2003 | /* Used to save the pipe-to-encoder mapping for audio */ |
2004 | struct intel_encoder *av_enc_map[I915_MAX_PIPES]; | |
0bdf5a05 | 2005 | |
eef57324 JA |
2006 | /* necessary resource sharing with HDMI LPE audio driver. */ |
2007 | struct { | |
2008 | struct platform_device *platdev; | |
2009 | int irq; | |
2010 | } lpe_audio; | |
2011 | ||
b46a33e2 TU |
2012 | struct i915_pmu pmu; |
2013 | ||
bdf1e7e3 DV |
2014 | /* |
2015 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2016 | * will be rejected. Instead look for a better place. | |
2017 | */ | |
77fec556 | 2018 | }; |
1da177e4 | 2019 | |
5771caf8 MK |
2020 | struct dram_channel_info { |
2021 | struct info { | |
2022 | u8 size, width; | |
2023 | enum dram_rank rank; | |
2024 | } l_info, s_info; | |
2025 | enum dram_rank rank; | |
86b59287 | 2026 | bool is_16gb_dimm; |
5771caf8 MK |
2027 | }; |
2028 | ||
2c1792a1 CW |
2029 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2030 | { | |
091387c1 | 2031 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2032 | } |
2033 | ||
c49d13ee | 2034 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
888d0d42 | 2035 | { |
c49d13ee | 2036 | return to_i915(dev_get_drvdata(kdev)); |
888d0d42 ID |
2037 | } |
2038 | ||
6b0478fb JL |
2039 | static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm) |
2040 | { | |
2041 | return container_of(wopcm, struct drm_i915_private, wopcm); | |
2042 | } | |
2043 | ||
33a732f4 AD |
2044 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2045 | { | |
2046 | return container_of(guc, struct drm_i915_private, guc); | |
2047 | } | |
2048 | ||
50beba55 AH |
2049 | static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) |
2050 | { | |
2051 | return container_of(huc, struct drm_i915_private, huc); | |
2052 | } | |
2053 | ||
b4ac5afc | 2054 | /* Simple iterator over all initialised engines */ |
3b3f1650 AG |
2055 | #define for_each_engine(engine__, dev_priv__, id__) \ |
2056 | for ((id__) = 0; \ | |
2057 | (id__) < I915_NUM_ENGINES; \ | |
2058 | (id__)++) \ | |
2059 | for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) | |
c3232b18 DG |
2060 | |
2061 | /* Iterator over subset of engines selected by mask */ | |
bafb0fce | 2062 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ |
19d3cf00 TU |
2063 | for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \ |
2064 | (tmp__) ? \ | |
2065 | ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \ | |
2066 | 0;) | |
ee4b6faf | 2067 | |
b1d7e4b4 WF |
2068 | enum hdmi_force_audio { |
2069 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2070 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2071 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2072 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2073 | }; | |
2074 | ||
190d6cd5 | 2075 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2076 | |
a071fa00 DV |
2077 | /* |
2078 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2079 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2080 | * doesn't mean that the hw necessarily already scans it out, but that any |
2081 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2082 | * | |
2083 | * We have one bit per pipe and per scanout plane type. | |
2084 | */ | |
d1b9d039 | 2085 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 |
aa81e2c3 VS |
2086 | #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ |
2087 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ | |
2088 | BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ | |
2089 | BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ | |
2090 | }) | |
a071fa00 | 2091 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
aa81e2c3 | 2092 | BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) |
cc36513c | 2093 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
aa81e2c3 VS |
2094 | GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ |
2095 | INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) | |
a071fa00 | 2096 | |
85d1225e DG |
2097 | /* |
2098 | * Optimised SGL iterator for GEM objects | |
2099 | */ | |
2100 | static __always_inline struct sgt_iter { | |
2101 | struct scatterlist *sgp; | |
2102 | union { | |
2103 | unsigned long pfn; | |
2104 | dma_addr_t dma; | |
2105 | }; | |
2106 | unsigned int curr; | |
2107 | unsigned int max; | |
2108 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2109 | struct sgt_iter s = { .sgp = sgl }; | |
2110 | ||
2111 | if (s.sgp) { | |
2112 | s.max = s.curr = s.sgp->offset; | |
2113 | s.max += s.sgp->length; | |
2114 | if (dma) | |
2115 | s.dma = sg_dma_address(s.sgp); | |
2116 | else | |
2117 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2118 | } | |
2119 | ||
2120 | return s; | |
2121 | } | |
2122 | ||
96d77634 CW |
2123 | static inline struct scatterlist *____sg_next(struct scatterlist *sg) |
2124 | { | |
2125 | ++sg; | |
2126 | if (unlikely(sg_is_chain(sg))) | |
2127 | sg = sg_chain_ptr(sg); | |
2128 | return sg; | |
2129 | } | |
2130 | ||
63d15326 DG |
2131 | /** |
2132 | * __sg_next - return the next scatterlist entry in a list | |
2133 | * @sg: The current sg entry | |
2134 | * | |
2135 | * Description: | |
2136 | * If the entry is the last, return NULL; otherwise, step to the next | |
2137 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2138 | * otherwise just return the pointer to the current element. | |
2139 | **/ | |
2140 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2141 | { | |
96d77634 | 2142 | return sg_is_last(sg) ? NULL : ____sg_next(sg); |
63d15326 DG |
2143 | } |
2144 | ||
85d1225e DG |
2145 | /** |
2146 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2147 | * @__dmap: DMA address (output) | |
2148 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2149 | * @__sgt: sg_table to iterate over (input) | |
2150 | */ | |
2151 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2152 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2153 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
f6e35cda | 2154 | (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \ |
e60b36f7 | 2155 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0) |
85d1225e DG |
2156 | |
2157 | /** | |
2158 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2159 | * @__pp: page pointer (output) | |
2160 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2161 | * @__sgt: sg_table to iterate over (input) | |
2162 | */ | |
2163 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2164 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2165 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2166 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
e60b36f7 CW |
2167 | (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ |
2168 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0) | |
a071fa00 | 2169 | |
f8e57863 TU |
2170 | bool i915_sg_trim(struct sg_table *orig_st); |
2171 | ||
a5c08166 MA |
2172 | static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg) |
2173 | { | |
2174 | unsigned int page_sizes; | |
2175 | ||
2176 | page_sizes = 0; | |
2177 | while (sg) { | |
2178 | GEM_BUG_ON(sg->offset); | |
2179 | GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE)); | |
2180 | page_sizes |= sg->length; | |
2181 | sg = __sg_next(sg); | |
2182 | } | |
2183 | ||
2184 | return page_sizes; | |
2185 | } | |
2186 | ||
5602452e TU |
2187 | static inline unsigned int i915_sg_segment_size(void) |
2188 | { | |
2189 | unsigned int size = swiotlb_max_segment(); | |
2190 | ||
2191 | if (size == 0) | |
2192 | return SCATTERLIST_MAX_SEGMENT; | |
2193 | ||
2194 | size = rounddown(size, PAGE_SIZE); | |
2195 | /* swiotlb_max_segment_size can return 1 byte when it means one page. */ | |
2196 | if (size < PAGE_SIZE) | |
2197 | size = PAGE_SIZE; | |
2198 | ||
2199 | return size; | |
2200 | } | |
2201 | ||
5ca43ef0 TU |
2202 | static inline const struct intel_device_info * |
2203 | intel_info(const struct drm_i915_private *dev_priv) | |
2204 | { | |
2205 | return &dev_priv->info; | |
2206 | } | |
2207 | ||
2208 | #define INTEL_INFO(dev_priv) intel_info((dev_priv)) | |
481827b4 | 2209 | #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) |
50a0bc90 | 2210 | |
55b8f2a7 | 2211 | #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) |
50a0bc90 | 2212 | #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) |
cae5852d | 2213 | |
e87a005d | 2214 | #define REVID_FOREVER 0xff |
4805fe82 | 2215 | #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) |
ac657f64 | 2216 | |
fe52e597 JL |
2217 | #define INTEL_GEN_MASK(s, e) ( \ |
2218 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ | |
2219 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ | |
5bc0e89f | 2220 | GENMASK((e) - 1, (s) - 1)) |
fe52e597 | 2221 | |
5bc0e89f | 2222 | /* Returns true if Gen is in inclusive range [Start, End] */ |
fe52e597 JL |
2223 | #define IS_GEN(dev_priv, s, e) \ |
2224 | (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) | |
ac657f64 | 2225 | |
e87a005d JN |
2226 | /* |
2227 | * Return true if revision is in range [since,until] inclusive. | |
2228 | * | |
2229 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2230 | */ | |
2231 | #define IS_REVID(p, since, until) \ | |
2232 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2233 | ||
ae7617f0 | 2234 | #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) |
5a127a8c TU |
2235 | |
2236 | #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) | |
2237 | #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) | |
2238 | #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) | |
2239 | #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) | |
2240 | #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) | |
2241 | #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) | |
2242 | #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) | |
2243 | #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) | |
2244 | #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) | |
2245 | #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) | |
2246 | #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) | |
2247 | #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) | |
f69c11ae | 2248 | #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) |
50a0bc90 TU |
2249 | #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) |
2250 | #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) | |
5a127a8c TU |
2251 | #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) |
2252 | #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) | |
50a0bc90 | 2253 | #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) |
5a127a8c | 2254 | #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) |
18b53818 LL |
2255 | #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ |
2256 | (dev_priv)->info.gt == 1) | |
5a127a8c TU |
2257 | #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) |
2258 | #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) | |
2259 | #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) | |
2260 | #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) | |
2261 | #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) | |
2262 | #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) | |
2263 | #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) | |
2264 | #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) | |
2265 | #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) | |
2266 | #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) | |
41231001 | 2267 | #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) |
646d5772 | 2268 | #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) |
50a0bc90 TU |
2269 | #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ |
2270 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) | |
2271 | #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2272 | ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ | |
2273 | (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ | |
2274 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) | |
ebb72aad | 2275 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2276 | #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ |
2277 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe) | |
2278 | #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
18b53818 | 2279 | (dev_priv)->info.gt == 3) |
50a0bc90 TU |
2280 | #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ |
2281 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) | |
2282 | #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ | |
18b53818 | 2283 | (dev_priv)->info.gt == 3) |
9bbfd20a | 2284 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2285 | #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ |
2286 | INTEL_DEVID(dev_priv) == 0x0A1E) | |
2287 | #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ | |
2288 | INTEL_DEVID(dev_priv) == 0x1913 || \ | |
2289 | INTEL_DEVID(dev_priv) == 0x1916 || \ | |
2290 | INTEL_DEVID(dev_priv) == 0x1921 || \ | |
2291 | INTEL_DEVID(dev_priv) == 0x1926) | |
2292 | #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ | |
2293 | INTEL_DEVID(dev_priv) == 0x1915 || \ | |
2294 | INTEL_DEVID(dev_priv) == 0x191E) | |
2295 | #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ | |
2296 | INTEL_DEVID(dev_priv) == 0x5913 || \ | |
2297 | INTEL_DEVID(dev_priv) == 0x5916 || \ | |
2298 | INTEL_DEVID(dev_priv) == 0x5921 || \ | |
2299 | INTEL_DEVID(dev_priv) == 0x5926) | |
2300 | #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ | |
2301 | INTEL_DEVID(dev_priv) == 0x5915 || \ | |
2302 | INTEL_DEVID(dev_priv) == 0x591E) | |
ab2da3f8 | 2303 | #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \ |
ba93f640 VS |
2304 | INTEL_DEVID(dev_priv) == 0x87C0 || \ |
2305 | INTEL_DEVID(dev_priv) == 0x87CA) | |
19f81df2 | 2306 | #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 2307 | (dev_priv)->info.gt == 2) |
50a0bc90 | 2308 | #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 2309 | (dev_priv)->info.gt == 3) |
50a0bc90 | 2310 | #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 2311 | (dev_priv)->info.gt == 4) |
3891589e | 2312 | #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ |
18b53818 | 2313 | (dev_priv)->info.gt == 2) |
3891589e | 2314 | #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ |
18b53818 | 2315 | (dev_priv)->info.gt == 3) |
da411a48 RV |
2316 | #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
2317 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) | |
22ea4f35 LL |
2318 | #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
2319 | (dev_priv)->info.gt == 2) | |
4407eaa9 LL |
2320 | #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
2321 | (dev_priv)->info.gt == 3) | |
3f43031b RV |
2322 | #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ |
2323 | (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004) | |
7a58bad0 | 2324 | |
c007fb4a | 2325 | #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) |
cae5852d | 2326 | |
ef712bb4 JN |
2327 | #define SKL_REVID_A0 0x0 |
2328 | #define SKL_REVID_B0 0x1 | |
2329 | #define SKL_REVID_C0 0x2 | |
2330 | #define SKL_REVID_D0 0x3 | |
2331 | #define SKL_REVID_E0 0x4 | |
2332 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
2333 | #define SKL_REVID_G0 0x6 |
2334 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2335 | |
e87a005d JN |
2336 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2337 | ||
ef712bb4 | 2338 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2339 | #define BXT_REVID_A1 0x1 |
ef712bb4 | 2340 | #define BXT_REVID_B0 0x3 |
a3f79ca6 | 2341 | #define BXT_REVID_B_LAST 0x8 |
ef712bb4 | 2342 | #define BXT_REVID_C0 0x9 |
6c74c87f | 2343 | |
e2d214ae TU |
2344 | #define IS_BXT_REVID(dev_priv, since, until) \ |
2345 | (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) | |
e87a005d | 2346 | |
c033a37c MK |
2347 | #define KBL_REVID_A0 0x0 |
2348 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2349 | #define KBL_REVID_C0 0x2 |
2350 | #define KBL_REVID_D0 0x3 | |
2351 | #define KBL_REVID_E0 0x4 | |
c033a37c | 2352 | |
0853723b TU |
2353 | #define IS_KBL_REVID(dev_priv, since, until) \ |
2354 | (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
c033a37c | 2355 | |
f4f4b59b ACO |
2356 | #define GLK_REVID_A0 0x0 |
2357 | #define GLK_REVID_A1 0x1 | |
2358 | ||
2359 | #define IS_GLK_REVID(dev_priv, since, until) \ | |
2360 | (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
2361 | ||
3c2e0fd9 PZ |
2362 | #define CNL_REVID_A0 0x0 |
2363 | #define CNL_REVID_B0 0x1 | |
e4ffc83d | 2364 | #define CNL_REVID_C0 0x2 |
3c2e0fd9 PZ |
2365 | |
2366 | #define IS_CNL_REVID(p, since, until) \ | |
2367 | (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) | |
2368 | ||
cc38cae7 OM |
2369 | #define ICL_REVID_A0 0x0 |
2370 | #define ICL_REVID_A2 0x1 | |
2371 | #define ICL_REVID_B0 0x3 | |
2372 | #define ICL_REVID_B2 0x4 | |
2373 | #define ICL_REVID_C0 0x5 | |
2374 | ||
2375 | #define IS_ICL_REVID(p, since, until) \ | |
2376 | (IS_ICELAKE(p) && IS_REVID(p, since, until)) | |
2377 | ||
85436696 JB |
2378 | /* |
2379 | * The genX designation typically refers to the render engine, so render | |
2380 | * capability related checks should use IS_GEN, while display and other checks | |
2381 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2382 | * chips, etc.). | |
2383 | */ | |
5db94019 TU |
2384 | #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) |
2385 | #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) | |
2386 | #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) | |
2387 | #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) | |
2388 | #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) | |
2389 | #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) | |
2390 | #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) | |
2391 | #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) | |
413f3c19 | 2392 | #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) |
41231001 | 2393 | #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) |
cae5852d | 2394 | |
8727dc09 | 2395 | #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) |
b976dc53 RV |
2396 | #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) |
2397 | #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) | |
3e4274f8 | 2398 | |
a19d6ff2 TU |
2399 | #define ENGINE_MASK(id) BIT(id) |
2400 | #define RENDER_RING ENGINE_MASK(RCS) | |
2401 | #define BSD_RING ENGINE_MASK(VCS) | |
2402 | #define BLT_RING ENGINE_MASK(BCS) | |
2403 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2404 | #define BSD2_RING ENGINE_MASK(VCS2) | |
022d3093 TU |
2405 | #define BSD3_RING ENGINE_MASK(VCS3) |
2406 | #define BSD4_RING ENGINE_MASK(VCS4) | |
2407 | #define VEBOX2_RING ENGINE_MASK(VECS2) | |
a19d6ff2 TU |
2408 | #define ALL_ENGINES (~0) |
2409 | ||
2410 | #define HAS_ENGINE(dev_priv, id) \ | |
0031fb96 | 2411 | (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2412 | |
2413 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2414 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2415 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2416 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2417 | ||
93c6e966 CW |
2418 | #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) |
2419 | ||
0031fb96 TU |
2420 | #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) |
2421 | #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) | |
2422 | #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) | |
8652744b TU |
2423 | #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ |
2424 | IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) | |
cae5852d | 2425 | |
0031fb96 | 2426 | #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) |
1d2a314c | 2427 | |
0031fb96 TU |
2428 | #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ |
2429 | ((dev_priv)->info.has_logical_ring_contexts) | |
05f0addd TD |
2430 | #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ |
2431 | ((dev_priv)->info.has_logical_ring_elsq) | |
a4598d17 MW |
2432 | #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ |
2433 | ((dev_priv)->info.has_logical_ring_preemption) | |
fb5c551a CW |
2434 | |
2435 | #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) | |
2436 | ||
4bdafb9d CW |
2437 | #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt) |
2438 | #define HAS_PPGTT(dev_priv) \ | |
2439 | (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) | |
2440 | #define HAS_FULL_PPGTT(dev_priv) \ | |
2441 | (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) | |
2442 | #define HAS_FULL_48BIT_PPGTT(dev_priv) \ | |
2443 | (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL) | |
2444 | ||
a5c08166 MA |
2445 | #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ |
2446 | GEM_BUG_ON((sizes) == 0); \ | |
2447 | ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ | |
2448 | }) | |
0031fb96 | 2449 | |
d53db442 | 2450 | #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay) |
0031fb96 | 2451 | #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ |
d53db442 | 2452 | ((dev_priv)->info.display.overlay_needs_physical) |
cae5852d | 2453 | |
b45305fc | 2454 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2a307c2e | 2455 | #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
06e668ac | 2456 | |
d66047e4 | 2457 | /* WaRsDisableCoarsePowerGating:skl,cnl */ |
61251512 | 2458 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
d66047e4 RV |
2459 | (IS_CANNONLAKE(dev_priv) || \ |
2460 | IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) | |
185c66e5 | 2461 | |
309bd8ed | 2462 | #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) |
d5dc0f43 R |
2463 | #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ |
2464 | IS_GEMINILAKE(dev_priv) || \ | |
2465 | IS_KABYLAKE(dev_priv)) | |
b45305fc | 2466 | |
cae5852d ZN |
2467 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2468 | * rows, which changed the alignment requirements and fence programming. | |
2469 | */ | |
50a0bc90 TU |
2470 | #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ |
2471 | !(IS_I915G(dev_priv) || \ | |
2472 | IS_I915GM(dev_priv))) | |
d53db442 JRS |
2473 | #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv) |
2474 | #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug) | |
cae5852d | 2475 | |
56b857a5 | 2476 | #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) |
d53db442 | 2477 | #define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc) |
c56b89f1 | 2478 | #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) |
cae5852d | 2479 | |
50a0bc90 | 2480 | #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) |
f5adf94e | 2481 | |
d53db442 | 2482 | #define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst) |
0c9b3715 | 2483 | |
d53db442 | 2484 | #define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi) |
56b857a5 | 2485 | #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) |
d53db442 | 2486 | #define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr) |
fb6db0f5 | 2487 | |
56b857a5 TU |
2488 | #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) |
2489 | #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) | |
fb6db0f5 | 2490 | #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ |
affa9354 | 2491 | |
d53db442 | 2492 | #define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr) |
eb805623 | 2493 | |
6772ffe0 | 2494 | #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) |
dfc5148f JL |
2495 | #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) |
2496 | ||
d53db442 | 2497 | #define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc) |
e57f1c02 | 2498 | |
1a3d1898 DG |
2499 | /* |
2500 | * For now, anything with a GuC requires uCode loading, and then supports | |
2501 | * command submission once loaded. But these are logically independent | |
2502 | * properties, so we have separate macros to test them. | |
2503 | */ | |
4805fe82 | 2504 | #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) |
f8a58d63 | 2505 | #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) |
4805fe82 TU |
2506 | #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
2507 | #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) | |
2fe2d4e3 MW |
2508 | |
2509 | /* For now, anything with a GuC has also HuC */ | |
2510 | #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv)) | |
bd132858 | 2511 | #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
33a732f4 | 2512 | |
93ffbe8e | 2513 | /* Having a GuC is not the same as using a GuC */ |
121981fa MW |
2514 | #define USES_GUC(dev_priv) intel_uc_is_using_guc() |
2515 | #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission() | |
2516 | #define USES_HUC(dev_priv) intel_uc_is_using_huc() | |
93ffbe8e | 2517 | |
4805fe82 | 2518 | #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) |
33e141ed | 2519 | |
c5e855d0 | 2520 | #define INTEL_PCH_DEVICE_ID_MASK 0xff80 |
17a303ec PZ |
2521 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
2522 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2523 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2524 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2525 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
c5e855d0 VS |
2526 | #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 |
2527 | #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 | |
e7e7ea20 S |
2528 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2529 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
c5e855d0 | 2530 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 |
7b22b8c4 | 2531 | #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 |
ec7e0bb3 | 2532 | #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 |
298d6aaf | 2533 | #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 |
5c8ea018 | 2534 | #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 |
30c964a6 | 2535 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2536 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2537 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2538 | |
6e266956 | 2539 | #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) |
81717504 | 2540 | #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) |
0b58436f | 2541 | #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) |
7b22b8c4 | 2542 | #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) |
ec7e0bb3 | 2543 | #define HAS_PCH_CNP_LP(dev_priv) \ |
81717504 | 2544 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) |
6e266956 TU |
2545 | #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) |
2546 | #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) | |
2547 | #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) | |
4f8036a2 | 2548 | #define HAS_PCH_LPT_LP(dev_priv) \ |
81717504 JN |
2549 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ |
2550 | INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) | |
4f8036a2 | 2551 | #define HAS_PCH_LPT_H(dev_priv) \ |
81717504 JN |
2552 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ |
2553 | INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) | |
6e266956 TU |
2554 | #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) |
2555 | #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) | |
2556 | #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) | |
2557 | #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) | |
cae5852d | 2558 | |
d53db442 | 2559 | #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display) |
5fafe292 | 2560 | |
ff15947e | 2561 | #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) |
6389dd83 | 2562 | |
040d2baa | 2563 | /* DPF == dynamic parity feature */ |
3c9192bc | 2564 | #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) |
50a0bc90 TU |
2565 | #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ |
2566 | 2 : HAS_L3_DPF(dev_priv)) | |
e1ef7cc2 | 2567 | |
c8735b0c | 2568 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2569 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2570 | |
e1bf094b JRS |
2571 | #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0) |
2572 | ||
05394f39 CW |
2573 | #include "i915_trace.h" |
2574 | ||
80debff8 | 2575 | static inline bool intel_vtd_active(void) |
48f112fe CW |
2576 | { |
2577 | #ifdef CONFIG_INTEL_IOMMU | |
80debff8 | 2578 | if (intel_iommu_gfx_mapped) |
48f112fe CW |
2579 | return true; |
2580 | #endif | |
2581 | return false; | |
2582 | } | |
2583 | ||
80debff8 CW |
2584 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
2585 | { | |
2586 | return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); | |
2587 | } | |
2588 | ||
0ef34ad6 JB |
2589 | static inline bool |
2590 | intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) | |
2591 | { | |
80debff8 | 2592 | return IS_BROXTON(dev_priv) && intel_vtd_active(); |
0ef34ad6 JB |
2593 | } |
2594 | ||
0673ad47 | 2595 | /* i915_drv.c */ |
d15d7538 ID |
2596 | void __printf(3, 4) |
2597 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2598 | const char *fmt, ...); | |
2599 | ||
2600 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2601 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2602 | ||
c43b5634 | 2603 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2604 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2605 | unsigned long arg); | |
55edf41b JN |
2606 | #else |
2607 | #define i915_compat_ioctl NULL | |
c43b5634 | 2608 | #endif |
efab0698 JN |
2609 | extern const struct dev_pm_ops i915_pm_ops; |
2610 | ||
2611 | extern int i915_driver_load(struct pci_dev *pdev, | |
2612 | const struct pci_device_id *ent); | |
2613 | extern void i915_driver_unload(struct drm_device *dev); | |
dc97997a CW |
2614 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
2615 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
535275d3 | 2616 | |
d0667e9c CW |
2617 | extern void i915_reset(struct drm_i915_private *i915, |
2618 | unsigned int stalled_mask, | |
2619 | const char *reason); | |
2620 | extern int i915_reset_engine(struct intel_engine_cs *engine, | |
2621 | const char *reason); | |
535275d3 | 2622 | |
142bc7d9 | 2623 | extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); |
cb20a3c0 | 2624 | extern int intel_reset_guc(struct drm_i915_private *dev_priv); |
6acbea89 MT |
2625 | extern int intel_guc_reset_engine(struct intel_guc *guc, |
2626 | struct intel_engine_cs *engine); | |
fc0768ce | 2627 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
3ac168a7 | 2628 | extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); |
7648fa99 JB |
2629 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2630 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2631 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2632 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2633 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2634 | |
63ffbcda | 2635 | int intel_engines_init_mmio(struct drm_i915_private *dev_priv); |
bb8f0f5a CW |
2636 | int intel_engines_init(struct drm_i915_private *dev_priv); |
2637 | ||
1e40d4ae YZ |
2638 | u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv); |
2639 | ||
77913b39 | 2640 | /* intel_hotplug.c */ |
91d14251 TU |
2641 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2642 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2643 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2644 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2645 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cf53902f RV |
2646 | enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, |
2647 | enum port port); | |
b236d7c8 L |
2648 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
2649 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 2650 | |
1da177e4 | 2651 | /* i915_irq.c */ |
26a02b8f CW |
2652 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
2653 | { | |
2654 | unsigned long delay; | |
2655 | ||
4f044a88 | 2656 | if (unlikely(!i915_modparams.enable_hangcheck)) |
26a02b8f CW |
2657 | return; |
2658 | ||
2659 | /* Don't continually defer the hangcheck so that it is always run at | |
2660 | * least once after work has been scheduled on any ring. Otherwise, | |
2661 | * we will ignore a hung ring if a second ring is kept busy. | |
2662 | */ | |
2663 | ||
2664 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2665 | queue_delayed_work(system_long_wq, | |
2666 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2667 | } | |
2668 | ||
ce800754 | 2669 | __printf(4, 5) |
c033666a CW |
2670 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2671 | u32 engine_mask, | |
ce800754 | 2672 | unsigned long flags, |
58174462 | 2673 | const char *fmt, ...); |
ce800754 | 2674 | #define I915_ERROR_CAPTURE BIT(0) |
1da177e4 | 2675 | |
b963291c | 2676 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
cefcff8f | 2677 | extern void intel_irq_fini(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2678 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2679 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 2680 | |
09605548 LL |
2681 | void i915_clear_error_registers(struct drm_i915_private *dev_priv); |
2682 | ||
0ad35fed ZW |
2683 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
2684 | { | |
feddf6e8 | 2685 | return dev_priv->gvt; |
0ad35fed ZW |
2686 | } |
2687 | ||
c033666a | 2688 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 2689 | { |
c033666a | 2690 | return dev_priv->vgpu.active; |
cf9d2890 | 2691 | } |
b1f14ad0 | 2692 | |
6b12ca56 VS |
2693 | u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, |
2694 | enum pipe pipe); | |
7c463586 | 2695 | void |
50227e1c | 2696 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2697 | u32 status_mask); |
7c463586 KP |
2698 | |
2699 | void | |
50227e1c | 2700 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2701 | u32 status_mask); |
7c463586 | 2702 | |
f8b79e58 ID |
2703 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2704 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2705 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2706 | uint32_t mask, | |
2707 | uint32_t bits); | |
fbdedaea VS |
2708 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2709 | uint32_t interrupt_mask, | |
2710 | uint32_t enabled_irq_mask); | |
2711 | static inline void | |
2712 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2713 | { | |
2714 | ilk_update_display_irq(dev_priv, bits, bits); | |
2715 | } | |
2716 | static inline void | |
2717 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2718 | { | |
2719 | ilk_update_display_irq(dev_priv, bits, 0); | |
2720 | } | |
013d3752 VS |
2721 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2722 | enum pipe pipe, | |
2723 | uint32_t interrupt_mask, | |
2724 | uint32_t enabled_irq_mask); | |
2725 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2726 | enum pipe pipe, uint32_t bits) | |
2727 | { | |
2728 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2729 | } | |
2730 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2731 | enum pipe pipe, uint32_t bits) | |
2732 | { | |
2733 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2734 | } | |
47339cd9 DV |
2735 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2736 | uint32_t interrupt_mask, | |
2737 | uint32_t enabled_irq_mask); | |
14443261 VS |
2738 | static inline void |
2739 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2740 | { | |
2741 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2742 | } | |
2743 | static inline void | |
2744 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2745 | { | |
2746 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2747 | } | |
2748 | ||
673a394b | 2749 | /* i915_gem.c */ |
673a394b EA |
2750 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2751 | struct drm_file *file_priv); | |
2752 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2753 | struct drm_file *file_priv); | |
2754 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2755 | struct drm_file *file_priv); | |
2756 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2757 | struct drm_file *file_priv); | |
de151cf6 JB |
2758 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2759 | struct drm_file *file_priv); | |
673a394b EA |
2760 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2761 | struct drm_file *file_priv); | |
2762 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2763 | struct drm_file *file_priv); | |
6a20fe7b VS |
2764 | int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, |
2765 | struct drm_file *file_priv); | |
2766 | int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, | |
2767 | struct drm_file *file_priv); | |
673a394b EA |
2768 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2769 | struct drm_file *file_priv); | |
199adf40 BW |
2770 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2771 | struct drm_file *file); | |
2772 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2773 | struct drm_file *file); | |
673a394b EA |
2774 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2775 | struct drm_file *file_priv); | |
3ef94daa CW |
2776 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2777 | struct drm_file *file_priv); | |
111dbcab CW |
2778 | int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
2779 | struct drm_file *file_priv); | |
2780 | int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
2781 | struct drm_file *file_priv); | |
8a2421bd CW |
2782 | int i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
2783 | void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); | |
5cc9ed4b CW |
2784 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
2785 | struct drm_file *file); | |
5a125c3c EA |
2786 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2787 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2788 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2789 | struct drm_file *file_priv); | |
24145517 | 2790 | void i915_gem_sanitize(struct drm_i915_private *i915); |
a0de908d MW |
2791 | int i915_gem_init_early(struct drm_i915_private *dev_priv); |
2792 | void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); | |
40ae4e16 | 2793 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
6a800eab | 2794 | int i915_gem_freeze(struct drm_i915_private *dev_priv); |
461fb99c CW |
2795 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
2796 | ||
187685cb | 2797 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv); |
42dcedd4 | 2798 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
37e680a1 CW |
2799 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2800 | const struct drm_i915_gem_object_ops *ops); | |
12d79d78 TU |
2801 | struct drm_i915_gem_object * |
2802 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size); | |
2803 | struct drm_i915_gem_object * | |
2804 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, | |
2805 | const void *data, size_t size); | |
b1f788c6 | 2806 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 2807 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 2808 | |
bdeb9785 CW |
2809 | static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) |
2810 | { | |
c9c70471 CW |
2811 | if (!atomic_read(&i915->mm.free_count)) |
2812 | return; | |
2813 | ||
bdeb9785 CW |
2814 | /* A single pass should suffice to release all the freed objects (along |
2815 | * most call paths) , but be a little more paranoid in that freeing | |
2816 | * the objects does take a little amount of time, during which the rcu | |
2817 | * callbacks could have added new objects into the freed list, and | |
2818 | * armed the work again. | |
2819 | */ | |
2820 | do { | |
2821 | rcu_barrier(); | |
2822 | } while (flush_work(&i915->mm.free_work)); | |
2823 | } | |
2824 | ||
3b19f16a CW |
2825 | static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) |
2826 | { | |
2827 | /* | |
2828 | * Similar to objects above (see i915_gem_drain_freed-objects), in | |
2829 | * general we have workers that are armed by RCU and then rearm | |
2830 | * themselves in their callbacks. To be paranoid, we need to | |
2831 | * drain the workqueue a second time after waiting for the RCU | |
2832 | * grace period so that we catch work queued via RCU from the first | |
2833 | * pass. As neither drain_workqueue() nor flush_workqueue() report | |
2834 | * a result, we make an assumption that we only don't require more | |
2835 | * than 2 passes to catch all recursive RCU delayed work. | |
2836 | * | |
2837 | */ | |
2838 | int pass = 2; | |
2839 | do { | |
2840 | rcu_barrier(); | |
2841 | drain_workqueue(i915->wq); | |
2842 | } while (--pass); | |
2843 | } | |
2844 | ||
058d88c4 | 2845 | struct i915_vma * __must_check |
ec7adb6e JL |
2846 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
2847 | const struct i915_ggtt_view *view, | |
91b2db6f | 2848 | u64 size, |
2ffffd0f CW |
2849 | u64 alignment, |
2850 | u64 flags); | |
fe14d5f4 | 2851 | |
aa653a68 | 2852 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 2853 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2854 | |
7c108fd8 CW |
2855 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); |
2856 | ||
a4f5ea64 | 2857 | static inline int __sg_page_count(const struct scatterlist *sg) |
9da3da66 | 2858 | { |
ee286370 CW |
2859 | return sg->length >> PAGE_SHIFT; |
2860 | } | |
67d5a50c | 2861 | |
96d77634 CW |
2862 | struct scatterlist * |
2863 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
2864 | unsigned int n, unsigned int *offset); | |
341be1cd | 2865 | |
96d77634 CW |
2866 | struct page * |
2867 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, | |
2868 | unsigned int n); | |
67d5a50c | 2869 | |
96d77634 CW |
2870 | struct page * |
2871 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
2872 | unsigned int n); | |
67d5a50c | 2873 | |
96d77634 CW |
2874 | dma_addr_t |
2875 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
2876 | unsigned long n); | |
ee286370 | 2877 | |
03ac84f1 | 2878 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, |
a5c08166 | 2879 | struct sg_table *pages, |
84e8978e | 2880 | unsigned int sg_page_sizes); |
a4f5ea64 CW |
2881 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
2882 | ||
2883 | static inline int __must_check | |
2884 | i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
2885 | { | |
1233e2db | 2886 | might_lock(&obj->mm.lock); |
a4f5ea64 | 2887 | |
1233e2db | 2888 | if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) |
a4f5ea64 CW |
2889 | return 0; |
2890 | ||
2891 | return __i915_gem_object_get_pages(obj); | |
2892 | } | |
2893 | ||
f1fa4f44 CW |
2894 | static inline bool |
2895 | i915_gem_object_has_pages(struct drm_i915_gem_object *obj) | |
2896 | { | |
2897 | return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages)); | |
2898 | } | |
2899 | ||
a4f5ea64 CW |
2900 | static inline void |
2901 | __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 2902 | { |
f1fa4f44 | 2903 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
a4f5ea64 | 2904 | |
1233e2db | 2905 | atomic_inc(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
2906 | } |
2907 | ||
2908 | static inline bool | |
2909 | i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj) | |
2910 | { | |
1233e2db | 2911 | return atomic_read(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
2912 | } |
2913 | ||
2914 | static inline void | |
2915 | __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2916 | { | |
f1fa4f44 | 2917 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
a4f5ea64 | 2918 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
a4f5ea64 | 2919 | |
1233e2db | 2920 | atomic_dec(&obj->mm.pages_pin_count); |
a5570178 | 2921 | } |
0a798eb9 | 2922 | |
1233e2db CW |
2923 | static inline void |
2924 | i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 2925 | { |
a4f5ea64 | 2926 | __i915_gem_object_unpin_pages(obj); |
a5570178 CW |
2927 | } |
2928 | ||
548625ee CW |
2929 | enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */ |
2930 | I915_MM_NORMAL = 0, | |
2931 | I915_MM_SHRINKER | |
2932 | }; | |
2933 | ||
2934 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, | |
2935 | enum i915_mm_subclass subclass); | |
03ac84f1 | 2936 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); |
a4f5ea64 | 2937 | |
d31d7cb1 CW |
2938 | enum i915_map_type { |
2939 | I915_MAP_WB = 0, | |
2940 | I915_MAP_WC, | |
a575c676 CW |
2941 | #define I915_MAP_OVERRIDE BIT(31) |
2942 | I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE, | |
2943 | I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE, | |
d31d7cb1 CW |
2944 | }; |
2945 | ||
666424ab CW |
2946 | static inline enum i915_map_type |
2947 | i915_coherent_map_type(struct drm_i915_private *i915) | |
2948 | { | |
2949 | return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; | |
2950 | } | |
2951 | ||
0a798eb9 CW |
2952 | /** |
2953 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
a73c7a44 CW |
2954 | * @obj: the object to map into kernel address space |
2955 | * @type: the type of mapping, used to select pgprot_t | |
0a798eb9 CW |
2956 | * |
2957 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
2958 | * pages and then returns a contiguous mapping of the backing storage into | |
d31d7cb1 CW |
2959 | * the kernel address space. Based on the @type of mapping, the PTE will be |
2960 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
0a798eb9 | 2961 | * |
1233e2db CW |
2962 | * The caller is responsible for calling i915_gem_object_unpin_map() when the |
2963 | * mapping is no longer required. | |
0a798eb9 | 2964 | * |
8305216f DG |
2965 | * Returns the pointer through which to access the mapped object, or an |
2966 | * ERR_PTR() on error. | |
0a798eb9 | 2967 | */ |
d31d7cb1 CW |
2968 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2969 | enum i915_map_type type); | |
0a798eb9 CW |
2970 | |
2971 | /** | |
2972 | * i915_gem_object_unpin_map - releases an earlier mapping | |
a73c7a44 | 2973 | * @obj: the object to unmap |
0a798eb9 CW |
2974 | * |
2975 | * After pinning the object and mapping its pages, once you are finished | |
2976 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
2977 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
2978 | * removed. | |
0a798eb9 CW |
2979 | */ |
2980 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
2981 | { | |
0a798eb9 CW |
2982 | i915_gem_object_unpin_pages(obj); |
2983 | } | |
2984 | ||
43394c7d CW |
2985 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2986 | unsigned int *needs_clflush); | |
2987 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
2988 | unsigned int *needs_clflush); | |
7f5f95d8 CW |
2989 | #define CLFLUSH_BEFORE BIT(0) |
2990 | #define CLFLUSH_AFTER BIT(1) | |
2991 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
43394c7d CW |
2992 | |
2993 | static inline void | |
2994 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
2995 | { | |
2996 | i915_gem_object_unpin_pages(obj); | |
2997 | } | |
2998 | ||
54cf91dc | 2999 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ff72145b DA |
3000 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3001 | struct drm_device *dev, | |
3002 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3003 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3004 | uint32_t handle, uint64_t *offset); | |
4cc69075 | 3005 | int i915_gem_mmap_gtt_version(void); |
85d1225e DG |
3006 | |
3007 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3008 | struct drm_i915_gem_object *new, | |
3009 | unsigned frontbuffer_bits); | |
3010 | ||
73cb9701 | 3011 | int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3012 | |
e61e0f51 | 3013 | struct i915_request * |
0bc40be8 | 3014 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3015 | |
8c185eca CW |
3016 | static inline bool i915_reset_backoff(struct i915_gpu_error *error) |
3017 | { | |
3018 | return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags)); | |
3019 | } | |
3020 | ||
3021 | static inline bool i915_reset_handoff(struct i915_gpu_error *error) | |
1f83fee0 | 3022 | { |
8c185eca | 3023 | return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags)); |
c19ae989 CW |
3024 | } |
3025 | ||
8af29b0c | 3026 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
c19ae989 | 3027 | { |
8af29b0c | 3028 | return unlikely(test_bit(I915_WEDGED, &error->flags)); |
1f83fee0 DV |
3029 | } |
3030 | ||
8c185eca | 3031 | static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error) |
1f83fee0 | 3032 | { |
8c185eca | 3033 | return i915_reset_backoff(error) | i915_terminally_wedged(error); |
2ac0f450 MK |
3034 | } |
3035 | ||
3036 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3037 | { | |
8af29b0c | 3038 | return READ_ONCE(error->reset_count); |
1f83fee0 | 3039 | } |
a71d8d94 | 3040 | |
702c8f8e MT |
3041 | static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, |
3042 | struct intel_engine_cs *engine) | |
3043 | { | |
3044 | return READ_ONCE(error->reset_engine_count[engine->id]); | |
3045 | } | |
3046 | ||
e61e0f51 | 3047 | struct i915_request * |
a1ef70e1 | 3048 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine); |
0e178aef | 3049 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); |
d0667e9c CW |
3050 | void i915_gem_reset(struct drm_i915_private *dev_priv, |
3051 | unsigned int stalled_mask); | |
a1ef70e1 | 3052 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine); |
b1ed35d9 | 3053 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv); |
821ed7df | 3054 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv); |
2e8f9d32 | 3055 | bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv); |
a1ef70e1 | 3056 | void i915_gem_reset_engine(struct intel_engine_cs *engine, |
bba0869b CW |
3057 | struct i915_request *request, |
3058 | bool stalled); | |
57822dc6 | 3059 | |
24145517 | 3060 | void i915_gem_init_mmio(struct drm_i915_private *i915); |
bf9e8429 TU |
3061 | int __must_check i915_gem_init(struct drm_i915_private *dev_priv); |
3062 | int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); | |
c6be607a | 3063 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); |
8979187a | 3064 | void i915_gem_fini(struct drm_i915_private *dev_priv); |
cb15d9f8 | 3065 | void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv); |
496b575e | 3066 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
ec625fb9 | 3067 | unsigned int flags, long timeout); |
bf9e8429 | 3068 | int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv); |
ec92ad00 | 3069 | void i915_gem_suspend_late(struct drm_i915_private *dev_priv); |
bf9e8429 | 3070 | void i915_gem_resume(struct drm_i915_private *dev_priv); |
52137010 | 3071 | vm_fault_t i915_gem_fault(struct vm_fault *vmf); |
e95433c7 CW |
3072 | int i915_gem_object_wait(struct drm_i915_gem_object *obj, |
3073 | unsigned int flags, | |
3074 | long timeout, | |
3075 | struct intel_rps_client *rps); | |
6b5e90f5 CW |
3076 | int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, |
3077 | unsigned int flags, | |
b7268c5e | 3078 | const struct i915_sched_attr *attr); |
7651a445 | 3079 | #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX) |
6b5e90f5 | 3080 | |
2e2f351d | 3081 | int __must_check |
e22d8e3c CW |
3082 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); |
3083 | int __must_check | |
3084 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); | |
2021746e | 3085 | int __must_check |
dabdfe02 | 3086 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
058d88c4 | 3087 | struct i915_vma * __must_check |
2da3b9b9 CW |
3088 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3089 | u32 alignment, | |
5935485f CW |
3090 | const struct i915_ggtt_view *view, |
3091 | unsigned int flags); | |
058d88c4 | 3092 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); |
00731155 | 3093 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3094 | int align); |
829a0af2 | 3095 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); |
05394f39 | 3096 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3097 | |
e4ffd173 CW |
3098 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3099 | enum i915_cache_level cache_level); | |
3100 | ||
1286ff73 DV |
3101 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3102 | struct dma_buf *dma_buf); | |
3103 | ||
3104 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3105 | struct drm_gem_object *gem_obj, int flags); | |
3106 | ||
841cd773 DV |
3107 | static inline struct i915_hw_ppgtt * |
3108 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3109 | { | |
82ad6443 | 3110 | return container_of(vm, struct i915_hw_ppgtt, vm); |
841cd773 DV |
3111 | } |
3112 | ||
b42fe9ca | 3113 | /* i915_gem_fence_reg.c */ |
969b0950 CD |
3114 | struct drm_i915_fence_reg * |
3115 | i915_reserve_fence(struct drm_i915_private *dev_priv); | |
3116 | void i915_unreserve_fence(struct drm_i915_fence_reg *fence); | |
49ef5294 | 3117 | |
b1ed35d9 | 3118 | void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); |
4362f4f6 | 3119 | void i915_gem_restore_fences(struct drm_i915_private *dev_priv); |
41a36b73 | 3120 | |
4362f4f6 | 3121 | void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); |
03ac84f1 CW |
3122 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, |
3123 | struct sg_table *pages); | |
3124 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, | |
3125 | struct sg_table *pages); | |
7f96ecaf | 3126 | |
1acfc104 CW |
3127 | static inline struct i915_gem_context * |
3128 | __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) | |
3129 | { | |
3130 | return idr_find(&file_priv->context_idr, id); | |
3131 | } | |
3132 | ||
ca585b5d CW |
3133 | static inline struct i915_gem_context * |
3134 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3135 | { | |
3136 | struct i915_gem_context *ctx; | |
3137 | ||
1acfc104 CW |
3138 | rcu_read_lock(); |
3139 | ctx = __i915_gem_context_lookup_rcu(file_priv, id); | |
3140 | if (ctx && !kref_get_unless_zero(&ctx->ref)) | |
3141 | ctx = NULL; | |
3142 | rcu_read_unlock(); | |
ca585b5d CW |
3143 | |
3144 | return ctx; | |
3145 | } | |
3146 | ||
eec688e1 RB |
3147 | int i915_perf_open_ioctl(struct drm_device *dev, void *data, |
3148 | struct drm_file *file); | |
f89823c2 LL |
3149 | int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, |
3150 | struct drm_file *file); | |
3151 | int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, | |
3152 | struct drm_file *file); | |
19f81df2 RB |
3153 | void i915_oa_init_reg_state(struct intel_engine_cs *engine, |
3154 | struct i915_gem_context *ctx, | |
3155 | uint32_t *reg_state); | |
eec688e1 | 3156 | |
679845ed | 3157 | /* i915_gem_evict.c */ |
e522ac23 | 3158 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3159 | u64 min_size, u64 alignment, |
679845ed | 3160 | unsigned cache_level, |
2ffffd0f | 3161 | u64 start, u64 end, |
1ec9e26d | 3162 | unsigned flags); |
625d988a CW |
3163 | int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, |
3164 | struct drm_mm_node *node, | |
3165 | unsigned int flags); | |
2889caa9 | 3166 | int i915_gem_evict_vm(struct i915_address_space *vm); |
1d2a314c | 3167 | |
7125397b CW |
3168 | void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv); |
3169 | ||
0260c420 | 3170 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3171 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3172 | { |
600f4368 | 3173 | wmb(); |
c033666a | 3174 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3175 | intel_gtt_chipset_flush(); |
3176 | } | |
246cbfb5 | 3177 | |
9797fbfb | 3178 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3179 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3180 | struct drm_mm_node *node, u64 size, | |
3181 | unsigned alignment); | |
a9da512b PZ |
3182 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3183 | struct drm_mm_node *node, u64 size, | |
3184 | unsigned alignment, u64 start, | |
3185 | u64 end); | |
d713fd49 PZ |
3186 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3187 | struct drm_mm_node *node); | |
7ace3d30 | 3188 | int i915_gem_init_stolen(struct drm_i915_private *dev_priv); |
8c01903c | 3189 | void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv); |
0104fdbb | 3190 | struct drm_i915_gem_object * |
b7128ef1 MA |
3191 | i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, |
3192 | resource_size_t size); | |
866d12b4 | 3193 | struct drm_i915_gem_object * |
187685cb | 3194 | i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, |
b7128ef1 MA |
3195 | resource_size_t stolen_offset, |
3196 | resource_size_t gtt_offset, | |
3197 | resource_size_t size); | |
9797fbfb | 3198 | |
920cf419 CW |
3199 | /* i915_gem_internal.c */ |
3200 | struct drm_i915_gem_object * | |
3201 | i915_gem_object_create_internal(struct drm_i915_private *dev_priv, | |
fcd46e53 | 3202 | phys_addr_t size); |
920cf419 | 3203 | |
be6a0376 | 3204 | /* i915_gem_shrinker.c */ |
56fa4bf2 | 3205 | unsigned long i915_gem_shrink(struct drm_i915_private *i915, |
14387540 | 3206 | unsigned long target, |
912d572d | 3207 | unsigned long *nr_scanned, |
be6a0376 DV |
3208 | unsigned flags); |
3209 | #define I915_SHRINK_PURGEABLE 0x1 | |
3210 | #define I915_SHRINK_UNBOUND 0x2 | |
3211 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3212 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3213 | #define I915_SHRINK_VMAPS 0x10 |
56fa4bf2 CW |
3214 | unsigned long i915_gem_shrink_all(struct drm_i915_private *i915); |
3215 | void i915_gem_shrinker_register(struct drm_i915_private *i915); | |
3216 | void i915_gem_shrinker_unregister(struct drm_i915_private *i915); | |
19bb33c7 | 3217 | void i915_gem_shrinker_taints_mutex(struct mutex *mutex); |
be6a0376 | 3218 | |
673a394b | 3219 | /* i915_gem_tiling.c */ |
2c1792a1 | 3220 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3221 | { |
091387c1 | 3222 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3223 | |
3224 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3225 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3226 | } |
3227 | ||
91d4e0aa CW |
3228 | u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, |
3229 | unsigned int tiling, unsigned int stride); | |
3230 | u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, | |
3231 | unsigned int tiling, unsigned int stride); | |
3232 | ||
2017263e | 3233 | /* i915_debugfs.c */ |
f8c168fa | 3234 | #ifdef CONFIG_DEBUG_FS |
1dac891c | 3235 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
249e87de | 3236 | int i915_debugfs_connector_add(struct drm_connector *connector); |
36cdd013 | 3237 | void intel_display_crc_init(struct drm_i915_private *dev_priv); |
07144428 | 3238 | #else |
8d35acba | 3239 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
101057fa DV |
3240 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3241 | { return 0; } | |
ce5e2ac1 | 3242 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} |
07144428 | 3243 | #endif |
84734a04 | 3244 | |
0a4cd7c8 | 3245 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3246 | |
351e3db2 | 3247 | /* i915_cmd_parser.c */ |
1ca3712c | 3248 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
7756e454 | 3249 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 | 3250 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 CW |
3251 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, |
3252 | struct drm_i915_gem_object *batch_obj, | |
3253 | struct drm_i915_gem_object *shadow_batch_obj, | |
3254 | u32 batch_start_offset, | |
3255 | u32 batch_len, | |
3256 | bool is_master); | |
351e3db2 | 3257 | |
eec688e1 RB |
3258 | /* i915_perf.c */ |
3259 | extern void i915_perf_init(struct drm_i915_private *dev_priv); | |
3260 | extern void i915_perf_fini(struct drm_i915_private *dev_priv); | |
442b8c06 RB |
3261 | extern void i915_perf_register(struct drm_i915_private *dev_priv); |
3262 | extern void i915_perf_unregister(struct drm_i915_private *dev_priv); | |
eec688e1 | 3263 | |
317c35d1 | 3264 | /* i915_suspend.c */ |
af6dc742 TU |
3265 | extern int i915_save_state(struct drm_i915_private *dev_priv); |
3266 | extern int i915_restore_state(struct drm_i915_private *dev_priv); | |
0a3e67a4 | 3267 | |
0136db58 | 3268 | /* i915_sysfs.c */ |
694c2828 DW |
3269 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); |
3270 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
0136db58 | 3271 | |
eef57324 JA |
3272 | /* intel_lpe_audio.c */ |
3273 | int intel_lpe_audio_init(struct drm_i915_private *dev_priv); | |
3274 | void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); | |
3275 | void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); | |
46d196ec | 3276 | void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, |
20be551e VS |
3277 | enum pipe pipe, enum port port, |
3278 | const void *eld, int ls_clock, bool dp_output); | |
eef57324 | 3279 | |
f899fc64 | 3280 | /* intel_i2c.c */ |
40196446 TU |
3281 | extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); |
3282 | extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); | |
88ac7939 JN |
3283 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3284 | unsigned int pin); | |
07e17a75 | 3285 | extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter); |
3bd7d909 | 3286 | |
0184df46 JN |
3287 | extern struct i2c_adapter * |
3288 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3289 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3290 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3291 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3292 | { |
3293 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3294 | } | |
af6dc742 | 3295 | extern void intel_i2c_reset(struct drm_i915_private *dev_priv); |
f899fc64 | 3296 | |
8b8e1a89 | 3297 | /* intel_bios.c */ |
66578857 | 3298 | void intel_bios_init(struct drm_i915_private *dev_priv); |
785f076b | 3299 | void intel_bios_cleanup(struct drm_i915_private *dev_priv); |
f0067a31 | 3300 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3301 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3302 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3303 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3304 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3305 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3306 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3307 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3308 | enum port port); | |
6389dd83 SS |
3309 | bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, |
3310 | enum port port); | |
39053089 | 3311 | enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port); |
6389dd83 | 3312 | |
723bfd70 JB |
3313 | /* intel_acpi.c */ |
3314 | #ifdef CONFIG_ACPI | |
3315 | extern void intel_register_dsm_handler(void); | |
3316 | extern void intel_unregister_dsm_handler(void); | |
3317 | #else | |
3318 | static inline void intel_register_dsm_handler(void) { return; } | |
3319 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3320 | #endif /* CONFIG_ACPI */ | |
3321 | ||
94b4f3ba CW |
3322 | /* intel_device_info.c */ |
3323 | static inline struct intel_device_info * | |
3324 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3325 | { | |
3326 | return (struct intel_device_info *)&dev_priv->info; | |
3327 | } | |
3328 | ||
79e53945 | 3329 | /* modesetting */ |
f817586c | 3330 | extern void intel_modeset_init_hw(struct drm_device *dev); |
b079bd17 | 3331 | extern int intel_modeset_init(struct drm_device *dev); |
79e53945 | 3332 | extern void intel_modeset_cleanup(struct drm_device *dev); |
6315b5d3 TU |
3333 | extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, |
3334 | bool state); | |
043e9bda | 3335 | extern void intel_display_resume(struct drm_device *dev); |
29b74b7f TU |
3336 | extern void i915_redisable_vga(struct drm_i915_private *dev_priv); |
3337 | extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); | |
91d14251 | 3338 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
c39055b0 | 3339 | extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); |
9fcee2f7 | 3340 | extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
60548c55 CW |
3341 | extern void intel_rps_mark_interactive(struct drm_i915_private *i915, |
3342 | bool interactive); | |
11a85d6a | 3343 | extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
5209b1f4 | 3344 | bool enable); |
7182414e MN |
3345 | void intel_dsc_enable(struct intel_encoder *encoder, |
3346 | const struct intel_crtc_state *crtc_state); | |
a600622c | 3347 | void intel_dsc_disable(const struct intel_crtc_state *crtc_state); |
3bad0781 | 3348 | |
c0c7babc BW |
3349 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3350 | struct drm_file *file); | |
575155a9 | 3351 | |
6ef3d427 | 3352 | /* overlay */ |
c033666a CW |
3353 | extern struct intel_overlay_error_state * |
3354 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3355 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3356 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3357 | |
c033666a CW |
3358 | extern struct intel_display_error_state * |
3359 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3360 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 | 3361 | struct intel_display_error_state *error); |
6ef3d427 | 3362 | |
151a49d0 | 3363 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
e76019a8 | 3364 | int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox, |
006bb4cc ID |
3365 | u32 val, int fast_timeout_us, |
3366 | int slow_timeout_ms); | |
e76019a8 | 3367 | #define sandybridge_pcode_write(dev_priv, mbox, val) \ |
006bb4cc | 3368 | sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0) |
e76019a8 | 3369 | |
a0b8a1fe ID |
3370 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, |
3371 | u32 reply_mask, u32 reply, int timeout_base_ms); | |
59de0813 JN |
3372 | |
3373 | /* intel_sideband.c */ | |
707b6e3d | 3374 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
9fcee2f7 | 3375 | int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); |
64936258 | 3376 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3377 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3378 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3379 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3380 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3381 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3382 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3383 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3384 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3385 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3386 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3387 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3388 | enum intel_sbi_destination destination); | |
3389 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3390 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3391 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3392 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3393 | |
b7fa22d8 | 3394 | /* intel_dpio_phy.c */ |
0a116ce8 | 3395 | void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, |
ed37892e | 3396 | enum dpio_phy *phy, enum dpio_channel *ch); |
b6e08203 ACO |
3397 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, |
3398 | enum port port, u32 margin, u32 scale, | |
3399 | u32 enable, u32 deemphasis); | |
47a6bc61 ACO |
3400 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); |
3401 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); | |
3402 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, | |
3403 | enum dpio_phy phy); | |
3404 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
3405 | enum dpio_phy phy); | |
5161d058 | 3406 | uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count); |
47a6bc61 ACO |
3407 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, |
3408 | uint8_t lane_lat_optim_mask); | |
3409 | uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); | |
3410 | ||
b7fa22d8 ACO |
3411 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
3412 | u32 deemph_reg_value, u32 margin_reg_value, | |
3413 | bool uniq_trans_scale); | |
844b2f9a | 3414 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2e1029c6 | 3415 | const struct intel_crtc_state *crtc_state, |
844b2f9a | 3416 | bool reset); |
2e1029c6 VS |
3417 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder, |
3418 | const struct intel_crtc_state *crtc_state); | |
3419 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, | |
3420 | const struct intel_crtc_state *crtc_state); | |
e7d2a717 | 3421 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); |
2e1029c6 VS |
3422 | void chv_phy_post_pll_disable(struct intel_encoder *encoder, |
3423 | const struct intel_crtc_state *old_crtc_state); | |
b7fa22d8 | 3424 | |
53d98725 ACO |
3425 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3426 | u32 demph_reg_value, u32 preemph_reg_value, | |
3427 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
2e1029c6 VS |
3428 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, |
3429 | const struct intel_crtc_state *crtc_state); | |
3430 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, | |
3431 | const struct intel_crtc_state *crtc_state); | |
3432 | void vlv_phy_reset_lanes(struct intel_encoder *encoder, | |
3433 | const struct intel_crtc_state *old_crtc_state); | |
53d98725 | 3434 | |
c45198b1 ID |
3435 | /* intel_combo_phy.c */ |
3436 | void icl_combo_phys_init(struct drm_i915_private *dev_priv); | |
3437 | void icl_combo_phys_uninit(struct drm_i915_private *dev_priv); | |
3438 | void cnl_combo_phys_init(struct drm_i915_private *dev_priv); | |
3439 | void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv); | |
3440 | ||
616bc820 VS |
3441 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3442 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
36cc8b96 | 3443 | u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, |
c5a0ad11 | 3444 | const i915_reg_t reg); |
c8d9a590 | 3445 | |
c84b2705 TU |
3446 | u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); |
3447 | ||
36cc8b96 TU |
3448 | static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
3449 | const i915_reg_t reg) | |
3450 | { | |
3451 | return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000); | |
3452 | } | |
3453 | ||
0b274481 BW |
3454 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3455 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3456 | ||
3457 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3458 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3459 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3460 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3461 | ||
3462 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3463 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3464 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3465 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3466 | ||
698b3135 CW |
3467 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3468 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3469 | * an arbitrary delay between them. This can cause the hardware to | |
3470 | * act upon the intermediate value, possibly leading to corruption and | |
b18c1bb4 CW |
3471 | * machine death. For this reason we do not support I915_WRITE64, or |
3472 | * dev_priv->uncore.funcs.mmio_writeq. | |
3473 | * | |
3474 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
3475 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
3476 | * occasionally a 64-bit register does not actualy support a full readq | |
3477 | * and must be read using two 32-bit reads. | |
3478 | * | |
3479 | * You have been warned. | |
698b3135 | 3480 | */ |
0b274481 | 3481 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
cae5852d | 3482 | |
50877445 | 3483 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3484 | u32 upper, lower, old_upper, loop = 0; \ |
3485 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3486 | do { \ |
acd29f7b | 3487 | old_upper = upper; \ |
ee0a227b | 3488 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3489 | upper = I915_READ(upper_reg); \ |
3490 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3491 | (u64)upper << 32 | lower; }) |
50877445 | 3492 | |
cae5852d ZN |
3493 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3494 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3495 | ||
75aa3f63 | 3496 | #define __raw_read(x, s) \ |
6e3955a5 | 3497 | static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 3498 | i915_reg_t reg) \ |
75aa3f63 | 3499 | { \ |
f0f59a00 | 3500 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3501 | } |
3502 | ||
3503 | #define __raw_write(x, s) \ | |
6e3955a5 | 3504 | static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 3505 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3506 | { \ |
f0f59a00 | 3507 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3508 | } |
3509 | __raw_read(8, b) | |
3510 | __raw_read(16, w) | |
3511 | __raw_read(32, l) | |
3512 | __raw_read(64, q) | |
3513 | ||
3514 | __raw_write(8, b) | |
3515 | __raw_write(16, w) | |
3516 | __raw_write(32, l) | |
3517 | __raw_write(64, q) | |
3518 | ||
3519 | #undef __raw_read | |
3520 | #undef __raw_write | |
3521 | ||
a6111f7b | 3522 | /* These are untraced mmio-accessors that are only valid to be used inside |
aafee2eb | 3523 | * critical sections, such as inside IRQ handlers, where forcewake is explicitly |
a6111f7b | 3524 | * controlled. |
aafee2eb | 3525 | * |
a6111f7b | 3526 | * Think twice, and think again, before using these. |
aafee2eb AH |
3527 | * |
3528 | * As an example, these accessors can possibly be used between: | |
3529 | * | |
3530 | * spin_lock_irq(&dev_priv->uncore.lock); | |
3531 | * intel_uncore_forcewake_get__locked(); | |
3532 | * | |
3533 | * and | |
3534 | * | |
3535 | * intel_uncore_forcewake_put__locked(); | |
3536 | * spin_unlock_irq(&dev_priv->uncore.lock); | |
3537 | * | |
3538 | * | |
3539 | * Note: some registers may not need forcewake held, so | |
3540 | * intel_uncore_forcewake_{get,put} can be omitted, see | |
3541 | * intel_uncore_forcewake_for_reg(). | |
3542 | * | |
3543 | * Certain architectures will die if the same cacheline is concurrently accessed | |
3544 | * by different clients (e.g. on Ivybridge). Access to registers should | |
3545 | * therefore generally be serialised, by either the dev_priv->uncore.lock or | |
3546 | * a more localised lock guarding all access to that bank of registers. | |
a6111f7b | 3547 | */ |
75aa3f63 VS |
3548 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3549 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 3550 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
3551 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3552 | ||
55bc60db VS |
3553 | /* "Broadcast RGB" property */ |
3554 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3555 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3556 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3557 | |
920a14b2 | 3558 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) |
766aa1c4 | 3559 | { |
920a14b2 | 3560 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
766aa1c4 | 3561 | return VLV_VGACNTRL; |
920a14b2 | 3562 | else if (INTEL_GEN(dev_priv) >= 5) |
92e23b99 | 3563 | return CPU_VGACNTRL; |
766aa1c4 VS |
3564 | else |
3565 | return VGACNTRL; | |
3566 | } | |
3567 | ||
df97729f ID |
3568 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3569 | { | |
3570 | unsigned long j = msecs_to_jiffies(m); | |
3571 | ||
3572 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3573 | } | |
3574 | ||
7bd0e226 DV |
3575 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3576 | { | |
b8050148 CW |
3577 | /* nsecs_to_jiffies64() does not guard against overflow */ |
3578 | if (NSEC_PER_SEC % HZ && | |
3579 | div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) | |
3580 | return MAX_JIFFY_OFFSET; | |
3581 | ||
7bd0e226 DV |
3582 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); |
3583 | } | |
3584 | ||
dce56b3c PZ |
3585 | /* |
3586 | * If you need to wait X milliseconds between events A and B, but event B | |
3587 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3588 | * when event A happened, then just before event B you call this function and | |
3589 | * pass the timestamp as the first argument, and X as the second argument. | |
3590 | */ | |
3591 | static inline void | |
3592 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3593 | { | |
ec5e0cfb | 3594 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3595 | |
3596 | /* | |
3597 | * Don't re-read the value of "jiffies" every time since it may change | |
3598 | * behind our back and break the math. | |
3599 | */ | |
3600 | tmp_jiffies = jiffies; | |
3601 | target_jiffies = timestamp_jiffies + | |
3602 | msecs_to_jiffies_timeout(to_wait_ms); | |
3603 | ||
3604 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3605 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3606 | while (remaining_jiffies) | |
3607 | remaining_jiffies = | |
3608 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3609 | } |
3610 | } | |
221fe799 CW |
3611 | |
3612 | static inline bool | |
e61e0f51 | 3613 | __i915_request_irq_complete(const struct i915_request *rq) |
688e6c72 | 3614 | { |
e61e0f51 | 3615 | struct intel_engine_cs *engine = rq->engine; |
754c9fd5 | 3616 | u32 seqno; |
f69a02c9 | 3617 | |
309663ab CW |
3618 | /* Note that the engine may have wrapped around the seqno, and |
3619 | * so our request->global_seqno will be ahead of the hardware, | |
3620 | * even though it completed the request before wrapping. We catch | |
3621 | * this by kicking all the waiters before resetting the seqno | |
3622 | * in hardware, and also signal the fence. | |
3623 | */ | |
e61e0f51 | 3624 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)) |
309663ab CW |
3625 | return true; |
3626 | ||
754c9fd5 CW |
3627 | /* The request was dequeued before we were awoken. We check after |
3628 | * inspecting the hw to confirm that this was the same request | |
3629 | * that generated the HWS update. The memory barriers within | |
3630 | * the request execution are sufficient to ensure that a check | |
3631 | * after reading the value from hw matches this request. | |
3632 | */ | |
e61e0f51 | 3633 | seqno = i915_request_global_seqno(rq); |
754c9fd5 CW |
3634 | if (!seqno) |
3635 | return false; | |
3636 | ||
7ec2c73b CW |
3637 | /* Before we do the heavier coherent read of the seqno, |
3638 | * check the value (hopefully) in the CPU cacheline. | |
3639 | */ | |
e61e0f51 | 3640 | if (__i915_request_completed(rq, seqno)) |
7ec2c73b CW |
3641 | return true; |
3642 | ||
688e6c72 CW |
3643 | /* Ensure our read of the seqno is coherent so that we |
3644 | * do not "miss an interrupt" (i.e. if this is the last | |
3645 | * request and the seqno write from the GPU is not visible | |
3646 | * by the time the interrupt fires, we will see that the | |
3647 | * request is incomplete and go back to sleep awaiting | |
3648 | * another interrupt that will never come.) | |
3649 | * | |
3650 | * Strictly, we only need to do this once after an interrupt, | |
3651 | * but it is easier and safer to do it every time the waiter | |
3652 | * is woken. | |
3653 | */ | |
3d5564e9 | 3654 | if (engine->irq_seqno_barrier && |
538b257d | 3655 | test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) { |
56299fb7 | 3656 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
99fe4a5f | 3657 | |
3d5564e9 CW |
3658 | /* The ordering of irq_posted versus applying the barrier |
3659 | * is crucial. The clearing of the current irq_posted must | |
3660 | * be visible before we perform the barrier operation, | |
3661 | * such that if a subsequent interrupt arrives, irq_posted | |
3662 | * is reasserted and our task rewoken (which causes us to | |
3663 | * do another __i915_request_irq_complete() immediately | |
3664 | * and reapply the barrier). Conversely, if the clear | |
3665 | * occurs after the barrier, then an interrupt that arrived | |
3666 | * whilst we waited on the barrier would not trigger a | |
3667 | * barrier on the next pass, and the read may not see the | |
3668 | * seqno update. | |
3669 | */ | |
f69a02c9 | 3670 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
3671 | |
3672 | /* If we consume the irq, but we are no longer the bottom-half, | |
3673 | * the real bottom-half may not have serialised their own | |
3674 | * seqno check with the irq-barrier (i.e. may have inspected | |
3675 | * the seqno before we believe it coherent since they see | |
3676 | * irq_posted == false but we are still running). | |
3677 | */ | |
2c33b541 | 3678 | spin_lock_irq(&b->irq_lock); |
61d3dc70 | 3679 | if (b->irq_wait && b->irq_wait->tsk != current) |
99fe4a5f CW |
3680 | /* Note that if the bottom-half is changed as we |
3681 | * are sending the wake-up, the new bottom-half will | |
3682 | * be woken by whomever made the change. We only have | |
3683 | * to worry about when we steal the irq-posted for | |
3684 | * ourself. | |
3685 | */ | |
61d3dc70 | 3686 | wake_up_process(b->irq_wait->tsk); |
2c33b541 | 3687 | spin_unlock_irq(&b->irq_lock); |
99fe4a5f | 3688 | |
e61e0f51 | 3689 | if (__i915_request_completed(rq, seqno)) |
7ec2c73b CW |
3690 | return true; |
3691 | } | |
688e6c72 | 3692 | |
688e6c72 CW |
3693 | return false; |
3694 | } | |
3695 | ||
0b1de5d5 CW |
3696 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); |
3697 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
3698 | ||
c4d3ae68 CW |
3699 | /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment, |
3700 | * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot | |
3701 | * perform the operation. To check beforehand, pass in the parameters to | |
3702 | * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits, | |
3703 | * you only need to pass in the minor offsets, page-aligned pointers are | |
3704 | * always valid. | |
3705 | * | |
3706 | * For just checking for SSE4.1, in the foreknowledge that the future use | |
3707 | * will be correctly aligned, just use i915_has_memcpy_from_wc(). | |
3708 | */ | |
3709 | #define i915_can_memcpy_from_wc(dst, src, len) \ | |
3710 | i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0) | |
3711 | ||
3712 | #define i915_has_memcpy_from_wc() \ | |
3713 | i915_memcpy_from_wc(NULL, NULL, 0) | |
3714 | ||
c58305af CW |
3715 | /* i915_mm.c */ |
3716 | int remap_io_mapping(struct vm_area_struct *vma, | |
3717 | unsigned long addr, unsigned long pfn, unsigned long size, | |
3718 | struct io_mapping *iomap); | |
3719 | ||
767a983a CW |
3720 | static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) |
3721 | { | |
3722 | if (INTEL_GEN(i915) >= 10) | |
3723 | return CNL_HWS_CSB_WRITE_INDEX; | |
3724 | else | |
3725 | return I915_HWS_CSB_WRITE_INDEX; | |
3726 | } | |
3727 | ||
51797499 CW |
3728 | static inline u32 i915_scratch_offset(const struct drm_i915_private *i915) |
3729 | { | |
3730 | return i915_ggtt_offset(i915->gt.scratch); | |
3731 | } | |
3732 | ||
1da177e4 | 3733 | #endif |