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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
0ade6386 | 37 | #include <drm/intel-gtt.h> |
585fb111 | 38 | |
1da177e4 LT |
39 | /* General customization: |
40 | */ | |
41 | ||
42 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
43 | ||
44 | #define DRIVER_NAME "i915" | |
45 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 46 | #define DRIVER_DATE "20080730" |
1da177e4 | 47 | |
317c35d1 JB |
48 | enum pipe { |
49 | PIPE_A = 0, | |
50 | PIPE_B, | |
51 | }; | |
52 | ||
80824003 JB |
53 | enum plane { |
54 | PLANE_A = 0, | |
55 | PLANE_B, | |
56 | }; | |
57 | ||
52440211 KP |
58 | #define I915_NUM_PIPE 2 |
59 | ||
62fdfeaf EA |
60 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
61 | ||
1da177e4 LT |
62 | /* Interface history: |
63 | * | |
64 | * 1.1: Original. | |
0d6aa60b DA |
65 | * 1.2: Add Power Management |
66 | * 1.3: Add vblank support | |
de227f5f | 67 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 68 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
69 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
70 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
71 | */ |
72 | #define DRIVER_MAJOR 1 | |
2228ed67 | 73 | #define DRIVER_MINOR 6 |
1da177e4 LT |
74 | #define DRIVER_PATCHLEVEL 0 |
75 | ||
673a394b EA |
76 | #define WATCH_COHERENCY 0 |
77 | #define WATCH_BUF 0 | |
78 | #define WATCH_EXEC 0 | |
79 | #define WATCH_LRU 0 | |
80 | #define WATCH_RELOC 0 | |
81 | #define WATCH_INACTIVE 0 | |
82 | #define WATCH_PWRITE 0 | |
83 | ||
71acb5eb DA |
84 | #define I915_GEM_PHYS_CURSOR_0 1 |
85 | #define I915_GEM_PHYS_CURSOR_1 2 | |
86 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
87 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
88 | ||
89 | struct drm_i915_gem_phys_object { | |
90 | int id; | |
91 | struct page **page_list; | |
92 | drm_dma_handle_t *handle; | |
93 | struct drm_gem_object *cur_obj; | |
94 | }; | |
95 | ||
1da177e4 LT |
96 | struct mem_block { |
97 | struct mem_block *next; | |
98 | struct mem_block *prev; | |
99 | int start; | |
100 | int size; | |
6c340eac | 101 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
102 | }; |
103 | ||
0a3e67a4 JB |
104 | struct opregion_header; |
105 | struct opregion_acpi; | |
106 | struct opregion_swsci; | |
107 | struct opregion_asle; | |
108 | ||
8ee1c3db MG |
109 | struct intel_opregion { |
110 | struct opregion_header *header; | |
111 | struct opregion_acpi *acpi; | |
112 | struct opregion_swsci *swsci; | |
113 | struct opregion_asle *asle; | |
44834a67 | 114 | void *vbt; |
8ee1c3db | 115 | }; |
44834a67 | 116 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 117 | |
6ef3d427 CW |
118 | struct intel_overlay; |
119 | struct intel_overlay_error_state; | |
120 | ||
7c1c2871 DA |
121 | struct drm_i915_master_private { |
122 | drm_local_map_t *sarea; | |
123 | struct _drm_i915_sarea *sarea_priv; | |
124 | }; | |
de151cf6 JB |
125 | #define I915_FENCE_REG_NONE -1 |
126 | ||
127 | struct drm_i915_fence_reg { | |
128 | struct drm_gem_object *obj; | |
007cc8ac | 129 | struct list_head lru_list; |
de151cf6 | 130 | }; |
7c1c2871 | 131 | |
9b9d172d | 132 | struct sdvo_device_mapping { |
133 | u8 dvo_port; | |
134 | u8 slave_addr; | |
135 | u8 dvo_wiring; | |
136 | u8 initialized; | |
b1083333 | 137 | u8 ddc_pin; |
9b9d172d | 138 | }; |
139 | ||
63eeaf38 JB |
140 | struct drm_i915_error_state { |
141 | u32 eir; | |
142 | u32 pgtbl_er; | |
143 | u32 pipeastat; | |
144 | u32 pipebstat; | |
145 | u32 ipeir; | |
146 | u32 ipehr; | |
147 | u32 instdone; | |
148 | u32 acthd; | |
149 | u32 instpm; | |
150 | u32 instps; | |
151 | u32 instdone1; | |
152 | u32 seqno; | |
9df30794 | 153 | u64 bbaddr; |
63eeaf38 | 154 | struct timeval time; |
9df30794 CW |
155 | struct drm_i915_error_object { |
156 | int page_count; | |
157 | u32 gtt_offset; | |
158 | u32 *pages[0]; | |
159 | } *ringbuffer, *batchbuffer[2]; | |
160 | struct drm_i915_error_buffer { | |
161 | size_t size; | |
162 | u32 name; | |
163 | u32 seqno; | |
164 | u32 gtt_offset; | |
165 | u32 read_domains; | |
166 | u32 write_domain; | |
167 | u32 fence_reg; | |
168 | s32 pinned:2; | |
169 | u32 tiling:2; | |
170 | u32 dirty:1; | |
171 | u32 purgeable:1; | |
172 | } *active_bo; | |
173 | u32 active_bo_count; | |
6ef3d427 | 174 | struct intel_overlay_error_state *overlay; |
63eeaf38 JB |
175 | }; |
176 | ||
e70236a8 JB |
177 | struct drm_i915_display_funcs { |
178 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 179 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
180 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
181 | void (*disable_fbc)(struct drm_device *dev); | |
182 | int (*get_display_clock_speed)(struct drm_device *dev); | |
183 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
184 | void (*update_wm)(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
185 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
186 | int pixel_size); | |
e70236a8 JB |
187 | /* clock updates for mode set */ |
188 | /* cursor updates */ | |
189 | /* render clock increase/decrease */ | |
190 | /* display clock increase/decrease */ | |
191 | /* pll clock increase/decrease */ | |
192 | /* clock gating init */ | |
193 | }; | |
194 | ||
cfdf1fa2 | 195 | struct intel_device_info { |
c96c3a8c | 196 | u8 gen; |
cfdf1fa2 KH |
197 | u8 is_mobile : 1; |
198 | u8 is_i8xx : 1; | |
5ce8ba7c | 199 | u8 is_i85x : 1; |
cfdf1fa2 KH |
200 | u8 is_i915g : 1; |
201 | u8 is_i9xx : 1; | |
202 | u8 is_i945gm : 1; | |
203 | u8 is_i965g : 1; | |
204 | u8 is_i965gm : 1; | |
205 | u8 is_g33 : 1; | |
206 | u8 need_gfx_hws : 1; | |
207 | u8 is_g4x : 1; | |
208 | u8 is_pineview : 1; | |
534843da CW |
209 | u8 is_broadwater : 1; |
210 | u8 is_crestline : 1; | |
cfdf1fa2 KH |
211 | u8 is_ironlake : 1; |
212 | u8 has_fbc : 1; | |
213 | u8 has_rc6 : 1; | |
214 | u8 has_pipe_cxsr : 1; | |
215 | u8 has_hotplug : 1; | |
b295d1b6 | 216 | u8 cursor_needs_physical : 1; |
31578148 CW |
217 | u8 has_overlay : 1; |
218 | u8 overlay_needs_physical : 1; | |
cfdf1fa2 KH |
219 | }; |
220 | ||
b5e50c3f | 221 | enum no_fbc_reason { |
bed4a673 | 222 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
223 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
224 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
225 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
226 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
227 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 228 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
b5e50c3f JB |
229 | }; |
230 | ||
3bad0781 ZW |
231 | enum intel_pch { |
232 | PCH_IBX, /* Ibexpeak PCH */ | |
233 | PCH_CPT, /* Cougarpoint PCH */ | |
234 | }; | |
235 | ||
b690e96c JB |
236 | #define QUIRK_PIPEA_FORCE (1<<0) |
237 | ||
8be48d92 | 238 | struct intel_fbdev; |
38651674 | 239 | |
1da177e4 | 240 | typedef struct drm_i915_private { |
673a394b EA |
241 | struct drm_device *dev; |
242 | ||
cfdf1fa2 KH |
243 | const struct intel_device_info *info; |
244 | ||
ac5c4e76 DA |
245 | int has_gem; |
246 | ||
3043c60c | 247 | void __iomem *regs; |
1da177e4 | 248 | |
ec2a4c3f | 249 | struct pci_dev *bridge_dev; |
8187a2b7 | 250 | struct intel_ring_buffer render_ring; |
d1b851fc | 251 | struct intel_ring_buffer bsd_ring; |
6f392d54 | 252 | uint32_t next_seqno; |
1da177e4 | 253 | |
9c8da5eb | 254 | drm_dma_handle_t *status_page_dmah; |
e552eb70 | 255 | void *seqno_page; |
1da177e4 | 256 | dma_addr_t dma_status_page; |
0a3e67a4 | 257 | uint32_t counter; |
e552eb70 | 258 | unsigned int seqno_gfx_addr; |
dc7a9319 | 259 | drm_local_map_t hws_map; |
e552eb70 | 260 | struct drm_gem_object *seqno_obj; |
97f5ab66 | 261 | struct drm_gem_object *pwrctx; |
aa40d6bb | 262 | struct drm_gem_object *renderctx; |
1da177e4 | 263 | |
d7658989 JB |
264 | struct resource mch_res; |
265 | ||
a6b54f3f | 266 | unsigned int cpp; |
1da177e4 LT |
267 | int back_offset; |
268 | int front_offset; | |
269 | int current_page; | |
270 | int page_flipping; | |
be282fd4 JB |
271 | #define I915_DEBUG_READ (1<<0) |
272 | #define I915_DEBUG_WRITE (1<<1) | |
273 | unsigned long debug_flags; | |
1da177e4 LT |
274 | |
275 | wait_queue_head_t irq_queue; | |
276 | atomic_t irq_received; | |
ed4cb414 EA |
277 | /** Protects user_irq_refcount and irq_mask_reg */ |
278 | spinlock_t user_irq_lock; | |
9d34e5db | 279 | u32 trace_irq_seqno; |
ed4cb414 EA |
280 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
281 | u32 irq_mask_reg; | |
7c463586 | 282 | u32 pipestat[2]; |
f2b115e6 | 283 | /** splitted irq regs for graphics and display engine on Ironlake, |
036a4a7d ZW |
284 | irq_mask_reg is still used for display irq. */ |
285 | u32 gt_irq_mask_reg; | |
286 | u32 gt_irq_enable_reg; | |
287 | u32 de_irq_enable_reg; | |
c650156a ZW |
288 | u32 pch_irq_mask_reg; |
289 | u32 pch_irq_enable_reg; | |
1da177e4 | 290 | |
5ca58282 JB |
291 | u32 hotplug_supported_mask; |
292 | struct work_struct hotplug_work; | |
293 | ||
1da177e4 LT |
294 | int tex_lru_log_granularity; |
295 | int allow_batchbuffer; | |
296 | struct mem_block *agp_heap; | |
0d6aa60b | 297 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 298 | int vblank_pipe; |
a3524f1b | 299 | int num_pipe; |
a6b54f3f | 300 | |
f65d9421 | 301 | /* For hangcheck timer */ |
b3b079db | 302 | #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */ |
f65d9421 BG |
303 | struct timer_list hangcheck_timer; |
304 | int hangcheck_count; | |
305 | uint32_t last_acthd; | |
cbb465e7 CW |
306 | uint32_t last_instdone; |
307 | uint32_t last_instdone1; | |
f65d9421 | 308 | |
80824003 JB |
309 | unsigned long cfb_size; |
310 | unsigned long cfb_pitch; | |
bed4a673 | 311 | unsigned long cfb_offset; |
80824003 JB |
312 | int cfb_fence; |
313 | int cfb_plane; | |
bed4a673 | 314 | int cfb_y; |
80824003 | 315 | |
79e53945 JB |
316 | int irq_enabled; |
317 | ||
8ee1c3db MG |
318 | struct intel_opregion opregion; |
319 | ||
02e792fb DV |
320 | /* overlay */ |
321 | struct intel_overlay *overlay; | |
322 | ||
79e53945 | 323 | /* LVDS info */ |
a9573556 | 324 | int backlight_level; /* restore backlight to this value */ |
79e53945 JB |
325 | bool panel_wants_dither; |
326 | struct drm_display_mode *panel_fixed_mode; | |
88631706 ML |
327 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
328 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
329 | |
330 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
331 | unsigned int int_tv_support:1; |
332 | unsigned int lvds_dither:1; | |
333 | unsigned int lvds_vbt:1; | |
334 | unsigned int int_crt_support:1; | |
43565a06 | 335 | unsigned int lvds_use_ssc:1; |
32f9d658 | 336 | unsigned int edp_support:1; |
43565a06 | 337 | int lvds_ssc_freq; |
500a8cc4 | 338 | int edp_bpp; |
79e53945 | 339 | |
c1c7af60 JB |
340 | struct notifier_block lid_notifier; |
341 | ||
29874f44 | 342 | int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ |
de151cf6 JB |
343 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
344 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
345 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
346 | ||
95534263 | 347 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 348 | |
63eeaf38 JB |
349 | spinlock_t error_lock; |
350 | struct drm_i915_error_state *first_error; | |
8a905236 | 351 | struct work_struct error_work; |
9c9fe1f8 | 352 | struct workqueue_struct *wq; |
63eeaf38 | 353 | |
e70236a8 JB |
354 | /* Display functions */ |
355 | struct drm_i915_display_funcs display; | |
356 | ||
3bad0781 ZW |
357 | /* PCH chipset type */ |
358 | enum intel_pch pch_type; | |
359 | ||
b690e96c JB |
360 | unsigned long quirks; |
361 | ||
ba8bbcf6 | 362 | /* Register state */ |
c9354c85 | 363 | bool modeset_on_lid; |
ba8bbcf6 JB |
364 | u8 saveLBB; |
365 | u32 saveDSPACNTR; | |
366 | u32 saveDSPBCNTR; | |
e948e994 | 367 | u32 saveDSPARB; |
461cba2d | 368 | u32 saveHWS; |
ba8bbcf6 JB |
369 | u32 savePIPEACONF; |
370 | u32 savePIPEBCONF; | |
371 | u32 savePIPEASRC; | |
372 | u32 savePIPEBSRC; | |
373 | u32 saveFPA0; | |
374 | u32 saveFPA1; | |
375 | u32 saveDPLL_A; | |
376 | u32 saveDPLL_A_MD; | |
377 | u32 saveHTOTAL_A; | |
378 | u32 saveHBLANK_A; | |
379 | u32 saveHSYNC_A; | |
380 | u32 saveVTOTAL_A; | |
381 | u32 saveVBLANK_A; | |
382 | u32 saveVSYNC_A; | |
383 | u32 saveBCLRPAT_A; | |
5586c8bc | 384 | u32 saveTRANSACONF; |
42048781 ZW |
385 | u32 saveTRANS_HTOTAL_A; |
386 | u32 saveTRANS_HBLANK_A; | |
387 | u32 saveTRANS_HSYNC_A; | |
388 | u32 saveTRANS_VTOTAL_A; | |
389 | u32 saveTRANS_VBLANK_A; | |
390 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 391 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
392 | u32 saveDSPASTRIDE; |
393 | u32 saveDSPASIZE; | |
394 | u32 saveDSPAPOS; | |
585fb111 | 395 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
396 | u32 saveDSPASURF; |
397 | u32 saveDSPATILEOFF; | |
398 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 399 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
400 | u32 saveBLC_PWM_CTL; |
401 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
402 | u32 saveBLC_CPU_PWM_CTL; |
403 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
404 | u32 saveFPB0; |
405 | u32 saveFPB1; | |
406 | u32 saveDPLL_B; | |
407 | u32 saveDPLL_B_MD; | |
408 | u32 saveHTOTAL_B; | |
409 | u32 saveHBLANK_B; | |
410 | u32 saveHSYNC_B; | |
411 | u32 saveVTOTAL_B; | |
412 | u32 saveVBLANK_B; | |
413 | u32 saveVSYNC_B; | |
414 | u32 saveBCLRPAT_B; | |
5586c8bc | 415 | u32 saveTRANSBCONF; |
42048781 ZW |
416 | u32 saveTRANS_HTOTAL_B; |
417 | u32 saveTRANS_HBLANK_B; | |
418 | u32 saveTRANS_HSYNC_B; | |
419 | u32 saveTRANS_VTOTAL_B; | |
420 | u32 saveTRANS_VBLANK_B; | |
421 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 422 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
423 | u32 saveDSPBSTRIDE; |
424 | u32 saveDSPBSIZE; | |
425 | u32 saveDSPBPOS; | |
585fb111 | 426 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
427 | u32 saveDSPBSURF; |
428 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
429 | u32 saveVGA0; |
430 | u32 saveVGA1; | |
431 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
432 | u32 saveVGACNTRL; |
433 | u32 saveADPA; | |
434 | u32 saveLVDS; | |
585fb111 JB |
435 | u32 savePP_ON_DELAYS; |
436 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
437 | u32 saveDVOA; |
438 | u32 saveDVOB; | |
439 | u32 saveDVOC; | |
440 | u32 savePP_ON; | |
441 | u32 savePP_OFF; | |
442 | u32 savePP_CONTROL; | |
585fb111 | 443 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
444 | u32 savePFIT_CONTROL; |
445 | u32 save_palette_a[256]; | |
446 | u32 save_palette_b[256]; | |
06027f91 | 447 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
448 | u32 saveFBC_CFB_BASE; |
449 | u32 saveFBC_LL_BASE; | |
450 | u32 saveFBC_CONTROL; | |
451 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
452 | u32 saveIER; |
453 | u32 saveIIR; | |
454 | u32 saveIMR; | |
42048781 ZW |
455 | u32 saveDEIER; |
456 | u32 saveDEIMR; | |
457 | u32 saveGTIER; | |
458 | u32 saveGTIMR; | |
459 | u32 saveFDI_RXA_IMR; | |
460 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 461 | u32 saveCACHE_MODE_0; |
1f84e550 | 462 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
463 | u32 saveSWF0[16]; |
464 | u32 saveSWF1[16]; | |
465 | u32 saveSWF2[3]; | |
466 | u8 saveMSR; | |
467 | u8 saveSR[8]; | |
123f794f | 468 | u8 saveGR[25]; |
ba8bbcf6 | 469 | u8 saveAR_INDEX; |
a59e122a | 470 | u8 saveAR[21]; |
ba8bbcf6 | 471 | u8 saveDACMASK; |
a59e122a | 472 | u8 saveCR[37]; |
79f11c19 | 473 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
474 | u32 saveCURACNTR; |
475 | u32 saveCURAPOS; | |
476 | u32 saveCURABASE; | |
477 | u32 saveCURBCNTR; | |
478 | u32 saveCURBPOS; | |
479 | u32 saveCURBBASE; | |
480 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
481 | u32 saveDP_B; |
482 | u32 saveDP_C; | |
483 | u32 saveDP_D; | |
484 | u32 savePIPEA_GMCH_DATA_M; | |
485 | u32 savePIPEB_GMCH_DATA_M; | |
486 | u32 savePIPEA_GMCH_DATA_N; | |
487 | u32 savePIPEB_GMCH_DATA_N; | |
488 | u32 savePIPEA_DP_LINK_M; | |
489 | u32 savePIPEB_DP_LINK_M; | |
490 | u32 savePIPEA_DP_LINK_N; | |
491 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
492 | u32 saveFDI_RXA_CTL; |
493 | u32 saveFDI_TXA_CTL; | |
494 | u32 saveFDI_RXB_CTL; | |
495 | u32 saveFDI_TXB_CTL; | |
496 | u32 savePFA_CTL_1; | |
497 | u32 savePFB_CTL_1; | |
498 | u32 savePFA_WIN_SZ; | |
499 | u32 savePFB_WIN_SZ; | |
500 | u32 savePFA_WIN_POS; | |
501 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
502 | u32 savePCH_DREF_CONTROL; |
503 | u32 saveDISP_ARB_CTL; | |
504 | u32 savePIPEA_DATA_M1; | |
505 | u32 savePIPEA_DATA_N1; | |
506 | u32 savePIPEA_LINK_M1; | |
507 | u32 savePIPEA_LINK_N1; | |
508 | u32 savePIPEB_DATA_M1; | |
509 | u32 savePIPEB_DATA_N1; | |
510 | u32 savePIPEB_LINK_M1; | |
511 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 512 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
513 | |
514 | struct { | |
19966754 DV |
515 | /** Bridge to intel-gtt-ko */ |
516 | struct intel_gtt *gtt; | |
517 | /** Memory allocator for GTT stolen memory */ | |
518 | struct drm_mm vram; | |
519 | /** Memory allocator for GTT */ | |
673a394b EA |
520 | struct drm_mm gtt_space; |
521 | ||
0839ccb8 | 522 | struct io_mapping *gtt_mapping; |
ab657db1 | 523 | int gtt_mtrr; |
0839ccb8 | 524 | |
31169714 CW |
525 | /** |
526 | * Membership on list of all loaded devices, used to evict | |
527 | * inactive buffers under memory pressure. | |
528 | * | |
529 | * Modifications should only be done whilst holding the | |
530 | * shrink_list_lock spinlock. | |
531 | */ | |
532 | struct list_head shrink_list; | |
533 | ||
673a394b EA |
534 | /** |
535 | * List of objects which are not in the ringbuffer but which | |
536 | * still have a write_domain which needs to be flushed before | |
537 | * unbinding. | |
538 | * | |
ce44b0ea EA |
539 | * last_rendering_seqno is 0 while an object is in this list. |
540 | * | |
673a394b EA |
541 | * A reference is held on the buffer while on this list. |
542 | */ | |
543 | struct list_head flushing_list; | |
544 | ||
99fcb766 DV |
545 | /** |
546 | * List of objects currently pending a GPU write flush. | |
547 | * | |
548 | * All elements on this list will belong to either the | |
549 | * active_list or flushing_list, last_rendering_seqno can | |
550 | * be used to differentiate between the two elements. | |
551 | */ | |
552 | struct list_head gpu_write_list; | |
553 | ||
673a394b EA |
554 | /** |
555 | * LRU list of objects which are not in the ringbuffer and | |
556 | * are ready to unbind, but are still in the GTT. | |
557 | * | |
ce44b0ea EA |
558 | * last_rendering_seqno is 0 while an object is in this list. |
559 | * | |
673a394b EA |
560 | * A reference is not held on the buffer while on this list, |
561 | * as merely being GTT-bound shouldn't prevent its being | |
562 | * freed, and we'll pull it off the list in the free path. | |
563 | */ | |
564 | struct list_head inactive_list; | |
565 | ||
a09ba7fa EA |
566 | /** LRU list of objects with fence regs on them. */ |
567 | struct list_head fence_list; | |
568 | ||
be72615b CW |
569 | /** |
570 | * List of objects currently pending being freed. | |
571 | * | |
572 | * These objects are no longer in use, but due to a signal | |
573 | * we were prevented from freeing them at the appointed time. | |
574 | */ | |
575 | struct list_head deferred_free_list; | |
576 | ||
673a394b EA |
577 | /** |
578 | * We leave the user IRQ off as much as possible, | |
579 | * but this means that requests will finish and never | |
580 | * be retired once the system goes idle. Set a timer to | |
581 | * fire periodically while the ring is running. When it | |
582 | * fires, go retire requests. | |
583 | */ | |
584 | struct delayed_work retire_work; | |
585 | ||
673a394b EA |
586 | /** |
587 | * Waiting sequence number, if any | |
588 | */ | |
589 | uint32_t waiting_gem_seqno; | |
590 | ||
591 | /** | |
592 | * Last seq seen at irq time | |
593 | */ | |
594 | uint32_t irq_gem_seqno; | |
595 | ||
596 | /** | |
597 | * Flag if the X Server, and thus DRM, is not currently in | |
598 | * control of the device. | |
599 | * | |
600 | * This is set between LeaveVT and EnterVT. It needs to be | |
601 | * replaced with a semaphore. It also needs to be | |
602 | * transitioned away from for kernel modesetting. | |
603 | */ | |
604 | int suspended; | |
605 | ||
606 | /** | |
607 | * Flag if the hardware appears to be wedged. | |
608 | * | |
609 | * This is set when attempts to idle the device timeout. | |
610 | * It prevents command submission from occuring and makes | |
611 | * every pending request fail | |
612 | */ | |
ba1234d1 | 613 | atomic_t wedged; |
673a394b EA |
614 | |
615 | /** Bit 6 swizzling required for X tiling */ | |
616 | uint32_t bit_6_swizzle_x; | |
617 | /** Bit 6 swizzling required for Y tiling */ | |
618 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
619 | |
620 | /* storage for physical objects */ | |
621 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
673a394b | 622 | } mm; |
9b9d172d | 623 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
624 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
625 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
626 | /* Panel fitter placement and size for Ironlake+ */ |
627 | u32 pch_pf_pos, pch_pf_size; | |
652c393a | 628 | |
6b95a207 KH |
629 | struct drm_crtc *plane_to_crtc_mapping[2]; |
630 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
631 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 632 | bool flip_pending_is_done; |
6b95a207 | 633 | |
652c393a JB |
634 | /* Reclocking support */ |
635 | bool render_reclock_avail; | |
636 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
637 | /* indicates the reduced downclock for LVDS*/ |
638 | int lvds_downclock; | |
652c393a JB |
639 | struct work_struct idle_work; |
640 | struct timer_list idle_timer; | |
641 | bool busy; | |
642 | u16 orig_clock; | |
6363ee6f ZY |
643 | int child_dev_num; |
644 | struct child_device_config *child_dev; | |
a2565377 | 645 | struct drm_connector *int_lvds_connector; |
f97108d1 | 646 | |
c4804411 | 647 | bool mchbar_need_disable; |
f97108d1 JB |
648 | |
649 | u8 cur_delay; | |
650 | u8 min_delay; | |
651 | u8 max_delay; | |
7648fa99 JB |
652 | u8 fmax; |
653 | u8 fstart; | |
654 | ||
655 | u64 last_count1; | |
656 | unsigned long last_time1; | |
657 | u64 last_count2; | |
658 | struct timespec last_time2; | |
659 | unsigned long gfx_power; | |
660 | int c_m; | |
661 | int r_t; | |
662 | u8 corr; | |
663 | spinlock_t *mchdev_lock; | |
b5e50c3f JB |
664 | |
665 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 666 | |
20bf377e JB |
667 | struct drm_mm_node *compressed_fb; |
668 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 669 | |
8be48d92 DA |
670 | /* list of fbdev register on this device */ |
671 | struct intel_fbdev *fbdev; | |
1da177e4 LT |
672 | } drm_i915_private_t; |
673 | ||
673a394b EA |
674 | /** driver private structure attached to each drm_gem_object */ |
675 | struct drm_i915_gem_object { | |
c397b908 | 676 | struct drm_gem_object base; |
673a394b EA |
677 | |
678 | /** Current space allocated to this object in the GTT, if any. */ | |
679 | struct drm_mm_node *gtt_space; | |
680 | ||
681 | /** This object's place on the active/flushing/inactive lists */ | |
682 | struct list_head list; | |
99fcb766 DV |
683 | /** This object's place on GPU write list */ |
684 | struct list_head gpu_write_list; | |
cd377ea9 CW |
685 | /** This object's place on eviction list */ |
686 | struct list_head evict_list; | |
673a394b EA |
687 | |
688 | /** | |
689 | * This is set if the object is on the active or flushing lists | |
690 | * (has pending rendering), and is not set if it's on inactive (ready | |
691 | * to be unbound). | |
692 | */ | |
778c3544 | 693 | unsigned int active : 1; |
673a394b EA |
694 | |
695 | /** | |
696 | * This is set if the object has been written to since last bound | |
697 | * to the GTT | |
698 | */ | |
778c3544 DV |
699 | unsigned int dirty : 1; |
700 | ||
701 | /** | |
702 | * Fence register bits (if any) for this object. Will be set | |
703 | * as needed when mapped into the GTT. | |
704 | * Protected by dev->struct_mutex. | |
705 | * | |
706 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
707 | */ | |
11824e8c | 708 | signed int fence_reg : 5; |
778c3544 DV |
709 | |
710 | /** | |
711 | * Used for checking the object doesn't appear more than once | |
712 | * in an execbuffer object list. | |
713 | */ | |
714 | unsigned int in_execbuffer : 1; | |
715 | ||
716 | /** | |
717 | * Advice: are the backing pages purgeable? | |
718 | */ | |
719 | unsigned int madv : 2; | |
720 | ||
721 | /** | |
722 | * Refcount for the pages array. With the current locking scheme, there | |
723 | * are at most two concurrent users: Binding a bo to the gtt and | |
724 | * pwrite/pread using physical addresses. So two bits for a maximum | |
725 | * of two users are enough. | |
726 | */ | |
727 | unsigned int pages_refcount : 2; | |
728 | #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3 | |
729 | ||
730 | /** | |
731 | * Current tiling mode for the object. | |
732 | */ | |
733 | unsigned int tiling_mode : 2; | |
734 | ||
735 | /** How many users have pinned this object in GTT space. The following | |
736 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
737 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
738 | * times for the same batchbuffer), and the framebuffer code. When | |
739 | * switching/pageflipping, the framebuffer code has at most two buffers | |
740 | * pinned per crtc. | |
741 | * | |
742 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
743 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 744 | unsigned int pin_count : 4; |
778c3544 | 745 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b EA |
746 | |
747 | /** AGP memory structure for our GTT binding. */ | |
748 | DRM_AGP_MEM *agp_mem; | |
749 | ||
856fa198 | 750 | struct page **pages; |
673a394b EA |
751 | |
752 | /** | |
753 | * Current offset of the object in GTT space. | |
754 | * | |
755 | * This is the same as gtt_space->start | |
756 | */ | |
757 | uint32_t gtt_offset; | |
e67b8ce1 | 758 | |
852835f3 ZN |
759 | /* Which ring is refering to is this object */ |
760 | struct intel_ring_buffer *ring; | |
761 | ||
de151cf6 JB |
762 | /** |
763 | * Fake offset for use by mmap(2) | |
764 | */ | |
765 | uint64_t mmap_offset; | |
766 | ||
673a394b EA |
767 | /** Breadcrumb of last rendering to the buffer. */ |
768 | uint32_t last_rendering_seqno; | |
769 | ||
778c3544 | 770 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 771 | uint32_t stride; |
673a394b | 772 | |
280b713b | 773 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 774 | unsigned long *bit_17; |
280b713b | 775 | |
ba1eb1d8 KP |
776 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
777 | uint32_t agp_type; | |
778 | ||
673a394b | 779 | /** |
e47c68e9 EA |
780 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
781 | * flags which individual pages are valid. | |
673a394b EA |
782 | */ |
783 | uint8_t *page_cpu_valid; | |
79e53945 JB |
784 | |
785 | /** User space pin count and filp owning the pin */ | |
786 | uint32_t user_pin_count; | |
787 | struct drm_file *pin_filp; | |
71acb5eb DA |
788 | |
789 | /** for phy allocated objects */ | |
790 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 791 | |
6b95a207 KH |
792 | /** |
793 | * Number of crtcs where this object is currently the fb, but | |
794 | * will be page flipped away on the next vblank. When it | |
795 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
796 | */ | |
797 | atomic_t pending_flip; | |
673a394b EA |
798 | }; |
799 | ||
62b8b215 | 800 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 801 | |
673a394b EA |
802 | /** |
803 | * Request queue structure. | |
804 | * | |
805 | * The request queue allows us to note sequence numbers that have been emitted | |
806 | * and may be associated with active buffers to be retired. | |
807 | * | |
808 | * By keeping this list, we can avoid having to do questionable | |
809 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
810 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
811 | */ | |
812 | struct drm_i915_gem_request { | |
852835f3 ZN |
813 | /** On Which ring this request was generated */ |
814 | struct intel_ring_buffer *ring; | |
815 | ||
673a394b EA |
816 | /** GEM sequence number associated with this request. */ |
817 | uint32_t seqno; | |
818 | ||
819 | /** Time at which this request was emitted, in jiffies. */ | |
820 | unsigned long emitted_jiffies; | |
821 | ||
b962442e | 822 | /** global list entry for this request */ |
673a394b | 823 | struct list_head list; |
b962442e EA |
824 | |
825 | /** file_priv list entry for this request */ | |
826 | struct list_head client_list; | |
673a394b EA |
827 | }; |
828 | ||
829 | struct drm_i915_file_private { | |
830 | struct { | |
b962442e | 831 | struct list_head request_list; |
673a394b EA |
832 | } mm; |
833 | }; | |
834 | ||
79e53945 JB |
835 | enum intel_chip_family { |
836 | CHIP_I8XX = 0x01, | |
837 | CHIP_I9XX = 0x02, | |
838 | CHIP_I915 = 0x04, | |
839 | CHIP_I965 = 0x08, | |
840 | }; | |
841 | ||
c153f45f | 842 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 843 | extern int i915_max_ioctl; |
79e53945 | 844 | extern unsigned int i915_fbpercrtc; |
652c393a | 845 | extern unsigned int i915_powersave; |
33814341 | 846 | extern unsigned int i915_lvds_downclock; |
b3a83639 | 847 | |
6a9ee8af DA |
848 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
849 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
850 | extern void i915_save_display(struct drm_device *dev); |
851 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
852 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
853 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
854 | ||
1da177e4 | 855 | /* i915_dma.c */ |
84b1fd10 | 856 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 857 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 858 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 859 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 860 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
861 | extern void i915_driver_preclose(struct drm_device *dev, |
862 | struct drm_file *file_priv); | |
673a394b EA |
863 | extern void i915_driver_postclose(struct drm_device *dev, |
864 | struct drm_file *file_priv); | |
84b1fd10 | 865 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
866 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
867 | unsigned long arg); | |
673a394b | 868 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 869 | struct drm_clip_rect *boxes, |
673a394b | 870 | int i, int DR1, int DR4); |
11ed50ec | 871 | extern int i965_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
872 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
873 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
874 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
875 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
876 | ||
af6061af | 877 | |
1da177e4 | 878 | /* i915_irq.c */ |
f65d9421 | 879 | void i915_hangcheck_elapsed(unsigned long data); |
c153f45f EA |
880 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
881 | struct drm_file *file_priv); | |
882 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
883 | struct drm_file *file_priv); | |
9d34e5db | 884 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
79e53945 | 885 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
886 | |
887 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 888 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 889 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 890 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
891 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
892 | struct drm_file *file_priv); | |
893 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
894 | struct drm_file *file_priv); | |
0a3e67a4 JB |
895 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
896 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
897 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 898 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
899 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
900 | struct drm_file *file_priv); | |
8ee1c3db | 901 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
62fdfeaf | 902 | extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); |
8187a2b7 ZN |
903 | extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, |
904 | u32 mask); | |
905 | extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, | |
906 | u32 mask); | |
1da177e4 | 907 | |
7c463586 KP |
908 | void |
909 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
910 | ||
911 | void | |
912 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
913 | ||
01c66889 ZY |
914 | void intel_enable_asle (struct drm_device *dev); |
915 | ||
3bd3c932 CW |
916 | #ifdef CONFIG_DEBUG_FS |
917 | extern void i915_destroy_error_state(struct drm_device *dev); | |
918 | #else | |
919 | #define i915_destroy_error_state(x) | |
920 | #endif | |
921 | ||
7c463586 | 922 | |
1da177e4 | 923 | /* i915_mem.c */ |
c153f45f EA |
924 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
925 | struct drm_file *file_priv); | |
926 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
927 | struct drm_file *file_priv); | |
928 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
929 | struct drm_file *file_priv); | |
930 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
931 | struct drm_file *file_priv); | |
1da177e4 | 932 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 933 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 934 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
935 | /* i915_gem.c */ |
936 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
937 | struct drm_file *file_priv); | |
938 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
939 | struct drm_file *file_priv); | |
940 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
941 | struct drm_file *file_priv); | |
942 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
943 | struct drm_file *file_priv); | |
944 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
945 | struct drm_file *file_priv); | |
de151cf6 JB |
946 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
947 | struct drm_file *file_priv); | |
673a394b EA |
948 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
949 | struct drm_file *file_priv); | |
950 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
951 | struct drm_file *file_priv); | |
952 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
953 | struct drm_file *file_priv); | |
76446cac JB |
954 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
955 | struct drm_file *file_priv); | |
673a394b EA |
956 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
957 | struct drm_file *file_priv); | |
958 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
959 | struct drm_file *file_priv); | |
960 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
961 | struct drm_file *file_priv); | |
962 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
963 | struct drm_file *file_priv); | |
3ef94daa CW |
964 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
965 | struct drm_file *file_priv); | |
673a394b EA |
966 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
967 | struct drm_file *file_priv); | |
968 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
969 | struct drm_file *file_priv); | |
970 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
971 | struct drm_file *file_priv); | |
972 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
973 | struct drm_file *file_priv); | |
5a125c3c EA |
974 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
975 | struct drm_file *file_priv); | |
673a394b | 976 | void i915_gem_load(struct drm_device *dev); |
673a394b | 977 | int i915_gem_init_object(struct drm_gem_object *obj); |
ac52bc56 DV |
978 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
979 | size_t size); | |
673a394b EA |
980 | void i915_gem_free_object(struct drm_gem_object *obj); |
981 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
982 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 983 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 984 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b | 985 | void i915_gem_lastclose(struct drm_device *dev); |
852835f3 ZN |
986 | uint32_t i915_get_gem_seqno(struct drm_device *dev, |
987 | struct intel_ring_buffer *ring); | |
22be1724 | 988 | bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); |
8c4b8c3f | 989 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
52dc7d32 | 990 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
b09a1fec | 991 | void i915_gem_retire_requests(struct drm_device *dev); |
673a394b | 992 | void i915_gem_clflush_object(struct drm_gem_object *obj); |
79e53945 JB |
993 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
994 | uint32_t read_domains, | |
995 | uint32_t write_domain); | |
996 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
997 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
998 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
999 | unsigned long end); | |
b47eb4a2 | 1000 | int i915_gpu_idle(struct drm_device *dev); |
5669fcac | 1001 | int i915_gem_idle(struct drm_device *dev); |
852835f3 | 1002 | uint32_t i915_add_request(struct drm_device *dev, |
8dc5d147 CW |
1003 | struct drm_file *file_priv, |
1004 | struct drm_i915_gem_request *request, | |
1005 | struct intel_ring_buffer *ring); | |
852835f3 | 1006 | int i915_do_wait_request(struct drm_device *dev, |
8a1a49f9 DV |
1007 | uint32_t seqno, |
1008 | bool interruptible, | |
1009 | struct intel_ring_buffer *ring); | |
de151cf6 | 1010 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
8a1a49f9 DV |
1011 | void i915_gem_process_flushing_list(struct drm_device *dev, |
1012 | uint32_t flush_domains, | |
1013 | struct intel_ring_buffer *ring); | |
79e53945 JB |
1014 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
1015 | int write); | |
b9241ea3 | 1016 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); |
71acb5eb | 1017 | int i915_gem_attach_phys_object(struct drm_device *dev, |
6eeefaf3 CW |
1018 | struct drm_gem_object *obj, |
1019 | int id, | |
1020 | int align); | |
71acb5eb DA |
1021 | void i915_gem_detach_phys_object(struct drm_device *dev, |
1022 | struct drm_gem_object *obj); | |
1023 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
4bdadb97 | 1024 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); |
6911a9b8 | 1025 | void i915_gem_object_put_pages(struct drm_gem_object *obj); |
1fd1c624 | 1026 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
673a394b | 1027 | |
31169714 CW |
1028 | void i915_gem_shrinker_init(void); |
1029 | void i915_gem_shrinker_exit(void); | |
1030 | ||
b47eb4a2 CW |
1031 | /* i915_gem_evict.c */ |
1032 | int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment); | |
1033 | int i915_gem_evict_everything(struct drm_device *dev); | |
1034 | int i915_gem_evict_inactive(struct drm_device *dev); | |
1035 | ||
673a394b EA |
1036 | /* i915_gem_tiling.c */ |
1037 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
1038 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
1039 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
76446cac JB |
1040 | bool i915_tiling_ok(struct drm_device *dev, int stride, int size, |
1041 | int tiling_mode); | |
f590d279 OA |
1042 | bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, |
1043 | int tiling_mode); | |
673a394b EA |
1044 | |
1045 | /* i915_gem_debug.c */ | |
1046 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1047 | const char *where, uint32_t mark); | |
1048 | #if WATCH_INACTIVE | |
1049 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
1050 | #else | |
1051 | #define i915_verify_inactive(dev, file, line) | |
1052 | #endif | |
1053 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
1054 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1055 | const char *where, uint32_t mark); | |
1056 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 1057 | |
2017263e | 1058 | /* i915_debugfs.c */ |
27c202ad BG |
1059 | int i915_debugfs_init(struct drm_minor *minor); |
1060 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1061 | |
317c35d1 JB |
1062 | /* i915_suspend.c */ |
1063 | extern int i915_save_state(struct drm_device *dev); | |
1064 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1065 | |
1066 | /* i915_suspend.c */ | |
1067 | extern int i915_save_state(struct drm_device *dev); | |
1068 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1069 | |
3b617967 | 1070 | /* intel_opregion.c */ |
44834a67 CW |
1071 | extern int intel_opregion_setup(struct drm_device *dev); |
1072 | #ifdef CONFIG_ACPI | |
1073 | extern void intel_opregion_init(struct drm_device *dev); | |
1074 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1075 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1076 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1077 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1078 | #else |
44834a67 CW |
1079 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1080 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1081 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1082 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1083 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1084 | #endif |
8ee1c3db | 1085 | |
79e53945 JB |
1086 | /* modesetting */ |
1087 | extern void intel_modeset_init(struct drm_device *dev); | |
1088 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1089 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1090 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1091 | extern void g4x_disable_fbc(struct drm_device *dev); |
b52eb4dc | 1092 | extern void ironlake_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1093 | extern void intel_disable_fbc(struct drm_device *dev); |
1094 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1095 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
7648fa99 | 1096 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
3bad0781 | 1097 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1098 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1099 | |
6ef3d427 | 1100 | /* overlay */ |
3bd3c932 | 1101 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1102 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1103 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
3bd3c932 | 1104 | #endif |
6ef3d427 | 1105 | |
546b0974 EA |
1106 | /** |
1107 | * Lock test for when it's just for synchronization of ring access. | |
1108 | * | |
1109 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1110 | * has access to the ring. | |
1111 | */ | |
1112 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
8187a2b7 ZN |
1113 | if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ |
1114 | == NULL) \ | |
546b0974 EA |
1115 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
1116 | } while (0) | |
1117 | ||
be282fd4 JB |
1118 | static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg) |
1119 | { | |
1120 | u32 val; | |
1121 | ||
1122 | val = readl(dev_priv->regs + reg); | |
1123 | if (dev_priv->debug_flags & I915_DEBUG_READ) | |
1124 | printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg); | |
1125 | return val; | |
1126 | } | |
1127 | ||
1128 | static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, | |
1129 | u32 val) | |
1130 | { | |
1131 | writel(val, dev_priv->regs + reg); | |
1132 | if (dev_priv->debug_flags & I915_DEBUG_WRITE) | |
1133 | printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg); | |
1134 | } | |
1135 | ||
1136 | #define I915_READ(reg) i915_read(dev_priv, (reg)) | |
1137 | #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val)) | |
3043c60c EA |
1138 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) |
1139 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
1140 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
1141 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 1142 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 1143 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 1144 | #define POSTING_READ(reg) (void)I915_READ(reg) |
7648fa99 | 1145 | #define POSTING_READ16(reg) (void)I915_READ16(reg) |
1da177e4 | 1146 | |
be282fd4 JB |
1147 | #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \ |
1148 | I915_DEBUG_WRITE) | |
1149 | #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \ | |
1150 | I915_DEBUG_WRITE)) | |
1151 | ||
1da177e4 LT |
1152 | #define I915_VERBOSE 0 |
1153 | ||
8187a2b7 | 1154 | #define BEGIN_LP_RING(n) do { \ |
dbd7ac96 | 1155 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
8187a2b7 ZN |
1156 | if (I915_VERBOSE) \ |
1157 | DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ | |
dbd7ac96 | 1158 | intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \ |
1da177e4 LT |
1159 | } while (0) |
1160 | ||
8187a2b7 ZN |
1161 | |
1162 | #define OUT_RING(x) do { \ | |
dbd7ac96 | 1163 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
8187a2b7 ZN |
1164 | if (I915_VERBOSE) \ |
1165 | DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ | |
dbd7ac96 | 1166 | intel_ring_emit(dev, &dev_priv__->render_ring, x); \ |
1da177e4 LT |
1167 | } while (0) |
1168 | ||
1169 | #define ADVANCE_LP_RING() do { \ | |
dbd7ac96 | 1170 | drm_i915_private_t *dev_priv__ = dev->dev_private; \ |
0ef82af7 | 1171 | if (I915_VERBOSE) \ |
8187a2b7 | 1172 | DRM_DEBUG("ADVANCE_LP_RING %x\n", \ |
dbd7ac96 CW |
1173 | dev_priv__->render_ring.tail); \ |
1174 | intel_ring_advance(dev, &dev_priv__->render_ring); \ | |
1da177e4 LT |
1175 | } while(0) |
1176 | ||
ba8bbcf6 | 1177 | /** |
585fb111 JB |
1178 | * Reads a dword out of the status page, which is written to from the command |
1179 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
1180 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 1181 | * |
585fb111 | 1182 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
1183 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
1184 | * 0x04: ring 0 head pointer | |
1185 | * 0x05: ring 1 head pointer (915-class) | |
1186 | * 0x06: ring 2 head pointer (915-class) | |
1187 | * 0x10-0x1b: Context status DWords (GM45) | |
1188 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 1189 | * |
0cdad7e8 | 1190 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 1191 | */ |
8187a2b7 ZN |
1192 | #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ |
1193 | (dev_priv->render_ring.status_page.page_addr))[reg]) | |
0baf823a | 1194 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 1195 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 1196 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 1197 | |
cfdf1fa2 KH |
1198 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1199 | ||
1200 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1201 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
5ce8ba7c | 1202 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
cfdf1fa2 | 1203 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
cfdf1fa2 KH |
1204 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
1205 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1206 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1207 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1208 | #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) | |
1209 | #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) | |
534843da CW |
1210 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
1211 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
cfdf1fa2 KH |
1212 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
1213 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1214 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1215 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1216 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1217 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
f2b115e6 AJ |
1218 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
1219 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
cfdf1fa2 KH |
1220 | #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) |
1221 | #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) | |
1222 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
ba8bbcf6 | 1223 | |
c96c3a8c CW |
1224 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1225 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1226 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1227 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1228 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
bad720ff | 1229 | |
d1b851fc | 1230 | #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) |
cfdf1fa2 | 1231 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
ba8bbcf6 | 1232 | |
31578148 CW |
1233 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
1234 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) | |
1235 | ||
0f973f27 JB |
1236 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1237 | * rows, which changed the alignment requirements and fence programming. | |
1238 | */ | |
1239 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ | |
1240 | IS_I915GM(dev))) | |
f2b115e6 AJ |
1241 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) |
1242 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1243 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1244 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
103a196f | 1245 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ |
7da9f6cb ZW |
1246 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \ |
1247 | !IS_GEN6(dev)) | |
cfdf1fa2 | 1248 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
7662c8bd | 1249 | /* dsparb controlled by hw only */ |
f2b115e6 | 1250 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
b39d50e5 | 1251 | |
f2b115e6 | 1252 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) |
cfdf1fa2 KH |
1253 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1254 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
1255 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) | |
652c393a | 1256 | |
bad720ff EA |
1257 | #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ |
1258 | IS_GEN6(dev)) | |
e552eb70 | 1259 | #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev)) |
bad720ff | 1260 | |
3bad0781 ZW |
1261 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1262 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
1263 | ||
ba8bbcf6 | 1264 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 1265 | |
1da177e4 | 1266 | #endif |