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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
62fdfeaf | 34 | #include "i915_drm.h" |
79e53945 | 35 | #include "intel_bios.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
585fb111 | 37 | |
1da177e4 LT |
38 | /* General customization: |
39 | */ | |
40 | ||
41 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
42 | ||
43 | #define DRIVER_NAME "i915" | |
44 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 45 | #define DRIVER_DATE "20080730" |
1da177e4 | 46 | |
317c35d1 JB |
47 | enum pipe { |
48 | PIPE_A = 0, | |
49 | PIPE_B, | |
50 | }; | |
51 | ||
80824003 JB |
52 | enum plane { |
53 | PLANE_A = 0, | |
54 | PLANE_B, | |
55 | }; | |
56 | ||
52440211 KP |
57 | #define I915_NUM_PIPE 2 |
58 | ||
62fdfeaf EA |
59 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
60 | ||
1da177e4 LT |
61 | /* Interface history: |
62 | * | |
63 | * 1.1: Original. | |
0d6aa60b DA |
64 | * 1.2: Add Power Management |
65 | * 1.3: Add vblank support | |
de227f5f | 66 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 67 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
68 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
69 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
70 | */ |
71 | #define DRIVER_MAJOR 1 | |
2228ed67 | 72 | #define DRIVER_MINOR 6 |
1da177e4 LT |
73 | #define DRIVER_PATCHLEVEL 0 |
74 | ||
673a394b EA |
75 | #define WATCH_COHERENCY 0 |
76 | #define WATCH_BUF 0 | |
77 | #define WATCH_EXEC 0 | |
78 | #define WATCH_LRU 0 | |
79 | #define WATCH_RELOC 0 | |
80 | #define WATCH_INACTIVE 0 | |
81 | #define WATCH_PWRITE 0 | |
82 | ||
71acb5eb DA |
83 | #define I915_GEM_PHYS_CURSOR_0 1 |
84 | #define I915_GEM_PHYS_CURSOR_1 2 | |
85 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
86 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
87 | ||
88 | struct drm_i915_gem_phys_object { | |
89 | int id; | |
90 | struct page **page_list; | |
91 | drm_dma_handle_t *handle; | |
92 | struct drm_gem_object *cur_obj; | |
93 | }; | |
94 | ||
1da177e4 | 95 | typedef struct _drm_i915_ring_buffer { |
1da177e4 LT |
96 | unsigned long Size; |
97 | u8 *virtual_start; | |
98 | int head; | |
99 | int tail; | |
100 | int space; | |
101 | drm_local_map_t map; | |
673a394b | 102 | struct drm_gem_object *ring_obj; |
1da177e4 LT |
103 | } drm_i915_ring_buffer_t; |
104 | ||
105 | struct mem_block { | |
106 | struct mem_block *next; | |
107 | struct mem_block *prev; | |
108 | int start; | |
109 | int size; | |
6c340eac | 110 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
111 | }; |
112 | ||
0a3e67a4 JB |
113 | struct opregion_header; |
114 | struct opregion_acpi; | |
115 | struct opregion_swsci; | |
116 | struct opregion_asle; | |
117 | ||
8ee1c3db MG |
118 | struct intel_opregion { |
119 | struct opregion_header *header; | |
120 | struct opregion_acpi *acpi; | |
121 | struct opregion_swsci *swsci; | |
122 | struct opregion_asle *asle; | |
123 | int enabled; | |
124 | }; | |
125 | ||
7c1c2871 DA |
126 | struct drm_i915_master_private { |
127 | drm_local_map_t *sarea; | |
128 | struct _drm_i915_sarea *sarea_priv; | |
129 | }; | |
de151cf6 JB |
130 | #define I915_FENCE_REG_NONE -1 |
131 | ||
132 | struct drm_i915_fence_reg { | |
133 | struct drm_gem_object *obj; | |
007cc8ac | 134 | struct list_head lru_list; |
de151cf6 | 135 | }; |
7c1c2871 | 136 | |
9b9d172d | 137 | struct sdvo_device_mapping { |
138 | u8 dvo_port; | |
139 | u8 slave_addr; | |
140 | u8 dvo_wiring; | |
141 | u8 initialized; | |
b1083333 | 142 | u8 ddc_pin; |
9b9d172d | 143 | }; |
144 | ||
63eeaf38 JB |
145 | struct drm_i915_error_state { |
146 | u32 eir; | |
147 | u32 pgtbl_er; | |
148 | u32 pipeastat; | |
149 | u32 pipebstat; | |
150 | u32 ipeir; | |
151 | u32 ipehr; | |
152 | u32 instdone; | |
153 | u32 acthd; | |
154 | u32 instpm; | |
155 | u32 instps; | |
156 | u32 instdone1; | |
157 | u32 seqno; | |
9df30794 | 158 | u64 bbaddr; |
63eeaf38 | 159 | struct timeval time; |
9df30794 CW |
160 | struct drm_i915_error_object { |
161 | int page_count; | |
162 | u32 gtt_offset; | |
163 | u32 *pages[0]; | |
164 | } *ringbuffer, *batchbuffer[2]; | |
165 | struct drm_i915_error_buffer { | |
166 | size_t size; | |
167 | u32 name; | |
168 | u32 seqno; | |
169 | u32 gtt_offset; | |
170 | u32 read_domains; | |
171 | u32 write_domain; | |
172 | u32 fence_reg; | |
173 | s32 pinned:2; | |
174 | u32 tiling:2; | |
175 | u32 dirty:1; | |
176 | u32 purgeable:1; | |
177 | } *active_bo; | |
178 | u32 active_bo_count; | |
63eeaf38 JB |
179 | }; |
180 | ||
e70236a8 JB |
181 | struct drm_i915_display_funcs { |
182 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 183 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
184 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
185 | void (*disable_fbc)(struct drm_device *dev); | |
186 | int (*get_display_clock_speed)(struct drm_device *dev); | |
187 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
188 | void (*update_wm)(struct drm_device *dev, int planea_clock, | |
189 | int planeb_clock, int sr_hdisplay, int pixel_size); | |
190 | /* clock updates for mode set */ | |
191 | /* cursor updates */ | |
192 | /* render clock increase/decrease */ | |
193 | /* display clock increase/decrease */ | |
194 | /* pll clock increase/decrease */ | |
195 | /* clock gating init */ | |
196 | }; | |
197 | ||
02e792fb DV |
198 | struct intel_overlay; |
199 | ||
cfdf1fa2 KH |
200 | struct intel_device_info { |
201 | u8 is_mobile : 1; | |
202 | u8 is_i8xx : 1; | |
5ce8ba7c | 203 | u8 is_i85x : 1; |
cfdf1fa2 KH |
204 | u8 is_i915g : 1; |
205 | u8 is_i9xx : 1; | |
206 | u8 is_i945gm : 1; | |
207 | u8 is_i965g : 1; | |
208 | u8 is_i965gm : 1; | |
209 | u8 is_g33 : 1; | |
210 | u8 need_gfx_hws : 1; | |
211 | u8 is_g4x : 1; | |
212 | u8 is_pineview : 1; | |
213 | u8 is_ironlake : 1; | |
59f2d0fc | 214 | u8 is_gen6 : 1; |
cfdf1fa2 KH |
215 | u8 has_fbc : 1; |
216 | u8 has_rc6 : 1; | |
217 | u8 has_pipe_cxsr : 1; | |
218 | u8 has_hotplug : 1; | |
b295d1b6 | 219 | u8 cursor_needs_physical : 1; |
cfdf1fa2 KH |
220 | }; |
221 | ||
b5e50c3f JB |
222 | enum no_fbc_reason { |
223 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ | |
224 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
225 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
226 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
227 | FBC_NOT_TILED, /* buffer not tiled */ | |
228 | }; | |
229 | ||
3bad0781 ZW |
230 | enum intel_pch { |
231 | PCH_IBX, /* Ibexpeak PCH */ | |
232 | PCH_CPT, /* Cougarpoint PCH */ | |
233 | }; | |
234 | ||
8be48d92 | 235 | struct intel_fbdev; |
38651674 | 236 | |
1da177e4 | 237 | typedef struct drm_i915_private { |
673a394b EA |
238 | struct drm_device *dev; |
239 | ||
cfdf1fa2 KH |
240 | const struct intel_device_info *info; |
241 | ||
ac5c4e76 DA |
242 | int has_gem; |
243 | ||
3043c60c | 244 | void __iomem *regs; |
1da177e4 | 245 | |
ec2a4c3f | 246 | struct pci_dev *bridge_dev; |
d3301d86 | 247 | drm_i915_ring_buffer_t render_ring; |
1da177e4 | 248 | |
9c8da5eb | 249 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 250 | void *hw_status_page; |
e552eb70 | 251 | void *seqno_page; |
1da177e4 | 252 | dma_addr_t dma_status_page; |
0a3e67a4 | 253 | uint32_t counter; |
dc7a9319 | 254 | unsigned int status_gfx_addr; |
e552eb70 | 255 | unsigned int seqno_gfx_addr; |
dc7a9319 | 256 | drm_local_map_t hws_map; |
673a394b | 257 | struct drm_gem_object *hws_obj; |
e552eb70 | 258 | struct drm_gem_object *seqno_obj; |
97f5ab66 | 259 | struct drm_gem_object *pwrctx; |
1da177e4 | 260 | |
d7658989 JB |
261 | struct resource mch_res; |
262 | ||
a6b54f3f | 263 | unsigned int cpp; |
1da177e4 LT |
264 | int back_offset; |
265 | int front_offset; | |
266 | int current_page; | |
267 | int page_flipping; | |
1da177e4 LT |
268 | |
269 | wait_queue_head_t irq_queue; | |
270 | atomic_t irq_received; | |
ed4cb414 EA |
271 | /** Protects user_irq_refcount and irq_mask_reg */ |
272 | spinlock_t user_irq_lock; | |
273 | /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ | |
274 | int user_irq_refcount; | |
9d34e5db | 275 | u32 trace_irq_seqno; |
ed4cb414 EA |
276 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
277 | u32 irq_mask_reg; | |
7c463586 | 278 | u32 pipestat[2]; |
f2b115e6 | 279 | /** splitted irq regs for graphics and display engine on Ironlake, |
036a4a7d ZW |
280 | irq_mask_reg is still used for display irq. */ |
281 | u32 gt_irq_mask_reg; | |
282 | u32 gt_irq_enable_reg; | |
283 | u32 de_irq_enable_reg; | |
c650156a ZW |
284 | u32 pch_irq_mask_reg; |
285 | u32 pch_irq_enable_reg; | |
1da177e4 | 286 | |
5ca58282 JB |
287 | u32 hotplug_supported_mask; |
288 | struct work_struct hotplug_work; | |
289 | ||
1da177e4 LT |
290 | int tex_lru_log_granularity; |
291 | int allow_batchbuffer; | |
292 | struct mem_block *agp_heap; | |
0d6aa60b | 293 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 294 | int vblank_pipe; |
a6b54f3f | 295 | |
f65d9421 BG |
296 | /* For hangcheck timer */ |
297 | #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ | |
298 | struct timer_list hangcheck_timer; | |
299 | int hangcheck_count; | |
300 | uint32_t last_acthd; | |
301 | ||
79e53945 JB |
302 | struct drm_mm vram; |
303 | ||
80824003 JB |
304 | unsigned long cfb_size; |
305 | unsigned long cfb_pitch; | |
306 | int cfb_fence; | |
307 | int cfb_plane; | |
308 | ||
79e53945 JB |
309 | int irq_enabled; |
310 | ||
8ee1c3db MG |
311 | struct intel_opregion opregion; |
312 | ||
02e792fb DV |
313 | /* overlay */ |
314 | struct intel_overlay *overlay; | |
315 | ||
79e53945 JB |
316 | /* LVDS info */ |
317 | int backlight_duty_cycle; /* restore backlight to this value */ | |
318 | bool panel_wants_dither; | |
319 | struct drm_display_mode *panel_fixed_mode; | |
88631706 ML |
320 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
321 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
322 | |
323 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
324 | unsigned int int_tv_support:1; |
325 | unsigned int lvds_dither:1; | |
326 | unsigned int lvds_vbt:1; | |
327 | unsigned int int_crt_support:1; | |
43565a06 | 328 | unsigned int lvds_use_ssc:1; |
32f9d658 | 329 | unsigned int edp_support:1; |
43565a06 | 330 | int lvds_ssc_freq; |
500a8cc4 | 331 | int edp_bpp; |
79e53945 | 332 | |
c1c7af60 JB |
333 | struct notifier_block lid_notifier; |
334 | ||
29874f44 | 335 | int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ |
de151cf6 JB |
336 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
337 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
338 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
339 | ||
7662c8bd SL |
340 | unsigned int fsb_freq, mem_freq; |
341 | ||
63eeaf38 JB |
342 | spinlock_t error_lock; |
343 | struct drm_i915_error_state *first_error; | |
8a905236 | 344 | struct work_struct error_work; |
9c9fe1f8 | 345 | struct workqueue_struct *wq; |
63eeaf38 | 346 | |
e70236a8 JB |
347 | /* Display functions */ |
348 | struct drm_i915_display_funcs display; | |
349 | ||
3bad0781 ZW |
350 | /* PCH chipset type */ |
351 | enum intel_pch pch_type; | |
352 | ||
ba8bbcf6 | 353 | /* Register state */ |
c9354c85 | 354 | bool modeset_on_lid; |
ba8bbcf6 JB |
355 | u8 saveLBB; |
356 | u32 saveDSPACNTR; | |
357 | u32 saveDSPBCNTR; | |
e948e994 | 358 | u32 saveDSPARB; |
461cba2d | 359 | u32 saveHWS; |
ba8bbcf6 JB |
360 | u32 savePIPEACONF; |
361 | u32 savePIPEBCONF; | |
362 | u32 savePIPEASRC; | |
363 | u32 savePIPEBSRC; | |
364 | u32 saveFPA0; | |
365 | u32 saveFPA1; | |
366 | u32 saveDPLL_A; | |
367 | u32 saveDPLL_A_MD; | |
368 | u32 saveHTOTAL_A; | |
369 | u32 saveHBLANK_A; | |
370 | u32 saveHSYNC_A; | |
371 | u32 saveVTOTAL_A; | |
372 | u32 saveVBLANK_A; | |
373 | u32 saveVSYNC_A; | |
374 | u32 saveBCLRPAT_A; | |
5586c8bc | 375 | u32 saveTRANSACONF; |
42048781 ZW |
376 | u32 saveTRANS_HTOTAL_A; |
377 | u32 saveTRANS_HBLANK_A; | |
378 | u32 saveTRANS_HSYNC_A; | |
379 | u32 saveTRANS_VTOTAL_A; | |
380 | u32 saveTRANS_VBLANK_A; | |
381 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 382 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
383 | u32 saveDSPASTRIDE; |
384 | u32 saveDSPASIZE; | |
385 | u32 saveDSPAPOS; | |
585fb111 | 386 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
387 | u32 saveDSPASURF; |
388 | u32 saveDSPATILEOFF; | |
389 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 390 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
391 | u32 saveBLC_PWM_CTL; |
392 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
393 | u32 saveBLC_CPU_PWM_CTL; |
394 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
395 | u32 saveFPB0; |
396 | u32 saveFPB1; | |
397 | u32 saveDPLL_B; | |
398 | u32 saveDPLL_B_MD; | |
399 | u32 saveHTOTAL_B; | |
400 | u32 saveHBLANK_B; | |
401 | u32 saveHSYNC_B; | |
402 | u32 saveVTOTAL_B; | |
403 | u32 saveVBLANK_B; | |
404 | u32 saveVSYNC_B; | |
405 | u32 saveBCLRPAT_B; | |
5586c8bc | 406 | u32 saveTRANSBCONF; |
42048781 ZW |
407 | u32 saveTRANS_HTOTAL_B; |
408 | u32 saveTRANS_HBLANK_B; | |
409 | u32 saveTRANS_HSYNC_B; | |
410 | u32 saveTRANS_VTOTAL_B; | |
411 | u32 saveTRANS_VBLANK_B; | |
412 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 413 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
414 | u32 saveDSPBSTRIDE; |
415 | u32 saveDSPBSIZE; | |
416 | u32 saveDSPBPOS; | |
585fb111 | 417 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
418 | u32 saveDSPBSURF; |
419 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
420 | u32 saveVGA0; |
421 | u32 saveVGA1; | |
422 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
423 | u32 saveVGACNTRL; |
424 | u32 saveADPA; | |
425 | u32 saveLVDS; | |
585fb111 JB |
426 | u32 savePP_ON_DELAYS; |
427 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
428 | u32 saveDVOA; |
429 | u32 saveDVOB; | |
430 | u32 saveDVOC; | |
431 | u32 savePP_ON; | |
432 | u32 savePP_OFF; | |
433 | u32 savePP_CONTROL; | |
585fb111 | 434 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
435 | u32 savePFIT_CONTROL; |
436 | u32 save_palette_a[256]; | |
437 | u32 save_palette_b[256]; | |
06027f91 | 438 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
439 | u32 saveFBC_CFB_BASE; |
440 | u32 saveFBC_LL_BASE; | |
441 | u32 saveFBC_CONTROL; | |
442 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
443 | u32 saveIER; |
444 | u32 saveIIR; | |
445 | u32 saveIMR; | |
42048781 ZW |
446 | u32 saveDEIER; |
447 | u32 saveDEIMR; | |
448 | u32 saveGTIER; | |
449 | u32 saveGTIMR; | |
450 | u32 saveFDI_RXA_IMR; | |
451 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 452 | u32 saveCACHE_MODE_0; |
1f84e550 | 453 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
454 | u32 saveSWF0[16]; |
455 | u32 saveSWF1[16]; | |
456 | u32 saveSWF2[3]; | |
457 | u8 saveMSR; | |
458 | u8 saveSR[8]; | |
123f794f | 459 | u8 saveGR[25]; |
ba8bbcf6 | 460 | u8 saveAR_INDEX; |
a59e122a | 461 | u8 saveAR[21]; |
ba8bbcf6 | 462 | u8 saveDACMASK; |
a59e122a | 463 | u8 saveCR[37]; |
79f11c19 | 464 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
465 | u32 saveCURACNTR; |
466 | u32 saveCURAPOS; | |
467 | u32 saveCURABASE; | |
468 | u32 saveCURBCNTR; | |
469 | u32 saveCURBPOS; | |
470 | u32 saveCURBBASE; | |
471 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
472 | u32 saveDP_B; |
473 | u32 saveDP_C; | |
474 | u32 saveDP_D; | |
475 | u32 savePIPEA_GMCH_DATA_M; | |
476 | u32 savePIPEB_GMCH_DATA_M; | |
477 | u32 savePIPEA_GMCH_DATA_N; | |
478 | u32 savePIPEB_GMCH_DATA_N; | |
479 | u32 savePIPEA_DP_LINK_M; | |
480 | u32 savePIPEB_DP_LINK_M; | |
481 | u32 savePIPEA_DP_LINK_N; | |
482 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
483 | u32 saveFDI_RXA_CTL; |
484 | u32 saveFDI_TXA_CTL; | |
485 | u32 saveFDI_RXB_CTL; | |
486 | u32 saveFDI_TXB_CTL; | |
487 | u32 savePFA_CTL_1; | |
488 | u32 savePFB_CTL_1; | |
489 | u32 savePFA_WIN_SZ; | |
490 | u32 savePFB_WIN_SZ; | |
491 | u32 savePFA_WIN_POS; | |
492 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
493 | u32 savePCH_DREF_CONTROL; |
494 | u32 saveDISP_ARB_CTL; | |
495 | u32 savePIPEA_DATA_M1; | |
496 | u32 savePIPEA_DATA_N1; | |
497 | u32 savePIPEA_LINK_M1; | |
498 | u32 savePIPEA_LINK_N1; | |
499 | u32 savePIPEB_DATA_M1; | |
500 | u32 savePIPEB_DATA_N1; | |
501 | u32 savePIPEB_LINK_M1; | |
502 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 503 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
504 | |
505 | struct { | |
506 | struct drm_mm gtt_space; | |
507 | ||
0839ccb8 | 508 | struct io_mapping *gtt_mapping; |
ab657db1 | 509 | int gtt_mtrr; |
0839ccb8 | 510 | |
31169714 CW |
511 | /** |
512 | * Membership on list of all loaded devices, used to evict | |
513 | * inactive buffers under memory pressure. | |
514 | * | |
515 | * Modifications should only be done whilst holding the | |
516 | * shrink_list_lock spinlock. | |
517 | */ | |
518 | struct list_head shrink_list; | |
519 | ||
673a394b EA |
520 | /** |
521 | * List of objects currently involved in rendering from the | |
522 | * ringbuffer. | |
523 | * | |
ce44b0ea EA |
524 | * Includes buffers having the contents of their GPU caches |
525 | * flushed, not necessarily primitives. last_rendering_seqno | |
526 | * represents when the rendering involved will be completed. | |
527 | * | |
673a394b EA |
528 | * A reference is held on the buffer while on this list. |
529 | */ | |
5e118f41 | 530 | spinlock_t active_list_lock; |
673a394b EA |
531 | struct list_head active_list; |
532 | ||
533 | /** | |
534 | * List of objects which are not in the ringbuffer but which | |
535 | * still have a write_domain which needs to be flushed before | |
536 | * unbinding. | |
537 | * | |
ce44b0ea EA |
538 | * last_rendering_seqno is 0 while an object is in this list. |
539 | * | |
673a394b EA |
540 | * A reference is held on the buffer while on this list. |
541 | */ | |
542 | struct list_head flushing_list; | |
543 | ||
99fcb766 DV |
544 | /** |
545 | * List of objects currently pending a GPU write flush. | |
546 | * | |
547 | * All elements on this list will belong to either the | |
548 | * active_list or flushing_list, last_rendering_seqno can | |
549 | * be used to differentiate between the two elements. | |
550 | */ | |
551 | struct list_head gpu_write_list; | |
552 | ||
673a394b EA |
553 | /** |
554 | * LRU list of objects which are not in the ringbuffer and | |
555 | * are ready to unbind, but are still in the GTT. | |
556 | * | |
ce44b0ea EA |
557 | * last_rendering_seqno is 0 while an object is in this list. |
558 | * | |
673a394b EA |
559 | * A reference is not held on the buffer while on this list, |
560 | * as merely being GTT-bound shouldn't prevent its being | |
561 | * freed, and we'll pull it off the list in the free path. | |
562 | */ | |
563 | struct list_head inactive_list; | |
564 | ||
a09ba7fa EA |
565 | /** LRU list of objects with fence regs on them. */ |
566 | struct list_head fence_list; | |
567 | ||
673a394b EA |
568 | /** |
569 | * List of breadcrumbs associated with GPU requests currently | |
570 | * outstanding. | |
571 | */ | |
572 | struct list_head request_list; | |
573 | ||
574 | /** | |
575 | * We leave the user IRQ off as much as possible, | |
576 | * but this means that requests will finish and never | |
577 | * be retired once the system goes idle. Set a timer to | |
578 | * fire periodically while the ring is running. When it | |
579 | * fires, go retire requests. | |
580 | */ | |
581 | struct delayed_work retire_work; | |
582 | ||
583 | uint32_t next_gem_seqno; | |
584 | ||
585 | /** | |
586 | * Waiting sequence number, if any | |
587 | */ | |
588 | uint32_t waiting_gem_seqno; | |
589 | ||
590 | /** | |
591 | * Last seq seen at irq time | |
592 | */ | |
593 | uint32_t irq_gem_seqno; | |
594 | ||
595 | /** | |
596 | * Flag if the X Server, and thus DRM, is not currently in | |
597 | * control of the device. | |
598 | * | |
599 | * This is set between LeaveVT and EnterVT. It needs to be | |
600 | * replaced with a semaphore. It also needs to be | |
601 | * transitioned away from for kernel modesetting. | |
602 | */ | |
603 | int suspended; | |
604 | ||
605 | /** | |
606 | * Flag if the hardware appears to be wedged. | |
607 | * | |
608 | * This is set when attempts to idle the device timeout. | |
609 | * It prevents command submission from occuring and makes | |
610 | * every pending request fail | |
611 | */ | |
ba1234d1 | 612 | atomic_t wedged; |
673a394b EA |
613 | |
614 | /** Bit 6 swizzling required for X tiling */ | |
615 | uint32_t bit_6_swizzle_x; | |
616 | /** Bit 6 swizzling required for Y tiling */ | |
617 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
618 | |
619 | /* storage for physical objects */ | |
620 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
673a394b | 621 | } mm; |
9b9d172d | 622 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
623 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
624 | unsigned int lvds_border_bits; | |
652c393a | 625 | |
6b95a207 KH |
626 | struct drm_crtc *plane_to_crtc_mapping[2]; |
627 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
628 | wait_queue_head_t pending_flip_queue; | |
629 | ||
652c393a JB |
630 | /* Reclocking support */ |
631 | bool render_reclock_avail; | |
632 | bool lvds_downclock_avail; | |
bfac4d67 ZY |
633 | /* indicate whether the LVDS EDID is OK */ |
634 | bool lvds_edid_good; | |
18f9ed12 ZY |
635 | /* indicates the reduced downclock for LVDS*/ |
636 | int lvds_downclock; | |
652c393a JB |
637 | struct work_struct idle_work; |
638 | struct timer_list idle_timer; | |
639 | bool busy; | |
640 | u16 orig_clock; | |
6363ee6f ZY |
641 | int child_dev_num; |
642 | struct child_device_config *child_dev; | |
a2565377 | 643 | struct drm_connector *int_lvds_connector; |
f97108d1 | 644 | |
c4804411 | 645 | bool mchbar_need_disable; |
f97108d1 JB |
646 | |
647 | u8 cur_delay; | |
648 | u8 min_delay; | |
649 | u8 max_delay; | |
b5e50c3f JB |
650 | |
651 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 652 | |
20bf377e JB |
653 | struct drm_mm_node *compressed_fb; |
654 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 655 | |
8be48d92 DA |
656 | /* list of fbdev register on this device */ |
657 | struct intel_fbdev *fbdev; | |
1da177e4 LT |
658 | } drm_i915_private_t; |
659 | ||
673a394b EA |
660 | /** driver private structure attached to each drm_gem_object */ |
661 | struct drm_i915_gem_object { | |
c397b908 | 662 | struct drm_gem_object base; |
673a394b EA |
663 | |
664 | /** Current space allocated to this object in the GTT, if any. */ | |
665 | struct drm_mm_node *gtt_space; | |
666 | ||
667 | /** This object's place on the active/flushing/inactive lists */ | |
668 | struct list_head list; | |
99fcb766 DV |
669 | /** This object's place on GPU write list */ |
670 | struct list_head gpu_write_list; | |
673a394b EA |
671 | |
672 | /** | |
673 | * This is set if the object is on the active or flushing lists | |
674 | * (has pending rendering), and is not set if it's on inactive (ready | |
675 | * to be unbound). | |
676 | */ | |
677 | int active; | |
678 | ||
679 | /** | |
680 | * This is set if the object has been written to since last bound | |
681 | * to the GTT | |
682 | */ | |
683 | int dirty; | |
684 | ||
685 | /** AGP memory structure for our GTT binding. */ | |
686 | DRM_AGP_MEM *agp_mem; | |
687 | ||
856fa198 EA |
688 | struct page **pages; |
689 | int pages_refcount; | |
673a394b EA |
690 | |
691 | /** | |
692 | * Current offset of the object in GTT space. | |
693 | * | |
694 | * This is the same as gtt_space->start | |
695 | */ | |
696 | uint32_t gtt_offset; | |
e67b8ce1 | 697 | |
de151cf6 JB |
698 | /** |
699 | * Fake offset for use by mmap(2) | |
700 | */ | |
701 | uint64_t mmap_offset; | |
702 | ||
703 | /** | |
704 | * Fence register bits (if any) for this object. Will be set | |
705 | * as needed when mapped into the GTT. | |
706 | * Protected by dev->struct_mutex. | |
707 | */ | |
708 | int fence_reg; | |
673a394b | 709 | |
673a394b EA |
710 | /** How many users have pinned this object in GTT space */ |
711 | int pin_count; | |
712 | ||
713 | /** Breadcrumb of last rendering to the buffer. */ | |
714 | uint32_t last_rendering_seqno; | |
715 | ||
716 | /** Current tiling mode for the object. */ | |
717 | uint32_t tiling_mode; | |
de151cf6 | 718 | uint32_t stride; |
673a394b | 719 | |
280b713b EA |
720 | /** Record of address bit 17 of each page at last unbind. */ |
721 | long *bit_17; | |
722 | ||
ba1eb1d8 KP |
723 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
724 | uint32_t agp_type; | |
725 | ||
673a394b | 726 | /** |
e47c68e9 EA |
727 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
728 | * flags which individual pages are valid. | |
673a394b EA |
729 | */ |
730 | uint8_t *page_cpu_valid; | |
79e53945 JB |
731 | |
732 | /** User space pin count and filp owning the pin */ | |
733 | uint32_t user_pin_count; | |
734 | struct drm_file *pin_filp; | |
71acb5eb DA |
735 | |
736 | /** for phy allocated objects */ | |
737 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da KH |
738 | |
739 | /** | |
740 | * Used for checking the object doesn't appear more than once | |
741 | * in an execbuffer object list. | |
742 | */ | |
743 | int in_execbuffer; | |
3ef94daa CW |
744 | |
745 | /** | |
746 | * Advice: are the backing pages purgeable? | |
747 | */ | |
748 | int madv; | |
6b95a207 KH |
749 | |
750 | /** | |
751 | * Number of crtcs where this object is currently the fb, but | |
752 | * will be page flipped away on the next vblank. When it | |
753 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
754 | */ | |
755 | atomic_t pending_flip; | |
673a394b EA |
756 | }; |
757 | ||
62b8b215 | 758 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 759 | |
673a394b EA |
760 | /** |
761 | * Request queue structure. | |
762 | * | |
763 | * The request queue allows us to note sequence numbers that have been emitted | |
764 | * and may be associated with active buffers to be retired. | |
765 | * | |
766 | * By keeping this list, we can avoid having to do questionable | |
767 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
768 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
769 | */ | |
770 | struct drm_i915_gem_request { | |
771 | /** GEM sequence number associated with this request. */ | |
772 | uint32_t seqno; | |
773 | ||
774 | /** Time at which this request was emitted, in jiffies. */ | |
775 | unsigned long emitted_jiffies; | |
776 | ||
b962442e | 777 | /** global list entry for this request */ |
673a394b | 778 | struct list_head list; |
b962442e EA |
779 | |
780 | /** file_priv list entry for this request */ | |
781 | struct list_head client_list; | |
673a394b EA |
782 | }; |
783 | ||
784 | struct drm_i915_file_private { | |
785 | struct { | |
b962442e | 786 | struct list_head request_list; |
673a394b EA |
787 | } mm; |
788 | }; | |
789 | ||
79e53945 JB |
790 | enum intel_chip_family { |
791 | CHIP_I8XX = 0x01, | |
792 | CHIP_I9XX = 0x02, | |
793 | CHIP_I915 = 0x04, | |
794 | CHIP_I965 = 0x08, | |
795 | }; | |
796 | ||
c153f45f | 797 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 798 | extern int i915_max_ioctl; |
79e53945 | 799 | extern unsigned int i915_fbpercrtc; |
652c393a | 800 | extern unsigned int i915_powersave; |
33814341 | 801 | extern unsigned int i915_lvds_downclock; |
b3a83639 | 802 | |
6a9ee8af DA |
803 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
804 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
805 | extern void i915_save_display(struct drm_device *dev); |
806 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
807 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
808 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
809 | ||
1da177e4 | 810 | /* i915_dma.c */ |
84b1fd10 | 811 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 812 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 813 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 814 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 815 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
816 | extern void i915_driver_preclose(struct drm_device *dev, |
817 | struct drm_file *file_priv); | |
673a394b EA |
818 | extern void i915_driver_postclose(struct drm_device *dev, |
819 | struct drm_file *file_priv); | |
84b1fd10 | 820 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
821 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
822 | unsigned long arg); | |
673a394b | 823 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 824 | struct drm_clip_rect *boxes, |
673a394b | 825 | int i, int DR1, int DR4); |
11ed50ec | 826 | extern int i965_reset(struct drm_device *dev, u8 flags); |
af6061af | 827 | |
1da177e4 | 828 | /* i915_irq.c */ |
f65d9421 | 829 | void i915_hangcheck_elapsed(unsigned long data); |
9df30794 | 830 | void i915_destroy_error_state(struct drm_device *dev); |
c153f45f EA |
831 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
832 | struct drm_file *file_priv); | |
833 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
834 | struct drm_file *file_priv); | |
673a394b | 835 | void i915_user_irq_get(struct drm_device *dev); |
9d34e5db | 836 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
673a394b | 837 | void i915_user_irq_put(struct drm_device *dev); |
79e53945 | 838 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
839 | |
840 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 841 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 842 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 843 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
844 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
845 | struct drm_file *file_priv); | |
846 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
847 | struct drm_file *file_priv); | |
0a3e67a4 JB |
848 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
849 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
850 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 851 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
852 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
853 | struct drm_file *file_priv); | |
8ee1c3db | 854 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
62fdfeaf EA |
855 | extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); |
856 | void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask); | |
857 | void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask); | |
1da177e4 | 858 | |
7c463586 KP |
859 | void |
860 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
861 | ||
862 | void | |
863 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
864 | ||
01c66889 ZY |
865 | void intel_enable_asle (struct drm_device *dev); |
866 | ||
7c463586 | 867 | |
1da177e4 | 868 | /* i915_mem.c */ |
c153f45f EA |
869 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
870 | struct drm_file *file_priv); | |
871 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
872 | struct drm_file *file_priv); | |
873 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
874 | struct drm_file *file_priv); | |
875 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
876 | struct drm_file *file_priv); | |
1da177e4 | 877 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 878 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 879 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
880 | /* i915_gem.c */ |
881 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
882 | struct drm_file *file_priv); | |
883 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
884 | struct drm_file *file_priv); | |
885 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
886 | struct drm_file *file_priv); | |
887 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
888 | struct drm_file *file_priv); | |
889 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
890 | struct drm_file *file_priv); | |
de151cf6 JB |
891 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
892 | struct drm_file *file_priv); | |
673a394b EA |
893 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
894 | struct drm_file *file_priv); | |
895 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
896 | struct drm_file *file_priv); | |
897 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
898 | struct drm_file *file_priv); | |
76446cac JB |
899 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
900 | struct drm_file *file_priv); | |
673a394b EA |
901 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
902 | struct drm_file *file_priv); | |
903 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
904 | struct drm_file *file_priv); | |
905 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
906 | struct drm_file *file_priv); | |
907 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
908 | struct drm_file *file_priv); | |
3ef94daa CW |
909 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
910 | struct drm_file *file_priv); | |
673a394b EA |
911 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
912 | struct drm_file *file_priv); | |
913 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
914 | struct drm_file *file_priv); | |
915 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
916 | struct drm_file *file_priv); | |
917 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
918 | struct drm_file *file_priv); | |
5a125c3c EA |
919 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
920 | struct drm_file *file_priv); | |
673a394b | 921 | void i915_gem_load(struct drm_device *dev); |
673a394b | 922 | int i915_gem_init_object(struct drm_gem_object *obj); |
ac52bc56 DV |
923 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
924 | size_t size); | |
673a394b EA |
925 | void i915_gem_free_object(struct drm_gem_object *obj); |
926 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
927 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 928 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 929 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b EA |
930 | void i915_gem_lastclose(struct drm_device *dev); |
931 | uint32_t i915_get_gem_seqno(struct drm_device *dev); | |
22be1724 | 932 | bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); |
8c4b8c3f | 933 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
52dc7d32 | 934 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
673a394b EA |
935 | void i915_gem_retire_requests(struct drm_device *dev); |
936 | void i915_gem_retire_work_handler(struct work_struct *work); | |
937 | void i915_gem_clflush_object(struct drm_gem_object *obj); | |
79e53945 JB |
938 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
939 | uint32_t read_domains, | |
940 | uint32_t write_domain); | |
941 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
942 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
943 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
944 | unsigned long end); | |
5669fcac | 945 | int i915_gem_idle(struct drm_device *dev); |
5a5a0c64 DV |
946 | uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
947 | uint32_t flush_domains); | |
948 | int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible); | |
de151cf6 | 949 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
79e53945 JB |
950 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
951 | int write); | |
b9241ea3 | 952 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); |
71acb5eb DA |
953 | int i915_gem_attach_phys_object(struct drm_device *dev, |
954 | struct drm_gem_object *obj, int id); | |
955 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
956 | struct drm_gem_object *obj); | |
957 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
4bdadb97 | 958 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); |
6911a9b8 | 959 | void i915_gem_object_put_pages(struct drm_gem_object *obj); |
1fd1c624 | 960 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
6b95a207 | 961 | void i915_gem_object_flush_write_domain(struct drm_gem_object *obj); |
673a394b | 962 | |
31169714 CW |
963 | void i915_gem_shrinker_init(void); |
964 | void i915_gem_shrinker_exit(void); | |
62fdfeaf EA |
965 | int i915_gem_init_pipe_control(struct drm_device *dev); |
966 | void i915_gem_cleanup_pipe_control(struct drm_device *dev); | |
31169714 | 967 | |
673a394b EA |
968 | /* i915_gem_tiling.c */ |
969 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
970 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
971 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
76446cac JB |
972 | bool i915_tiling_ok(struct drm_device *dev, int stride, int size, |
973 | int tiling_mode); | |
f590d279 OA |
974 | bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, |
975 | int tiling_mode); | |
673a394b EA |
976 | |
977 | /* i915_gem_debug.c */ | |
978 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
979 | const char *where, uint32_t mark); | |
980 | #if WATCH_INACTIVE | |
981 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
982 | #else | |
983 | #define i915_verify_inactive(dev, file, line) | |
984 | #endif | |
985 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
986 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
987 | const char *where, uint32_t mark); | |
988 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 989 | |
2017263e | 990 | /* i915_debugfs.c */ |
27c202ad BG |
991 | int i915_debugfs_init(struct drm_minor *minor); |
992 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 993 | |
317c35d1 JB |
994 | /* i915_suspend.c */ |
995 | extern int i915_save_state(struct drm_device *dev); | |
996 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
997 | |
998 | /* i915_suspend.c */ | |
999 | extern int i915_save_state(struct drm_device *dev); | |
1000 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1001 | |
65e082c9 | 1002 | #ifdef CONFIG_ACPI |
8ee1c3db | 1003 | /* i915_opregion.c */ |
74a365b3 | 1004 | extern int intel_opregion_init(struct drm_device *dev, int resume); |
3b1c1c11 | 1005 | extern void intel_opregion_free(struct drm_device *dev, int suspend); |
8ee1c3db | 1006 | extern void opregion_asle_intr(struct drm_device *dev); |
01c66889 | 1007 | extern void ironlake_opregion_gse_intr(struct drm_device *dev); |
8ee1c3db | 1008 | extern void opregion_enable_asle(struct drm_device *dev); |
65e082c9 | 1009 | #else |
03ae61dd | 1010 | static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } |
3b1c1c11 | 1011 | static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } |
65e082c9 | 1012 | static inline void opregion_asle_intr(struct drm_device *dev) { return; } |
01c66889 | 1013 | static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; } |
65e082c9 LB |
1014 | static inline void opregion_enable_asle(struct drm_device *dev) { return; } |
1015 | #endif | |
8ee1c3db | 1016 | |
62fdfeaf EA |
1017 | /* intel_ringbuffer.c */ |
1018 | extern void i915_gem_flush(struct drm_device *dev, | |
1019 | uint32_t invalidate_domains, | |
1020 | uint32_t flush_domains); | |
1021 | extern int i915_dispatch_gem_execbuffer(struct drm_device *dev, | |
1022 | struct drm_i915_gem_execbuffer2 *exec, | |
1023 | struct drm_clip_rect *cliprects, | |
1024 | uint64_t exec_offset); | |
1025 | extern uint32_t i915_ring_add_request(struct drm_device *dev); | |
1026 | ||
79e53945 JB |
1027 | /* modesetting */ |
1028 | extern void intel_modeset_init(struct drm_device *dev); | |
1029 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1030 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1031 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1032 | extern void g4x_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1033 | extern void intel_disable_fbc(struct drm_device *dev); |
1034 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1035 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
79e53945 | 1036 | |
3bad0781 | 1037 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1038 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1039 | |
546b0974 EA |
1040 | /** |
1041 | * Lock test for when it's just for synchronization of ring access. | |
1042 | * | |
1043 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1044 | * has access to the ring. | |
1045 | */ | |
1046 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
d3301d86 | 1047 | if (((drm_i915_private_t *)dev->dev_private)->render_ring.ring_obj == NULL) \ |
546b0974 EA |
1048 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
1049 | } while (0) | |
1050 | ||
3043c60c EA |
1051 | #define I915_READ(reg) readl(dev_priv->regs + (reg)) |
1052 | #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) | |
1053 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) | |
1054 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
1055 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
1056 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 1057 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 1058 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 1059 | #define POSTING_READ(reg) (void)I915_READ(reg) |
1da177e4 LT |
1060 | |
1061 | #define I915_VERBOSE 0 | |
1062 | ||
0ef82af7 CW |
1063 | #define RING_LOCALS volatile unsigned int *ring_virt__; |
1064 | ||
1065 | #define BEGIN_LP_RING(n) do { \ | |
1066 | int bytes__ = 4*(n); \ | |
1067 | if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ | |
1068 | /* a wrap must occur between instructions so pad beforehand */ \ | |
d3301d86 | 1069 | if (unlikely (dev_priv->render_ring.tail + bytes__ > dev_priv->render_ring.Size)) \ |
0ef82af7 | 1070 | i915_wrap_ring(dev); \ |
d3301d86 | 1071 | if (unlikely (dev_priv->render_ring.space < bytes__)) \ |
0ef82af7 CW |
1072 | i915_wait_ring(dev, bytes__, __func__); \ |
1073 | ring_virt__ = (unsigned int *) \ | |
d3301d86 EA |
1074 | (dev_priv->render_ring.virtual_start + dev_priv->render_ring.tail); \ |
1075 | dev_priv->render_ring.tail += bytes__; \ | |
1076 | dev_priv->render_ring.tail &= dev_priv->render_ring.Size - 1; \ | |
1077 | dev_priv->render_ring.space -= bytes__; \ | |
1da177e4 LT |
1078 | } while (0) |
1079 | ||
0ef82af7 | 1080 | #define OUT_RING(n) do { \ |
1da177e4 | 1081 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ |
0ef82af7 | 1082 | *ring_virt__++ = (n); \ |
1da177e4 LT |
1083 | } while (0) |
1084 | ||
1085 | #define ADVANCE_LP_RING() do { \ | |
0ef82af7 | 1086 | if (I915_VERBOSE) \ |
d3301d86 EA |
1087 | DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->render_ring.tail); \ |
1088 | I915_WRITE(PRB0_TAIL, dev_priv->render_ring.tail); \ | |
1da177e4 LT |
1089 | } while(0) |
1090 | ||
ba8bbcf6 | 1091 | /** |
585fb111 JB |
1092 | * Reads a dword out of the status page, which is written to from the command |
1093 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
1094 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 1095 | * |
585fb111 | 1096 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
1097 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
1098 | * 0x04: ring 0 head pointer | |
1099 | * 0x05: ring 1 head pointer (915-class) | |
1100 | * 0x06: ring 2 head pointer (915-class) | |
1101 | * 0x10-0x1b: Context status DWords (GM45) | |
1102 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 1103 | * |
0cdad7e8 | 1104 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 1105 | */ |
585fb111 | 1106 | #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) |
0baf823a | 1107 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 1108 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 1109 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 1110 | |
0ef82af7 | 1111 | extern int i915_wrap_ring(struct drm_device * dev); |
585fb111 | 1112 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
ba8bbcf6 | 1113 | |
cfdf1fa2 KH |
1114 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1115 | ||
1116 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1117 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
5ce8ba7c | 1118 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
cfdf1fa2 | 1119 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
bad720ff | 1120 | #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx) |
cfdf1fa2 KH |
1121 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
1122 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1123 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1124 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1125 | #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) | |
1126 | #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) | |
1127 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1128 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1129 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1130 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1131 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1132 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
f2b115e6 AJ |
1133 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
1134 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
cfdf1fa2 KH |
1135 | #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) |
1136 | #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) | |
59f2d0fc | 1137 | #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6) |
cfdf1fa2 | 1138 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ba8bbcf6 | 1139 | |
bad720ff EA |
1140 | #define IS_GEN3(dev) (IS_I915G(dev) || \ |
1141 | IS_I915GM(dev) || \ | |
1142 | IS_I945G(dev) || \ | |
1143 | IS_I945GM(dev) || \ | |
1144 | IS_G33(dev) || \ | |
1145 | IS_PINEVIEW(dev)) | |
1146 | #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \ | |
1147 | (dev)->pci_device == 0x2982 || \ | |
1148 | (dev)->pci_device == 0x2992 || \ | |
1149 | (dev)->pci_device == 0x29A2 || \ | |
1150 | (dev)->pci_device == 0x2A02 || \ | |
1151 | (dev)->pci_device == 0x2A12 || \ | |
1152 | (dev)->pci_device == 0x2E02 || \ | |
1153 | (dev)->pci_device == 0x2E12 || \ | |
1154 | (dev)->pci_device == 0x2E22 || \ | |
1155 | (dev)->pci_device == 0x2E32 || \ | |
1156 | (dev)->pci_device == 0x2A42 || \ | |
1157 | (dev)->pci_device == 0x2E42) | |
1158 | ||
cfdf1fa2 | 1159 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
ba8bbcf6 | 1160 | |
0f973f27 JB |
1161 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1162 | * rows, which changed the alignment requirements and fence programming. | |
1163 | */ | |
1164 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ | |
1165 | IS_I915GM(dev))) | |
f2b115e6 AJ |
1166 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) |
1167 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1168 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1169 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
103a196f | 1170 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ |
7da9f6cb ZW |
1171 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \ |
1172 | !IS_GEN6(dev)) | |
cfdf1fa2 | 1173 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
7662c8bd | 1174 | /* dsparb controlled by hw only */ |
f2b115e6 | 1175 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
b39d50e5 | 1176 | |
f2b115e6 | 1177 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) |
cfdf1fa2 KH |
1178 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1179 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
1180 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) | |
652c393a | 1181 | |
bad720ff EA |
1182 | #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ |
1183 | IS_GEN6(dev)) | |
e552eb70 | 1184 | #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev)) |
bad720ff | 1185 | |
3bad0781 ZW |
1186 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1187 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
1188 | ||
ba8bbcf6 | 1189 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 1190 | |
1da177e4 | 1191 | #endif |