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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
585fb111 | 37 | |
1da177e4 LT |
38 | /* General customization: |
39 | */ | |
40 | ||
41 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
42 | ||
43 | #define DRIVER_NAME "i915" | |
44 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 45 | #define DRIVER_DATE "20080730" |
1da177e4 | 46 | |
317c35d1 JB |
47 | enum pipe { |
48 | PIPE_A = 0, | |
49 | PIPE_B, | |
50 | }; | |
51 | ||
80824003 JB |
52 | enum plane { |
53 | PLANE_A = 0, | |
54 | PLANE_B, | |
55 | }; | |
56 | ||
52440211 KP |
57 | #define I915_NUM_PIPE 2 |
58 | ||
62fdfeaf EA |
59 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
60 | ||
1da177e4 LT |
61 | /* Interface history: |
62 | * | |
63 | * 1.1: Original. | |
0d6aa60b DA |
64 | * 1.2: Add Power Management |
65 | * 1.3: Add vblank support | |
de227f5f | 66 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 67 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
68 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
69 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
70 | */ |
71 | #define DRIVER_MAJOR 1 | |
2228ed67 | 72 | #define DRIVER_MINOR 6 |
1da177e4 LT |
73 | #define DRIVER_PATCHLEVEL 0 |
74 | ||
673a394b EA |
75 | #define WATCH_COHERENCY 0 |
76 | #define WATCH_BUF 0 | |
77 | #define WATCH_EXEC 0 | |
78 | #define WATCH_LRU 0 | |
79 | #define WATCH_RELOC 0 | |
80 | #define WATCH_INACTIVE 0 | |
81 | #define WATCH_PWRITE 0 | |
82 | ||
71acb5eb DA |
83 | #define I915_GEM_PHYS_CURSOR_0 1 |
84 | #define I915_GEM_PHYS_CURSOR_1 2 | |
85 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
86 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
87 | ||
88 | struct drm_i915_gem_phys_object { | |
89 | int id; | |
90 | struct page **page_list; | |
91 | drm_dma_handle_t *handle; | |
92 | struct drm_gem_object *cur_obj; | |
93 | }; | |
94 | ||
1da177e4 LT |
95 | struct mem_block { |
96 | struct mem_block *next; | |
97 | struct mem_block *prev; | |
98 | int start; | |
99 | int size; | |
6c340eac | 100 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
101 | }; |
102 | ||
0a3e67a4 JB |
103 | struct opregion_header; |
104 | struct opregion_acpi; | |
105 | struct opregion_swsci; | |
106 | struct opregion_asle; | |
107 | ||
8ee1c3db MG |
108 | struct intel_opregion { |
109 | struct opregion_header *header; | |
110 | struct opregion_acpi *acpi; | |
111 | struct opregion_swsci *swsci; | |
112 | struct opregion_asle *asle; | |
113 | int enabled; | |
114 | }; | |
115 | ||
7c1c2871 DA |
116 | struct drm_i915_master_private { |
117 | drm_local_map_t *sarea; | |
118 | struct _drm_i915_sarea *sarea_priv; | |
119 | }; | |
de151cf6 JB |
120 | #define I915_FENCE_REG_NONE -1 |
121 | ||
122 | struct drm_i915_fence_reg { | |
123 | struct drm_gem_object *obj; | |
007cc8ac | 124 | struct list_head lru_list; |
de151cf6 | 125 | }; |
7c1c2871 | 126 | |
9b9d172d | 127 | struct sdvo_device_mapping { |
128 | u8 dvo_port; | |
129 | u8 slave_addr; | |
130 | u8 dvo_wiring; | |
131 | u8 initialized; | |
b1083333 | 132 | u8 ddc_pin; |
9b9d172d | 133 | }; |
134 | ||
63eeaf38 JB |
135 | struct drm_i915_error_state { |
136 | u32 eir; | |
137 | u32 pgtbl_er; | |
138 | u32 pipeastat; | |
139 | u32 pipebstat; | |
140 | u32 ipeir; | |
141 | u32 ipehr; | |
142 | u32 instdone; | |
143 | u32 acthd; | |
144 | u32 instpm; | |
145 | u32 instps; | |
146 | u32 instdone1; | |
147 | u32 seqno; | |
9df30794 | 148 | u64 bbaddr; |
63eeaf38 | 149 | struct timeval time; |
9df30794 CW |
150 | struct drm_i915_error_object { |
151 | int page_count; | |
152 | u32 gtt_offset; | |
153 | u32 *pages[0]; | |
154 | } *ringbuffer, *batchbuffer[2]; | |
155 | struct drm_i915_error_buffer { | |
156 | size_t size; | |
157 | u32 name; | |
158 | u32 seqno; | |
159 | u32 gtt_offset; | |
160 | u32 read_domains; | |
161 | u32 write_domain; | |
162 | u32 fence_reg; | |
163 | s32 pinned:2; | |
164 | u32 tiling:2; | |
165 | u32 dirty:1; | |
166 | u32 purgeable:1; | |
167 | } *active_bo; | |
168 | u32 active_bo_count; | |
63eeaf38 JB |
169 | }; |
170 | ||
e70236a8 JB |
171 | struct drm_i915_display_funcs { |
172 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 173 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
174 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
175 | void (*disable_fbc)(struct drm_device *dev); | |
176 | int (*get_display_clock_speed)(struct drm_device *dev); | |
177 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
178 | void (*update_wm)(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
179 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
180 | int pixel_size); | |
e70236a8 JB |
181 | /* clock updates for mode set */ |
182 | /* cursor updates */ | |
183 | /* render clock increase/decrease */ | |
184 | /* display clock increase/decrease */ | |
185 | /* pll clock increase/decrease */ | |
186 | /* clock gating init */ | |
187 | }; | |
188 | ||
02e792fb DV |
189 | struct intel_overlay; |
190 | ||
cfdf1fa2 KH |
191 | struct intel_device_info { |
192 | u8 is_mobile : 1; | |
193 | u8 is_i8xx : 1; | |
5ce8ba7c | 194 | u8 is_i85x : 1; |
cfdf1fa2 KH |
195 | u8 is_i915g : 1; |
196 | u8 is_i9xx : 1; | |
197 | u8 is_i945gm : 1; | |
198 | u8 is_i965g : 1; | |
199 | u8 is_i965gm : 1; | |
200 | u8 is_g33 : 1; | |
201 | u8 need_gfx_hws : 1; | |
202 | u8 is_g4x : 1; | |
203 | u8 is_pineview : 1; | |
534843da CW |
204 | u8 is_broadwater : 1; |
205 | u8 is_crestline : 1; | |
cfdf1fa2 | 206 | u8 is_ironlake : 1; |
59f2d0fc | 207 | u8 is_gen6 : 1; |
cfdf1fa2 KH |
208 | u8 has_fbc : 1; |
209 | u8 has_rc6 : 1; | |
210 | u8 has_pipe_cxsr : 1; | |
211 | u8 has_hotplug : 1; | |
b295d1b6 | 212 | u8 cursor_needs_physical : 1; |
cfdf1fa2 KH |
213 | }; |
214 | ||
b5e50c3f JB |
215 | enum no_fbc_reason { |
216 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ | |
217 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
218 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
219 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
220 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 221 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
b5e50c3f JB |
222 | }; |
223 | ||
3bad0781 ZW |
224 | enum intel_pch { |
225 | PCH_IBX, /* Ibexpeak PCH */ | |
226 | PCH_CPT, /* Cougarpoint PCH */ | |
227 | }; | |
228 | ||
b690e96c JB |
229 | #define QUIRK_PIPEA_FORCE (1<<0) |
230 | ||
8be48d92 | 231 | struct intel_fbdev; |
38651674 | 232 | |
1da177e4 | 233 | typedef struct drm_i915_private { |
673a394b EA |
234 | struct drm_device *dev; |
235 | ||
cfdf1fa2 KH |
236 | const struct intel_device_info *info; |
237 | ||
ac5c4e76 DA |
238 | int has_gem; |
239 | ||
3043c60c | 240 | void __iomem *regs; |
1da177e4 | 241 | |
ec2a4c3f | 242 | struct pci_dev *bridge_dev; |
8187a2b7 | 243 | struct intel_ring_buffer render_ring; |
d1b851fc | 244 | struct intel_ring_buffer bsd_ring; |
1da177e4 | 245 | |
9c8da5eb | 246 | drm_dma_handle_t *status_page_dmah; |
e552eb70 | 247 | void *seqno_page; |
1da177e4 | 248 | dma_addr_t dma_status_page; |
0a3e67a4 | 249 | uint32_t counter; |
e552eb70 | 250 | unsigned int seqno_gfx_addr; |
dc7a9319 | 251 | drm_local_map_t hws_map; |
e552eb70 | 252 | struct drm_gem_object *seqno_obj; |
97f5ab66 | 253 | struct drm_gem_object *pwrctx; |
1da177e4 | 254 | |
d7658989 JB |
255 | struct resource mch_res; |
256 | ||
a6b54f3f | 257 | unsigned int cpp; |
1da177e4 LT |
258 | int back_offset; |
259 | int front_offset; | |
260 | int current_page; | |
261 | int page_flipping; | |
1da177e4 LT |
262 | |
263 | wait_queue_head_t irq_queue; | |
264 | atomic_t irq_received; | |
ed4cb414 EA |
265 | /** Protects user_irq_refcount and irq_mask_reg */ |
266 | spinlock_t user_irq_lock; | |
9d34e5db | 267 | u32 trace_irq_seqno; |
ed4cb414 EA |
268 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
269 | u32 irq_mask_reg; | |
7c463586 | 270 | u32 pipestat[2]; |
f2b115e6 | 271 | /** splitted irq regs for graphics and display engine on Ironlake, |
036a4a7d ZW |
272 | irq_mask_reg is still used for display irq. */ |
273 | u32 gt_irq_mask_reg; | |
274 | u32 gt_irq_enable_reg; | |
275 | u32 de_irq_enable_reg; | |
c650156a ZW |
276 | u32 pch_irq_mask_reg; |
277 | u32 pch_irq_enable_reg; | |
1da177e4 | 278 | |
5ca58282 JB |
279 | u32 hotplug_supported_mask; |
280 | struct work_struct hotplug_work; | |
281 | ||
1da177e4 LT |
282 | int tex_lru_log_granularity; |
283 | int allow_batchbuffer; | |
284 | struct mem_block *agp_heap; | |
0d6aa60b | 285 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 286 | int vblank_pipe; |
a3524f1b | 287 | int num_pipe; |
88f356b7 CW |
288 | u32 flush_rings; |
289 | #define FLUSH_RENDER_RING 0x1 | |
290 | #define FLUSH_BSD_RING 0x2 | |
a6b54f3f | 291 | |
f65d9421 BG |
292 | /* For hangcheck timer */ |
293 | #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ | |
294 | struct timer_list hangcheck_timer; | |
295 | int hangcheck_count; | |
296 | uint32_t last_acthd; | |
cbb465e7 CW |
297 | uint32_t last_instdone; |
298 | uint32_t last_instdone1; | |
f65d9421 | 299 | |
79e53945 JB |
300 | struct drm_mm vram; |
301 | ||
80824003 JB |
302 | unsigned long cfb_size; |
303 | unsigned long cfb_pitch; | |
304 | int cfb_fence; | |
305 | int cfb_plane; | |
306 | ||
79e53945 JB |
307 | int irq_enabled; |
308 | ||
8ee1c3db MG |
309 | struct intel_opregion opregion; |
310 | ||
02e792fb DV |
311 | /* overlay */ |
312 | struct intel_overlay *overlay; | |
313 | ||
79e53945 JB |
314 | /* LVDS info */ |
315 | int backlight_duty_cycle; /* restore backlight to this value */ | |
316 | bool panel_wants_dither; | |
317 | struct drm_display_mode *panel_fixed_mode; | |
88631706 ML |
318 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
319 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
320 | |
321 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
322 | unsigned int int_tv_support:1; |
323 | unsigned int lvds_dither:1; | |
324 | unsigned int lvds_vbt:1; | |
325 | unsigned int int_crt_support:1; | |
43565a06 | 326 | unsigned int lvds_use_ssc:1; |
32f9d658 | 327 | unsigned int edp_support:1; |
43565a06 | 328 | int lvds_ssc_freq; |
500a8cc4 | 329 | int edp_bpp; |
79e53945 | 330 | |
c1c7af60 JB |
331 | struct notifier_block lid_notifier; |
332 | ||
29874f44 | 333 | int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ |
de151cf6 JB |
334 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
335 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
336 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
337 | ||
95534263 | 338 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 339 | |
63eeaf38 JB |
340 | spinlock_t error_lock; |
341 | struct drm_i915_error_state *first_error; | |
8a905236 | 342 | struct work_struct error_work; |
9c9fe1f8 | 343 | struct workqueue_struct *wq; |
63eeaf38 | 344 | |
e70236a8 JB |
345 | /* Display functions */ |
346 | struct drm_i915_display_funcs display; | |
347 | ||
3bad0781 ZW |
348 | /* PCH chipset type */ |
349 | enum intel_pch pch_type; | |
350 | ||
b690e96c JB |
351 | unsigned long quirks; |
352 | ||
ba8bbcf6 | 353 | /* Register state */ |
c9354c85 | 354 | bool modeset_on_lid; |
ba8bbcf6 JB |
355 | u8 saveLBB; |
356 | u32 saveDSPACNTR; | |
357 | u32 saveDSPBCNTR; | |
e948e994 | 358 | u32 saveDSPARB; |
461cba2d | 359 | u32 saveHWS; |
ba8bbcf6 JB |
360 | u32 savePIPEACONF; |
361 | u32 savePIPEBCONF; | |
362 | u32 savePIPEASRC; | |
363 | u32 savePIPEBSRC; | |
364 | u32 saveFPA0; | |
365 | u32 saveFPA1; | |
366 | u32 saveDPLL_A; | |
367 | u32 saveDPLL_A_MD; | |
368 | u32 saveHTOTAL_A; | |
369 | u32 saveHBLANK_A; | |
370 | u32 saveHSYNC_A; | |
371 | u32 saveVTOTAL_A; | |
372 | u32 saveVBLANK_A; | |
373 | u32 saveVSYNC_A; | |
374 | u32 saveBCLRPAT_A; | |
5586c8bc | 375 | u32 saveTRANSACONF; |
42048781 ZW |
376 | u32 saveTRANS_HTOTAL_A; |
377 | u32 saveTRANS_HBLANK_A; | |
378 | u32 saveTRANS_HSYNC_A; | |
379 | u32 saveTRANS_VTOTAL_A; | |
380 | u32 saveTRANS_VBLANK_A; | |
381 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 382 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
383 | u32 saveDSPASTRIDE; |
384 | u32 saveDSPASIZE; | |
385 | u32 saveDSPAPOS; | |
585fb111 | 386 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
387 | u32 saveDSPASURF; |
388 | u32 saveDSPATILEOFF; | |
389 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 390 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
391 | u32 saveBLC_PWM_CTL; |
392 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
393 | u32 saveBLC_CPU_PWM_CTL; |
394 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
395 | u32 saveFPB0; |
396 | u32 saveFPB1; | |
397 | u32 saveDPLL_B; | |
398 | u32 saveDPLL_B_MD; | |
399 | u32 saveHTOTAL_B; | |
400 | u32 saveHBLANK_B; | |
401 | u32 saveHSYNC_B; | |
402 | u32 saveVTOTAL_B; | |
403 | u32 saveVBLANK_B; | |
404 | u32 saveVSYNC_B; | |
405 | u32 saveBCLRPAT_B; | |
5586c8bc | 406 | u32 saveTRANSBCONF; |
42048781 ZW |
407 | u32 saveTRANS_HTOTAL_B; |
408 | u32 saveTRANS_HBLANK_B; | |
409 | u32 saveTRANS_HSYNC_B; | |
410 | u32 saveTRANS_VTOTAL_B; | |
411 | u32 saveTRANS_VBLANK_B; | |
412 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 413 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
414 | u32 saveDSPBSTRIDE; |
415 | u32 saveDSPBSIZE; | |
416 | u32 saveDSPBPOS; | |
585fb111 | 417 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
418 | u32 saveDSPBSURF; |
419 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
420 | u32 saveVGA0; |
421 | u32 saveVGA1; | |
422 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
423 | u32 saveVGACNTRL; |
424 | u32 saveADPA; | |
425 | u32 saveLVDS; | |
585fb111 JB |
426 | u32 savePP_ON_DELAYS; |
427 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
428 | u32 saveDVOA; |
429 | u32 saveDVOB; | |
430 | u32 saveDVOC; | |
431 | u32 savePP_ON; | |
432 | u32 savePP_OFF; | |
433 | u32 savePP_CONTROL; | |
585fb111 | 434 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
435 | u32 savePFIT_CONTROL; |
436 | u32 save_palette_a[256]; | |
437 | u32 save_palette_b[256]; | |
06027f91 | 438 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
439 | u32 saveFBC_CFB_BASE; |
440 | u32 saveFBC_LL_BASE; | |
441 | u32 saveFBC_CONTROL; | |
442 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
443 | u32 saveIER; |
444 | u32 saveIIR; | |
445 | u32 saveIMR; | |
42048781 ZW |
446 | u32 saveDEIER; |
447 | u32 saveDEIMR; | |
448 | u32 saveGTIER; | |
449 | u32 saveGTIMR; | |
450 | u32 saveFDI_RXA_IMR; | |
451 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 452 | u32 saveCACHE_MODE_0; |
1f84e550 | 453 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
454 | u32 saveSWF0[16]; |
455 | u32 saveSWF1[16]; | |
456 | u32 saveSWF2[3]; | |
457 | u8 saveMSR; | |
458 | u8 saveSR[8]; | |
123f794f | 459 | u8 saveGR[25]; |
ba8bbcf6 | 460 | u8 saveAR_INDEX; |
a59e122a | 461 | u8 saveAR[21]; |
ba8bbcf6 | 462 | u8 saveDACMASK; |
a59e122a | 463 | u8 saveCR[37]; |
79f11c19 | 464 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
465 | u32 saveCURACNTR; |
466 | u32 saveCURAPOS; | |
467 | u32 saveCURABASE; | |
468 | u32 saveCURBCNTR; | |
469 | u32 saveCURBPOS; | |
470 | u32 saveCURBBASE; | |
471 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
472 | u32 saveDP_B; |
473 | u32 saveDP_C; | |
474 | u32 saveDP_D; | |
475 | u32 savePIPEA_GMCH_DATA_M; | |
476 | u32 savePIPEB_GMCH_DATA_M; | |
477 | u32 savePIPEA_GMCH_DATA_N; | |
478 | u32 savePIPEB_GMCH_DATA_N; | |
479 | u32 savePIPEA_DP_LINK_M; | |
480 | u32 savePIPEB_DP_LINK_M; | |
481 | u32 savePIPEA_DP_LINK_N; | |
482 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
483 | u32 saveFDI_RXA_CTL; |
484 | u32 saveFDI_TXA_CTL; | |
485 | u32 saveFDI_RXB_CTL; | |
486 | u32 saveFDI_TXB_CTL; | |
487 | u32 savePFA_CTL_1; | |
488 | u32 savePFB_CTL_1; | |
489 | u32 savePFA_WIN_SZ; | |
490 | u32 savePFB_WIN_SZ; | |
491 | u32 savePFA_WIN_POS; | |
492 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
493 | u32 savePCH_DREF_CONTROL; |
494 | u32 saveDISP_ARB_CTL; | |
495 | u32 savePIPEA_DATA_M1; | |
496 | u32 savePIPEA_DATA_N1; | |
497 | u32 savePIPEA_LINK_M1; | |
498 | u32 savePIPEA_LINK_N1; | |
499 | u32 savePIPEB_DATA_M1; | |
500 | u32 savePIPEB_DATA_N1; | |
501 | u32 savePIPEB_LINK_M1; | |
502 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 503 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
504 | |
505 | struct { | |
506 | struct drm_mm gtt_space; | |
507 | ||
0839ccb8 | 508 | struct io_mapping *gtt_mapping; |
ab657db1 | 509 | int gtt_mtrr; |
0839ccb8 | 510 | |
31169714 CW |
511 | /** |
512 | * Membership on list of all loaded devices, used to evict | |
513 | * inactive buffers under memory pressure. | |
514 | * | |
515 | * Modifications should only be done whilst holding the | |
516 | * shrink_list_lock spinlock. | |
517 | */ | |
518 | struct list_head shrink_list; | |
519 | ||
5e118f41 | 520 | spinlock_t active_list_lock; |
673a394b EA |
521 | |
522 | /** | |
523 | * List of objects which are not in the ringbuffer but which | |
524 | * still have a write_domain which needs to be flushed before | |
525 | * unbinding. | |
526 | * | |
ce44b0ea EA |
527 | * last_rendering_seqno is 0 while an object is in this list. |
528 | * | |
673a394b EA |
529 | * A reference is held on the buffer while on this list. |
530 | */ | |
531 | struct list_head flushing_list; | |
532 | ||
99fcb766 DV |
533 | /** |
534 | * List of objects currently pending a GPU write flush. | |
535 | * | |
536 | * All elements on this list will belong to either the | |
537 | * active_list or flushing_list, last_rendering_seqno can | |
538 | * be used to differentiate between the two elements. | |
539 | */ | |
540 | struct list_head gpu_write_list; | |
541 | ||
673a394b EA |
542 | /** |
543 | * LRU list of objects which are not in the ringbuffer and | |
544 | * are ready to unbind, but are still in the GTT. | |
545 | * | |
ce44b0ea EA |
546 | * last_rendering_seqno is 0 while an object is in this list. |
547 | * | |
673a394b EA |
548 | * A reference is not held on the buffer while on this list, |
549 | * as merely being GTT-bound shouldn't prevent its being | |
550 | * freed, and we'll pull it off the list in the free path. | |
551 | */ | |
552 | struct list_head inactive_list; | |
553 | ||
a09ba7fa EA |
554 | /** LRU list of objects with fence regs on them. */ |
555 | struct list_head fence_list; | |
556 | ||
be72615b CW |
557 | /** |
558 | * List of objects currently pending being freed. | |
559 | * | |
560 | * These objects are no longer in use, but due to a signal | |
561 | * we were prevented from freeing them at the appointed time. | |
562 | */ | |
563 | struct list_head deferred_free_list; | |
564 | ||
673a394b EA |
565 | /** |
566 | * We leave the user IRQ off as much as possible, | |
567 | * but this means that requests will finish and never | |
568 | * be retired once the system goes idle. Set a timer to | |
569 | * fire periodically while the ring is running. When it | |
570 | * fires, go retire requests. | |
571 | */ | |
572 | struct delayed_work retire_work; | |
573 | ||
574 | uint32_t next_gem_seqno; | |
575 | ||
576 | /** | |
577 | * Waiting sequence number, if any | |
578 | */ | |
579 | uint32_t waiting_gem_seqno; | |
580 | ||
581 | /** | |
582 | * Last seq seen at irq time | |
583 | */ | |
584 | uint32_t irq_gem_seqno; | |
585 | ||
586 | /** | |
587 | * Flag if the X Server, and thus DRM, is not currently in | |
588 | * control of the device. | |
589 | * | |
590 | * This is set between LeaveVT and EnterVT. It needs to be | |
591 | * replaced with a semaphore. It also needs to be | |
592 | * transitioned away from for kernel modesetting. | |
593 | */ | |
594 | int suspended; | |
595 | ||
596 | /** | |
597 | * Flag if the hardware appears to be wedged. | |
598 | * | |
599 | * This is set when attempts to idle the device timeout. | |
600 | * It prevents command submission from occuring and makes | |
601 | * every pending request fail | |
602 | */ | |
ba1234d1 | 603 | atomic_t wedged; |
673a394b EA |
604 | |
605 | /** Bit 6 swizzling required for X tiling */ | |
606 | uint32_t bit_6_swizzle_x; | |
607 | /** Bit 6 swizzling required for Y tiling */ | |
608 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
609 | |
610 | /* storage for physical objects */ | |
611 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
673a394b | 612 | } mm; |
9b9d172d | 613 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
614 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
615 | unsigned int lvds_border_bits; | |
652c393a | 616 | |
6b95a207 KH |
617 | struct drm_crtc *plane_to_crtc_mapping[2]; |
618 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
619 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 620 | bool flip_pending_is_done; |
6b95a207 | 621 | |
652c393a JB |
622 | /* Reclocking support */ |
623 | bool render_reclock_avail; | |
624 | bool lvds_downclock_avail; | |
bfac4d67 ZY |
625 | /* indicate whether the LVDS EDID is OK */ |
626 | bool lvds_edid_good; | |
18f9ed12 ZY |
627 | /* indicates the reduced downclock for LVDS*/ |
628 | int lvds_downclock; | |
652c393a JB |
629 | struct work_struct idle_work; |
630 | struct timer_list idle_timer; | |
631 | bool busy; | |
632 | u16 orig_clock; | |
6363ee6f ZY |
633 | int child_dev_num; |
634 | struct child_device_config *child_dev; | |
a2565377 | 635 | struct drm_connector *int_lvds_connector; |
f97108d1 | 636 | |
c4804411 | 637 | bool mchbar_need_disable; |
f97108d1 JB |
638 | |
639 | u8 cur_delay; | |
640 | u8 min_delay; | |
641 | u8 max_delay; | |
7648fa99 JB |
642 | u8 fmax; |
643 | u8 fstart; | |
644 | ||
645 | u64 last_count1; | |
646 | unsigned long last_time1; | |
647 | u64 last_count2; | |
648 | struct timespec last_time2; | |
649 | unsigned long gfx_power; | |
650 | int c_m; | |
651 | int r_t; | |
652 | u8 corr; | |
653 | spinlock_t *mchdev_lock; | |
b5e50c3f JB |
654 | |
655 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 656 | |
20bf377e JB |
657 | struct drm_mm_node *compressed_fb; |
658 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 659 | |
8be48d92 DA |
660 | /* list of fbdev register on this device */ |
661 | struct intel_fbdev *fbdev; | |
1da177e4 LT |
662 | } drm_i915_private_t; |
663 | ||
673a394b EA |
664 | /** driver private structure attached to each drm_gem_object */ |
665 | struct drm_i915_gem_object { | |
c397b908 | 666 | struct drm_gem_object base; |
673a394b EA |
667 | |
668 | /** Current space allocated to this object in the GTT, if any. */ | |
669 | struct drm_mm_node *gtt_space; | |
670 | ||
671 | /** This object's place on the active/flushing/inactive lists */ | |
672 | struct list_head list; | |
99fcb766 DV |
673 | /** This object's place on GPU write list */ |
674 | struct list_head gpu_write_list; | |
673a394b EA |
675 | |
676 | /** | |
677 | * This is set if the object is on the active or flushing lists | |
678 | * (has pending rendering), and is not set if it's on inactive (ready | |
679 | * to be unbound). | |
680 | */ | |
778c3544 | 681 | unsigned int active : 1; |
673a394b EA |
682 | |
683 | /** | |
684 | * This is set if the object has been written to since last bound | |
685 | * to the GTT | |
686 | */ | |
778c3544 DV |
687 | unsigned int dirty : 1; |
688 | ||
689 | /** | |
690 | * Fence register bits (if any) for this object. Will be set | |
691 | * as needed when mapped into the GTT. | |
692 | * Protected by dev->struct_mutex. | |
693 | * | |
694 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
695 | */ | |
11824e8c | 696 | signed int fence_reg : 5; |
778c3544 DV |
697 | |
698 | /** | |
699 | * Used for checking the object doesn't appear more than once | |
700 | * in an execbuffer object list. | |
701 | */ | |
702 | unsigned int in_execbuffer : 1; | |
703 | ||
704 | /** | |
705 | * Advice: are the backing pages purgeable? | |
706 | */ | |
707 | unsigned int madv : 2; | |
708 | ||
709 | /** | |
710 | * Refcount for the pages array. With the current locking scheme, there | |
711 | * are at most two concurrent users: Binding a bo to the gtt and | |
712 | * pwrite/pread using physical addresses. So two bits for a maximum | |
713 | * of two users are enough. | |
714 | */ | |
715 | unsigned int pages_refcount : 2; | |
716 | #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3 | |
717 | ||
718 | /** | |
719 | * Current tiling mode for the object. | |
720 | */ | |
721 | unsigned int tiling_mode : 2; | |
722 | ||
723 | /** How many users have pinned this object in GTT space. The following | |
724 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
725 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
726 | * times for the same batchbuffer), and the framebuffer code. When | |
727 | * switching/pageflipping, the framebuffer code has at most two buffers | |
728 | * pinned per crtc. | |
729 | * | |
730 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
731 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 732 | unsigned int pin_count : 4; |
778c3544 | 733 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b EA |
734 | |
735 | /** AGP memory structure for our GTT binding. */ | |
736 | DRM_AGP_MEM *agp_mem; | |
737 | ||
856fa198 | 738 | struct page **pages; |
673a394b EA |
739 | |
740 | /** | |
741 | * Current offset of the object in GTT space. | |
742 | * | |
743 | * This is the same as gtt_space->start | |
744 | */ | |
745 | uint32_t gtt_offset; | |
e67b8ce1 | 746 | |
852835f3 ZN |
747 | /* Which ring is refering to is this object */ |
748 | struct intel_ring_buffer *ring; | |
749 | ||
de151cf6 JB |
750 | /** |
751 | * Fake offset for use by mmap(2) | |
752 | */ | |
753 | uint64_t mmap_offset; | |
754 | ||
673a394b EA |
755 | /** Breadcrumb of last rendering to the buffer. */ |
756 | uint32_t last_rendering_seqno; | |
757 | ||
778c3544 | 758 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 759 | uint32_t stride; |
673a394b | 760 | |
280b713b | 761 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 762 | unsigned long *bit_17; |
280b713b | 763 | |
ba1eb1d8 KP |
764 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
765 | uint32_t agp_type; | |
766 | ||
673a394b | 767 | /** |
e47c68e9 EA |
768 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
769 | * flags which individual pages are valid. | |
673a394b EA |
770 | */ |
771 | uint8_t *page_cpu_valid; | |
79e53945 JB |
772 | |
773 | /** User space pin count and filp owning the pin */ | |
774 | uint32_t user_pin_count; | |
775 | struct drm_file *pin_filp; | |
71acb5eb DA |
776 | |
777 | /** for phy allocated objects */ | |
778 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 779 | |
6b95a207 KH |
780 | /** |
781 | * Number of crtcs where this object is currently the fb, but | |
782 | * will be page flipped away on the next vblank. When it | |
783 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
784 | */ | |
785 | atomic_t pending_flip; | |
673a394b EA |
786 | }; |
787 | ||
62b8b215 | 788 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 789 | |
673a394b EA |
790 | /** |
791 | * Request queue structure. | |
792 | * | |
793 | * The request queue allows us to note sequence numbers that have been emitted | |
794 | * and may be associated with active buffers to be retired. | |
795 | * | |
796 | * By keeping this list, we can avoid having to do questionable | |
797 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
798 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
799 | */ | |
800 | struct drm_i915_gem_request { | |
852835f3 ZN |
801 | /** On Which ring this request was generated */ |
802 | struct intel_ring_buffer *ring; | |
803 | ||
673a394b EA |
804 | /** GEM sequence number associated with this request. */ |
805 | uint32_t seqno; | |
806 | ||
807 | /** Time at which this request was emitted, in jiffies. */ | |
808 | unsigned long emitted_jiffies; | |
809 | ||
b962442e | 810 | /** global list entry for this request */ |
673a394b | 811 | struct list_head list; |
b962442e EA |
812 | |
813 | /** file_priv list entry for this request */ | |
814 | struct list_head client_list; | |
673a394b EA |
815 | }; |
816 | ||
817 | struct drm_i915_file_private { | |
818 | struct { | |
b962442e | 819 | struct list_head request_list; |
673a394b EA |
820 | } mm; |
821 | }; | |
822 | ||
79e53945 JB |
823 | enum intel_chip_family { |
824 | CHIP_I8XX = 0x01, | |
825 | CHIP_I9XX = 0x02, | |
826 | CHIP_I915 = 0x04, | |
827 | CHIP_I965 = 0x08, | |
828 | }; | |
829 | ||
c153f45f | 830 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 831 | extern int i915_max_ioctl; |
79e53945 | 832 | extern unsigned int i915_fbpercrtc; |
652c393a | 833 | extern unsigned int i915_powersave; |
33814341 | 834 | extern unsigned int i915_lvds_downclock; |
b3a83639 | 835 | |
6a9ee8af DA |
836 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
837 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
838 | extern void i915_save_display(struct drm_device *dev); |
839 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
840 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
841 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
842 | ||
1da177e4 | 843 | /* i915_dma.c */ |
84b1fd10 | 844 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 845 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 846 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 847 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 848 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
849 | extern void i915_driver_preclose(struct drm_device *dev, |
850 | struct drm_file *file_priv); | |
673a394b EA |
851 | extern void i915_driver_postclose(struct drm_device *dev, |
852 | struct drm_file *file_priv); | |
84b1fd10 | 853 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
854 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
855 | unsigned long arg); | |
673a394b | 856 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 857 | struct drm_clip_rect *boxes, |
673a394b | 858 | int i, int DR1, int DR4); |
11ed50ec | 859 | extern int i965_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
860 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
861 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
862 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
863 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
864 | ||
af6061af | 865 | |
1da177e4 | 866 | /* i915_irq.c */ |
f65d9421 | 867 | void i915_hangcheck_elapsed(unsigned long data); |
9df30794 | 868 | void i915_destroy_error_state(struct drm_device *dev); |
c153f45f EA |
869 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
870 | struct drm_file *file_priv); | |
871 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
872 | struct drm_file *file_priv); | |
9d34e5db | 873 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
79e53945 | 874 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
875 | |
876 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 877 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 878 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 879 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
880 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
881 | struct drm_file *file_priv); | |
882 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
883 | struct drm_file *file_priv); | |
0a3e67a4 JB |
884 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
885 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
886 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 887 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
888 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
889 | struct drm_file *file_priv); | |
8ee1c3db | 890 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
62fdfeaf | 891 | extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); |
8187a2b7 ZN |
892 | extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, |
893 | u32 mask); | |
894 | extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, | |
895 | u32 mask); | |
1da177e4 | 896 | |
7c463586 KP |
897 | void |
898 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
899 | ||
900 | void | |
901 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
902 | ||
01c66889 ZY |
903 | void intel_enable_asle (struct drm_device *dev); |
904 | ||
7c463586 | 905 | |
1da177e4 | 906 | /* i915_mem.c */ |
c153f45f EA |
907 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
908 | struct drm_file *file_priv); | |
909 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
910 | struct drm_file *file_priv); | |
911 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
912 | struct drm_file *file_priv); | |
913 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
914 | struct drm_file *file_priv); | |
1da177e4 | 915 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 916 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 917 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
918 | /* i915_gem.c */ |
919 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
920 | struct drm_file *file_priv); | |
921 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
922 | struct drm_file *file_priv); | |
923 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
924 | struct drm_file *file_priv); | |
925 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
926 | struct drm_file *file_priv); | |
927 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
928 | struct drm_file *file_priv); | |
de151cf6 JB |
929 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
930 | struct drm_file *file_priv); | |
673a394b EA |
931 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
932 | struct drm_file *file_priv); | |
933 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
934 | struct drm_file *file_priv); | |
935 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
936 | struct drm_file *file_priv); | |
76446cac JB |
937 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
938 | struct drm_file *file_priv); | |
673a394b EA |
939 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
940 | struct drm_file *file_priv); | |
941 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
942 | struct drm_file *file_priv); | |
943 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
944 | struct drm_file *file_priv); | |
945 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
946 | struct drm_file *file_priv); | |
3ef94daa CW |
947 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
948 | struct drm_file *file_priv); | |
673a394b EA |
949 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
950 | struct drm_file *file_priv); | |
951 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
952 | struct drm_file *file_priv); | |
953 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
954 | struct drm_file *file_priv); | |
955 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
956 | struct drm_file *file_priv); | |
5a125c3c EA |
957 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
958 | struct drm_file *file_priv); | |
673a394b | 959 | void i915_gem_load(struct drm_device *dev); |
673a394b | 960 | int i915_gem_init_object(struct drm_gem_object *obj); |
ac52bc56 DV |
961 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
962 | size_t size); | |
673a394b EA |
963 | void i915_gem_free_object(struct drm_gem_object *obj); |
964 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
965 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 966 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 967 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b | 968 | void i915_gem_lastclose(struct drm_device *dev); |
852835f3 ZN |
969 | uint32_t i915_get_gem_seqno(struct drm_device *dev, |
970 | struct intel_ring_buffer *ring); | |
22be1724 | 971 | bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); |
8c4b8c3f | 972 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
52dc7d32 | 973 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
b09a1fec | 974 | void i915_gem_retire_requests(struct drm_device *dev); |
673a394b EA |
975 | void i915_gem_retire_work_handler(struct work_struct *work); |
976 | void i915_gem_clflush_object(struct drm_gem_object *obj); | |
79e53945 JB |
977 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
978 | uint32_t read_domains, | |
979 | uint32_t write_domain); | |
980 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
981 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
982 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
983 | unsigned long end); | |
5669fcac | 984 | int i915_gem_idle(struct drm_device *dev); |
852835f3 ZN |
985 | uint32_t i915_add_request(struct drm_device *dev, |
986 | struct drm_file *file_priv, | |
987 | uint32_t flush_domains, | |
988 | struct intel_ring_buffer *ring); | |
989 | int i915_do_wait_request(struct drm_device *dev, | |
990 | uint32_t seqno, int interruptible, | |
991 | struct intel_ring_buffer *ring); | |
de151cf6 | 992 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
79e53945 JB |
993 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
994 | int write); | |
b9241ea3 | 995 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); |
71acb5eb DA |
996 | int i915_gem_attach_phys_object(struct drm_device *dev, |
997 | struct drm_gem_object *obj, int id); | |
998 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
999 | struct drm_gem_object *obj); | |
1000 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
4bdadb97 | 1001 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); |
6911a9b8 | 1002 | void i915_gem_object_put_pages(struct drm_gem_object *obj); |
1fd1c624 | 1003 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
2dafb1e0 | 1004 | int i915_gem_object_flush_write_domain(struct drm_gem_object *obj); |
673a394b | 1005 | |
31169714 CW |
1006 | void i915_gem_shrinker_init(void); |
1007 | void i915_gem_shrinker_exit(void); | |
1008 | ||
673a394b EA |
1009 | /* i915_gem_tiling.c */ |
1010 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
1011 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
1012 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
76446cac JB |
1013 | bool i915_tiling_ok(struct drm_device *dev, int stride, int size, |
1014 | int tiling_mode); | |
f590d279 OA |
1015 | bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, |
1016 | int tiling_mode); | |
673a394b EA |
1017 | |
1018 | /* i915_gem_debug.c */ | |
1019 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1020 | const char *where, uint32_t mark); | |
1021 | #if WATCH_INACTIVE | |
1022 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
1023 | #else | |
1024 | #define i915_verify_inactive(dev, file, line) | |
1025 | #endif | |
1026 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
1027 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
1028 | const char *where, uint32_t mark); | |
1029 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 1030 | |
2017263e | 1031 | /* i915_debugfs.c */ |
27c202ad BG |
1032 | int i915_debugfs_init(struct drm_minor *minor); |
1033 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1034 | |
317c35d1 JB |
1035 | /* i915_suspend.c */ |
1036 | extern int i915_save_state(struct drm_device *dev); | |
1037 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1038 | |
1039 | /* i915_suspend.c */ | |
1040 | extern int i915_save_state(struct drm_device *dev); | |
1041 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1042 | |
65e082c9 | 1043 | #ifdef CONFIG_ACPI |
8ee1c3db | 1044 | /* i915_opregion.c */ |
74a365b3 | 1045 | extern int intel_opregion_init(struct drm_device *dev, int resume); |
3b1c1c11 | 1046 | extern void intel_opregion_free(struct drm_device *dev, int suspend); |
8ee1c3db | 1047 | extern void opregion_asle_intr(struct drm_device *dev); |
01c66889 | 1048 | extern void ironlake_opregion_gse_intr(struct drm_device *dev); |
8ee1c3db | 1049 | extern void opregion_enable_asle(struct drm_device *dev); |
65e082c9 | 1050 | #else |
03ae61dd | 1051 | static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } |
3b1c1c11 | 1052 | static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } |
65e082c9 | 1053 | static inline void opregion_asle_intr(struct drm_device *dev) { return; } |
01c66889 | 1054 | static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; } |
65e082c9 LB |
1055 | static inline void opregion_enable_asle(struct drm_device *dev) { return; } |
1056 | #endif | |
8ee1c3db | 1057 | |
79e53945 JB |
1058 | /* modesetting */ |
1059 | extern void intel_modeset_init(struct drm_device *dev); | |
1060 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1061 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1062 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1063 | extern void g4x_disable_fbc(struct drm_device *dev); |
b52eb4dc | 1064 | extern void ironlake_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1065 | extern void intel_disable_fbc(struct drm_device *dev); |
1066 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1067 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
7648fa99 | 1068 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
3bad0781 | 1069 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1070 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1071 | |
546b0974 EA |
1072 | /** |
1073 | * Lock test for when it's just for synchronization of ring access. | |
1074 | * | |
1075 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1076 | * has access to the ring. | |
1077 | */ | |
1078 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
8187a2b7 ZN |
1079 | if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ |
1080 | == NULL) \ | |
546b0974 EA |
1081 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
1082 | } while (0) | |
1083 | ||
3043c60c EA |
1084 | #define I915_READ(reg) readl(dev_priv->regs + (reg)) |
1085 | #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) | |
1086 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) | |
1087 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
1088 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
1089 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 1090 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 1091 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 1092 | #define POSTING_READ(reg) (void)I915_READ(reg) |
7648fa99 | 1093 | #define POSTING_READ16(reg) (void)I915_READ16(reg) |
1da177e4 LT |
1094 | |
1095 | #define I915_VERBOSE 0 | |
1096 | ||
8187a2b7 ZN |
1097 | #define BEGIN_LP_RING(n) do { \ |
1098 | drm_i915_private_t *dev_priv = dev->dev_private; \ | |
1099 | if (I915_VERBOSE) \ | |
1100 | DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ | |
be26a10b | 1101 | intel_ring_begin(dev, &dev_priv->render_ring, (n)); \ |
1da177e4 LT |
1102 | } while (0) |
1103 | ||
8187a2b7 ZN |
1104 | |
1105 | #define OUT_RING(x) do { \ | |
1106 | drm_i915_private_t *dev_priv = dev->dev_private; \ | |
1107 | if (I915_VERBOSE) \ | |
1108 | DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ | |
1109 | intel_ring_emit(dev, &dev_priv->render_ring, x); \ | |
1da177e4 LT |
1110 | } while (0) |
1111 | ||
1112 | #define ADVANCE_LP_RING() do { \ | |
8187a2b7 | 1113 | drm_i915_private_t *dev_priv = dev->dev_private; \ |
0ef82af7 | 1114 | if (I915_VERBOSE) \ |
8187a2b7 ZN |
1115 | DRM_DEBUG("ADVANCE_LP_RING %x\n", \ |
1116 | dev_priv->render_ring.tail); \ | |
1117 | intel_ring_advance(dev, &dev_priv->render_ring); \ | |
1da177e4 LT |
1118 | } while(0) |
1119 | ||
ba8bbcf6 | 1120 | /** |
585fb111 JB |
1121 | * Reads a dword out of the status page, which is written to from the command |
1122 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
1123 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 1124 | * |
585fb111 | 1125 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
1126 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
1127 | * 0x04: ring 0 head pointer | |
1128 | * 0x05: ring 1 head pointer (915-class) | |
1129 | * 0x06: ring 2 head pointer (915-class) | |
1130 | * 0x10-0x1b: Context status DWords (GM45) | |
1131 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 1132 | * |
0cdad7e8 | 1133 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 1134 | */ |
8187a2b7 ZN |
1135 | #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ |
1136 | (dev_priv->render_ring.status_page.page_addr))[reg]) | |
0baf823a | 1137 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 1138 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 1139 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 1140 | |
cfdf1fa2 KH |
1141 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1142 | ||
1143 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1144 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
5ce8ba7c | 1145 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
cfdf1fa2 | 1146 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
bad720ff | 1147 | #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx) |
cfdf1fa2 KH |
1148 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
1149 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1150 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1151 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1152 | #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) | |
1153 | #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) | |
534843da CW |
1154 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
1155 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
cfdf1fa2 KH |
1156 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
1157 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1158 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1159 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1160 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1161 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
f2b115e6 AJ |
1162 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
1163 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
cfdf1fa2 KH |
1164 | #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) |
1165 | #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) | |
59f2d0fc | 1166 | #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6) |
cfdf1fa2 | 1167 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ba8bbcf6 | 1168 | |
bad720ff EA |
1169 | #define IS_GEN3(dev) (IS_I915G(dev) || \ |
1170 | IS_I915GM(dev) || \ | |
1171 | IS_I945G(dev) || \ | |
1172 | IS_I945GM(dev) || \ | |
1173 | IS_G33(dev) || \ | |
1174 | IS_PINEVIEW(dev)) | |
1175 | #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \ | |
1176 | (dev)->pci_device == 0x2982 || \ | |
1177 | (dev)->pci_device == 0x2992 || \ | |
1178 | (dev)->pci_device == 0x29A2 || \ | |
1179 | (dev)->pci_device == 0x2A02 || \ | |
1180 | (dev)->pci_device == 0x2A12 || \ | |
1181 | (dev)->pci_device == 0x2E02 || \ | |
1182 | (dev)->pci_device == 0x2E12 || \ | |
1183 | (dev)->pci_device == 0x2E22 || \ | |
1184 | (dev)->pci_device == 0x2E32 || \ | |
1185 | (dev)->pci_device == 0x2A42 || \ | |
1186 | (dev)->pci_device == 0x2E42) | |
1187 | ||
d1b851fc | 1188 | #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) |
cfdf1fa2 | 1189 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
ba8bbcf6 | 1190 | |
0f973f27 JB |
1191 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1192 | * rows, which changed the alignment requirements and fence programming. | |
1193 | */ | |
1194 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ | |
1195 | IS_I915GM(dev))) | |
f2b115e6 AJ |
1196 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) |
1197 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1198 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1199 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
103a196f | 1200 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ |
7da9f6cb ZW |
1201 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \ |
1202 | !IS_GEN6(dev)) | |
cfdf1fa2 | 1203 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
7662c8bd | 1204 | /* dsparb controlled by hw only */ |
f2b115e6 | 1205 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
b39d50e5 | 1206 | |
f2b115e6 | 1207 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) |
cfdf1fa2 KH |
1208 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1209 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
1210 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) | |
652c393a | 1211 | |
bad720ff EA |
1212 | #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ |
1213 | IS_GEN6(dev)) | |
e552eb70 | 1214 | #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev)) |
bad720ff | 1215 | |
3bad0781 ZW |
1216 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
1217 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
1218 | ||
ba8bbcf6 | 1219 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 1220 | |
1da177e4 | 1221 | #endif |