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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
ee0ce478 VS |
33 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
34 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 35 | |
cfa7c862 DV |
36 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
37 | { | |
1893a71b CW |
38 | bool has_aliasing_ppgtt; |
39 | bool has_full_ppgtt; | |
40 | ||
41 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
42 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
43 | if (IS_GEN8(dev)) | |
44 | has_full_ppgtt = false; /* XXX why? */ | |
45 | ||
46 | if (enable_ppgtt == 0 || !has_aliasing_ppgtt) | |
cfa7c862 DV |
47 | return 0; |
48 | ||
49 | if (enable_ppgtt == 1) | |
50 | return 1; | |
51 | ||
1893a71b | 52 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
53 | return 2; |
54 | ||
93a25a9e DV |
55 | #ifdef CONFIG_INTEL_IOMMU |
56 | /* Disable ppgtt on SNB if VT-d is on. */ | |
57 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
58 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 59 | return 0; |
93a25a9e DV |
60 | } |
61 | #endif | |
62 | ||
62942ed7 | 63 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
64 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
65 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
66 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
67 | return 0; | |
68 | } | |
69 | ||
cacc6c83 | 70 | return has_aliasing_ppgtt ? 1 : 0; |
93a25a9e DV |
71 | } |
72 | ||
fbe5d36e | 73 | |
6f65e29a BW |
74 | static void ppgtt_bind_vma(struct i915_vma *vma, |
75 | enum i915_cache_level cache_level, | |
76 | u32 flags); | |
77 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
78 | ||
94ec8f61 BW |
79 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
80 | enum i915_cache_level level, | |
81 | bool valid) | |
82 | { | |
83 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
84 | pte |= addr; | |
63c42e56 BW |
85 | |
86 | switch (level) { | |
87 | case I915_CACHE_NONE: | |
fbe5d36e | 88 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
89 | break; |
90 | case I915_CACHE_WT: | |
91 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
92 | break; | |
93 | default: | |
94 | pte |= PPAT_CACHED_INDEX; | |
95 | break; | |
96 | } | |
97 | ||
94ec8f61 BW |
98 | return pte; |
99 | } | |
100 | ||
b1fe6673 BW |
101 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
102 | dma_addr_t addr, | |
103 | enum i915_cache_level level) | |
104 | { | |
105 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
106 | pde |= addr; | |
107 | if (level != I915_CACHE_NONE) | |
108 | pde |= PPAT_CACHED_PDE_INDEX; | |
109 | else | |
110 | pde |= PPAT_UNCACHED_INDEX; | |
111 | return pde; | |
112 | } | |
113 | ||
350ec881 | 114 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e | 115 | enum i915_cache_level level, |
24f3a8cf | 116 | bool valid, u32 unused) |
54d12527 | 117 | { |
b35b380e | 118 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 119 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
120 | |
121 | switch (level) { | |
350ec881 CW |
122 | case I915_CACHE_L3_LLC: |
123 | case I915_CACHE_LLC: | |
124 | pte |= GEN6_PTE_CACHE_LLC; | |
125 | break; | |
126 | case I915_CACHE_NONE: | |
127 | pte |= GEN6_PTE_UNCACHED; | |
128 | break; | |
129 | default: | |
130 | WARN_ON(1); | |
131 | } | |
132 | ||
133 | return pte; | |
134 | } | |
135 | ||
136 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e | 137 | enum i915_cache_level level, |
24f3a8cf | 138 | bool valid, u32 unused) |
350ec881 | 139 | { |
b35b380e | 140 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
141 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
142 | ||
143 | switch (level) { | |
144 | case I915_CACHE_L3_LLC: | |
145 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
146 | break; |
147 | case I915_CACHE_LLC: | |
148 | pte |= GEN6_PTE_CACHE_LLC; | |
149 | break; | |
150 | case I915_CACHE_NONE: | |
9119708c | 151 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
152 | break; |
153 | default: | |
350ec881 | 154 | WARN_ON(1); |
e7210c3c BW |
155 | } |
156 | ||
54d12527 BW |
157 | return pte; |
158 | } | |
159 | ||
80a74f7f | 160 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e | 161 | enum i915_cache_level level, |
24f3a8cf | 162 | bool valid, u32 flags) |
93c34e70 | 163 | { |
b35b380e | 164 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
165 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
166 | ||
24f3a8cf AG |
167 | if (!(flags & PTE_READ_ONLY)) |
168 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
169 | |
170 | if (level != I915_CACHE_NONE) | |
171 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
172 | ||
173 | return pte; | |
174 | } | |
175 | ||
80a74f7f | 176 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e | 177 | enum i915_cache_level level, |
24f3a8cf | 178 | bool valid, u32 unused) |
9119708c | 179 | { |
b35b380e | 180 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 181 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
182 | |
183 | if (level != I915_CACHE_NONE) | |
87a6b688 | 184 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
185 | |
186 | return pte; | |
187 | } | |
188 | ||
4d15c145 | 189 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e | 190 | enum i915_cache_level level, |
24f3a8cf | 191 | bool valid, u32 unused) |
4d15c145 | 192 | { |
b35b380e | 193 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
194 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
195 | ||
651d794f CW |
196 | switch (level) { |
197 | case I915_CACHE_NONE: | |
198 | break; | |
199 | case I915_CACHE_WT: | |
c51e9701 | 200 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
201 | break; |
202 | default: | |
c51e9701 | 203 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
204 | break; |
205 | } | |
4d15c145 BW |
206 | |
207 | return pte; | |
208 | } | |
209 | ||
94e409c1 | 210 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 211 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
6689c167 | 212 | uint64_t val) |
94e409c1 BW |
213 | { |
214 | int ret; | |
215 | ||
216 | BUG_ON(entry >= 4); | |
217 | ||
218 | ret = intel_ring_begin(ring, 6); | |
219 | if (ret) | |
220 | return ret; | |
221 | ||
222 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
223 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
224 | intel_ring_emit(ring, (u32)(val >> 32)); | |
225 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
226 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
227 | intel_ring_emit(ring, (u32)(val)); | |
228 | intel_ring_advance(ring); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
eeb9488e | 233 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 234 | struct intel_engine_cs *ring) |
94e409c1 | 235 | { |
eeb9488e | 236 | int i, ret; |
94e409c1 BW |
237 | |
238 | /* bit of a hack to find the actual last used pd */ | |
239 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
240 | ||
94e409c1 BW |
241 | for (i = used_pd - 1; i >= 0; i--) { |
242 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
6689c167 | 243 | ret = gen8_write_pdp(ring, i, addr); |
eeb9488e BW |
244 | if (ret) |
245 | return ret; | |
94e409c1 | 246 | } |
d595bd4b | 247 | |
eeb9488e | 248 | return 0; |
94e409c1 BW |
249 | } |
250 | ||
459108b8 | 251 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
252 | uint64_t start, |
253 | uint64_t length, | |
459108b8 BW |
254 | bool use_scratch) |
255 | { | |
256 | struct i915_hw_ppgtt *ppgtt = | |
257 | container_of(vm, struct i915_hw_ppgtt, base); | |
258 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
259 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
260 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
261 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 262 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
263 | unsigned last_pte, i; |
264 | ||
265 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
266 | I915_CACHE_LLC, use_scratch); | |
267 | ||
268 | while (num_entries) { | |
7ad47cf2 | 269 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 270 | |
7ad47cf2 | 271 | last_pte = pte + num_entries; |
459108b8 BW |
272 | if (last_pte > GEN8_PTES_PER_PAGE) |
273 | last_pte = GEN8_PTES_PER_PAGE; | |
274 | ||
275 | pt_vaddr = kmap_atomic(page_table); | |
276 | ||
7ad47cf2 | 277 | for (i = pte; i < last_pte; i++) { |
459108b8 | 278 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
279 | num_entries--; |
280 | } | |
459108b8 | 281 | |
fd1ab8f4 RB |
282 | if (!HAS_LLC(ppgtt->base.dev)) |
283 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
284 | kunmap_atomic(pt_vaddr); |
285 | ||
7ad47cf2 BW |
286 | pte = 0; |
287 | if (++pde == GEN8_PDES_PER_PAGE) { | |
288 | pdpe++; | |
289 | pde = 0; | |
290 | } | |
459108b8 BW |
291 | } |
292 | } | |
293 | ||
9df15b49 BW |
294 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
295 | struct sg_table *pages, | |
782f1495 | 296 | uint64_t start, |
24f3a8cf | 297 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
298 | { |
299 | struct i915_hw_ppgtt *ppgtt = | |
300 | container_of(vm, struct i915_hw_ppgtt, base); | |
301 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
302 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
303 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
304 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
305 | struct sg_page_iter sg_iter; |
306 | ||
6f1cc993 | 307 | pt_vaddr = NULL; |
7ad47cf2 | 308 | |
9df15b49 | 309 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
310 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
311 | break; | |
312 | ||
6f1cc993 | 313 | if (pt_vaddr == NULL) |
7ad47cf2 | 314 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 315 | |
7ad47cf2 | 316 | pt_vaddr[pte] = |
6f1cc993 CW |
317 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
318 | cache_level, true); | |
7ad47cf2 | 319 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
320 | if (!HAS_LLC(ppgtt->base.dev)) |
321 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 322 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 323 | pt_vaddr = NULL; |
7ad47cf2 BW |
324 | if (++pde == GEN8_PDES_PER_PAGE) { |
325 | pdpe++; | |
326 | pde = 0; | |
327 | } | |
328 | pte = 0; | |
9df15b49 BW |
329 | } |
330 | } | |
fd1ab8f4 RB |
331 | if (pt_vaddr) { |
332 | if (!HAS_LLC(ppgtt->base.dev)) | |
333 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 334 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 335 | } |
9df15b49 BW |
336 | } |
337 | ||
7ad47cf2 BW |
338 | static void gen8_free_page_tables(struct page **pt_pages) |
339 | { | |
340 | int i; | |
341 | ||
342 | if (pt_pages == NULL) | |
343 | return; | |
344 | ||
345 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
346 | if (pt_pages[i]) | |
347 | __free_pages(pt_pages[i], 0); | |
348 | } | |
349 | ||
350 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
351 | { |
352 | int i; | |
353 | ||
7ad47cf2 BW |
354 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
355 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
356 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 357 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 358 | } |
b45a6715 | 359 | |
b45a6715 BW |
360 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
361 | } | |
362 | ||
363 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
364 | { | |
f3a964b9 | 365 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
366 | int i, j; |
367 | ||
368 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
369 | /* TODO: In the future we'll support sparse mappings, so this | |
370 | * will have to change. */ | |
371 | if (!ppgtt->pd_dma_addr[i]) | |
372 | continue; | |
373 | ||
f3a964b9 BW |
374 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
375 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
376 | |
377 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
378 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
379 | if (addr) | |
f3a964b9 BW |
380 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
381 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
382 | } |
383 | } | |
384 | } | |
385 | ||
37aca44a BW |
386 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
387 | { | |
388 | struct i915_hw_ppgtt *ppgtt = | |
389 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 390 | |
b45a6715 BW |
391 | gen8_ppgtt_unmap_pages(ppgtt); |
392 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
393 | } |
394 | ||
7ad47cf2 BW |
395 | static struct page **__gen8_alloc_page_tables(void) |
396 | { | |
397 | struct page **pt_pages; | |
398 | int i; | |
399 | ||
400 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
401 | if (!pt_pages) | |
402 | return ERR_PTR(-ENOMEM); | |
403 | ||
404 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
405 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
406 | if (!pt_pages[i]) | |
407 | goto bail; | |
408 | } | |
409 | ||
410 | return pt_pages; | |
411 | ||
412 | bail: | |
413 | gen8_free_page_tables(pt_pages); | |
414 | kfree(pt_pages); | |
415 | return ERR_PTR(-ENOMEM); | |
416 | } | |
417 | ||
bf2b4ed2 BW |
418 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
419 | const int max_pdp) | |
420 | { | |
7ad47cf2 | 421 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 422 | int i, ret; |
bf2b4ed2 | 423 | |
7ad47cf2 BW |
424 | for (i = 0; i < max_pdp; i++) { |
425 | pt_pages[i] = __gen8_alloc_page_tables(); | |
426 | if (IS_ERR(pt_pages[i])) { | |
427 | ret = PTR_ERR(pt_pages[i]); | |
428 | goto unwind_out; | |
429 | } | |
430 | } | |
431 | ||
432 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
433 | * "atomic" - for cleanup purposes. | |
434 | */ | |
435 | for (i = 0; i < max_pdp; i++) | |
436 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 437 | |
bf2b4ed2 | 438 | return 0; |
7ad47cf2 BW |
439 | |
440 | unwind_out: | |
441 | while (i--) { | |
442 | gen8_free_page_tables(pt_pages[i]); | |
443 | kfree(pt_pages[i]); | |
444 | } | |
445 | ||
446 | return ret; | |
bf2b4ed2 BW |
447 | } |
448 | ||
449 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
450 | { | |
451 | int i; | |
452 | ||
453 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
454 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
455 | sizeof(dma_addr_t), | |
456 | GFP_KERNEL); | |
457 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
458 | return -ENOMEM; | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
465 | const int max_pdp) | |
466 | { | |
467 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
468 | if (!ppgtt->pd_pages) | |
469 | return -ENOMEM; | |
470 | ||
471 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
472 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
478 | const int max_pdp) | |
479 | { | |
480 | int ret; | |
481 | ||
482 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
483 | if (ret) | |
484 | return ret; | |
485 | ||
486 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
487 | if (ret) { | |
488 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
489 | return ret; | |
490 | } | |
491 | ||
492 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
493 | ||
494 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
495 | if (ret) | |
496 | gen8_ppgtt_free(ppgtt); | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
502 | const int pd) | |
503 | { | |
504 | dma_addr_t pd_addr; | |
505 | int ret; | |
506 | ||
507 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
508 | &ppgtt->pd_pages[pd], 0, | |
509 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
510 | ||
511 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
512 | if (ret) | |
513 | return ret; | |
514 | ||
515 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
521 | const int pd, | |
522 | const int pt) | |
523 | { | |
524 | dma_addr_t pt_addr; | |
525 | struct page *p; | |
526 | int ret; | |
527 | ||
7ad47cf2 | 528 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
529 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
530 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
531 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
532 | if (ret) | |
533 | return ret; | |
534 | ||
535 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
37aca44a | 540 | /** |
f3a964b9 BW |
541 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
542 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
543 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
544 | * space. | |
37aca44a | 545 | * |
f3a964b9 BW |
546 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
547 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 548 | * TODO: Do something with the size parameter |
f3a964b9 | 549 | */ |
37aca44a BW |
550 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
551 | { | |
37aca44a | 552 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 553 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 554 | int i, j, ret; |
37aca44a BW |
555 | |
556 | if (size % (1<<30)) | |
557 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
558 | ||
bf2b4ed2 BW |
559 | /* 1. Do all our allocations for page directories and page tables. */ |
560 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
561 | if (ret) | |
562 | return ret; | |
f3a964b9 | 563 | |
37aca44a | 564 | /* |
bf2b4ed2 | 565 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
566 | */ |
567 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 568 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
569 | if (ret) |
570 | goto bail; | |
37aca44a | 571 | |
37aca44a | 572 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 573 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
574 | if (ret) |
575 | goto bail; | |
37aca44a BW |
576 | } |
577 | } | |
578 | ||
f3a964b9 BW |
579 | /* |
580 | * 3. Map all the page directory entires to point to the page tables | |
581 | * we've allocated. | |
582 | * | |
583 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 584 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
585 | * will never need to touch the PDEs again. |
586 | */ | |
b1fe6673 BW |
587 | for (i = 0; i < max_pdp; i++) { |
588 | gen8_ppgtt_pde_t *pd_vaddr; | |
589 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
590 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
591 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
592 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
593 | I915_CACHE_LLC); | |
594 | } | |
fd1ab8f4 RB |
595 | if (!HAS_LLC(ppgtt->base.dev)) |
596 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
597 | kunmap_atomic(pd_vaddr); |
598 | } | |
599 | ||
f3a964b9 BW |
600 | ppgtt->switch_mm = gen8_mm_switch; |
601 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
602 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
603 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
604 | ppgtt->base.start = 0; | |
5abbcca3 | 605 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 606 | |
5abbcca3 | 607 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 608 | |
37aca44a BW |
609 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
610 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
611 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
612 | ppgtt->num_pd_entries, |
613 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 614 | return 0; |
37aca44a | 615 | |
f3a964b9 BW |
616 | bail: |
617 | gen8_ppgtt_unmap_pages(ppgtt); | |
618 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
619 | return ret; |
620 | } | |
621 | ||
87d60b63 BW |
622 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
623 | { | |
624 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
625 | struct i915_address_space *vm = &ppgtt->base; | |
626 | gen6_gtt_pte_t __iomem *pd_addr; | |
627 | gen6_gtt_pte_t scratch_pte; | |
628 | uint32_t pd_entry; | |
629 | int pte, pde; | |
630 | ||
24f3a8cf | 631 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 BW |
632 | |
633 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
634 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
635 | ||
636 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
637 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
638 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
639 | u32 expected; | |
640 | gen6_gtt_pte_t *pt_vaddr; | |
641 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
642 | pd_entry = readl(pd_addr + pde); | |
643 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
644 | ||
645 | if (pd_entry != expected) | |
646 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
647 | pde, | |
648 | pd_entry, | |
649 | expected); | |
650 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
651 | ||
652 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
653 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
654 | unsigned long va = | |
655 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
656 | (pte * PAGE_SIZE); | |
657 | int i; | |
658 | bool found = false; | |
659 | for (i = 0; i < 4; i++) | |
660 | if (pt_vaddr[pte + i] != scratch_pte) | |
661 | found = true; | |
662 | if (!found) | |
663 | continue; | |
664 | ||
665 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
666 | for (i = 0; i < 4; i++) { | |
667 | if (pt_vaddr[pte + i] != scratch_pte) | |
668 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
669 | else | |
670 | seq_puts(m, " SCRATCH "); | |
671 | } | |
672 | seq_puts(m, "\n"); | |
673 | } | |
674 | kunmap_atomic(pt_vaddr); | |
675 | } | |
676 | } | |
677 | ||
3e302542 | 678 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 679 | { |
853ba5d2 | 680 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
681 | gen6_gtt_pte_t __iomem *pd_addr; |
682 | uint32_t pd_entry; | |
683 | int i; | |
684 | ||
0a732870 | 685 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
686 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
687 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
688 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
689 | dma_addr_t pt_addr; | |
690 | ||
691 | pt_addr = ppgtt->pt_dma_addr[i]; | |
692 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
693 | pd_entry |= GEN6_PDE_VALID; | |
694 | ||
695 | writel(pd_entry, pd_addr + i); | |
696 | } | |
697 | readl(pd_addr); | |
3e302542 BW |
698 | } |
699 | ||
b4a74e3a | 700 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 701 | { |
b4a74e3a BW |
702 | BUG_ON(ppgtt->pd_offset & 0x3f); |
703 | ||
704 | return (ppgtt->pd_offset / 64) << 16; | |
705 | } | |
706 | ||
90252e5c | 707 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 708 | struct intel_engine_cs *ring) |
90252e5c | 709 | { |
90252e5c BW |
710 | int ret; |
711 | ||
90252e5c BW |
712 | /* NB: TLBs must be flushed and invalidated before a switch */ |
713 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
714 | if (ret) | |
715 | return ret; | |
716 | ||
717 | ret = intel_ring_begin(ring, 6); | |
718 | if (ret) | |
719 | return ret; | |
720 | ||
721 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
722 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
723 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
724 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
725 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
726 | intel_ring_emit(ring, MI_NOOP); | |
727 | intel_ring_advance(ring); | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
48a10389 | 732 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 733 | struct intel_engine_cs *ring) |
48a10389 | 734 | { |
48a10389 BW |
735 | int ret; |
736 | ||
48a10389 BW |
737 | /* NB: TLBs must be flushed and invalidated before a switch */ |
738 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
739 | if (ret) | |
740 | return ret; | |
741 | ||
742 | ret = intel_ring_begin(ring, 6); | |
743 | if (ret) | |
744 | return ret; | |
745 | ||
746 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
747 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
748 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
749 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
750 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
751 | intel_ring_emit(ring, MI_NOOP); | |
752 | intel_ring_advance(ring); | |
753 | ||
90252e5c BW |
754 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
755 | if (ring->id != RCS) { | |
756 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
757 | if (ret) | |
758 | return ret; | |
759 | } | |
760 | ||
48a10389 BW |
761 | return 0; |
762 | } | |
763 | ||
eeb9488e | 764 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 765 | struct intel_engine_cs *ring) |
eeb9488e BW |
766 | { |
767 | struct drm_device *dev = ppgtt->base.dev; | |
768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
769 | ||
48a10389 | 770 | |
eeb9488e BW |
771 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
772 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
773 | ||
774 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
82460d97 | 779 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 780 | { |
eeb9488e | 781 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 782 | struct intel_engine_cs *ring; |
82460d97 | 783 | int j; |
3e302542 | 784 | |
eeb9488e BW |
785 | for_each_ring(ring, dev_priv, j) { |
786 | I915_WRITE(RING_MODE_GEN7(ring), | |
787 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 788 | } |
eeb9488e | 789 | } |
6197349b | 790 | |
82460d97 | 791 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 792 | { |
50227e1c | 793 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 794 | struct intel_engine_cs *ring; |
b4a74e3a | 795 | uint32_t ecochk, ecobits; |
3e302542 | 796 | int i; |
6197349b | 797 | |
b4a74e3a BW |
798 | ecobits = I915_READ(GAC_ECO_BITS); |
799 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 800 | |
b4a74e3a BW |
801 | ecochk = I915_READ(GAM_ECOCHK); |
802 | if (IS_HASWELL(dev)) { | |
803 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
804 | } else { | |
805 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
806 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
807 | } | |
808 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 809 | |
b4a74e3a | 810 | for_each_ring(ring, dev_priv, i) { |
6197349b | 811 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
812 | I915_WRITE(RING_MODE_GEN7(ring), |
813 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 814 | } |
b4a74e3a | 815 | } |
6197349b | 816 | |
82460d97 | 817 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 818 | { |
50227e1c | 819 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 820 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 821 | |
b4a74e3a BW |
822 | ecobits = I915_READ(GAC_ECO_BITS); |
823 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
824 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 825 | |
b4a74e3a BW |
826 | gab_ctl = I915_READ(GAB_CTL); |
827 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
828 | ||
829 | ecochk = I915_READ(GAM_ECOCHK); | |
830 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
831 | ||
832 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
833 | } |
834 | ||
1d2a314c | 835 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 836 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
837 | uint64_t start, |
838 | uint64_t length, | |
828c7908 | 839 | bool use_scratch) |
1d2a314c | 840 | { |
853ba5d2 BW |
841 | struct i915_hw_ppgtt *ppgtt = |
842 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 843 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
844 | unsigned first_entry = start >> PAGE_SHIFT; |
845 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 846 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
847 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
848 | unsigned last_pte, i; | |
1d2a314c | 849 | |
24f3a8cf | 850 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 851 | |
7bddb01f DV |
852 | while (num_entries) { |
853 | last_pte = first_pte + num_entries; | |
854 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
855 | last_pte = I915_PPGTT_PT_ENTRIES; | |
856 | ||
a15326a5 | 857 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 858 | |
7bddb01f DV |
859 | for (i = first_pte; i < last_pte; i++) |
860 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
861 | |
862 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 863 | |
7bddb01f DV |
864 | num_entries -= last_pte - first_pte; |
865 | first_pte = 0; | |
a15326a5 | 866 | act_pt++; |
7bddb01f | 867 | } |
1d2a314c DV |
868 | } |
869 | ||
853ba5d2 | 870 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 871 | struct sg_table *pages, |
782f1495 | 872 | uint64_t start, |
24f3a8cf | 873 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 874 | { |
853ba5d2 BW |
875 | struct i915_hw_ppgtt *ppgtt = |
876 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 877 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 878 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 879 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
880 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
881 | struct sg_page_iter sg_iter; | |
882 | ||
cc79714f | 883 | pt_vaddr = NULL; |
6e995e23 | 884 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
885 | if (pt_vaddr == NULL) |
886 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 887 | |
cc79714f CW |
888 | pt_vaddr[act_pte] = |
889 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
890 | cache_level, true, flags); |
891 | ||
6e995e23 ID |
892 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
893 | kunmap_atomic(pt_vaddr); | |
cc79714f | 894 | pt_vaddr = NULL; |
a15326a5 | 895 | act_pt++; |
6e995e23 | 896 | act_pte = 0; |
def886c3 | 897 | } |
def886c3 | 898 | } |
cc79714f CW |
899 | if (pt_vaddr) |
900 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
901 | } |
902 | ||
a00d825d | 903 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 904 | { |
3440d265 DV |
905 | int i; |
906 | ||
907 | if (ppgtt->pt_dma_addr) { | |
908 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 909 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
910 | ppgtt->pt_dma_addr[i], |
911 | 4096, PCI_DMA_BIDIRECTIONAL); | |
912 | } | |
a00d825d BW |
913 | } |
914 | ||
915 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
916 | { | |
917 | int i; | |
3440d265 DV |
918 | |
919 | kfree(ppgtt->pt_dma_addr); | |
920 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
921 | __free_page(ppgtt->pt_pages[i]); | |
922 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
923 | } |
924 | ||
a00d825d BW |
925 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
926 | { | |
927 | struct i915_hw_ppgtt *ppgtt = | |
928 | container_of(vm, struct i915_hw_ppgtt, base); | |
929 | ||
a00d825d BW |
930 | drm_mm_remove_node(&ppgtt->node); |
931 | ||
932 | gen6_ppgtt_unmap_pages(ppgtt); | |
933 | gen6_ppgtt_free(ppgtt); | |
934 | } | |
935 | ||
b146520f | 936 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 937 | { |
853ba5d2 | 938 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 939 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 940 | bool retried = false; |
b146520f | 941 | int ret; |
1d2a314c | 942 | |
c8d4c0d6 BW |
943 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
944 | * allocator works in address space sizes, so it's multiplied by page | |
945 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
946 | */ | |
947 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 948 | alloc: |
c8d4c0d6 BW |
949 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
950 | &ppgtt->node, GEN6_PD_SIZE, | |
951 | GEN6_PD_ALIGN, 0, | |
952 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 953 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
954 | if (ret == -ENOSPC && !retried) { |
955 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
956 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
957 | I915_CACHE_NONE, |
958 | 0, dev_priv->gtt.base.total, | |
959 | 0); | |
e3cc1995 BW |
960 | if (ret) |
961 | return ret; | |
962 | ||
963 | retried = true; | |
964 | goto alloc; | |
965 | } | |
c8d4c0d6 BW |
966 | |
967 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
968 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 969 | |
6670a5a5 | 970 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
971 | return ret; |
972 | } | |
973 | ||
974 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
975 | { | |
976 | int i; | |
977 | ||
a1e22653 | 978 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 979 | GFP_KERNEL); |
b146520f BW |
980 | |
981 | if (!ppgtt->pt_pages) | |
3440d265 | 982 | return -ENOMEM; |
1d2a314c DV |
983 | |
984 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
985 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
986 | if (!ppgtt->pt_pages[i]) { |
987 | gen6_ppgtt_free(ppgtt); | |
988 | return -ENOMEM; | |
989 | } | |
990 | } | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
995 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
996 | { | |
997 | int ret; | |
998 | ||
999 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1000 | if (ret) | |
1001 | return ret; | |
1002 | ||
1003 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1004 | if (ret) { | |
1005 | drm_mm_remove_node(&ppgtt->node); | |
1006 | return ret; | |
1d2a314c DV |
1007 | } |
1008 | ||
a1e22653 | 1009 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1010 | GFP_KERNEL); |
b146520f BW |
1011 | if (!ppgtt->pt_dma_addr) { |
1012 | drm_mm_remove_node(&ppgtt->node); | |
1013 | gen6_ppgtt_free(ppgtt); | |
1014 | return -ENOMEM; | |
1015 | } | |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
1020 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1021 | { | |
1022 | struct drm_device *dev = ppgtt->base.dev; | |
1023 | int i; | |
1d2a314c | 1024 | |
8d2e6308 BW |
1025 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1026 | dma_addr_t pt_addr; | |
211c568b | 1027 | |
8d2e6308 BW |
1028 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1029 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1030 | |
8d2e6308 | 1031 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1032 | gen6_ppgtt_unmap_pages(ppgtt); |
1033 | return -EIO; | |
211c568b | 1034 | } |
b146520f | 1035 | |
8d2e6308 | 1036 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1037 | } |
1d2a314c | 1038 | |
b146520f BW |
1039 | return 0; |
1040 | } | |
1041 | ||
1042 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1043 | { | |
1044 | struct drm_device *dev = ppgtt->base.dev; | |
1045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1046 | int ret; | |
1047 | ||
1048 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1049 | if (IS_GEN6(dev)) { | |
b146520f BW |
1050 | ppgtt->switch_mm = gen6_mm_switch; |
1051 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1052 | ppgtt->switch_mm = hsw_mm_switch; |
1053 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1054 | ppgtt->switch_mm = gen7_mm_switch; |
1055 | } else | |
1056 | BUG(); | |
1057 | ||
1058 | ret = gen6_ppgtt_alloc(ppgtt); | |
1059 | if (ret) | |
1060 | return ret; | |
1061 | ||
1062 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1063 | if (ret) { | |
1064 | gen6_ppgtt_free(ppgtt); | |
1065 | return ret; | |
1066 | } | |
1067 | ||
1068 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1069 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1070 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1071 | ppgtt->base.start = 0; |
5a6c93fe | 1072 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1073 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1074 | |
c8d4c0d6 BW |
1075 | ppgtt->pd_offset = |
1076 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1077 | |
b146520f | 1078 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1079 | |
b146520f BW |
1080 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1081 | ppgtt->node.size >> 20, | |
1082 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1083 | |
fa76da34 DV |
1084 | gen6_write_pdes(ppgtt); |
1085 | DRM_DEBUG("Adding PPGTT at offset %x\n", | |
1086 | ppgtt->pd_offset << 10); | |
1087 | ||
b146520f | 1088 | return 0; |
3440d265 DV |
1089 | } |
1090 | ||
fa76da34 | 1091 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1092 | { |
1093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1094 | |
853ba5d2 | 1095 | ppgtt->base.dev = dev; |
8407bb91 | 1096 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1097 | |
3ed124b2 | 1098 | if (INTEL_INFO(dev)->gen < 8) |
fa76da34 | 1099 | return gen6_ppgtt_init(ppgtt); |
3fdcf80f | 1100 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
fa76da34 | 1101 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1102 | else |
1103 | BUG(); | |
fa76da34 DV |
1104 | } |
1105 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1106 | { | |
1107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1108 | int ret = 0; | |
3ed124b2 | 1109 | |
fa76da34 DV |
1110 | ret = __hw_ppgtt_init(dev, ppgtt); |
1111 | if (ret == 0) { | |
c7c48dfd | 1112 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1113 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1114 | ppgtt->base.total); | |
7e0d96bc | 1115 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1116 | } |
1d2a314c DV |
1117 | |
1118 | return ret; | |
1119 | } | |
1120 | ||
82460d97 DV |
1121 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1122 | { | |
1123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1124 | struct intel_engine_cs *ring; | |
1125 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1126 | int i, ret = 0; | |
1127 | ||
671b5013 TD |
1128 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1129 | * and the PDPs are contained within the context itself. We don't | |
1130 | * need to do anything here. */ | |
1131 | if (i915.enable_execlists) | |
1132 | return 0; | |
1133 | ||
82460d97 DV |
1134 | if (!USES_PPGTT(dev)) |
1135 | return 0; | |
1136 | ||
1137 | if (IS_GEN6(dev)) | |
1138 | gen6_ppgtt_enable(dev); | |
1139 | else if (IS_GEN7(dev)) | |
1140 | gen7_ppgtt_enable(dev); | |
1141 | else if (INTEL_INFO(dev)->gen >= 8) | |
1142 | gen8_ppgtt_enable(dev); | |
1143 | else | |
1144 | WARN_ON(1); | |
1145 | ||
1146 | if (ppgtt) { | |
1147 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1148 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1149 | if (ret != 0) |
1150 | return ret; | |
7e0d96bc | 1151 | } |
93bd8649 | 1152 | } |
1d2a314c DV |
1153 | |
1154 | return ret; | |
1155 | } | |
4d884705 DV |
1156 | struct i915_hw_ppgtt * |
1157 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1158 | { | |
1159 | struct i915_hw_ppgtt *ppgtt; | |
1160 | int ret; | |
1161 | ||
1162 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1163 | if (!ppgtt) | |
1164 | return ERR_PTR(-ENOMEM); | |
1165 | ||
1166 | ret = i915_ppgtt_init(dev, ppgtt); | |
1167 | if (ret) { | |
1168 | kfree(ppgtt); | |
1169 | return ERR_PTR(ret); | |
1170 | } | |
1171 | ||
1172 | ppgtt->file_priv = fpriv; | |
1173 | ||
198c974d DCS |
1174 | trace_i915_ppgtt_create(&ppgtt->base); |
1175 | ||
4d884705 DV |
1176 | return ppgtt; |
1177 | } | |
1178 | ||
ee960be7 DV |
1179 | void i915_ppgtt_release(struct kref *kref) |
1180 | { | |
1181 | struct i915_hw_ppgtt *ppgtt = | |
1182 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1183 | ||
198c974d DCS |
1184 | trace_i915_ppgtt_release(&ppgtt->base); |
1185 | ||
ee960be7 DV |
1186 | /* vmas should already be unbound */ |
1187 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1188 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1189 | ||
19dd120c DV |
1190 | list_del(&ppgtt->base.global_link); |
1191 | drm_mm_takedown(&ppgtt->base.mm); | |
1192 | ||
ee960be7 DV |
1193 | ppgtt->base.cleanup(&ppgtt->base); |
1194 | kfree(ppgtt); | |
1195 | } | |
1d2a314c | 1196 | |
7e0d96bc | 1197 | static void |
6f65e29a BW |
1198 | ppgtt_bind_vma(struct i915_vma *vma, |
1199 | enum i915_cache_level cache_level, | |
1200 | u32 flags) | |
1d2a314c | 1201 | { |
24f3a8cf AG |
1202 | /* Currently applicable only to VLV */ |
1203 | if (vma->obj->gt_ro) | |
1204 | flags |= PTE_READ_ONLY; | |
1205 | ||
782f1495 | 1206 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1207 | cache_level, flags); |
1d2a314c DV |
1208 | } |
1209 | ||
7e0d96bc | 1210 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1211 | { |
6f65e29a | 1212 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1213 | vma->node.start, |
1214 | vma->obj->base.size, | |
6f65e29a | 1215 | true); |
7bddb01f DV |
1216 | } |
1217 | ||
a81cc00c BW |
1218 | extern int intel_iommu_gfx_mapped; |
1219 | /* Certain Gen5 chipsets require require idling the GPU before | |
1220 | * unmapping anything from the GTT when VT-d is enabled. | |
1221 | */ | |
1222 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1223 | { | |
1224 | #ifdef CONFIG_INTEL_IOMMU | |
1225 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1226 | * was loaded first. | |
1227 | */ | |
1228 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1229 | return true; | |
1230 | #endif | |
1231 | return false; | |
1232 | } | |
1233 | ||
5c042287 BW |
1234 | static bool do_idling(struct drm_i915_private *dev_priv) |
1235 | { | |
1236 | bool ret = dev_priv->mm.interruptible; | |
1237 | ||
a81cc00c | 1238 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1239 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1240 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1241 | DRM_ERROR("Couldn't idle GPU\n"); |
1242 | /* Wait a bit, in hopes it avoids the hang */ | |
1243 | udelay(10); | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | return ret; | |
1248 | } | |
1249 | ||
1250 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1251 | { | |
a81cc00c | 1252 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1253 | dev_priv->mm.interruptible = interruptible; |
1254 | } | |
1255 | ||
828c7908 BW |
1256 | void i915_check_and_clear_faults(struct drm_device *dev) |
1257 | { | |
1258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1259 | struct intel_engine_cs *ring; |
828c7908 BW |
1260 | int i; |
1261 | ||
1262 | if (INTEL_INFO(dev)->gen < 6) | |
1263 | return; | |
1264 | ||
1265 | for_each_ring(ring, dev_priv, i) { | |
1266 | u32 fault_reg; | |
1267 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1268 | if (fault_reg & RING_FAULT_VALID) { | |
1269 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1270 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1271 | "\tAddress space: %s\n" |
1272 | "\tSource ID: %d\n" | |
1273 | "\tType: %d\n", | |
1274 | fault_reg & PAGE_MASK, | |
1275 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1276 | RING_FAULT_SRCID(fault_reg), | |
1277 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1278 | I915_WRITE(RING_FAULT_REG(ring), | |
1279 | fault_reg & ~RING_FAULT_VALID); | |
1280 | } | |
1281 | } | |
1282 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1283 | } | |
1284 | ||
91e56499 CW |
1285 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1286 | { | |
1287 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1288 | intel_gtt_chipset_flush(); | |
1289 | } else { | |
1290 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1291 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1292 | } | |
1293 | } | |
1294 | ||
828c7908 BW |
1295 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1296 | { | |
1297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1298 | ||
1299 | /* Don't bother messing with faults pre GEN6 as we have little | |
1300 | * documentation supporting that it's a good idea. | |
1301 | */ | |
1302 | if (INTEL_INFO(dev)->gen < 6) | |
1303 | return; | |
1304 | ||
1305 | i915_check_and_clear_faults(dev); | |
1306 | ||
1307 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1308 | dev_priv->gtt.base.start, |
1309 | dev_priv->gtt.base.total, | |
e568af1c | 1310 | true); |
91e56499 CW |
1311 | |
1312 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1313 | } |
1314 | ||
76aaf220 DV |
1315 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1316 | { | |
1317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1318 | struct drm_i915_gem_object *obj; |
80da2161 | 1319 | struct i915_address_space *vm; |
76aaf220 | 1320 | |
828c7908 BW |
1321 | i915_check_and_clear_faults(dev); |
1322 | ||
bee4a186 | 1323 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1324 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1325 | dev_priv->gtt.base.start, |
1326 | dev_priv->gtt.base.total, | |
828c7908 | 1327 | true); |
bee4a186 | 1328 | |
35c20a60 | 1329 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1330 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1331 | &dev_priv->gtt.base); | |
1332 | if (!vma) | |
1333 | continue; | |
1334 | ||
2c22569b | 1335 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1336 | /* The bind_vma code tries to be smart about tracking mappings. |
1337 | * Unfortunately above, we've just wiped out the mappings | |
1338 | * without telling our object about it. So we need to fake it. | |
1339 | */ | |
aff43766 | 1340 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1341 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
76aaf220 DV |
1342 | } |
1343 | ||
80da2161 | 1344 | |
a2319c08 | 1345 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1346 | if (IS_CHERRYVIEW(dev)) |
1347 | chv_setup_private_ppat(dev_priv); | |
1348 | else | |
1349 | bdw_setup_private_ppat(dev_priv); | |
1350 | ||
80da2161 | 1351 | return; |
a2319c08 | 1352 | } |
80da2161 BW |
1353 | |
1354 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1355 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1356 | if (i915_is_ggtt(vm)) { | |
1357 | if (dev_priv->mm.aliasing_ppgtt) | |
1358 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1359 | continue; | |
1360 | } | |
1361 | ||
1362 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1363 | } |
1364 | ||
91e56499 | 1365 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1366 | } |
7c2e6fdf | 1367 | |
74163907 | 1368 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1369 | { |
9da3da66 | 1370 | if (obj->has_dma_mapping) |
74163907 | 1371 | return 0; |
9da3da66 CW |
1372 | |
1373 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1374 | obj->pages->sgl, obj->pages->nents, | |
1375 | PCI_DMA_BIDIRECTIONAL)) | |
1376 | return -ENOSPC; | |
1377 | ||
1378 | return 0; | |
7c2e6fdf DV |
1379 | } |
1380 | ||
94ec8f61 BW |
1381 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1382 | { | |
1383 | #ifdef writeq | |
1384 | writeq(pte, addr); | |
1385 | #else | |
1386 | iowrite32((u32)pte, addr); | |
1387 | iowrite32(pte >> 32, addr + 4); | |
1388 | #endif | |
1389 | } | |
1390 | ||
1391 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1392 | struct sg_table *st, | |
782f1495 | 1393 | uint64_t start, |
24f3a8cf | 1394 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1395 | { |
1396 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1397 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1398 | gen8_gtt_pte_t __iomem *gtt_entries = |
1399 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1400 | int i = 0; | |
1401 | struct sg_page_iter sg_iter; | |
57007df7 | 1402 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1403 | |
1404 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1405 | addr = sg_dma_address(sg_iter.sg) + | |
1406 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1407 | gen8_set_pte(>t_entries[i], | |
1408 | gen8_pte_encode(addr, level, true)); | |
1409 | i++; | |
1410 | } | |
1411 | ||
1412 | /* | |
1413 | * XXX: This serves as a posting read to make sure that the PTE has | |
1414 | * actually been updated. There is some concern that even though | |
1415 | * registers and PTEs are within the same BAR that they are potentially | |
1416 | * of NUMA access patterns. Therefore, even with the way we assume | |
1417 | * hardware should work, we must keep this posting read for paranoia. | |
1418 | */ | |
1419 | if (i != 0) | |
1420 | WARN_ON(readq(>t_entries[i-1]) | |
1421 | != gen8_pte_encode(addr, level, true)); | |
1422 | ||
94ec8f61 BW |
1423 | /* This next bit makes the above posting read even more important. We |
1424 | * want to flush the TLBs only after we're certain all the PTE updates | |
1425 | * have finished. | |
1426 | */ | |
1427 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1428 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1429 | } |
1430 | ||
e76e9aeb BW |
1431 | /* |
1432 | * Binds an object into the global gtt with the specified cache level. The object | |
1433 | * will be accessible to the GPU via commands whose operands reference offsets | |
1434 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1435 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1436 | */ | |
853ba5d2 | 1437 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1438 | struct sg_table *st, |
782f1495 | 1439 | uint64_t start, |
24f3a8cf | 1440 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1441 | { |
853ba5d2 | 1442 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1443 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1444 | gen6_gtt_pte_t __iomem *gtt_entries = |
1445 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1446 | int i = 0; |
1447 | struct sg_page_iter sg_iter; | |
57007df7 | 1448 | dma_addr_t addr = 0; |
e76e9aeb | 1449 | |
6e995e23 | 1450 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1451 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1452 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1453 | i++; |
e76e9aeb BW |
1454 | } |
1455 | ||
e76e9aeb BW |
1456 | /* XXX: This serves as a posting read to make sure that the PTE has |
1457 | * actually been updated. There is some concern that even though | |
1458 | * registers and PTEs are within the same BAR that they are potentially | |
1459 | * of NUMA access patterns. Therefore, even with the way we assume | |
1460 | * hardware should work, we must keep this posting read for paranoia. | |
1461 | */ | |
57007df7 PM |
1462 | if (i != 0) { |
1463 | unsigned long gtt = readl(>t_entries[i-1]); | |
1464 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1465 | } | |
0f9b91c7 BW |
1466 | |
1467 | /* This next bit makes the above posting read even more important. We | |
1468 | * want to flush the TLBs only after we're certain all the PTE updates | |
1469 | * have finished. | |
1470 | */ | |
1471 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1472 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1473 | } |
1474 | ||
94ec8f61 | 1475 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1476 | uint64_t start, |
1477 | uint64_t length, | |
94ec8f61 BW |
1478 | bool use_scratch) |
1479 | { | |
1480 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1481 | unsigned first_entry = start >> PAGE_SHIFT; |
1482 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1483 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1484 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1485 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1486 | int i; | |
1487 | ||
1488 | if (WARN(num_entries > max_entries, | |
1489 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1490 | first_entry, num_entries, max_entries)) | |
1491 | num_entries = max_entries; | |
1492 | ||
1493 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1494 | I915_CACHE_LLC, | |
1495 | use_scratch); | |
1496 | for (i = 0; i < num_entries; i++) | |
1497 | gen8_set_pte(>t_base[i], scratch_pte); | |
1498 | readl(gtt_base); | |
1499 | } | |
1500 | ||
853ba5d2 | 1501 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1502 | uint64_t start, |
1503 | uint64_t length, | |
828c7908 | 1504 | bool use_scratch) |
7faf1ab2 | 1505 | { |
853ba5d2 | 1506 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1507 | unsigned first_entry = start >> PAGE_SHIFT; |
1508 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1509 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1510 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1511 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1512 | int i; |
1513 | ||
1514 | if (WARN(num_entries > max_entries, | |
1515 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1516 | first_entry, num_entries, max_entries)) | |
1517 | num_entries = max_entries; | |
1518 | ||
24f3a8cf | 1519 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1520 | |
7faf1ab2 DV |
1521 | for (i = 0; i < num_entries; i++) |
1522 | iowrite32(scratch_pte, >t_base[i]); | |
1523 | readl(gtt_base); | |
1524 | } | |
1525 | ||
6f65e29a BW |
1526 | |
1527 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1528 | enum i915_cache_level cache_level, | |
1529 | u32 unused) | |
7faf1ab2 | 1530 | { |
6f65e29a | 1531 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1532 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1533 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1534 | ||
6f65e29a BW |
1535 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1536 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
aff43766 | 1537 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1538 | } |
1539 | ||
853ba5d2 | 1540 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1541 | uint64_t start, |
1542 | uint64_t length, | |
828c7908 | 1543 | bool unused) |
7faf1ab2 | 1544 | { |
782f1495 BW |
1545 | unsigned first_entry = start >> PAGE_SHIFT; |
1546 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1547 | intel_gtt_clear_range(first_entry, num_entries); |
1548 | } | |
1549 | ||
6f65e29a BW |
1550 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1551 | { | |
1552 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1553 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1554 | |
6f65e29a | 1555 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1556 | vma->bound = 0; |
6f65e29a BW |
1557 | intel_gtt_clear_range(first, size); |
1558 | } | |
7faf1ab2 | 1559 | |
6f65e29a BW |
1560 | static void ggtt_bind_vma(struct i915_vma *vma, |
1561 | enum i915_cache_level cache_level, | |
1562 | u32 flags) | |
d5bd1449 | 1563 | { |
6f65e29a | 1564 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1565 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1566 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1567 | |
24f3a8cf AG |
1568 | /* Currently applicable only to VLV */ |
1569 | if (obj->gt_ro) | |
1570 | flags |= PTE_READ_ONLY; | |
1571 | ||
6f65e29a BW |
1572 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1573 | * or we have a global mapping already but the cacheability flags have | |
1574 | * changed, set the global PTEs. | |
1575 | * | |
1576 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1577 | * instead if none of the above hold true. | |
1578 | * | |
1579 | * NB: A global mapping should only be needed for special regions like | |
1580 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1581 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1582 | */ | |
1583 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 1584 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 1585 | (cache_level != obj->cache_level)) { |
782f1495 BW |
1586 | vma->vm->insert_entries(vma->vm, obj->pages, |
1587 | vma->node.start, | |
24f3a8cf | 1588 | cache_level, flags); |
aff43766 | 1589 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
1590 | } |
1591 | } | |
d5bd1449 | 1592 | |
6f65e29a | 1593 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 1594 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
1595 | (cache_level != obj->cache_level))) { |
1596 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1597 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1598 | vma->obj->pages, |
1599 | vma->node.start, | |
24f3a8cf | 1600 | cache_level, flags); |
aff43766 | 1601 | vma->bound |= LOCAL_BIND; |
6f65e29a | 1602 | } |
d5bd1449 CW |
1603 | } |
1604 | ||
6f65e29a | 1605 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1606 | { |
6f65e29a | 1607 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1608 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1609 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1610 | |
aff43766 | 1611 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1612 | vma->vm->clear_range(vma->vm, |
1613 | vma->node.start, | |
1614 | obj->base.size, | |
6f65e29a | 1615 | true); |
aff43766 | 1616 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1617 | } |
74898d7e | 1618 | |
aff43766 | 1619 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1620 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1621 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1622 | vma->node.start, |
1623 | obj->base.size, | |
6f65e29a | 1624 | true); |
aff43766 | 1625 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 1626 | } |
74163907 DV |
1627 | } |
1628 | ||
1629 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1630 | { |
5c042287 BW |
1631 | struct drm_device *dev = obj->base.dev; |
1632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1633 | bool interruptible; | |
1634 | ||
1635 | interruptible = do_idling(dev_priv); | |
1636 | ||
9da3da66 CW |
1637 | if (!obj->has_dma_mapping) |
1638 | dma_unmap_sg(&dev->pdev->dev, | |
1639 | obj->pages->sgl, obj->pages->nents, | |
1640 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1641 | |
1642 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1643 | } |
644ec02b | 1644 | |
42d6ab48 CW |
1645 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1646 | unsigned long color, | |
1647 | unsigned long *start, | |
1648 | unsigned long *end) | |
1649 | { | |
1650 | if (node->color != color) | |
1651 | *start += 4096; | |
1652 | ||
1653 | if (!list_empty(&node->node_list)) { | |
1654 | node = list_entry(node->node_list.next, | |
1655 | struct drm_mm_node, | |
1656 | node_list); | |
1657 | if (node->allocated && node->color != color) | |
1658 | *end -= 4096; | |
1659 | } | |
1660 | } | |
fbe5d36e | 1661 | |
6c5566a8 DV |
1662 | int i915_gem_setup_global_gtt(struct drm_device *dev, |
1663 | unsigned long start, | |
1664 | unsigned long mappable_end, | |
1665 | unsigned long end) | |
644ec02b | 1666 | { |
e78891ca BW |
1667 | /* Let GEM Manage all of the aperture. |
1668 | * | |
1669 | * However, leave one page at the end still bound to the scratch page. | |
1670 | * There are a number of places where the hardware apparently prefetches | |
1671 | * past the end of the object, and we've seen multiple hangs with the | |
1672 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1673 | * aperture. One page should be enough to keep any prefetching inside | |
1674 | * of the aperture. | |
1675 | */ | |
40d74980 BW |
1676 | struct drm_i915_private *dev_priv = dev->dev_private; |
1677 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1678 | struct drm_mm_node *entry; |
1679 | struct drm_i915_gem_object *obj; | |
1680 | unsigned long hole_start, hole_end; | |
fa76da34 | 1681 | int ret; |
644ec02b | 1682 | |
35451cb6 BW |
1683 | BUG_ON(mappable_end > end); |
1684 | ||
ed2f3452 | 1685 | /* Subtract the guard page ... */ |
40d74980 | 1686 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1687 | if (!HAS_LLC(dev)) |
93bd8649 | 1688 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1689 | |
ed2f3452 | 1690 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1691 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1692 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 1693 | |
edd41a87 | 1694 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1695 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1696 | ||
1697 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1698 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
1699 | if (ret) { |
1700 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
1701 | return ret; | |
1702 | } | |
aff43766 | 1703 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
1704 | } |
1705 | ||
853ba5d2 BW |
1706 | dev_priv->gtt.base.start = start; |
1707 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1708 | |
ed2f3452 | 1709 | /* Clear any non-preallocated blocks */ |
40d74980 | 1710 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1711 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1712 | hole_start, hole_end); | |
782f1495 BW |
1713 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1714 | hole_end - hole_start, true); | |
ed2f3452 CW |
1715 | } |
1716 | ||
1717 | /* And finally clear the reserved guard page */ | |
782f1495 | 1718 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 1719 | |
fa76da34 DV |
1720 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
1721 | struct i915_hw_ppgtt *ppgtt; | |
1722 | ||
1723 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1724 | if (!ppgtt) | |
1725 | return -ENOMEM; | |
1726 | ||
1727 | ret = __hw_ppgtt_init(dev, ppgtt); | |
1728 | if (ret != 0) | |
1729 | return ret; | |
1730 | ||
1731 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1732 | } | |
1733 | ||
6c5566a8 | 1734 | return 0; |
e76e9aeb BW |
1735 | } |
1736 | ||
d7e5008f BW |
1737 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1738 | { | |
1739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1740 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1741 | |
853ba5d2 | 1742 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1743 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1744 | |
e78891ca | 1745 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1746 | } |
1747 | ||
90d0a0e8 DV |
1748 | void i915_global_gtt_cleanup(struct drm_device *dev) |
1749 | { | |
1750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1751 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
1752 | ||
70e32544 DV |
1753 | if (dev_priv->mm.aliasing_ppgtt) { |
1754 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1755 | ||
1756 | ppgtt->base.cleanup(&ppgtt->base); | |
1757 | } | |
1758 | ||
90d0a0e8 DV |
1759 | if (drm_mm_initialized(&vm->mm)) { |
1760 | drm_mm_takedown(&vm->mm); | |
1761 | list_del(&vm->global_link); | |
1762 | } | |
1763 | ||
1764 | vm->cleanup(vm); | |
1765 | } | |
70e32544 | 1766 | |
e76e9aeb BW |
1767 | static int setup_scratch_page(struct drm_device *dev) |
1768 | { | |
1769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1770 | struct page *page; | |
1771 | dma_addr_t dma_addr; | |
1772 | ||
1773 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1774 | if (page == NULL) | |
1775 | return -ENOMEM; | |
e76e9aeb BW |
1776 | set_pages_uc(page, 1); |
1777 | ||
1778 | #ifdef CONFIG_INTEL_IOMMU | |
1779 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1780 | PCI_DMA_BIDIRECTIONAL); | |
1781 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1782 | return -EINVAL; | |
1783 | #else | |
1784 | dma_addr = page_to_phys(page); | |
1785 | #endif | |
853ba5d2 BW |
1786 | dev_priv->gtt.base.scratch.page = page; |
1787 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1788 | |
1789 | return 0; | |
1790 | } | |
1791 | ||
1792 | static void teardown_scratch_page(struct drm_device *dev) | |
1793 | { | |
1794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1795 | struct page *page = dev_priv->gtt.base.scratch.page; |
1796 | ||
1797 | set_pages_wb(page, 1); | |
1798 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1799 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 1800 | __free_page(page); |
e76e9aeb BW |
1801 | } |
1802 | ||
1803 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1804 | { | |
1805 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1806 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1807 | return snb_gmch_ctl << 20; | |
1808 | } | |
1809 | ||
9459d252 BW |
1810 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1811 | { | |
1812 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1813 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1814 | if (bdw_gmch_ctl) | |
1815 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
1816 | |
1817 | #ifdef CONFIG_X86_32 | |
1818 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
1819 | if (bdw_gmch_ctl > 4) | |
1820 | bdw_gmch_ctl = 4; | |
1821 | #endif | |
1822 | ||
9459d252 BW |
1823 | return bdw_gmch_ctl << 20; |
1824 | } | |
1825 | ||
d7f25f23 DL |
1826 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1827 | { | |
1828 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
1829 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
1830 | ||
1831 | if (gmch_ctrl) | |
1832 | return 1 << (20 + gmch_ctrl); | |
1833 | ||
1834 | return 0; | |
1835 | } | |
1836 | ||
baa09f5f | 1837 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1838 | { |
1839 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1840 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1841 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1842 | } | |
1843 | ||
9459d252 BW |
1844 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1845 | { | |
1846 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1847 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1848 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1849 | } | |
1850 | ||
d7f25f23 DL |
1851 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1852 | { | |
1853 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
1854 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
1855 | ||
1856 | /* | |
1857 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
1858 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
1859 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
1860 | */ | |
1861 | if (gmch_ctrl < 0x11) | |
1862 | return gmch_ctrl << 25; | |
1863 | else if (gmch_ctrl < 0x17) | |
1864 | return (gmch_ctrl - 0x11 + 2) << 22; | |
1865 | else | |
1866 | return (gmch_ctrl - 0x17 + 9) << 22; | |
1867 | } | |
1868 | ||
66375014 DL |
1869 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
1870 | { | |
1871 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1872 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1873 | ||
1874 | if (gen9_gmch_ctl < 0xf0) | |
1875 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
1876 | else | |
1877 | /* 4MB increments starting at 0xf0 for 4MB */ | |
1878 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
1879 | } | |
1880 | ||
63340133 BW |
1881 | static int ggtt_probe_common(struct drm_device *dev, |
1882 | size_t gtt_size) | |
1883 | { | |
1884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1885 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1886 | int ret; |
1887 | ||
1888 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1889 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1890 | (pci_resource_len(dev->pdev, 0) / 2); |
1891 | ||
21c34607 | 1892 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1893 | if (!dev_priv->gtt.gsm) { |
1894 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1895 | return -ENOMEM; | |
1896 | } | |
1897 | ||
1898 | ret = setup_scratch_page(dev); | |
1899 | if (ret) { | |
1900 | DRM_ERROR("Scratch setup failed\n"); | |
1901 | /* iounmap will also get called at remove, but meh */ | |
1902 | iounmap(dev_priv->gtt.gsm); | |
1903 | } | |
1904 | ||
1905 | return ret; | |
1906 | } | |
1907 | ||
fbe5d36e BW |
1908 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1909 | * bits. When using advanced contexts each context stores its own PAT, but | |
1910 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1911 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1912 | { |
fbe5d36e BW |
1913 | uint64_t pat; |
1914 | ||
1915 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1916 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1917 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1918 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1919 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1920 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1921 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1922 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1923 | ||
1924 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1925 | * write would work. */ | |
1926 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1927 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1928 | } | |
1929 | ||
ee0ce478 VS |
1930 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
1931 | { | |
1932 | uint64_t pat; | |
1933 | ||
1934 | /* | |
1935 | * Map WB on BDW to snooped on CHV. | |
1936 | * | |
1937 | * Only the snoop bit has meaning for CHV, the rest is | |
1938 | * ignored. | |
1939 | * | |
1940 | * Note that the harware enforces snooping for all page | |
1941 | * table accesses. The snoop bit is actually ignored for | |
1942 | * PDEs. | |
1943 | */ | |
1944 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
1945 | GEN8_PPAT(1, 0) | | |
1946 | GEN8_PPAT(2, 0) | | |
1947 | GEN8_PPAT(3, 0) | | |
1948 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
1949 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
1950 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
1951 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
1952 | ||
1953 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1954 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1955 | } | |
1956 | ||
63340133 BW |
1957 | static int gen8_gmch_probe(struct drm_device *dev, |
1958 | size_t *gtt_total, | |
1959 | size_t *stolen, | |
1960 | phys_addr_t *mappable_base, | |
1961 | unsigned long *mappable_end) | |
1962 | { | |
1963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1964 | unsigned int gtt_size; | |
1965 | u16 snb_gmch_ctl; | |
1966 | int ret; | |
1967 | ||
1968 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1969 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1970 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1971 | ||
1972 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1973 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1974 | ||
1975 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1976 | ||
66375014 DL |
1977 | if (INTEL_INFO(dev)->gen >= 9) { |
1978 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
1979 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
1980 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
1981 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
1982 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
1983 | } else { | |
1984 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1985 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
1986 | } | |
63340133 | 1987 | |
d31eb10e | 1988 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1989 | |
ee0ce478 VS |
1990 | if (IS_CHERRYVIEW(dev)) |
1991 | chv_setup_private_ppat(dev_priv); | |
1992 | else | |
1993 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 1994 | |
63340133 BW |
1995 | ret = ggtt_probe_common(dev, gtt_size); |
1996 | ||
94ec8f61 BW |
1997 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1998 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1999 | |
2000 | return ret; | |
2001 | } | |
2002 | ||
baa09f5f BW |
2003 | static int gen6_gmch_probe(struct drm_device *dev, |
2004 | size_t *gtt_total, | |
41907ddc BW |
2005 | size_t *stolen, |
2006 | phys_addr_t *mappable_base, | |
2007 | unsigned long *mappable_end) | |
e76e9aeb BW |
2008 | { |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2010 | unsigned int gtt_size; |
e76e9aeb | 2011 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2012 | int ret; |
2013 | ||
41907ddc BW |
2014 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2015 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2016 | ||
baa09f5f BW |
2017 | /* 64/512MB is the current min/max we actually know of, but this is just |
2018 | * a coarse sanity check. | |
e76e9aeb | 2019 | */ |
41907ddc | 2020 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2021 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2022 | dev_priv->gtt.mappable_end); | |
2023 | return -ENXIO; | |
e76e9aeb BW |
2024 | } |
2025 | ||
e76e9aeb BW |
2026 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2027 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2028 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2029 | |
c4ae25ec | 2030 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2031 | |
63340133 BW |
2032 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
2033 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 2034 | |
63340133 | 2035 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2036 | |
853ba5d2 BW |
2037 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2038 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2039 | |
e76e9aeb BW |
2040 | return ret; |
2041 | } | |
2042 | ||
853ba5d2 | 2043 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2044 | { |
853ba5d2 BW |
2045 | |
2046 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2047 | |
853ba5d2 BW |
2048 | iounmap(gtt->gsm); |
2049 | teardown_scratch_page(vm->dev); | |
644ec02b | 2050 | } |
baa09f5f BW |
2051 | |
2052 | static int i915_gmch_probe(struct drm_device *dev, | |
2053 | size_t *gtt_total, | |
41907ddc BW |
2054 | size_t *stolen, |
2055 | phys_addr_t *mappable_base, | |
2056 | unsigned long *mappable_end) | |
baa09f5f BW |
2057 | { |
2058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2059 | int ret; | |
2060 | ||
baa09f5f BW |
2061 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2062 | if (!ret) { | |
2063 | DRM_ERROR("failed to set up gmch\n"); | |
2064 | return -EIO; | |
2065 | } | |
2066 | ||
41907ddc | 2067 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2068 | |
2069 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2070 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2071 | |
c0a7f818 CW |
2072 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2073 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2074 | ||
baa09f5f BW |
2075 | return 0; |
2076 | } | |
2077 | ||
853ba5d2 | 2078 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2079 | { |
2080 | intel_gmch_remove(); | |
2081 | } | |
2082 | ||
2083 | int i915_gem_gtt_init(struct drm_device *dev) | |
2084 | { | |
2085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2086 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2087 | int ret; |
2088 | ||
baa09f5f | 2089 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2090 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2091 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2092 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2093 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2094 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2095 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2096 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2097 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2098 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2099 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2100 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2101 | else if (INTEL_INFO(dev)->gen >= 7) |
2102 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2103 | else |
350ec881 | 2104 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2105 | } else { |
2106 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2107 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2108 | } |
2109 | ||
853ba5d2 | 2110 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2111 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2112 | if (ret) |
baa09f5f | 2113 | return ret; |
baa09f5f | 2114 | |
853ba5d2 BW |
2115 | gtt->base.dev = dev; |
2116 | ||
baa09f5f | 2117 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2118 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2119 | gtt->base.total >> 20); | |
b2f21b4d BW |
2120 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2121 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2122 | #ifdef CONFIG_INTEL_IOMMU |
2123 | if (intel_iommu_gfx_mapped) | |
2124 | DRM_INFO("VT-d active for gfx access\n"); | |
2125 | #endif | |
cfa7c862 DV |
2126 | /* |
2127 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2128 | * user's requested state against the hardware/driver capabilities. We | |
2129 | * do this now so that we can print out any log messages once rather | |
2130 | * than every time we check intel_enable_ppgtt(). | |
2131 | */ | |
2132 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2133 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2134 | |
2135 | return 0; | |
2136 | } | |
6f65e29a BW |
2137 | |
2138 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2139 | struct i915_address_space *vm) | |
2140 | { | |
2141 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2142 | if (vma == NULL) | |
2143 | return ERR_PTR(-ENOMEM); | |
2144 | ||
2145 | INIT_LIST_HEAD(&vma->vma_link); | |
2146 | INIT_LIST_HEAD(&vma->mm_list); | |
2147 | INIT_LIST_HEAD(&vma->exec_list); | |
2148 | vma->vm = vm; | |
2149 | vma->obj = obj; | |
2150 | ||
2151 | switch (INTEL_INFO(vm->dev)->gen) { | |
fb8aad4b | 2152 | case 9: |
6f65e29a BW |
2153 | case 8: |
2154 | case 7: | |
2155 | case 6: | |
7e0d96bc BW |
2156 | if (i915_is_ggtt(vm)) { |
2157 | vma->unbind_vma = ggtt_unbind_vma; | |
2158 | vma->bind_vma = ggtt_bind_vma; | |
2159 | } else { | |
2160 | vma->unbind_vma = ppgtt_unbind_vma; | |
2161 | vma->bind_vma = ppgtt_bind_vma; | |
2162 | } | |
6f65e29a BW |
2163 | break; |
2164 | case 5: | |
2165 | case 4: | |
2166 | case 3: | |
2167 | case 2: | |
2168 | BUG_ON(!i915_is_ggtt(vm)); | |
2169 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2170 | vma->bind_vma = i915_ggtt_bind_vma; | |
2171 | break; | |
2172 | default: | |
2173 | BUG(); | |
2174 | } | |
2175 | ||
2176 | /* Keep GGTT vmas first to make debug easier */ | |
2177 | if (i915_is_ggtt(vm)) | |
2178 | list_add(&vma->vma_link, &obj->vma_list); | |
e07f0552 | 2179 | else { |
6f65e29a | 2180 | list_add_tail(&vma->vma_link, &obj->vma_list); |
e07f0552 MT |
2181 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
2182 | } | |
6f65e29a BW |
2183 | |
2184 | return vma; | |
2185 | } | |
2186 | ||
2187 | struct i915_vma * | |
2188 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2189 | struct i915_address_space *vm) | |
2190 | { | |
2191 | struct i915_vma *vma; | |
2192 | ||
2193 | vma = i915_gem_obj_to_vma(obj, vm); | |
2194 | if (!vma) | |
2195 | vma = __i915_gem_vma_create(obj, vm); | |
2196 | ||
2197 | return vma; | |
2198 | } |