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drm/i915/gen8: page directories rework allocation
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
76aaf220 29#include "i915_drv.h"
5dda8fa3 30#include "i915_vgpu.h"
76aaf220
DV		 31#include "i915_trace.h"
32#include "intel_drv.h"
33
45f8f69a
TU		 34/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 73 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
fe14d5f4 95const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648
JL		 96const struct i915_ggtt_view i915_ggtt_view_rotated = {
97 .type = I915_GGTT_VIEW_ROTATED
98};
fe14d5f4 99
ee0ce478
VS		 100static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
101static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
a2319c08 102
cfa7c862
DV		 103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
1893a71b
CW		 105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
107
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1893a71b 110
71ba2d64
YZ		 111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
113
70ee45e1
DL		 114 /*
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
117 */
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV		 120 return 0;
121
122 if (enable_ppgtt == 1)
123 return 1;
124
1893a71b 125 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 126 return 2;
127
93a25a9e
DV		 128#ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 132 return 0;
93a25a9e
DV		 133 }
134#endif
135
62942ed7 136 /* Early VLV doesn't have this */
ca2aed6c
VS		 137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
62942ed7
JB		 139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 return 0;
141 }
142
2f82bbdf
MT		 143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
144 return 2;
145 else
146 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 147}
148
6f65e29a
BW		 149static void ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
151 u32 flags);
152static void ppgtt_unbind_vma(struct i915_vma *vma);
153
07749ef3
MT		 154static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr,
155 enum i915_cache_level level,
156 bool valid)
94ec8f61 157{
07749ef3 158 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 159 pte |= addr;
63c42e56
BW		 160
161 switch (level) {
162 case I915_CACHE_NONE:
fbe5d36e 163 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 164 break;
165 case I915_CACHE_WT:
166 pte |= PPAT_DISPLAY_ELLC_INDEX;
167 break;
168 default:
169 pte |= PPAT_CACHED_INDEX;
170 break;
171 }
172
94ec8f61
BW		 173 return pte;
174}
175
07749ef3
MT		 176static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev,
177 dma_addr_t addr,
178 enum i915_cache_level level)
b1fe6673 179{
07749ef3 180 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 181 pde |= addr;
182 if (level != I915_CACHE_NONE)
183 pde |= PPAT_CACHED_PDE_INDEX;
184 else
185 pde |= PPAT_UNCACHED_INDEX;
186 return pde;
187}
188
07749ef3
MT		 189static gen6_pte_t snb_pte_encode(dma_addr_t addr,
190 enum i915_cache_level level,
191 bool valid, u32 unused)
54d12527 192{
07749ef3 193 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 194 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 195
196 switch (level) {
350ec881
CW		 197 case I915_CACHE_L3_LLC:
198 case I915_CACHE_LLC:
199 pte |= GEN6_PTE_CACHE_LLC;
200 break;
201 case I915_CACHE_NONE:
202 pte |= GEN6_PTE_UNCACHED;
203 break;
204 default:
5f77eeb0 205 MISSING_CASE(level);
350ec881
CW		 206 }
207
208 return pte;
209}
210
07749ef3
MT		 211static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
212 enum i915_cache_level level,
213 bool valid, u32 unused)
350ec881 214{
07749ef3 215 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 216 pte |= GEN6_PTE_ADDR_ENCODE(addr);
217
218 switch (level) {
219 case I915_CACHE_L3_LLC:
220 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 221 break;
222 case I915_CACHE_LLC:
223 pte |= GEN6_PTE_CACHE_LLC;
224 break;
225 case I915_CACHE_NONE:
9119708c 226 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 227 break;
228 default:
5f77eeb0 229 MISSING_CASE(level);
e7210c3c
BW		 230 }
231
54d12527
BW		 232 return pte;
233}
234
07749ef3
MT		 235static gen6_pte_t byt_pte_encode(dma_addr_t addr,
236 enum i915_cache_level level,
237 bool valid, u32 flags)
93c34e70 238{
07749ef3 239 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 240 pte |= GEN6_PTE_ADDR_ENCODE(addr);
241
24f3a8cf
AG		 242 if (!(flags & PTE_READ_ONLY))
243 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 244
245 if (level != I915_CACHE_NONE)
246 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
247
248 return pte;
249}
250
07749ef3
MT		 251static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
252 enum i915_cache_level level,
253 bool valid, u32 unused)
9119708c 254{
07749ef3 255 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 256 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 257
258 if (level != I915_CACHE_NONE)
87a6b688 259 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 260
261 return pte;
262}
263
07749ef3
MT		 264static gen6_pte_t iris_pte_encode(dma_addr_t addr,
265 enum i915_cache_level level,
266 bool valid, u32 unused)
4d15c145 267{
07749ef3 268 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 269 pte |= HSW_PTE_ADDR_ENCODE(addr);
270
651d794f
CW		 271 switch (level) {
272 case I915_CACHE_NONE:
273 break;
274 case I915_CACHE_WT:
c51e9701 275 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 276 break;
277 default:
c51e9701 278 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 279 break;
280 }
4d15c145
BW		 281
282 return pte;
283}
284
678d96fb
BW		 285#define i915_dma_unmap_single(px, dev) \
286 __i915_dma_unmap_single((px)->daddr, dev)
287
288static inline void __i915_dma_unmap_single(dma_addr_t daddr,
289 struct drm_device *dev)
290{
291 struct device *device = &dev->pdev->dev;
292
293 dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
294}
295
296/**
297 * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc.
298 * @px: Page table/dir/etc to get a DMA map for
299 * @dev: drm device
300 *
301 * Page table allocations are unified across all gens. They always require a
302 * single 4k allocation, as well as a DMA mapping. If we keep the structs
303 * symmetric here, the simple macro covers us for every page table type.
304 *
305 * Return: 0 if success.
306 */
307#define i915_dma_map_single(px, dev) \
308 i915_dma_map_page_single((px)->page, (dev), &(px)->daddr)
309
310static inline int i915_dma_map_page_single(struct page *page,
311 struct drm_device *dev,
312 dma_addr_t *daddr)
313{
314 struct device *device = &dev->pdev->dev;
315
316 *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
1266cdb1
MT		 317 if (dma_mapping_error(device, *daddr))
318 return -ENOMEM;
319
320 return 0;
678d96fb
BW		 321}
322
ec565b3c 323static void unmap_and_free_pt(struct i915_page_table *pt,
678d96fb 324 struct drm_device *dev)
06fda602
BW		 325{
326 if (WARN_ON(!pt->page))
327 return;
678d96fb
BW		 328
329 i915_dma_unmap_single(pt, dev);
06fda602 330 __free_page(pt->page);
678d96fb 331 kfree(pt->used_ptes);
06fda602
BW		 332 kfree(pt);
333}
334
5a8e9943
MT		 335static void gen8_initialize_pt(struct i915_address_space *vm,
336 struct i915_page_table *pt)
337{
338 gen8_pte_t *pt_vaddr, scratch_pte;
339 int i;
340
341 pt_vaddr = kmap_atomic(pt->page);
342 scratch_pte = gen8_pte_encode(vm->scratch.addr,
343 I915_CACHE_LLC, true);
344
345 for (i = 0; i < GEN8_PTES; i++)
346 pt_vaddr[i] = scratch_pte;
347
348 if (!HAS_LLC(vm->dev))
349 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
350 kunmap_atomic(pt_vaddr);
351}
352
ec565b3c 353static struct i915_page_table *alloc_pt_single(struct drm_device *dev)
06fda602 354{
ec565b3c 355 struct i915_page_table *pt;
678d96fb
BW		 356 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
357 GEN8_PTES : GEN6_PTES;
358 int ret = -ENOMEM;
06fda602
BW		 359
360 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
361 if (!pt)
362 return ERR_PTR(-ENOMEM);
363
678d96fb
BW		 364 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
365 GFP_KERNEL);
366
367 if (!pt->used_ptes)
368 goto fail_bitmap;
369
4933d519 370 pt->page = alloc_page(GFP_KERNEL);
678d96fb
BW		 371 if (!pt->page)
372 goto fail_page;
373
374 ret = i915_dma_map_single(pt, dev);
375 if (ret)
376 goto fail_dma;
06fda602
BW		 377
378 return pt;
678d96fb
BW		 379
380fail_dma:
381 __free_page(pt->page);
382fail_page:
383 kfree(pt->used_ptes);
384fail_bitmap:
385 kfree(pt);
386
387 return ERR_PTR(ret);
06fda602
BW		 388}
389
390/**
391 * alloc_pt_range() - Allocate a multiple page tables
392 * @pd: The page directory which will have at least @count entries
393 * available to point to the allocated page tables.
394 * @pde: First page directory entry for which we are allocating.
395 * @count: Number of pages to allocate.
719cd21c 396 * @dev: DRM device.
06fda602
BW		 397 *
398 * Allocates multiple page table pages and sets the appropriate entries in the
399 * page table structure within the page directory. Function cleans up after
400 * itself on any failures.
401 *
402 * Return: 0 if allocation succeeded.
403 */
ec565b3c 404static int alloc_pt_range(struct i915_page_directory *pd, uint16_t pde, size_t count,
4933d519 405 struct drm_device *dev)
06fda602
BW		 406{
407 int i, ret;
408
409 /* 512 is the max page tables per page_directory on any platform. */
07749ef3 410 if (WARN_ON(pde + count > I915_PDES))
06fda602
BW		 411 return -EINVAL;
412
413 for (i = pde; i < pde + count; i++) {
ec565b3c 414 struct i915_page_table *pt = alloc_pt_single(dev);
06fda602
BW		 415
416 if (IS_ERR(pt)) {
417 ret = PTR_ERR(pt);
418 goto err_out;
419 }
420 WARN(pd->page_table[i],
686135da 421 "Leaking page directory entry %d (%p)\n",
06fda602
BW		 422 i, pd->page_table[i]);
423 pd->page_table[i] = pt;
424 }
425
426 return 0;
427
428err_out:
429 while (i-- > pde)
06dc68d6 430 unmap_and_free_pt(pd->page_table[i], dev);
06fda602
BW		 431 return ret;
432}
433
ec565b3c 434static void unmap_and_free_pd(struct i915_page_directory *pd)
06fda602
BW		 435{
436 if (pd->page) {
437 __free_page(pd->page);
438 kfree(pd);
439 }
440}
441
ec565b3c 442static struct i915_page_directory *alloc_pd_single(void)
06fda602 443{
ec565b3c 444 struct i915_page_directory *pd;
06fda602
BW		 445
446 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
447 if (!pd)
448 return ERR_PTR(-ENOMEM);
449
5a8e9943 450 pd->page = alloc_page(GFP_KERNEL);
06fda602
BW		 451 if (!pd->page) {
452 kfree(pd);
453 return ERR_PTR(-ENOMEM);
454 }
455
456 return pd;
457}
458
94e409c1 459/* Broadwell Page Directory Pointer Descriptors */
a4872ba6 460static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
6689c167 461 uint64_t val)
94e409c1
BW		 462{
463 int ret;
464
465 BUG_ON(entry >= 4);
466
467 ret = intel_ring_begin(ring, 6);
468 if (ret)
469 return ret;
470
471 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
472 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
473 intel_ring_emit(ring, (u32)(val >> 32));
474 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
475 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
476 intel_ring_emit(ring, (u32)(val));
477 intel_ring_advance(ring);
478
479 return 0;
480}
481
eeb9488e 482static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
6689c167 483 struct intel_engine_cs *ring)
94e409c1 484{
eeb9488e 485 int i, ret;
94e409c1
BW		 486
487 /* bit of a hack to find the actual last used pd */
07749ef3 488 int used_pd = ppgtt->num_pd_entries / I915_PDES;
94e409c1 489
94e409c1 490 for (i = used_pd - 1; i >= 0; i--) {
06fda602 491 dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr;
6689c167 492 ret = gen8_write_pdp(ring, i, addr);
eeb9488e
BW		 493 if (ret)
494 return ret;
94e409c1 495 }
d595bd4b 496
eeb9488e 497 return 0;
94e409c1
BW		 498}
499
459108b8 500static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 501 uint64_t start,
502 uint64_t length,
459108b8
BW		 503 bool use_scratch)
504{
505 struct i915_hw_ppgtt *ppgtt =
506 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 507 gen8_pte_t *pt_vaddr, scratch_pte;
7ad47cf2
BW		 508 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
509 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
510 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
782f1495 511 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 512 unsigned last_pte, i;
513
514 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
515 I915_CACHE_LLC, use_scratch);
516
517 while (num_entries) {
ec565b3c
MT		 518 struct i915_page_directory *pd;
519 struct i915_page_table *pt;
06fda602
BW		 520 struct page *page_table;
521
522 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
523 continue;
524
525 pd = ppgtt->pdp.page_directory[pdpe];
526
527 if (WARN_ON(!pd->page_table[pde]))
528 continue;
529
530 pt = pd->page_table[pde];
531
532 if (WARN_ON(!pt->page))
533 continue;
534
535 page_table = pt->page;
459108b8 536
7ad47cf2 537 last_pte = pte + num_entries;
07749ef3
MT		 538 if (last_pte > GEN8_PTES)
539 last_pte = GEN8_PTES;
459108b8
BW		 540
541 pt_vaddr = kmap_atomic(page_table);
542
7ad47cf2 543 for (i = pte; i < last_pte; i++) {
459108b8 544 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 545 num_entries--;
546 }
459108b8 547
fd1ab8f4
RB		 548 if (!HAS_LLC(ppgtt->base.dev))
549 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
459108b8
BW		 550 kunmap_atomic(pt_vaddr);
551
7ad47cf2 552 pte = 0;
07749ef3 553 if (++pde == I915_PDES) {
7ad47cf2
BW		 554 pdpe++;
555 pde = 0;
556 }
459108b8
BW		 557 }
558}
559
9df15b49
BW		 560static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
561 struct sg_table *pages,
782f1495 562 uint64_t start,
24f3a8cf 563 enum i915_cache_level cache_level, u32 unused)
9df15b49
BW		 564{
565 struct i915_hw_ppgtt *ppgtt =
566 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 567 gen8_pte_t *pt_vaddr;
7ad47cf2
BW		 568 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
569 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
570 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
9df15b49
BW		 571 struct sg_page_iter sg_iter;
572
6f1cc993 573 pt_vaddr = NULL;
7ad47cf2 574
9df15b49 575 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
76643600 576 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
7ad47cf2
BW		 577 break;
578
d7b3de91 579 if (pt_vaddr == NULL) {
ec565b3c
MT		 580 struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
581 struct i915_page_table *pt = pd->page_table[pde];
06fda602 582 struct page *page_table = pt->page;
d7b3de91
BW		 583
584 pt_vaddr = kmap_atomic(page_table);
585 }
9df15b49 586
7ad47cf2 587 pt_vaddr[pte] =
6f1cc993
CW		 588 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
589 cache_level, true);
07749ef3 590 if (++pte == GEN8_PTES) {
fd1ab8f4
RB		 591 if (!HAS_LLC(ppgtt->base.dev))
592 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
9df15b49 593 kunmap_atomic(pt_vaddr);
6f1cc993 594 pt_vaddr = NULL;
07749ef3 595 if (++pde == I915_PDES) {
7ad47cf2
BW		 596 pdpe++;
597 pde = 0;
598 }
599 pte = 0;
9df15b49
BW		 600 }
601 }
fd1ab8f4
RB		 602 if (pt_vaddr) {
603 if (!HAS_LLC(ppgtt->base.dev))
604 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
6f1cc993 605 kunmap_atomic(pt_vaddr);
fd1ab8f4 606 }
9df15b49
BW		 607}
608
69876bed
MT		 609static void __gen8_do_map_pt(gen8_pde_t * const pde,
610 struct i915_page_table *pt,
611 struct drm_device *dev)
612{
613 gen8_pde_t entry =
614 gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC);
615 *pde = entry;
616}
617
618static void gen8_initialize_pd(struct i915_address_space *vm,
619 struct i915_page_directory *pd)
620{
621 struct i915_hw_ppgtt *ppgtt =
622 container_of(vm, struct i915_hw_ppgtt, base);
623 gen8_pde_t *page_directory;
624 struct i915_page_table *pt;
625 int i;
626
627 page_directory = kmap_atomic(pd->page);
628 pt = ppgtt->scratch_pt;
629 for (i = 0; i < I915_PDES; i++)
630 /* Map the PDE to the page table */
631 __gen8_do_map_pt(page_directory + i, pt, vm->dev);
632
633 if (!HAS_LLC(vm->dev))
634 drm_clflush_virt_range(page_directory, PAGE_SIZE);
635
636 kunmap_atomic(page_directory);
637}
638
ec565b3c 639static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
7ad47cf2
BW		 640{
641 int i;
642
06fda602 643 if (!pd->page)
7ad47cf2
BW		 644 return;
645
07749ef3 646 for (i = 0; i < I915_PDES; i++) {
06fda602
BW		 647 if (WARN_ON(!pd->page_table[i]))
648 continue;
7ad47cf2 649
06dc68d6 650 unmap_and_free_pt(pd->page_table[i], dev);
06fda602
BW		 651 pd->page_table[i] = NULL;
652 }
d7b3de91
BW		 653}
654
655static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
b45a6715
BW		 656{
657 int i;
658
7ad47cf2 659 for (i = 0; i < ppgtt->num_pd_pages; i++) {
06fda602
BW		 660 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
661 continue;
662
06dc68d6 663 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
06fda602 664 unmap_and_free_pd(ppgtt->pdp.page_directory[i]);
7ad47cf2 665 }
69876bed
MT		 666
667 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
b45a6715
BW		 668}
669
37aca44a
BW		 670static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
671{
672 struct i915_hw_ppgtt *ppgtt =
673 container_of(vm, struct i915_hw_ppgtt, base);
37aca44a 674
b45a6715 675 gen8_ppgtt_free(ppgtt);
37aca44a
BW		 676}
677
d7b3de91 678static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
bf2b4ed2 679{
06fda602 680 int i, ret;
bf2b4ed2 681
d7b3de91 682 for (i = 0; i < ppgtt->num_pd_pages; i++) {
06fda602 683 ret = alloc_pt_range(ppgtt->pdp.page_directory[i],
07749ef3 684 0, I915_PDES, ppgtt->base.dev);
06fda602
BW		 685 if (ret)
686 goto unwind_out;
7ad47cf2
BW		 687 }
688
bf2b4ed2 689 return 0;
7ad47cf2
BW		 690
691unwind_out:
d7b3de91 692 while (i--)
06dc68d6 693 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
7ad47cf2 694
d7b3de91 695 return -ENOMEM;
bf2b4ed2
BW		 696}
697
69876bed
MT		 698static int gen8_ppgtt_alloc_page_directories(struct i915_page_directory_pointer *pdp,
699 uint64_t start,
700 uint64_t length)
bf2b4ed2 701{
69876bed
MT		 702 struct i915_hw_ppgtt *ppgtt =
703 container_of(pdp, struct i915_hw_ppgtt, pdp);
704 struct i915_page_directory *unused;
705 uint64_t temp;
706 uint32_t pdpe;
707
708 /* FIXME: PPGTT container_of won't work for 64b */
709 WARN_ON((start + length) > 0x800000000ULL);
710
711 gen8_for_each_pdpe(unused, pdp, start, length, temp, pdpe) {
712 WARN_ON(unused);
713 pdp->page_directory[pdpe] = alloc_pd_single();
714 if (IS_ERR(ppgtt->pdp.page_directory[pdpe]))
715 goto unwind_out;
bf2b4ed2 716
69876bed
MT		 717 gen8_initialize_pd(&ppgtt->base,
718 ppgtt->pdp.page_directory[pdpe]);
719 ppgtt->num_pd_pages++;
720 }
721
722 /* XXX: Still alloc all page directories in systems with less than
723 * 4GB of memory. This won't be needed after a subsequent patch.
724 */
725 while (ppgtt->num_pd_pages < GEN8_LEGACY_PDPES) {
726 ppgtt->pdp.page_directory[ppgtt->num_pd_pages] = alloc_pd_single();
727 if (IS_ERR(ppgtt->pdp.page_directory[ppgtt->num_pd_pages]))
d7b3de91 728 goto unwind_out;
69876bed
MT		 729
730 gen8_initialize_pd(&ppgtt->base,
731 ppgtt->pdp.page_directory[ppgtt->num_pd_pages]);
732 pdpe++;
733 ppgtt->num_pd_pages++;
d7b3de91
BW		 734 }
735
76643600 736 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES);
bf2b4ed2
BW		 737
738 return 0;
d7b3de91
BW		 739
740unwind_out:
69876bed
MT		 741 while (pdpe--) {
742 unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe]);
743 ppgtt->num_pd_pages--;
744 }
745
746 WARN_ON(ppgtt->num_pd_pages);
d7b3de91
BW		 747
748 return -ENOMEM;
bf2b4ed2
BW		 749}
750
751static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
752 const int max_pdp)
753{
754 int ret;
755
69876bed
MT		 756 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->pdp, ppgtt->base.start,
757 ppgtt->base.total);
bf2b4ed2
BW		 758 if (ret)
759 return ret;
760
d7b3de91
BW		 761 ret = gen8_ppgtt_allocate_page_tables(ppgtt);
762 if (ret)
763 goto err_out;
bf2b4ed2 764
07749ef3 765 ppgtt->num_pd_entries = max_pdp * I915_PDES;
bf2b4ed2 766
d7b3de91 767 return 0;
bf2b4ed2 768
d7b3de91
BW		 769err_out:
770 gen8_ppgtt_free(ppgtt);
bf2b4ed2
BW		 771 return ret;
772}
773
774static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
775 const int pd)
776{
777 dma_addr_t pd_addr;
778 int ret;
779
780 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
06fda602 781 ppgtt->pdp.page_directory[pd]->page, 0,
bf2b4ed2
BW		 782 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
783
784 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
785 if (ret)
786 return ret;
787
06fda602 788 ppgtt->pdp.page_directory[pd]->daddr = pd_addr;
bf2b4ed2
BW		 789
790 return 0;
791}
792
793static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
794 const int pd,
795 const int pt)
796{
797 dma_addr_t pt_addr;
ec565b3c
MT		 798 struct i915_page_directory *pdir = ppgtt->pdp.page_directory[pd];
799 struct i915_page_table *ptab = pdir->page_table[pt];
7324cc04 800 struct page *p = ptab->page;
bf2b4ed2
BW		 801 int ret;
802
5a8e9943
MT		 803 gen8_initialize_pt(&ppgtt->base, ptab);
804
bf2b4ed2
BW		 805 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
806 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
807 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
808 if (ret)
809 return ret;
810
7324cc04 811 ptab->daddr = pt_addr;
bf2b4ed2
BW		 812
813 return 0;
814}
815
eb0b44ad 816/*
f3a964b9
BW		 817 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
818 * with a net effect resembling a 2-level page table in normal x86 terms. Each
819 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
820 * space.
37aca44a 821 *
f3a964b9
BW		 822 * FIXME: split allocation into smaller pieces. For now we only ever do this
823 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
37aca44a 824 * TODO: Do something with the size parameter
f3a964b9 825 */
37aca44a
BW		 826static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
827{
37aca44a 828 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
07749ef3 829 const int min_pt_pages = I915_PDES * max_pdp;
f3a964b9 830 int i, j, ret;
37aca44a
BW		 831
832 if (size % (1<<30))
833 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
834
69876bed
MT		 835 ppgtt->base.start = 0;
836 /* This is the area that we advertise as usable for the caller */
837 ppgtt->base.total = max_pdp * I915_PDES * GEN8_PTES * PAGE_SIZE;
838 WARN_ON(ppgtt->base.total == 0);
839
840 ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
841 if (IS_ERR(ppgtt->scratch_pt))
842 return PTR_ERR(ppgtt->scratch_pt);
843
844 gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
845
2934368e
MK		 846 /* 1. Do all our allocations for page directories and page tables.
847 * We allocate more than was asked so that we can point the unused parts
848 * to valid entries that point to scratch page. Dynamic page tables
849 * will fix this eventually.
850 */
851 ret = gen8_ppgtt_alloc(ppgtt, GEN8_LEGACY_PDPES);
bf2b4ed2
BW		 852 if (ret)
853 return ret;
f3a964b9 854
37aca44a 855 /*
bf2b4ed2 856 * 2. Create DMA mappings for the page directories and page tables.
37aca44a 857 */
2934368e 858 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
bf2b4ed2 859 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
f3a964b9
BW		 860 if (ret)
861 goto bail;
37aca44a 862
07749ef3 863 for (j = 0; j < I915_PDES; j++) {
bf2b4ed2 864 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
f3a964b9
BW		 865 if (ret)
866 goto bail;
37aca44a
BW		 867 }
868 }
869
f3a964b9 870 /*
69876bed 871 * 3. Map all the page directory entries to point to the page tables
f3a964b9
BW		 872 * we've allocated.
873 *
874 * For now, the PPGTT helper functions all require that the PDEs are
b1fe6673 875 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
f3a964b9
BW		 876 * will never need to touch the PDEs again.
877 */
2934368e 878 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
ec565b3c 879 struct i915_page_directory *pd = ppgtt->pdp.page_directory[i];
07749ef3 880 gen8_pde_t *pd_vaddr;
06fda602 881 pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page);
07749ef3 882 for (j = 0; j < I915_PDES; j++) {
ec565b3c 883 struct i915_page_table *pt = pd->page_table[j];
06fda602 884 dma_addr_t addr = pt->daddr;
b1fe6673
BW		 885 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
886 I915_CACHE_LLC);
887 }
fd1ab8f4
RB		 888 if (!HAS_LLC(ppgtt->base.dev))
889 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
b1fe6673
BW		 890 kunmap_atomic(pd_vaddr);
891 }
892
f3a964b9
BW		 893 ppgtt->switch_mm = gen8_mm_switch;
894 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
895 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
896 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
2934368e
MK		 897
898 /* Set all ptes to a valid scratch page. Also above requested space */
899 ppgtt->base.clear_range(&ppgtt->base, 0,
07749ef3 900 ppgtt->num_pd_pages * GEN8_PTES * PAGE_SIZE,
2934368e 901 true);
459108b8 902
37aca44a
BW		 903 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
904 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
905 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
5abbcca3
BW		 906 ppgtt->num_pd_entries,
907 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
28cf5415 908 return 0;
37aca44a 909
f3a964b9 910bail:
f3a964b9 911 gen8_ppgtt_free(ppgtt);
37aca44a
BW		 912 return ret;
913}
914
87d60b63
BW		 915static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
916{
917 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
918 struct i915_address_space *vm = &ppgtt->base;
07749ef3
MT		 919 gen6_pte_t __iomem *pd_addr;
920 gen6_pte_t scratch_pte;
87d60b63
BW		 921 uint32_t pd_entry;
922 int pte, pde;
923
24f3a8cf 924 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
87d60b63 925
07749ef3
MT		 926 pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
927 ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
87d60b63
BW		 928
929 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
7324cc04
BW		 930 ppgtt->pd.pd_offset,
931 ppgtt->pd.pd_offset + ppgtt->num_pd_entries);
87d60b63
BW		 932 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
933 u32 expected;
07749ef3 934 gen6_pte_t *pt_vaddr;
06fda602 935 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
87d60b63
BW		 936 pd_entry = readl(pd_addr + pde);
937 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
938
939 if (pd_entry != expected)
940 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
941 pde,
942 pd_entry,
943 expected);
944 seq_printf(m, "\tPDE: %x\n", pd_entry);
945
06fda602 946 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
07749ef3 947 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 948 unsigned long va =
07749ef3 949 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 950 (pte * PAGE_SIZE);
951 int i;
952 bool found = false;
953 for (i = 0; i < 4; i++)
954 if (pt_vaddr[pte + i] != scratch_pte)
955 found = true;
956 if (!found)
957 continue;
958
959 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
960 for (i = 0; i < 4; i++) {
961 if (pt_vaddr[pte + i] != scratch_pte)
962 seq_printf(m, " %08x", pt_vaddr[pte + i]);
963 else
964 seq_puts(m, " SCRATCH ");
965 }
966 seq_puts(m, "\n");
967 }
968 kunmap_atomic(pt_vaddr);
969 }
970}
971
678d96fb 972/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 973static void gen6_write_pde(struct i915_page_directory *pd,
974 const int pde, struct i915_page_table *pt)
6197349b 975{
678d96fb
BW		 976 /* Caller needs to make sure the write completes if necessary */
977 struct i915_hw_ppgtt *ppgtt =
978 container_of(pd, struct i915_hw_ppgtt, pd);
979 u32 pd_entry;
6197349b 980
678d96fb
BW		 981 pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr);
982 pd_entry |= GEN6_PDE_VALID;
6197349b 983
678d96fb
BW		 984 writel(pd_entry, ppgtt->pd_addr + pde);
985}
6197349b 986
678d96fb
BW		 987/* Write all the page tables found in the ppgtt structure to incrementing page
988 * directories. */
989static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 990 struct i915_page_directory *pd,
678d96fb
BW		 991 uint32_t start, uint32_t length)
992{
ec565b3c 993 struct i915_page_table *pt;
678d96fb
BW		 994 uint32_t pde, temp;
995
996 gen6_for_each_pde(pt, pd, start, length, temp, pde)
997 gen6_write_pde(pd, pde, pt);
998
999 /* Make sure write is complete before other code can use this page
1000 * table. Also require for WC mapped PTEs */
1001 readl(dev_priv->gtt.gsm);
3e302542
BW		 1002}
1003
b4a74e3a 1004static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1005{
7324cc04 1006 BUG_ON(ppgtt->pd.pd_offset & 0x3f);
b4a74e3a 1007
7324cc04 1008 return (ppgtt->pd.pd_offset / 64) << 16;
b4a74e3a
BW		 1009}
1010
90252e5c 1011static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
6689c167 1012 struct intel_engine_cs *ring)
90252e5c 1013{
90252e5c
BW		 1014 int ret;
1015
90252e5c
BW		 1016 /* NB: TLBs must be flushed and invalidated before a switch */
1017 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1018 if (ret)
1019 return ret;
1020
1021 ret = intel_ring_begin(ring, 6);
1022 if (ret)
1023 return ret;
1024
1025 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1026 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1027 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1028 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1029 intel_ring_emit(ring, get_pd_offset(ppgtt));
1030 intel_ring_emit(ring, MI_NOOP);
1031 intel_ring_advance(ring);
1032
1033 return 0;
1034}
1035
71ba2d64
YZ		 1036static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1037 struct intel_engine_cs *ring)
1038{
1039 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1040
1041 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1042 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1043 return 0;
1044}
1045
48a10389 1046static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
6689c167 1047 struct intel_engine_cs *ring)
48a10389 1048{
48a10389
BW		 1049 int ret;
1050
48a10389
BW		 1051 /* NB: TLBs must be flushed and invalidated before a switch */
1052 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1053 if (ret)
1054 return ret;
1055
1056 ret = intel_ring_begin(ring, 6);
1057 if (ret)
1058 return ret;
1059
1060 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1061 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1062 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1063 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1064 intel_ring_emit(ring, get_pd_offset(ppgtt));
1065 intel_ring_emit(ring, MI_NOOP);
1066 intel_ring_advance(ring);
1067
90252e5c
BW		 1068 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1069 if (ring->id != RCS) {
1070 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1071 if (ret)
1072 return ret;
1073 }
1074
48a10389
BW		 1075 return 0;
1076}
1077
eeb9488e 1078static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
6689c167 1079 struct intel_engine_cs *ring)
eeb9488e
BW		 1080{
1081 struct drm_device *dev = ppgtt->base.dev;
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1083
48a10389 1084
eeb9488e
BW		 1085 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1086 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1087
1088 POSTING_READ(RING_PP_DIR_DCLV(ring));
1089
1090 return 0;
1091}
1092
82460d97 1093static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1094{
eeb9488e 1095 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1096 struct intel_engine_cs *ring;
82460d97 1097 int j;
3e302542 1098
eeb9488e
BW		 1099 for_each_ring(ring, dev_priv, j) {
1100 I915_WRITE(RING_MODE_GEN7(ring),
1101 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
eeb9488e 1102 }
eeb9488e 1103}
6197349b 1104
82460d97 1105static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1106{
50227e1c 1107 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1108 struct intel_engine_cs *ring;
b4a74e3a 1109 uint32_t ecochk, ecobits;
3e302542 1110 int i;
6197349b 1111
b4a74e3a
BW		 1112 ecobits = I915_READ(GAC_ECO_BITS);
1113 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1114
b4a74e3a
BW		 1115 ecochk = I915_READ(GAM_ECOCHK);
1116 if (IS_HASWELL(dev)) {
1117 ecochk |= ECOCHK_PPGTT_WB_HSW;
1118 } else {
1119 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1120 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1121 }
1122 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1123
b4a74e3a 1124 for_each_ring(ring, dev_priv, i) {
6197349b 1125 /* GFX_MODE is per-ring on gen7+ */
b4a74e3a
BW		 1126 I915_WRITE(RING_MODE_GEN7(ring),
1127 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1128 }
b4a74e3a 1129}
6197349b 1130
82460d97 1131static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1132{
50227e1c 1133 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1134 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1135
b4a74e3a
BW		 1136 ecobits = I915_READ(GAC_ECO_BITS);
1137 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1138 ECOBITS_PPGTT_CACHE64B);
6197349b 1139
b4a74e3a
BW		 1140 gab_ctl = I915_READ(GAB_CTL);
1141 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1142
1143 ecochk = I915_READ(GAM_ECOCHK);
1144 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1145
1146 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1147}
1148
1d2a314c 1149/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1150static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1151 uint64_t start,
1152 uint64_t length,
828c7908 1153 bool use_scratch)
1d2a314c 1154{
853ba5d2
BW		 1155 struct i915_hw_ppgtt *ppgtt =
1156 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1157 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1158 unsigned first_entry = start >> PAGE_SHIFT;
1159 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1160 unsigned act_pt = first_entry / GEN6_PTES;
1161 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1162 unsigned last_pte, i;
1d2a314c 1163
24f3a8cf 1164 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1d2a314c 1165
7bddb01f
DV		 1166 while (num_entries) {
1167 last_pte = first_pte + num_entries;
07749ef3
MT		 1168 if (last_pte > GEN6_PTES)
1169 last_pte = GEN6_PTES;
7bddb01f 1170
06fda602 1171 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1d2a314c 1172
7bddb01f
DV		 1173 for (i = first_pte; i < last_pte; i++)
1174 pt_vaddr[i] = scratch_pte;
1d2a314c
DV		 1175
1176 kunmap_atomic(pt_vaddr);
1d2a314c 1177
7bddb01f
DV		 1178 num_entries -= last_pte - first_pte;
1179 first_pte = 0;
a15326a5 1180 act_pt++;
7bddb01f 1181 }
1d2a314c
DV		 1182}
1183
853ba5d2 1184static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1185 struct sg_table *pages,
782f1495 1186 uint64_t start,
24f3a8cf 1187 enum i915_cache_level cache_level, u32 flags)
def886c3 1188{
853ba5d2
BW		 1189 struct i915_hw_ppgtt *ppgtt =
1190 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1191 gen6_pte_t *pt_vaddr;
782f1495 1192 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1193 unsigned act_pt = first_entry / GEN6_PTES;
1194 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID		 1195 struct sg_page_iter sg_iter;
1196
cc79714f 1197 pt_vaddr = NULL;
6e995e23 1198 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1199 if (pt_vaddr == NULL)
06fda602 1200 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
6e995e23 1201
cc79714f
CW		 1202 pt_vaddr[act_pte] =
1203 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG		 1204 cache_level, true, flags);
1205
07749ef3 1206 if (++act_pte == GEN6_PTES) {
6e995e23 1207 kunmap_atomic(pt_vaddr);
cc79714f 1208 pt_vaddr = NULL;
a15326a5 1209 act_pt++;
6e995e23 1210 act_pte = 0;
def886c3 1211 }
def886c3 1212 }
cc79714f
CW		 1213 if (pt_vaddr)
1214 kunmap_atomic(pt_vaddr);
def886c3
DV		 1215}
1216
563222a7
BW		 1217/* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we
1218 * are switching between contexts with the same LRCA, we also must do a force
1219 * restore.
1220 */
1221static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1222{
1223 /* If current vm != vm, */
1224 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1225}
1226
4933d519 1227static void gen6_initialize_pt(struct i915_address_space *vm,
ec565b3c 1228 struct i915_page_table *pt)
4933d519
MT		 1229{
1230 gen6_pte_t *pt_vaddr, scratch_pte;
1231 int i;
1232
1233 WARN_ON(vm->scratch.addr == 0);
1234
1235 scratch_pte = vm->pte_encode(vm->scratch.addr,
1236 I915_CACHE_LLC, true, 0);
1237
1238 pt_vaddr = kmap_atomic(pt->page);
1239
1240 for (i = 0; i < GEN6_PTES; i++)
1241 pt_vaddr[i] = scratch_pte;
1242
1243 kunmap_atomic(pt_vaddr);
1244}
1245
678d96fb
BW		 1246static int gen6_alloc_va_range(struct i915_address_space *vm,
1247 uint64_t start, uint64_t length)
1248{
4933d519
MT		 1249 DECLARE_BITMAP(new_page_tables, I915_PDES);
1250 struct drm_device *dev = vm->dev;
1251 struct drm_i915_private *dev_priv = dev->dev_private;
678d96fb
BW		 1252 struct i915_hw_ppgtt *ppgtt =
1253 container_of(vm, struct i915_hw_ppgtt, base);
ec565b3c 1254 struct i915_page_table *pt;
4933d519 1255 const uint32_t start_save = start, length_save = length;
678d96fb 1256 uint32_t pde, temp;
4933d519
MT		 1257 int ret;
1258
1259 WARN_ON(upper_32_bits(start));
1260
1261 bitmap_zero(new_page_tables, I915_PDES);
1262
1263 /* The allocation is done in two stages so that we can bail out with
1264 * minimal amount of pain. The first stage finds new page tables that
1265 * need allocation. The second stage marks use ptes within the page
1266 * tables.
1267 */
1268 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1269 if (pt != ppgtt->scratch_pt) {
1270 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1271 continue;
1272 }
1273
1274 /* We've already allocated a page table */
1275 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1276
1277 pt = alloc_pt_single(dev);
1278 if (IS_ERR(pt)) {
1279 ret = PTR_ERR(pt);
1280 goto unwind_out;
1281 }
1282
1283 gen6_initialize_pt(vm, pt);
1284
1285 ppgtt->pd.page_table[pde] = pt;
1286 set_bit(pde, new_page_tables);
72744cb1 1287 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1288 }
1289
1290 start = start_save;
1291 length = length_save;
678d96fb
BW		 1292
1293 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1294 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1295
1296 bitmap_zero(tmp_bitmap, GEN6_PTES);
1297 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1298 gen6_pte_count(start, length));
1299
4933d519
MT		 1300 if (test_and_clear_bit(pde, new_page_tables))
1301 gen6_write_pde(&ppgtt->pd, pde, pt);
1302
72744cb1
MT		 1303 trace_i915_page_table_entry_map(vm, pde, pt,
1304 gen6_pte_index(start),
1305 gen6_pte_count(start, length),
1306 GEN6_PTES);
4933d519 1307 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1308 GEN6_PTES);
1309 }
1310
4933d519
MT		 1311 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1312
1313 /* Make sure write is complete before other code can use this page
1314 * table. Also require for WC mapped PTEs */
1315 readl(dev_priv->gtt.gsm);
1316
563222a7 1317 mark_tlbs_dirty(ppgtt);
678d96fb 1318 return 0;
4933d519
MT		 1319
1320unwind_out:
1321 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1322 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519
MT		 1323
1324 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1325 unmap_and_free_pt(pt, vm->dev);
1326 }
1327
1328 mark_tlbs_dirty(ppgtt);
1329 return ret;
678d96fb
BW		 1330}
1331
a00d825d
BW		 1332static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1333{
1334 int i;
3440d265 1335
4933d519 1336 for (i = 0; i < ppgtt->num_pd_entries; i++) {
ec565b3c 1337 struct i915_page_table *pt = ppgtt->pd.page_table[i];
4933d519
MT		 1338
1339 if (pt != ppgtt->scratch_pt)
1340 unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev);
1341 }
06fda602 1342
4933d519 1343 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
06fda602 1344 unmap_and_free_pd(&ppgtt->pd);
3440d265
DV		 1345}
1346
a00d825d
BW		 1347static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1348{
1349 struct i915_hw_ppgtt *ppgtt =
1350 container_of(vm, struct i915_hw_ppgtt, base);
1351
a00d825d
BW		 1352 drm_mm_remove_node(&ppgtt->node);
1353
a00d825d
BW		 1354 gen6_ppgtt_free(ppgtt);
1355}
1356
b146520f 1357static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1358{
853ba5d2 1359 struct drm_device *dev = ppgtt->base.dev;
1d2a314c 1360 struct drm_i915_private *dev_priv = dev->dev_private;
e3cc1995 1361 bool retried = false;
b146520f 1362 int ret;
1d2a314c 1363
c8d4c0d6
BW		 1364 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1365 * allocator works in address space sizes, so it's multiplied by page
1366 * size. We allocate at the top of the GTT to avoid fragmentation.
1367 */
1368 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
4933d519
MT		 1369 ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev);
1370 if (IS_ERR(ppgtt->scratch_pt))
1371 return PTR_ERR(ppgtt->scratch_pt);
1372
1373 gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1374
e3cc1995 1375alloc:
c8d4c0d6
BW		 1376 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1377 &ppgtt->node, GEN6_PD_SIZE,
1378 GEN6_PD_ALIGN, 0,
1379 0, dev_priv->gtt.base.total,
3e8b5ae9 1380 DRM_MM_TOPDOWN);
e3cc1995
BW		 1381 if (ret == -ENOSPC && !retried) {
1382 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1383 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c
CW		 1384 I915_CACHE_NONE,
1385 0, dev_priv->gtt.base.total,
1386 0);
e3cc1995 1387 if (ret)
678d96fb 1388 goto err_out;
e3cc1995
BW		 1389
1390 retried = true;
1391 goto alloc;
1392 }
c8d4c0d6 1393
c8c26622 1394 if (ret)
678d96fb
BW		 1395 goto err_out;
1396
c8c26622 1397
c8d4c0d6
BW		 1398 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1399 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 1400
07749ef3 1401 ppgtt->num_pd_entries = I915_PDES;
c8c26622 1402 return 0;
678d96fb
BW		 1403
1404err_out:
4933d519 1405 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev);
678d96fb 1406 return ret;
b146520f
BW		 1407}
1408
b146520f
BW		 1409static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1410{
2f2cf682 1411 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 1412}
06dc68d6 1413
4933d519
MT		 1414static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1415 uint64_t start, uint64_t length)
1416{
ec565b3c 1417 struct i915_page_table *unused;
4933d519 1418 uint32_t pde, temp;
1d2a314c 1419
4933d519
MT		 1420 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1421 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
b146520f
BW		 1422}
1423
4933d519 1424static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing)
b146520f
BW		 1425{
1426 struct drm_device *dev = ppgtt->base.dev;
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 int ret;
1429
1430 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1431 if (IS_GEN6(dev)) {
b146520f
BW		 1432 ppgtt->switch_mm = gen6_mm_switch;
1433 } else if (IS_HASWELL(dev)) {
b146520f
BW		 1434 ppgtt->switch_mm = hsw_mm_switch;
1435 } else if (IS_GEN7(dev)) {
b146520f
BW		 1436 ppgtt->switch_mm = gen7_mm_switch;
1437 } else
1438 BUG();
1439
71ba2d64
YZ		 1440 if (intel_vgpu_active(dev))
1441 ppgtt->switch_mm = vgpu_mm_switch;
1442
b146520f
BW		 1443 ret = gen6_ppgtt_alloc(ppgtt);
1444 if (ret)
1445 return ret;
1446
4933d519
MT		 1447 if (aliasing) {
1448 /* preallocate all pts */
1449 ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries,
1450 ppgtt->base.dev);
1451
1452 if (ret) {
1453 gen6_ppgtt_cleanup(&ppgtt->base);
1454 return ret;
1455 }
1456 }
1457
678d96fb 1458 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 1459 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1460 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1461 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 1462 ppgtt->base.start = 0;
07749ef3 1463 ppgtt->base.total = ppgtt->num_pd_entries * GEN6_PTES * PAGE_SIZE;
87d60b63 1464 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 1465
7324cc04 1466 ppgtt->pd.pd_offset =
07749ef3 1467 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 1468
678d96fb
BW		 1469 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1470 ppgtt->pd.pd_offset / sizeof(gen6_pte_t);
1471
4933d519
MT		 1472 if (aliasing)
1473 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1474 else
1475 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 1476
678d96fb
BW		 1477 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1478
440fd528 1479 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 1480 ppgtt->node.size >> 20,
1481 ppgtt->node.start / PAGE_SIZE);
3440d265 1482
fa76da34 1483 DRM_DEBUG("Adding PPGTT at offset %x\n",
7324cc04 1484 ppgtt->pd.pd_offset << 10);
fa76da34 1485
b146520f 1486 return 0;
3440d265
DV		 1487}
1488
4933d519
MT		 1489static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt,
1490 bool aliasing)
3440d265
DV		 1491{
1492 struct drm_i915_private *dev_priv = dev->dev_private;
3440d265 1493
853ba5d2 1494 ppgtt->base.dev = dev;
8407bb91 1495 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
3440d265 1496
3ed124b2 1497 if (INTEL_INFO(dev)->gen < 8)
4933d519 1498 return gen6_ppgtt_init(ppgtt, aliasing);
3ed124b2 1499 else
1eb0f006 1500 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
fa76da34
DV		 1501}
1502int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1503{
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 int ret = 0;
3ed124b2 1506
4933d519 1507 ret = __hw_ppgtt_init(dev, ppgtt, false);
fa76da34 1508 if (ret == 0) {
c7c48dfd 1509 kref_init(&ppgtt->ref);
93bd8649
BW		 1510 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1511 ppgtt->base.total);
7e0d96bc 1512 i915_init_vm(dev_priv, &ppgtt->base);
93bd8649 1513 }
1d2a314c
DV		 1514
1515 return ret;
1516}
1517
82460d97
DV		 1518int i915_ppgtt_init_hw(struct drm_device *dev)
1519{
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 struct intel_engine_cs *ring;
1522 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1523 int i, ret = 0;
1524
671b5013
TD		 1525 /* In the case of execlists, PPGTT is enabled by the context descriptor
1526 * and the PDPs are contained within the context itself. We don't
1527 * need to do anything here. */
1528 if (i915.enable_execlists)
1529 return 0;
1530
82460d97
DV		 1531 if (!USES_PPGTT(dev))
1532 return 0;
1533
1534 if (IS_GEN6(dev))
1535 gen6_ppgtt_enable(dev);
1536 else if (IS_GEN7(dev))
1537 gen7_ppgtt_enable(dev);
1538 else if (INTEL_INFO(dev)->gen >= 8)
1539 gen8_ppgtt_enable(dev);
1540 else
5f77eeb0 1541 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97
DV		 1542
1543 if (ppgtt) {
1544 for_each_ring(ring, dev_priv, i) {
6689c167 1545 ret = ppgtt->switch_mm(ppgtt, ring);
82460d97
DV		 1546 if (ret != 0)
1547 return ret;
7e0d96bc 1548 }
93bd8649 1549 }
1d2a314c
DV		 1550
1551 return ret;
1552}
4d884705
DV		 1553struct i915_hw_ppgtt *
1554i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1555{
1556 struct i915_hw_ppgtt *ppgtt;
1557 int ret;
1558
1559 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1560 if (!ppgtt)
1561 return ERR_PTR(-ENOMEM);
1562
1563 ret = i915_ppgtt_init(dev, ppgtt);
1564 if (ret) {
1565 kfree(ppgtt);
1566 return ERR_PTR(ret);
1567 }
1568
1569 ppgtt->file_priv = fpriv;
1570
198c974d
DCS		 1571 trace_i915_ppgtt_create(&ppgtt->base);
1572
4d884705
DV		 1573 return ppgtt;
1574}
1575
ee960be7
DV		 1576void i915_ppgtt_release(struct kref *kref)
1577{
1578 struct i915_hw_ppgtt *ppgtt =
1579 container_of(kref, struct i915_hw_ppgtt, ref);
1580
198c974d
DCS		 1581 trace_i915_ppgtt_release(&ppgtt->base);
1582
ee960be7
DV		 1583 /* vmas should already be unbound */
1584 WARN_ON(!list_empty(&ppgtt->base.active_list));
1585 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1586
19dd120c
DV		 1587 list_del(&ppgtt->base.global_link);
1588 drm_mm_takedown(&ppgtt->base.mm);
1589
ee960be7
DV		 1590 ppgtt->base.cleanup(&ppgtt->base);
1591 kfree(ppgtt);
1592}
1d2a314c 1593
7e0d96bc 1594static void
6f65e29a
BW		 1595ppgtt_bind_vma(struct i915_vma *vma,
1596 enum i915_cache_level cache_level,
1597 u32 flags)
1d2a314c 1598{
24f3a8cf
AG		 1599 /* Currently applicable only to VLV */
1600 if (vma->obj->gt_ro)
1601 flags |= PTE_READ_ONLY;
1602
782f1495 1603 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
24f3a8cf 1604 cache_level, flags);
1d2a314c
DV		 1605}
1606
7e0d96bc 1607static void ppgtt_unbind_vma(struct i915_vma *vma)
7bddb01f 1608{
6f65e29a 1609 vma->vm->clear_range(vma->vm,
782f1495
BW		 1610 vma->node.start,
1611 vma->obj->base.size,
6f65e29a 1612 true);
7bddb01f
DV		 1613}
1614
a81cc00c
BW		 1615extern int intel_iommu_gfx_mapped;
1616/* Certain Gen5 chipsets require require idling the GPU before
1617 * unmapping anything from the GTT when VT-d is enabled.
1618 */
1619static inline bool needs_idle_maps(struct drm_device *dev)
1620{
1621#ifdef CONFIG_INTEL_IOMMU
1622 /* Query intel_iommu to see if we need the workaround. Presumably that
1623 * was loaded first.
1624 */
1625 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1626 return true;
1627#endif
1628 return false;
1629}
1630
5c042287
BW		 1631static bool do_idling(struct drm_i915_private *dev_priv)
1632{
1633 bool ret = dev_priv->mm.interruptible;
1634
a81cc00c 1635 if (unlikely(dev_priv->gtt.do_idle_maps)) {
5c042287 1636 dev_priv->mm.interruptible = false;
b2da9fe5 1637 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW		 1638 DRM_ERROR("Couldn't idle GPU\n");
1639 /* Wait a bit, in hopes it avoids the hang */
1640 udelay(10);
1641 }
1642 }
1643
1644 return ret;
1645}
1646
1647static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1648{
a81cc00c 1649 if (unlikely(dev_priv->gtt.do_idle_maps))
5c042287
BW		 1650 dev_priv->mm.interruptible = interruptible;
1651}
1652
828c7908
BW		 1653void i915_check_and_clear_faults(struct drm_device *dev)
1654{
1655 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1656 struct intel_engine_cs *ring;
828c7908
BW		 1657 int i;
1658
1659 if (INTEL_INFO(dev)->gen < 6)
1660 return;
1661
1662 for_each_ring(ring, dev_priv, i) {
1663 u32 fault_reg;
1664 fault_reg = I915_READ(RING_FAULT_REG(ring));
1665 if (fault_reg & RING_FAULT_VALID) {
1666 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 1667 "\tAddr: 0x%08lx\n"
828c7908
BW		 1668 "\tAddress space: %s\n"
1669 "\tSource ID: %d\n"
1670 "\tType: %d\n",
1671 fault_reg & PAGE_MASK,
1672 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1673 RING_FAULT_SRCID(fault_reg),
1674 RING_FAULT_FAULT_TYPE(fault_reg));
1675 I915_WRITE(RING_FAULT_REG(ring),
1676 fault_reg & ~RING_FAULT_VALID);
1677 }
1678 }
1679 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1680}
1681
91e56499
CW		 1682static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1683{
1684 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1685 intel_gtt_chipset_flush();
1686 } else {
1687 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1688 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1689 }
1690}
1691
828c7908
BW		 1692void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1693{
1694 struct drm_i915_private *dev_priv = dev->dev_private;
1695
1696 /* Don't bother messing with faults pre GEN6 as we have little
1697 * documentation supporting that it's a good idea.
1698 */
1699 if (INTEL_INFO(dev)->gen < 6)
1700 return;
1701
1702 i915_check_and_clear_faults(dev);
1703
1704 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
782f1495
BW		 1705 dev_priv->gtt.base.start,
1706 dev_priv->gtt.base.total,
e568af1c 1707 true);
91e56499
CW		 1708
1709 i915_ggtt_flush(dev_priv);
828c7908
BW		 1710}
1711
76aaf220
DV		 1712void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1713{
1714 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1715 struct drm_i915_gem_object *obj;
80da2161 1716 struct i915_address_space *vm;
76aaf220 1717
828c7908
BW		 1718 i915_check_and_clear_faults(dev);
1719
bee4a186 1720 /* First fill our portion of the GTT with scratch pages */
853ba5d2 1721 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
782f1495
BW		 1722 dev_priv->gtt.base.start,
1723 dev_priv->gtt.base.total,
828c7908 1724 true);
bee4a186 1725
35c20a60 1726 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6f65e29a
BW		 1727 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1728 &dev_priv->gtt.base);
1729 if (!vma)
1730 continue;
1731
2c22569b 1732 i915_gem_clflush_object(obj, obj->pin_display);
6f65e29a
BW		 1733 /* The bind_vma code tries to be smart about tracking mappings.
1734 * Unfortunately above, we've just wiped out the mappings
1735 * without telling our object about it. So we need to fake it.
fe14d5f4
TU		 1736 *
1737 * Bind is not expected to fail since this is only called on
1738 * resume and assumption is all requirements exist already.
6f65e29a 1739 */
aff43766 1740 vma->bound &= ~GLOBAL_BIND;
fe14d5f4 1741 WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND));
76aaf220
DV		 1742 }
1743
80da2161 1744
a2319c08 1745 if (INTEL_INFO(dev)->gen >= 8) {
ee0ce478
VS		 1746 if (IS_CHERRYVIEW(dev))
1747 chv_setup_private_ppat(dev_priv);
1748 else
1749 bdw_setup_private_ppat(dev_priv);
1750
80da2161 1751 return;
a2319c08 1752 }
80da2161 1753
678d96fb
BW		 1754 if (USES_PPGTT(dev)) {
1755 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1756 /* TODO: Perhaps it shouldn't be gen6 specific */
1757
1758 struct i915_hw_ppgtt *ppgtt =
1759 container_of(vm, struct i915_hw_ppgtt,
1760 base);
80da2161 1761
678d96fb
BW		 1762 if (i915_is_ggtt(vm))
1763 ppgtt = dev_priv->mm.aliasing_ppgtt;
1764
1765 gen6_write_page_range(dev_priv, &ppgtt->pd,
1766 0, ppgtt->base.total);
1767 }
76aaf220
DV		 1768 }
1769
91e56499 1770 i915_ggtt_flush(dev_priv);
76aaf220 1771}
7c2e6fdf 1772
74163907 1773int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 1774{
9da3da66 1775 if (obj->has_dma_mapping)
74163907 1776 return 0;
9da3da66
CW		 1777
1778 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1779 obj->pages->sgl, obj->pages->nents,
1780 PCI_DMA_BIDIRECTIONAL))
1781 return -ENOSPC;
1782
1783 return 0;
7c2e6fdf
DV		 1784}
1785
07749ef3 1786static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 1787{
1788#ifdef writeq
1789 writeq(pte, addr);
1790#else
1791 iowrite32((u32)pte, addr);
1792 iowrite32(pte >> 32, addr + 4);
1793#endif
1794}
1795
1796static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1797 struct sg_table *st,
782f1495 1798 uint64_t start,
24f3a8cf 1799 enum i915_cache_level level, u32 unused)
94ec8f61
BW		 1800{
1801 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1802 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1803 gen8_pte_t __iomem *gtt_entries =
1804 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 1805 int i = 0;
1806 struct sg_page_iter sg_iter;
57007df7 1807 dma_addr_t addr = 0; /* shut up gcc */
94ec8f61
BW		 1808
1809 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1810 addr = sg_dma_address(sg_iter.sg) +
1811 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1812 gen8_set_pte(&gtt_entries[i],
1813 gen8_pte_encode(addr, level, true));
1814 i++;
1815 }
1816
1817 /*
1818 * XXX: This serves as a posting read to make sure that the PTE has
1819 * actually been updated. There is some concern that even though
1820 * registers and PTEs are within the same BAR that they are potentially
1821 * of NUMA access patterns. Therefore, even with the way we assume
1822 * hardware should work, we must keep this posting read for paranoia.
1823 */
1824 if (i != 0)
1825 WARN_ON(readq(&gtt_entries[i-1])
1826 != gen8_pte_encode(addr, level, true));
1827
94ec8f61
BW		 1828 /* This next bit makes the above posting read even more important. We
1829 * want to flush the TLBs only after we're certain all the PTE updates
1830 * have finished.
1831 */
1832 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1833 POSTING_READ(GFX_FLSH_CNTL_GEN6);
94ec8f61
BW		 1834}
1835
e76e9aeb
BW		 1836/*
1837 * Binds an object into the global gtt with the specified cache level. The object
1838 * will be accessible to the GPU via commands whose operands reference offsets
1839 * within the global GTT as well as accessible by the GPU through the GMADR
1840 * mapped BAR (dev_priv->mm.gtt->gtt).
1841 */
853ba5d2 1842static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 1843 struct sg_table *st,
782f1495 1844 uint64_t start,
24f3a8cf 1845 enum i915_cache_level level, u32 flags)
e76e9aeb 1846{
853ba5d2 1847 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1848 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1849 gen6_pte_t __iomem *gtt_entries =
1850 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
6e995e23
ID		 1851 int i = 0;
1852 struct sg_page_iter sg_iter;
57007df7 1853 dma_addr_t addr = 0;
e76e9aeb 1854
6e995e23 1855 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 1856 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 1857 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 1858 i++;
e76e9aeb
BW		 1859 }
1860
e76e9aeb
BW		 1861 /* XXX: This serves as a posting read to make sure that the PTE has
1862 * actually been updated. There is some concern that even though
1863 * registers and PTEs are within the same BAR that they are potentially
1864 * of NUMA access patterns. Therefore, even with the way we assume
1865 * hardware should work, we must keep this posting read for paranoia.
1866 */
57007df7
PM		 1867 if (i != 0) {
1868 unsigned long gtt = readl(&gtt_entries[i-1]);
1869 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1870 }
0f9b91c7
BW		 1871
1872 /* This next bit makes the above posting read even more important. We
1873 * want to flush the TLBs only after we're certain all the PTE updates
1874 * have finished.
1875 */
1876 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1877 POSTING_READ(GFX_FLSH_CNTL_GEN6);
e76e9aeb
BW		 1878}
1879
94ec8f61 1880static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1881 uint64_t start,
1882 uint64_t length,
94ec8f61
BW		 1883 bool use_scratch)
1884{
1885 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 1886 unsigned first_entry = start >> PAGE_SHIFT;
1887 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1888 gen8_pte_t scratch_pte, __iomem *gtt_base =
1889 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 1890 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1891 int i;
1892
1893 if (WARN(num_entries > max_entries,
1894 "First entry = %d; Num entries = %d (max=%d)\n",
1895 first_entry, num_entries, max_entries))
1896 num_entries = max_entries;
1897
1898 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1899 I915_CACHE_LLC,
1900 use_scratch);
1901 for (i = 0; i < num_entries; i++)
1902 gen8_set_pte(&gtt_base[i], scratch_pte);
1903 readl(gtt_base);
1904}
1905
853ba5d2 1906static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1907 uint64_t start,
1908 uint64_t length,
828c7908 1909 bool use_scratch)
7faf1ab2 1910{
853ba5d2 1911 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 1912 unsigned first_entry = start >> PAGE_SHIFT;
1913 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1914 gen6_pte_t scratch_pte, __iomem *gtt_base =
1915 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
a54c0c27 1916 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
7faf1ab2
DV		 1917 int i;
1918
1919 if (WARN(num_entries > max_entries,
1920 "First entry = %d; Num entries = %d (max=%d)\n",
1921 first_entry, num_entries, max_entries))
1922 num_entries = max_entries;
1923
24f3a8cf 1924 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
828c7908 1925
7faf1ab2
DV		 1926 for (i = 0; i < num_entries; i++)
1927 iowrite32(scratch_pte, &gtt_base[i]);
1928 readl(gtt_base);
1929}
1930
6f65e29a
BW		 1931
1932static void i915_ggtt_bind_vma(struct i915_vma *vma,
1933 enum i915_cache_level cache_level,
1934 u32 unused)
7faf1ab2 1935{
6f65e29a 1936 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
7faf1ab2
DV		 1937 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1938 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1939
6f65e29a 1940 BUG_ON(!i915_is_ggtt(vma->vm));
fe14d5f4 1941 intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags);
aff43766 1942 vma->bound = GLOBAL_BIND;
7faf1ab2
DV		 1943}
1944
853ba5d2 1945static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1946 uint64_t start,
1947 uint64_t length,
828c7908 1948 bool unused)
7faf1ab2 1949{
782f1495
BW		 1950 unsigned first_entry = start >> PAGE_SHIFT;
1951 unsigned num_entries = length >> PAGE_SHIFT;
7faf1ab2
DV		 1952 intel_gtt_clear_range(first_entry, num_entries);
1953}
1954
6f65e29a
BW		 1955static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1956{
1957 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1958 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
7faf1ab2 1959
6f65e29a 1960 BUG_ON(!i915_is_ggtt(vma->vm));
aff43766 1961 vma->bound = 0;
6f65e29a
BW		 1962 intel_gtt_clear_range(first, size);
1963}
7faf1ab2 1964
6f65e29a
BW		 1965static void ggtt_bind_vma(struct i915_vma *vma,
1966 enum i915_cache_level cache_level,
1967 u32 flags)
d5bd1449 1968{
6f65e29a 1969 struct drm_device *dev = vma->vm->dev;
7faf1ab2 1970 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 1971 struct drm_i915_gem_object *obj = vma->obj;
ec7adb6e 1972 struct sg_table *pages = obj->pages;
7faf1ab2 1973
24f3a8cf
AG		 1974 /* Currently applicable only to VLV */
1975 if (obj->gt_ro)
1976 flags |= PTE_READ_ONLY;
1977
ec7adb6e
JL		 1978 if (i915_is_ggtt(vma->vm))
1979 pages = vma->ggtt_view.pages;
1980
6f65e29a
BW		 1981 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1982 * or we have a global mapping already but the cacheability flags have
1983 * changed, set the global PTEs.
1984 *
1985 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1986 * instead if none of the above hold true.
1987 *
1988 * NB: A global mapping should only be needed for special regions like
1989 * "gtt mappable", SNB errata, or if specified via special execbuf
1990 * flags. At all other times, the GPU will use the aliasing PPGTT.
1991 */
1992 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
aff43766 1993 if (!(vma->bound & GLOBAL_BIND) ||
6f65e29a 1994 (cache_level != obj->cache_level)) {
ec7adb6e 1995 vma->vm->insert_entries(vma->vm, pages,
782f1495 1996 vma->node.start,
24f3a8cf 1997 cache_level, flags);
aff43766 1998 vma->bound |= GLOBAL_BIND;
6f65e29a
BW		 1999 }
2000 }
d5bd1449 2001
6f65e29a 2002 if (dev_priv->mm.aliasing_ppgtt &&
aff43766 2003 (!(vma->bound & LOCAL_BIND) ||
6f65e29a
BW		 2004 (cache_level != obj->cache_level))) {
2005 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
ec7adb6e 2006 appgtt->base.insert_entries(&appgtt->base, pages,
782f1495 2007 vma->node.start,
24f3a8cf 2008 cache_level, flags);
aff43766 2009 vma->bound |= LOCAL_BIND;
6f65e29a 2010 }
d5bd1449
CW		 2011}
2012
6f65e29a 2013static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2014{
6f65e29a 2015 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2016 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2017 struct drm_i915_gem_object *obj = vma->obj;
6f65e29a 2018
aff43766 2019 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2020 vma->vm->clear_range(vma->vm,
2021 vma->node.start,
2022 obj->base.size,
6f65e29a 2023 true);
aff43766 2024 vma->bound &= ~GLOBAL_BIND;
6f65e29a 2025 }
74898d7e 2026
aff43766 2027 if (vma->bound & LOCAL_BIND) {
6f65e29a
BW		 2028 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2029 appgtt->base.clear_range(&appgtt->base,
782f1495
BW		 2030 vma->node.start,
2031 obj->base.size,
6f65e29a 2032 true);
aff43766 2033 vma->bound &= ~LOCAL_BIND;
6f65e29a 2034 }
74163907
DV		 2035}
2036
2037void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2038{
5c042287
BW		 2039 struct drm_device *dev = obj->base.dev;
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 bool interruptible;
2042
2043 interruptible = do_idling(dev_priv);
2044
9da3da66
CW		 2045 if (!obj->has_dma_mapping)
2046 dma_unmap_sg(&dev->pdev->dev,
2047 obj->pages->sgl, obj->pages->nents,
2048 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2049
2050 undo_idling(dev_priv, interruptible);
7c2e6fdf 2051}
644ec02b 2052
42d6ab48
CW		 2053static void i915_gtt_color_adjust(struct drm_mm_node *node,
2054 unsigned long color,
440fd528
TR		 2055 u64 *start,
2056 u64 *end)
42d6ab48
CW		 2057{
2058 if (node->color != color)
2059 *start += 4096;
2060
2061 if (!list_empty(&node->node_list)) {
2062 node = list_entry(node->node_list.next,
2063 struct drm_mm_node,
2064 node_list);
2065 if (node->allocated && node->color != color)
2066 *end -= 4096;
2067 }
2068}
fbe5d36e 2069
f548c0e9
DV		 2070static int i915_gem_setup_global_gtt(struct drm_device *dev,
2071 unsigned long start,
2072 unsigned long mappable_end,
2073 unsigned long end)
644ec02b 2074{
e78891ca
BW		 2075 /* Let GEM Manage all of the aperture.
2076 *
2077 * However, leave one page at the end still bound to the scratch page.
2078 * There are a number of places where the hardware apparently prefetches
2079 * past the end of the object, and we've seen multiple hangs with the
2080 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2081 * aperture. One page should be enough to keep any prefetching inside
2082 * of the aperture.
2083 */
40d74980
BW		 2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
ed2f3452
CW		 2086 struct drm_mm_node *entry;
2087 struct drm_i915_gem_object *obj;
2088 unsigned long hole_start, hole_end;
fa76da34 2089 int ret;
644ec02b 2090
35451cb6
BW		 2091 BUG_ON(mappable_end > end);
2092
ed2f3452 2093 /* Subtract the guard page ... */
40d74980 2094 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
5dda8fa3
YZ		 2095
2096 dev_priv->gtt.base.start = start;
2097 dev_priv->gtt.base.total = end - start;
2098
2099 if (intel_vgpu_active(dev)) {
2100 ret = intel_vgt_balloon(dev);
2101 if (ret)
2102 return ret;
2103 }
2104
42d6ab48 2105 if (!HAS_LLC(dev))
93bd8649 2106 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2107
ed2f3452 2108 /* Mark any preallocated objects as occupied */
35c20a60 2109 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
40d74980 2110 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
fa76da34 2111
edd41a87 2112 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
c6cfb325
BW		 2113 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2114
2115 WARN_ON(i915_gem_obj_ggtt_bound(obj));
40d74980 2116 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
6c5566a8
DV		 2117 if (ret) {
2118 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2119 return ret;
2120 }
aff43766 2121 vma->bound |= GLOBAL_BIND;
ed2f3452
CW		 2122 }
2123
ed2f3452 2124 /* Clear any non-preallocated blocks */
40d74980 2125 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
ed2f3452
CW		 2126 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2127 hole_start, hole_end);
782f1495
BW		 2128 ggtt_vm->clear_range(ggtt_vm, hole_start,
2129 hole_end - hole_start, true);
ed2f3452
CW		 2130 }
2131
2132 /* And finally clear the reserved guard page */
782f1495 2133 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2134
fa76da34
DV		 2135 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2136 struct i915_hw_ppgtt *ppgtt;
2137
2138 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2139 if (!ppgtt)
2140 return -ENOMEM;
2141
4933d519
MT		 2142 ret = __hw_ppgtt_init(dev, ppgtt, true);
2143 if (ret) {
2144 kfree(ppgtt);
fa76da34 2145 return ret;
4933d519 2146 }
fa76da34
DV		 2147
2148 dev_priv->mm.aliasing_ppgtt = ppgtt;
2149 }
2150
6c5566a8 2151 return 0;
e76e9aeb
BW		 2152}
2153
d7e5008f
BW		 2154void i915_gem_init_global_gtt(struct drm_device *dev)
2155{
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 unsigned long gtt_size, mappable_size;
d7e5008f 2158
853ba5d2 2159 gtt_size = dev_priv->gtt.base.total;
93d18799 2160 mappable_size = dev_priv->gtt.mappable_end;
d7e5008f 2161
e78891ca 2162 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
e76e9aeb
BW		 2163}
2164
90d0a0e8
DV		 2165void i915_global_gtt_cleanup(struct drm_device *dev)
2166{
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 struct i915_address_space *vm = &dev_priv->gtt.base;
2169
70e32544
DV		 2170 if (dev_priv->mm.aliasing_ppgtt) {
2171 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2172
2173 ppgtt->base.cleanup(&ppgtt->base);
2174 }
2175
90d0a0e8 2176 if (drm_mm_initialized(&vm->mm)) {
5dda8fa3
YZ		 2177 if (intel_vgpu_active(dev))
2178 intel_vgt_deballoon();
2179
90d0a0e8
DV		 2180 drm_mm_takedown(&vm->mm);
2181 list_del(&vm->global_link);
2182 }
2183
2184 vm->cleanup(vm);
2185}
70e32544 2186
e76e9aeb
BW		 2187static int setup_scratch_page(struct drm_device *dev)
2188{
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190 struct page *page;
2191 dma_addr_t dma_addr;
2192
2193 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2194 if (page == NULL)
2195 return -ENOMEM;
e76e9aeb
BW		 2196 set_pages_uc(page, 1);
2197
2198#ifdef CONFIG_INTEL_IOMMU
2199 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2200 PCI_DMA_BIDIRECTIONAL);
2201 if (pci_dma_mapping_error(dev->pdev, dma_addr))
2202 return -EINVAL;
2203#else
2204 dma_addr = page_to_phys(page);
2205#endif
853ba5d2
BW		 2206 dev_priv->gtt.base.scratch.page = page;
2207 dev_priv->gtt.base.scratch.addr = dma_addr;
e76e9aeb
BW		 2208
2209 return 0;
2210}
2211
2212static void teardown_scratch_page(struct drm_device *dev)
2213{
2214 struct drm_i915_private *dev_priv = dev->dev_private;
853ba5d2
BW		 2215 struct page *page = dev_priv->gtt.base.scratch.page;
2216
2217 set_pages_wb(page, 1);
2218 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
e76e9aeb 2219 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
853ba5d2 2220 __free_page(page);
e76e9aeb
BW		 2221}
2222
2223static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2224{
2225 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2226 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2227 return snb_gmch_ctl << 20;
2228}
2229
9459d252
BW		 2230static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2231{
2232 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2233 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2234 if (bdw_gmch_ctl)
2235 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2236
2237#ifdef CONFIG_X86_32
2238 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2239 if (bdw_gmch_ctl > 4)
2240 bdw_gmch_ctl = 4;
2241#endif
2242
9459d252
BW		 2243 return bdw_gmch_ctl << 20;
2244}
2245
d7f25f23
DL		 2246static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2247{
2248 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2249 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2250
2251 if (gmch_ctrl)
2252 return 1 << (20 + gmch_ctrl);
2253
2254 return 0;
2255}
2256
baa09f5f 2257static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2258{
2259 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2260 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2261 return snb_gmch_ctl << 25; /* 32 MB units */
2262}
2263
9459d252
BW		 2264static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2265{
2266 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2267 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2268 return bdw_gmch_ctl << 25; /* 32 MB units */
2269}
2270
d7f25f23
DL		 2271static size_t chv_get_stolen_size(u16 gmch_ctrl)
2272{
2273 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2274 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2275
2276 /*
2277 * 0x0 to 0x10: 32MB increments starting at 0MB
2278 * 0x11 to 0x16: 4MB increments starting at 8MB
2279 * 0x17 to 0x1d: 4MB increments start at 36MB
2280 */
2281 if (gmch_ctrl < 0x11)
2282 return gmch_ctrl << 25;
2283 else if (gmch_ctrl < 0x17)
2284 return (gmch_ctrl - 0x11 + 2) << 22;
2285 else
2286 return (gmch_ctrl - 0x17 + 9) << 22;
2287}
2288
66375014
DL		 2289static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2290{
2291 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2292 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2293
2294 if (gen9_gmch_ctl < 0xf0)
2295 return gen9_gmch_ctl << 25; /* 32 MB units */
2296 else
2297 /* 4MB increments starting at 0xf0 for 4MB */
2298 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2299}
2300
63340133
BW		 2301static int ggtt_probe_common(struct drm_device *dev,
2302 size_t gtt_size)
2303{
2304 struct drm_i915_private *dev_priv = dev->dev_private;
21c34607 2305 phys_addr_t gtt_phys_addr;
63340133
BW		 2306 int ret;
2307
2308 /* For Modern GENs the PTEs and register space are split in the BAR */
21c34607 2309 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
63340133
BW		 2310 (pci_resource_len(dev->pdev, 0) / 2);
2311
21c34607 2312 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
63340133
BW		 2313 if (!dev_priv->gtt.gsm) {
2314 DRM_ERROR("Failed to map the gtt page table\n");
2315 return -ENOMEM;
2316 }
2317
2318 ret = setup_scratch_page(dev);
2319 if (ret) {
2320 DRM_ERROR("Scratch setup failed\n");
2321 /* iounmap will also get called at remove, but meh */
2322 iounmap(dev_priv->gtt.gsm);
2323 }
2324
2325 return ret;
2326}
2327
fbe5d36e
BW		 2328/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2329 * bits. When using advanced contexts each context stores its own PAT, but
2330 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2331static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2332{
fbe5d36e
BW		 2333 uint64_t pat;
2334
2335 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2336 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2337 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2338 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2339 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2340 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2341 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2342 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2343
d6a8b72e
RV		 2344 if (!USES_PPGTT(dev_priv->dev))
2345 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2346 * so RTL will always use the value corresponding to
2347 * pat_sel = 000".
2348 * So let's disable cache for GGTT to avoid screen corruptions.
2349 * MOCS still can be used though.
2350 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2351 * before this patch, i.e. the same uncached + snooping access
2352 * like on gen6/7 seems to be in effect.
2353 * - So this just fixes blitter/render access. Again it looks
2354 * like it's not just uncached access, but uncached + snooping.
2355 * So we can still hold onto all our assumptions wrt cpu
2356 * clflushing on LLC machines.
2357 */
2358 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2359
fbe5d36e
BW		 2360 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2361 * write would work. */
2362 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2363 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2364}
2365
ee0ce478
VS		 2366static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2367{
2368 uint64_t pat;
2369
2370 /*
2371 * Map WB on BDW to snooped on CHV.
2372 *
2373 * Only the snoop bit has meaning for CHV, the rest is
2374 * ignored.
2375 *
cf3d262e
VS		 2376 * The hardware will never snoop for certain types of accesses:
2377 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2378 * - PPGTT page tables
2379 * - some other special cycles
2380 *
2381 * As with BDW, we also need to consider the following for GT accesses:
2382 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2383 * so RTL will always use the value corresponding to
2384 * pat_sel = 000".
2385 * Which means we must set the snoop bit in PAT entry 0
2386 * in order to keep the global status page working.
ee0ce478
VS		 2387 */
2388 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2389 GEN8_PPAT(1, 0) |
2390 GEN8_PPAT(2, 0) |
2391 GEN8_PPAT(3, 0) |
2392 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2393 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2394 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2395 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2396
2397 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2398 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2399}
2400
63340133
BW		 2401static int gen8_gmch_probe(struct drm_device *dev,
2402 size_t *gtt_total,
2403 size_t *stolen,
2404 phys_addr_t *mappable_base,
2405 unsigned long *mappable_end)
2406{
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 unsigned int gtt_size;
2409 u16 snb_gmch_ctl;
2410 int ret;
2411
2412 /* TODO: We're not aware of mappable constraints on gen8 yet */
2413 *mappable_base = pci_resource_start(dev->pdev, 2);
2414 *mappable_end = pci_resource_len(dev->pdev, 2);
2415
2416 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2417 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2418
2419 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2420
66375014
DL		 2421 if (INTEL_INFO(dev)->gen >= 9) {
2422 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2423 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2424 } else if (IS_CHERRYVIEW(dev)) {
d7f25f23
DL		 2425 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2426 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2427 } else {
2428 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2429 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2430 }
63340133 2431
07749ef3 2432 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 2433
ee0ce478
VS		 2434 if (IS_CHERRYVIEW(dev))
2435 chv_setup_private_ppat(dev_priv);
2436 else
2437 bdw_setup_private_ppat(dev_priv);
fbe5d36e 2438
63340133
BW		 2439 ret = ggtt_probe_common(dev, gtt_size);
2440
94ec8f61
BW		 2441 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2442 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
63340133
BW		 2443
2444 return ret;
2445}
2446
baa09f5f
BW		 2447static int gen6_gmch_probe(struct drm_device *dev,
2448 size_t *gtt_total,
41907ddc
BW		 2449 size_t *stolen,
2450 phys_addr_t *mappable_base,
2451 unsigned long *mappable_end)
e76e9aeb
BW		 2452{
2453 struct drm_i915_private *dev_priv = dev->dev_private;
baa09f5f 2454 unsigned int gtt_size;
e76e9aeb 2455 u16 snb_gmch_ctl;
e76e9aeb
BW		 2456 int ret;
2457
41907ddc
BW		 2458 *mappable_base = pci_resource_start(dev->pdev, 2);
2459 *mappable_end = pci_resource_len(dev->pdev, 2);
2460
baa09f5f
BW		 2461 /* 64/512MB is the current min/max we actually know of, but this is just
2462 * a coarse sanity check.
e76e9aeb 2463 */
41907ddc 2464 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
baa09f5f
BW		 2465 DRM_ERROR("Unknown GMADR size (%lx)\n",
2466 dev_priv->gtt.mappable_end);
2467 return -ENXIO;
e76e9aeb
BW		 2468 }
2469
e76e9aeb
BW		 2470 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2471 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 2472 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 2473
c4ae25ec 2474 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
a93e4161 2475
63340133 2476 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
07749ef3 2477 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 2478
63340133 2479 ret = ggtt_probe_common(dev, gtt_size);
e76e9aeb 2480
853ba5d2
BW		 2481 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2482 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
7faf1ab2 2483
e76e9aeb
BW		 2484 return ret;
2485}
2486
853ba5d2 2487static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 2488{
853ba5d2
BW		 2489
2490 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
5ed16782 2491
853ba5d2
BW		 2492 iounmap(gtt->gsm);
2493 teardown_scratch_page(vm->dev);
644ec02b 2494}
baa09f5f
BW		 2495
2496static int i915_gmch_probe(struct drm_device *dev,
2497 size_t *gtt_total,
41907ddc
BW		 2498 size_t *stolen,
2499 phys_addr_t *mappable_base,
2500 unsigned long *mappable_end)
baa09f5f
BW		 2501{
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 int ret;
2504
baa09f5f
BW		 2505 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2506 if (!ret) {
2507 DRM_ERROR("failed to set up gmch\n");
2508 return -EIO;
2509 }
2510
41907ddc 2511 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
baa09f5f
BW		 2512
2513 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
853ba5d2 2514 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
baa09f5f 2515
c0a7f818
CW		 2516 if (unlikely(dev_priv->gtt.do_idle_maps))
2517 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2518
baa09f5f
BW		 2519 return 0;
2520}
2521
853ba5d2 2522static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 2523{
2524 intel_gmch_remove();
2525}
2526
2527int i915_gem_gtt_init(struct drm_device *dev)
2528{
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct i915_gtt *gtt = &dev_priv->gtt;
baa09f5f
BW		 2531 int ret;
2532
baa09f5f 2533 if (INTEL_INFO(dev)->gen <= 5) {
b2f21b4d 2534 gtt->gtt_probe = i915_gmch_probe;
853ba5d2 2535 gtt->base.cleanup = i915_gmch_remove;
63340133 2536 } else if (INTEL_INFO(dev)->gen < 8) {
b2f21b4d 2537 gtt->gtt_probe = gen6_gmch_probe;
853ba5d2 2538 gtt->base.cleanup = gen6_gmch_remove;
4d15c145 2539 if (IS_HASWELL(dev) && dev_priv->ellc_size)
853ba5d2 2540 gtt->base.pte_encode = iris_pte_encode;
4d15c145 2541 else if (IS_HASWELL(dev))
853ba5d2 2542 gtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 2543 else if (IS_VALLEYVIEW(dev))
853ba5d2 2544 gtt->base.pte_encode = byt_pte_encode;
350ec881
CW		 2545 else if (INTEL_INFO(dev)->gen >= 7)
2546 gtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 2547 else
350ec881 2548 gtt->base.pte_encode = snb_pte_encode;
63340133
BW		 2549 } else {
2550 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2551 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 2552 }
2553
853ba5d2 2554 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
b2f21b4d 2555 &gtt->mappable_base, &gtt->mappable_end);
a54c0c27 2556 if (ret)
baa09f5f 2557 return ret;
baa09f5f 2558
853ba5d2
BW		 2559 gtt->base.dev = dev;
2560
baa09f5f 2561 /* GMADR is the PCI mmio aperture into the global GTT. */
853ba5d2
BW		 2562 DRM_INFO("Memory usable by graphics device = %zdM\n",
2563 gtt->base.total >> 20);
b2f21b4d
BW		 2564 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2565 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
5db6c735
DV		 2566#ifdef CONFIG_INTEL_IOMMU
2567 if (intel_iommu_gfx_mapped)
2568 DRM_INFO("VT-d active for gfx access\n");
2569#endif
cfa7c862
DV		 2570 /*
2571 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2572 * user's requested state against the hardware/driver capabilities. We
2573 * do this now so that we can print out any log messages once rather
2574 * than every time we check intel_enable_ppgtt().
2575 */
2576 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2577 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW		 2578
2579 return 0;
2580}
6f65e29a 2581
ec7adb6e
JL		 2582static struct i915_vma *
2583__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2584 struct i915_address_space *vm,
2585 const struct i915_ggtt_view *ggtt_view)
6f65e29a 2586{
dabde5c7 2587 struct i915_vma *vma;
6f65e29a 2588
ec7adb6e
JL		 2589 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2590 return ERR_PTR(-EINVAL);
dabde5c7
DC		 2591 vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2592 if (vma == NULL)
2593 return ERR_PTR(-ENOMEM);
ec7adb6e 2594
6f65e29a
BW		 2595 INIT_LIST_HEAD(&vma->vma_link);
2596 INIT_LIST_HEAD(&vma->mm_list);
2597 INIT_LIST_HEAD(&vma->exec_list);
2598 vma->vm = vm;
2599 vma->obj = obj;
2600
b1252bcf 2601 if (INTEL_INFO(vm->dev)->gen >= 6) {
7e0d96bc 2602 if (i915_is_ggtt(vm)) {
ec7adb6e
JL		 2603 vma->ggtt_view = *ggtt_view;
2604
7e0d96bc
BW		 2605 vma->unbind_vma = ggtt_unbind_vma;
2606 vma->bind_vma = ggtt_bind_vma;
2607 } else {
2608 vma->unbind_vma = ppgtt_unbind_vma;
2609 vma->bind_vma = ppgtt_bind_vma;
2610 }
b1252bcf 2611 } else {
6f65e29a 2612 BUG_ON(!i915_is_ggtt(vm));
ec7adb6e 2613 vma->ggtt_view = *ggtt_view;
6f65e29a
BW		 2614 vma->unbind_vma = i915_ggtt_unbind_vma;
2615 vma->bind_vma = i915_ggtt_bind_vma;
6f65e29a
BW		 2616 }
2617
f7635669
TU		 2618 list_add_tail(&vma->vma_link, &obj->vma_list);
2619 if (!i915_is_ggtt(vm))
e07f0552 2620 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a
BW		 2621
2622 return vma;
2623}
2624
2625struct i915_vma *
ec7adb6e
JL		 2626i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2627 struct i915_address_space *vm)
2628{
2629 struct i915_vma *vma;
2630
2631 vma = i915_gem_obj_to_vma(obj, vm);
2632 if (!vma)
2633 vma = __i915_gem_vma_create(obj, vm,
2634 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2635
2636 return vma;
2637}
2638
2639struct i915_vma *
2640i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 2641 const struct i915_ggtt_view *view)
6f65e29a 2642{
ec7adb6e 2643 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
6f65e29a
BW		 2644 struct i915_vma *vma;
2645
ec7adb6e
JL		 2646 if (WARN_ON(!view))
2647 return ERR_PTR(-EINVAL);
2648
2649 vma = i915_gem_obj_to_ggtt_view(obj, view);
2650
2651 if (IS_ERR(vma))
2652 return vma;
2653
6f65e29a 2654 if (!vma)
ec7adb6e 2655 vma = __i915_gem_vma_create(obj, ggtt, view);
6f65e29a
BW		 2656
2657 return vma;
ec7adb6e 2658
6f65e29a 2659}
fe14d5f4 2660
50470bb0
TU		 2661static void
2662rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2663 struct sg_table *st)
2664{
2665 unsigned int column, row;
2666 unsigned int src_idx;
2667 struct scatterlist *sg = st->sgl;
2668
2669 st->nents = 0;
2670
2671 for (column = 0; column < width; column++) {
2672 src_idx = width * (height - 1) + column;
2673 for (row = 0; row < height; row++) {
2674 st->nents++;
2675 /* We don't need the pages, but need to initialize
2676 * the entries so the sg list can be happily traversed.
2677 * The only thing we need are DMA addresses.
2678 */
2679 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2680 sg_dma_address(sg) = in[src_idx];
2681 sg_dma_len(sg) = PAGE_SIZE;
2682 sg = sg_next(sg);
2683 src_idx -= width;
2684 }
2685 }
2686}
2687
2688static struct sg_table *
2689intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2690 struct drm_i915_gem_object *obj)
2691{
2692 struct drm_device *dev = obj->base.dev;
2693 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2694 unsigned long size, pages, rot_pages;
2695 struct sg_page_iter sg_iter;
2696 unsigned long i;
2697 dma_addr_t *page_addr_list;
2698 struct sg_table *st;
2699 unsigned int tile_pitch, tile_height;
2700 unsigned int width_pages, height_pages;
1d00dad5 2701 int ret = -ENOMEM;
50470bb0
TU		 2702
2703 pages = obj->base.size / PAGE_SIZE;
2704
2705 /* Calculate tiling geometry. */
2706 tile_height = intel_tile_height(dev, rot_info->pixel_format,
2707 rot_info->fb_modifier);
2708 tile_pitch = PAGE_SIZE / tile_height;
2709 width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch);
2710 height_pages = DIV_ROUND_UP(rot_info->height, tile_height);
2711 rot_pages = width_pages * height_pages;
2712 size = rot_pages * PAGE_SIZE;
2713
2714 /* Allocate a temporary list of source pages for random access. */
2715 page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t));
2716 if (!page_addr_list)
2717 return ERR_PTR(ret);
2718
2719 /* Allocate target SG list. */
2720 st = kmalloc(sizeof(*st), GFP_KERNEL);
2721 if (!st)
2722 goto err_st_alloc;
2723
2724 ret = sg_alloc_table(st, rot_pages, GFP_KERNEL);
2725 if (ret)
2726 goto err_sg_alloc;
2727
2728 /* Populate source page list from the object. */
2729 i = 0;
2730 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2731 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2732 i++;
2733 }
2734
2735 /* Rotate the pages. */
2736 rotate_pages(page_addr_list, width_pages, height_pages, st);
2737
2738 DRM_DEBUG_KMS(
2739 "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n",
2740 size, rot_info->pitch, rot_info->height,
2741 rot_info->pixel_format, width_pages, height_pages,
2742 rot_pages);
2743
2744 drm_free_large(page_addr_list);
2745
2746 return st;
2747
2748err_sg_alloc:
2749 kfree(st);
2750err_st_alloc:
2751 drm_free_large(page_addr_list);
2752
2753 DRM_DEBUG_KMS(
2754 "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n",
2755 size, ret, rot_info->pitch, rot_info->height,
2756 rot_info->pixel_format, width_pages, height_pages,
2757 rot_pages);
2758 return ERR_PTR(ret);
2759}
ec7adb6e 2760
50470bb0
TU		 2761static inline int
2762i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 2763{
50470bb0
TU		 2764 int ret = 0;
2765
fe14d5f4
TU		 2766 if (vma->ggtt_view.pages)
2767 return 0;
2768
2769 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2770 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 2771 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2772 vma->ggtt_view.pages =
2773 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 2774 else
2775 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2776 vma->ggtt_view.type);
2777
2778 if (!vma->ggtt_view.pages) {
ec7adb6e 2779 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 2780 vma->ggtt_view.type);
50470bb0
TU		 2781 ret = -EINVAL;
2782 } else if (IS_ERR(vma->ggtt_view.pages)) {
2783 ret = PTR_ERR(vma->ggtt_view.pages);
2784 vma->ggtt_view.pages = NULL;
2785 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2786 vma->ggtt_view.type, ret);
fe14d5f4
TU		 2787 }
2788
50470bb0 2789 return ret;
fe14d5f4
TU		 2790}
2791
2792/**
2793 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2794 * @vma: VMA to map
2795 * @cache_level: mapping cache level
2796 * @flags: flags like global or local mapping
2797 *
2798 * DMA addresses are taken from the scatter-gather table of this object (or of
2799 * this VMA in case of non-default GGTT views) and PTE entries set up.
2800 * Note that DMA addresses are also the only part of the SG table we care about.
2801 */
2802int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2803 u32 flags)
2804{
ec7adb6e
JL		 2805 if (i915_is_ggtt(vma->vm)) {
2806 int ret = i915_get_ggtt_vma_pages(vma);
fe14d5f4 2807
ec7adb6e
JL		 2808 if (ret)
2809 return ret;
2810 }
fe14d5f4
TU		 2811
2812 vma->bind_vma(vma, cache_level, flags);
2813
2814 return 0;
2815}
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