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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
0e46ce2e | 25 | #include <linux/seq_file.h> |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/i915_drm.h> | |
76aaf220 DV |
28 | #include "i915_drv.h" |
29 | #include "i915_trace.h" | |
30 | #include "intel_drv.h" | |
31 | ||
6670a5a5 BW |
32 | #define GEN6_PPGTT_PD_ENTRIES 512 |
33 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 34 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 35 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 36 | |
26b1ff35 BW |
37 | /* PPGTT stuff */ |
38 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 39 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
40 | |
41 | #define GEN6_PDE_VALID (1 << 0) | |
42 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
43 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
44 | ||
45 | #define GEN6_PTE_VALID (1 << 0) | |
46 | #define GEN6_PTE_UNCACHED (1 << 1) | |
47 | #define HSW_PTE_UNCACHED (0) | |
48 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 49 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 50 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
51 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
52 | ||
53 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
54 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
55 | */ | |
56 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
57 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 58 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 59 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 60 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
c51e9701 | 61 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
651d794f | 62 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
c51e9701 | 63 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
26b1ff35 | 64 | |
459108b8 | 65 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a | 66 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
7ad47cf2 BW |
67 | |
68 | /* GEN8 legacy style addressis defined as a 3 level page table: | |
69 | * 31:30 | 29:21 | 20:12 | 11:0 | |
70 | * PDPE | PDE | PTE | offset | |
71 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
72 | * programmed via register. | |
73 | */ | |
74 | #define GEN8_PDPE_SHIFT 30 | |
75 | #define GEN8_PDPE_MASK 0x3 | |
76 | #define GEN8_PDE_SHIFT 21 | |
77 | #define GEN8_PDE_MASK 0x1ff | |
78 | #define GEN8_PTE_SHIFT 12 | |
79 | #define GEN8_PTE_MASK 0x1ff | |
37aca44a | 80 | |
fbe5d36e BW |
81 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
82 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
83 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
84 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
85 | ||
6f65e29a BW |
86 | static void ppgtt_bind_vma(struct i915_vma *vma, |
87 | enum i915_cache_level cache_level, | |
88 | u32 flags); | |
89 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 90 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 91 | |
94ec8f61 BW |
92 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
93 | enum i915_cache_level level, | |
94 | bool valid) | |
95 | { | |
96 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
97 | pte |= addr; | |
fbe5d36e BW |
98 | if (level != I915_CACHE_NONE) |
99 | pte |= PPAT_CACHED_INDEX; | |
100 | else | |
101 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
102 | return pte; |
103 | } | |
104 | ||
b1fe6673 BW |
105 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
106 | dma_addr_t addr, | |
107 | enum i915_cache_level level) | |
108 | { | |
109 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
110 | pde |= addr; | |
111 | if (level != I915_CACHE_NONE) | |
112 | pde |= PPAT_CACHED_PDE_INDEX; | |
113 | else | |
114 | pde |= PPAT_UNCACHED_INDEX; | |
115 | return pde; | |
116 | } | |
117 | ||
350ec881 | 118 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
119 | enum i915_cache_level level, |
120 | bool valid) | |
54d12527 | 121 | { |
b35b380e | 122 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 123 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
124 | |
125 | switch (level) { | |
350ec881 CW |
126 | case I915_CACHE_L3_LLC: |
127 | case I915_CACHE_LLC: | |
128 | pte |= GEN6_PTE_CACHE_LLC; | |
129 | break; | |
130 | case I915_CACHE_NONE: | |
131 | pte |= GEN6_PTE_UNCACHED; | |
132 | break; | |
133 | default: | |
134 | WARN_ON(1); | |
135 | } | |
136 | ||
137 | return pte; | |
138 | } | |
139 | ||
140 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
141 | enum i915_cache_level level, |
142 | bool valid) | |
350ec881 | 143 | { |
b35b380e | 144 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
145 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
146 | ||
147 | switch (level) { | |
148 | case I915_CACHE_L3_LLC: | |
149 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
150 | break; |
151 | case I915_CACHE_LLC: | |
152 | pte |= GEN6_PTE_CACHE_LLC; | |
153 | break; | |
154 | case I915_CACHE_NONE: | |
9119708c | 155 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
156 | break; |
157 | default: | |
350ec881 | 158 | WARN_ON(1); |
e7210c3c BW |
159 | } |
160 | ||
54d12527 BW |
161 | return pte; |
162 | } | |
163 | ||
93c34e70 KG |
164 | #define BYT_PTE_WRITEABLE (1 << 1) |
165 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
166 | ||
80a74f7f | 167 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
168 | enum i915_cache_level level, |
169 | bool valid) | |
93c34e70 | 170 | { |
b35b380e | 171 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
172 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
173 | ||
174 | /* Mark the page as writeable. Other platforms don't have a | |
175 | * setting for read-only/writable, so this matches that behavior. | |
176 | */ | |
177 | pte |= BYT_PTE_WRITEABLE; | |
178 | ||
179 | if (level != I915_CACHE_NONE) | |
180 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
181 | ||
182 | return pte; | |
183 | } | |
184 | ||
80a74f7f | 185 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
186 | enum i915_cache_level level, |
187 | bool valid) | |
9119708c | 188 | { |
b35b380e | 189 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 190 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
191 | |
192 | if (level != I915_CACHE_NONE) | |
87a6b688 | 193 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
194 | |
195 | return pte; | |
196 | } | |
197 | ||
4d15c145 | 198 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
199 | enum i915_cache_level level, |
200 | bool valid) | |
4d15c145 | 201 | { |
b35b380e | 202 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
203 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
204 | ||
651d794f CW |
205 | switch (level) { |
206 | case I915_CACHE_NONE: | |
207 | break; | |
208 | case I915_CACHE_WT: | |
c51e9701 | 209 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
210 | break; |
211 | default: | |
c51e9701 | 212 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
213 | break; |
214 | } | |
4d15c145 BW |
215 | |
216 | return pte; | |
217 | } | |
218 | ||
94e409c1 BW |
219 | /* Broadwell Page Directory Pointer Descriptors */ |
220 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 221 | uint64_t val, bool synchronous) |
94e409c1 | 222 | { |
e178f705 | 223 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
224 | int ret; |
225 | ||
226 | BUG_ON(entry >= 4); | |
227 | ||
e178f705 BW |
228 | if (synchronous) { |
229 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
230 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
231 | return 0; | |
232 | } | |
233 | ||
94e409c1 BW |
234 | ret = intel_ring_begin(ring, 6); |
235 | if (ret) | |
236 | return ret; | |
237 | ||
238 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
239 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
240 | intel_ring_emit(ring, (u32)(val >> 32)); | |
241 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
242 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
243 | intel_ring_emit(ring, (u32)(val)); | |
244 | intel_ring_advance(ring); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
eeb9488e BW |
249 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
250 | struct intel_ring_buffer *ring, | |
251 | bool synchronous) | |
94e409c1 | 252 | { |
eeb9488e | 253 | int i, ret; |
94e409c1 BW |
254 | |
255 | /* bit of a hack to find the actual last used pd */ | |
256 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
257 | ||
94e409c1 BW |
258 | for (i = used_pd - 1; i >= 0; i--) { |
259 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
260 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
261 | if (ret) | |
262 | return ret; | |
94e409c1 | 263 | } |
d595bd4b | 264 | |
eeb9488e | 265 | return 0; |
94e409c1 BW |
266 | } |
267 | ||
459108b8 | 268 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
269 | uint64_t start, |
270 | uint64_t length, | |
459108b8 BW |
271 | bool use_scratch) |
272 | { | |
273 | struct i915_hw_ppgtt *ppgtt = | |
274 | container_of(vm, struct i915_hw_ppgtt, base); | |
275 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
276 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
277 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
278 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 279 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
280 | unsigned last_pte, i; |
281 | ||
282 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
283 | I915_CACHE_LLC, use_scratch); | |
284 | ||
285 | while (num_entries) { | |
7ad47cf2 | 286 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 287 | |
7ad47cf2 | 288 | last_pte = pte + num_entries; |
459108b8 BW |
289 | if (last_pte > GEN8_PTES_PER_PAGE) |
290 | last_pte = GEN8_PTES_PER_PAGE; | |
291 | ||
292 | pt_vaddr = kmap_atomic(page_table); | |
293 | ||
7ad47cf2 | 294 | for (i = pte; i < last_pte; i++) { |
459108b8 | 295 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
296 | num_entries--; |
297 | } | |
459108b8 BW |
298 | |
299 | kunmap_atomic(pt_vaddr); | |
300 | ||
7ad47cf2 BW |
301 | pte = 0; |
302 | if (++pde == GEN8_PDES_PER_PAGE) { | |
303 | pdpe++; | |
304 | pde = 0; | |
305 | } | |
459108b8 BW |
306 | } |
307 | } | |
308 | ||
9df15b49 BW |
309 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
310 | struct sg_table *pages, | |
782f1495 | 311 | uint64_t start, |
9df15b49 BW |
312 | enum i915_cache_level cache_level) |
313 | { | |
314 | struct i915_hw_ppgtt *ppgtt = | |
315 | container_of(vm, struct i915_hw_ppgtt, base); | |
316 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
317 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
318 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
319 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
320 | struct sg_page_iter sg_iter; |
321 | ||
6f1cc993 | 322 | pt_vaddr = NULL; |
7ad47cf2 | 323 | |
9df15b49 | 324 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
325 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
326 | break; | |
327 | ||
6f1cc993 | 328 | if (pt_vaddr == NULL) |
7ad47cf2 | 329 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 330 | |
7ad47cf2 | 331 | pt_vaddr[pte] = |
6f1cc993 CW |
332 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
333 | cache_level, true); | |
7ad47cf2 | 334 | if (++pte == GEN8_PTES_PER_PAGE) { |
9df15b49 | 335 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 336 | pt_vaddr = NULL; |
7ad47cf2 BW |
337 | if (++pde == GEN8_PDES_PER_PAGE) { |
338 | pdpe++; | |
339 | pde = 0; | |
340 | } | |
341 | pte = 0; | |
9df15b49 BW |
342 | } |
343 | } | |
6f1cc993 CW |
344 | if (pt_vaddr) |
345 | kunmap_atomic(pt_vaddr); | |
9df15b49 BW |
346 | } |
347 | ||
7ad47cf2 BW |
348 | static void gen8_free_page_tables(struct page **pt_pages) |
349 | { | |
350 | int i; | |
351 | ||
352 | if (pt_pages == NULL) | |
353 | return; | |
354 | ||
355 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
356 | if (pt_pages[i]) | |
357 | __free_pages(pt_pages[i], 0); | |
358 | } | |
359 | ||
360 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
361 | { |
362 | int i; | |
363 | ||
7ad47cf2 BW |
364 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
365 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
366 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 367 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 368 | } |
b45a6715 | 369 | |
b45a6715 BW |
370 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
371 | } | |
372 | ||
373 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
374 | { | |
f3a964b9 | 375 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
376 | int i, j; |
377 | ||
378 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
379 | /* TODO: In the future we'll support sparse mappings, so this | |
380 | * will have to change. */ | |
381 | if (!ppgtt->pd_dma_addr[i]) | |
382 | continue; | |
383 | ||
f3a964b9 BW |
384 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
385 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
386 | |
387 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
388 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
389 | if (addr) | |
f3a964b9 BW |
390 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
391 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
392 | } |
393 | } | |
394 | } | |
395 | ||
37aca44a BW |
396 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
397 | { | |
398 | struct i915_hw_ppgtt *ppgtt = | |
399 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 400 | |
7e0d96bc | 401 | list_del(&vm->global_link); |
686e1f6f BW |
402 | drm_mm_takedown(&vm->mm); |
403 | ||
b45a6715 BW |
404 | gen8_ppgtt_unmap_pages(ppgtt); |
405 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
406 | } |
407 | ||
7ad47cf2 BW |
408 | static struct page **__gen8_alloc_page_tables(void) |
409 | { | |
410 | struct page **pt_pages; | |
411 | int i; | |
412 | ||
413 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
414 | if (!pt_pages) | |
415 | return ERR_PTR(-ENOMEM); | |
416 | ||
417 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
418 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
419 | if (!pt_pages[i]) | |
420 | goto bail; | |
421 | } | |
422 | ||
423 | return pt_pages; | |
424 | ||
425 | bail: | |
426 | gen8_free_page_tables(pt_pages); | |
427 | kfree(pt_pages); | |
428 | return ERR_PTR(-ENOMEM); | |
429 | } | |
430 | ||
bf2b4ed2 BW |
431 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
432 | const int max_pdp) | |
433 | { | |
7ad47cf2 | 434 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
bf2b4ed2 | 435 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
7ad47cf2 | 436 | int i, ret; |
bf2b4ed2 | 437 | |
7ad47cf2 BW |
438 | for (i = 0; i < max_pdp; i++) { |
439 | pt_pages[i] = __gen8_alloc_page_tables(); | |
440 | if (IS_ERR(pt_pages[i])) { | |
441 | ret = PTR_ERR(pt_pages[i]); | |
442 | goto unwind_out; | |
443 | } | |
444 | } | |
445 | ||
446 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
447 | * "atomic" - for cleanup purposes. | |
448 | */ | |
449 | for (i = 0; i < max_pdp; i++) | |
450 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 451 | |
bf2b4ed2 BW |
452 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); |
453 | ||
454 | return 0; | |
7ad47cf2 BW |
455 | |
456 | unwind_out: | |
457 | while (i--) { | |
458 | gen8_free_page_tables(pt_pages[i]); | |
459 | kfree(pt_pages[i]); | |
460 | } | |
461 | ||
462 | return ret; | |
bf2b4ed2 BW |
463 | } |
464 | ||
465 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
466 | { | |
467 | int i; | |
468 | ||
469 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
470 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
471 | sizeof(dma_addr_t), | |
472 | GFP_KERNEL); | |
473 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
474 | return -ENOMEM; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
481 | const int max_pdp) | |
482 | { | |
483 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
484 | if (!ppgtt->pd_pages) | |
485 | return -ENOMEM; | |
486 | ||
487 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
488 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
494 | const int max_pdp) | |
495 | { | |
496 | int ret; | |
497 | ||
498 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
499 | if (ret) | |
500 | return ret; | |
501 | ||
502 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
503 | if (ret) { | |
504 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
505 | return ret; | |
506 | } | |
507 | ||
508 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
509 | ||
510 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
511 | if (ret) | |
512 | gen8_ppgtt_free(ppgtt); | |
513 | ||
514 | return ret; | |
515 | } | |
516 | ||
517 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
518 | const int pd) | |
519 | { | |
520 | dma_addr_t pd_addr; | |
521 | int ret; | |
522 | ||
523 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
524 | &ppgtt->pd_pages[pd], 0, | |
525 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
526 | ||
527 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
528 | if (ret) | |
529 | return ret; | |
530 | ||
531 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
537 | const int pd, | |
538 | const int pt) | |
539 | { | |
540 | dma_addr_t pt_addr; | |
541 | struct page *p; | |
542 | int ret; | |
543 | ||
7ad47cf2 | 544 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
545 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
546 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
547 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
548 | if (ret) | |
549 | return ret; | |
550 | ||
551 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
37aca44a | 556 | /** |
f3a964b9 BW |
557 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
558 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
559 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
560 | * space. | |
37aca44a | 561 | * |
f3a964b9 BW |
562 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
563 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 564 | * TODO: Do something with the size parameter |
f3a964b9 | 565 | */ |
37aca44a BW |
566 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
567 | { | |
37aca44a | 568 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 569 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 570 | int i, j, ret; |
37aca44a BW |
571 | |
572 | if (size % (1<<30)) | |
573 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
574 | ||
bf2b4ed2 BW |
575 | /* 1. Do all our allocations for page directories and page tables. */ |
576 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
577 | if (ret) | |
578 | return ret; | |
f3a964b9 | 579 | |
37aca44a | 580 | /* |
bf2b4ed2 | 581 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
582 | */ |
583 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 584 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
585 | if (ret) |
586 | goto bail; | |
37aca44a | 587 | |
37aca44a | 588 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 589 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
590 | if (ret) |
591 | goto bail; | |
37aca44a BW |
592 | } |
593 | } | |
594 | ||
f3a964b9 BW |
595 | /* |
596 | * 3. Map all the page directory entires to point to the page tables | |
597 | * we've allocated. | |
598 | * | |
599 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 600 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
601 | * will never need to touch the PDEs again. |
602 | */ | |
b1fe6673 BW |
603 | for (i = 0; i < max_pdp; i++) { |
604 | gen8_ppgtt_pde_t *pd_vaddr; | |
605 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
606 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
607 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
608 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
609 | I915_CACHE_LLC); | |
610 | } | |
611 | kunmap_atomic(pd_vaddr); | |
612 | } | |
613 | ||
f3a964b9 BW |
614 | ppgtt->enable = gen8_ppgtt_enable; |
615 | ppgtt->switch_mm = gen8_mm_switch; | |
616 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
617 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
618 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
619 | ppgtt->base.start = 0; | |
620 | ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; | |
621 | ||
459108b8 | 622 | ppgtt->base.clear_range(&ppgtt->base, 0, |
782f1495 | 623 | ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE, |
459108b8 BW |
624 | true); |
625 | ||
37aca44a BW |
626 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
627 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
628 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
629 | ppgtt->num_pt_pages, | |
bf2b4ed2 | 630 | (ppgtt->num_pt_pages - min_pt_pages) + |
37aca44a | 631 | size % (1<<30)); |
28cf5415 | 632 | return 0; |
37aca44a | 633 | |
f3a964b9 BW |
634 | bail: |
635 | gen8_ppgtt_unmap_pages(ppgtt); | |
636 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
637 | return ret; |
638 | } | |
639 | ||
87d60b63 BW |
640 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
641 | { | |
642 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
643 | struct i915_address_space *vm = &ppgtt->base; | |
644 | gen6_gtt_pte_t __iomem *pd_addr; | |
645 | gen6_gtt_pte_t scratch_pte; | |
646 | uint32_t pd_entry; | |
647 | int pte, pde; | |
648 | ||
649 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); | |
650 | ||
651 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
652 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
653 | ||
654 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
655 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
656 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
657 | u32 expected; | |
658 | gen6_gtt_pte_t *pt_vaddr; | |
659 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
660 | pd_entry = readl(pd_addr + pde); | |
661 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
662 | ||
663 | if (pd_entry != expected) | |
664 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
665 | pde, | |
666 | pd_entry, | |
667 | expected); | |
668 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
669 | ||
670 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
671 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
672 | unsigned long va = | |
673 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
674 | (pte * PAGE_SIZE); | |
675 | int i; | |
676 | bool found = false; | |
677 | for (i = 0; i < 4; i++) | |
678 | if (pt_vaddr[pte + i] != scratch_pte) | |
679 | found = true; | |
680 | if (!found) | |
681 | continue; | |
682 | ||
683 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
684 | for (i = 0; i < 4; i++) { | |
685 | if (pt_vaddr[pte + i] != scratch_pte) | |
686 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
687 | else | |
688 | seq_puts(m, " SCRATCH "); | |
689 | } | |
690 | seq_puts(m, "\n"); | |
691 | } | |
692 | kunmap_atomic(pt_vaddr); | |
693 | } | |
694 | } | |
695 | ||
3e302542 | 696 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 697 | { |
853ba5d2 | 698 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
699 | gen6_gtt_pte_t __iomem *pd_addr; |
700 | uint32_t pd_entry; | |
701 | int i; | |
702 | ||
0a732870 | 703 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
704 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
705 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
706 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
707 | dma_addr_t pt_addr; | |
708 | ||
709 | pt_addr = ppgtt->pt_dma_addr[i]; | |
710 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
711 | pd_entry |= GEN6_PDE_VALID; | |
712 | ||
713 | writel(pd_entry, pd_addr + i); | |
714 | } | |
715 | readl(pd_addr); | |
3e302542 BW |
716 | } |
717 | ||
b4a74e3a | 718 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 719 | { |
b4a74e3a BW |
720 | BUG_ON(ppgtt->pd_offset & 0x3f); |
721 | ||
722 | return (ppgtt->pd_offset / 64) << 16; | |
723 | } | |
724 | ||
90252e5c BW |
725 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
726 | struct intel_ring_buffer *ring, | |
727 | bool synchronous) | |
728 | { | |
729 | struct drm_device *dev = ppgtt->base.dev; | |
730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
731 | int ret; | |
732 | ||
733 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
734 | * manually frob these bits. Ideally we could use the ring functions, | |
735 | * except our error handling makes it quite difficult (can't use | |
736 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
737 | * | |
738 | * FIXME: We should try not to special case reset | |
739 | */ | |
740 | if (synchronous || | |
741 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
742 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
743 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
744 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
745 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
746 | return 0; | |
747 | } | |
748 | ||
749 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
750 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
751 | if (ret) | |
752 | return ret; | |
753 | ||
754 | ret = intel_ring_begin(ring, 6); | |
755 | if (ret) | |
756 | return ret; | |
757 | ||
758 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
759 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
760 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
761 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
762 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
763 | intel_ring_emit(ring, MI_NOOP); | |
764 | intel_ring_advance(ring); | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
48a10389 BW |
769 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
770 | struct intel_ring_buffer *ring, | |
771 | bool synchronous) | |
772 | { | |
773 | struct drm_device *dev = ppgtt->base.dev; | |
774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
775 | int ret; | |
776 | ||
777 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
778 | * manually frob these bits. Ideally we could use the ring functions, | |
779 | * except our error handling makes it quite difficult (can't use | |
780 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
781 | * | |
782 | * FIXME: We should try not to special case reset | |
783 | */ | |
784 | if (synchronous || | |
785 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
786 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
787 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
788 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
789 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
790 | return 0; | |
791 | } | |
792 | ||
793 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
794 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
795 | if (ret) | |
796 | return ret; | |
797 | ||
798 | ret = intel_ring_begin(ring, 6); | |
799 | if (ret) | |
800 | return ret; | |
801 | ||
802 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
803 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
804 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
805 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
806 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
807 | intel_ring_emit(ring, MI_NOOP); | |
808 | intel_ring_advance(ring); | |
809 | ||
90252e5c BW |
810 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
811 | if (ring->id != RCS) { | |
812 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
813 | if (ret) | |
814 | return ret; | |
815 | } | |
816 | ||
48a10389 BW |
817 | return 0; |
818 | } | |
819 | ||
eeb9488e BW |
820 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
821 | struct intel_ring_buffer *ring, | |
822 | bool synchronous) | |
823 | { | |
824 | struct drm_device *dev = ppgtt->base.dev; | |
825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
826 | ||
48a10389 BW |
827 | if (!synchronous) |
828 | return 0; | |
829 | ||
eeb9488e BW |
830 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
831 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
832 | ||
833 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
838 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
839 | { | |
840 | struct drm_device *dev = ppgtt->base.dev; | |
841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3e302542 | 842 | struct intel_ring_buffer *ring; |
eeb9488e | 843 | int j, ret; |
3e302542 | 844 | |
eeb9488e BW |
845 | for_each_ring(ring, dev_priv, j) { |
846 | I915_WRITE(RING_MODE_GEN7(ring), | |
847 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
3e302542 | 848 | |
d2ff7192 BW |
849 | /* We promise to do a switch later with FULL PPGTT. If this is |
850 | * aliasing, this is the one and only switch we'll do */ | |
851 | if (USES_FULL_PPGTT(dev)) | |
852 | continue; | |
6197349b | 853 | |
eeb9488e BW |
854 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
855 | if (ret) | |
856 | goto err_out; | |
857 | } | |
6197349b | 858 | |
eeb9488e | 859 | return 0; |
6197349b | 860 | |
eeb9488e BW |
861 | err_out: |
862 | for_each_ring(ring, dev_priv, j) | |
863 | I915_WRITE(RING_MODE_GEN7(ring), | |
864 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
865 | return ret; | |
866 | } | |
6197349b | 867 | |
b4a74e3a | 868 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 869 | { |
a3d67d23 | 870 | struct drm_device *dev = ppgtt->base.dev; |
3e302542 | 871 | drm_i915_private_t *dev_priv = dev->dev_private; |
3e302542 | 872 | struct intel_ring_buffer *ring; |
b4a74e3a | 873 | uint32_t ecochk, ecobits; |
3e302542 | 874 | int i; |
6197349b | 875 | |
b4a74e3a BW |
876 | ecobits = I915_READ(GAC_ECO_BITS); |
877 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 878 | |
b4a74e3a BW |
879 | ecochk = I915_READ(GAM_ECOCHK); |
880 | if (IS_HASWELL(dev)) { | |
881 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
882 | } else { | |
883 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
884 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
885 | } | |
886 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 887 | |
b4a74e3a | 888 | for_each_ring(ring, dev_priv, i) { |
eeb9488e | 889 | int ret; |
6197349b | 890 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
891 | I915_WRITE(RING_MODE_GEN7(ring), |
892 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
893 | |
894 | /* We promise to do a switch later with FULL PPGTT. If this is | |
895 | * aliasing, this is the one and only switch we'll do */ | |
896 | if (USES_FULL_PPGTT(dev)) | |
897 | continue; | |
898 | ||
eeb9488e BW |
899 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
900 | if (ret) | |
901 | return ret; | |
6197349b BW |
902 | } |
903 | ||
b4a74e3a BW |
904 | return 0; |
905 | } | |
6197349b | 906 | |
b4a74e3a BW |
907 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
908 | { | |
909 | struct drm_device *dev = ppgtt->base.dev; | |
910 | drm_i915_private_t *dev_priv = dev->dev_private; | |
911 | struct intel_ring_buffer *ring; | |
912 | uint32_t ecochk, gab_ctl, ecobits; | |
913 | int i; | |
a65c2fcd | 914 | |
b4a74e3a BW |
915 | ecobits = I915_READ(GAC_ECO_BITS); |
916 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
917 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 918 | |
b4a74e3a BW |
919 | gab_ctl = I915_READ(GAB_CTL); |
920 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
921 | ||
922 | ecochk = I915_READ(GAM_ECOCHK); | |
923 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
924 | ||
925 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 926 | |
b4a74e3a | 927 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
928 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
929 | if (ret) | |
930 | return ret; | |
6197349b | 931 | } |
b4a74e3a | 932 | |
b7c36d25 | 933 | return 0; |
6197349b BW |
934 | } |
935 | ||
1d2a314c | 936 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 937 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
938 | uint64_t start, |
939 | uint64_t length, | |
828c7908 | 940 | bool use_scratch) |
1d2a314c | 941 | { |
853ba5d2 BW |
942 | struct i915_hw_ppgtt *ppgtt = |
943 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 944 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
945 | unsigned first_entry = start >> PAGE_SHIFT; |
946 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 947 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
948 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
949 | unsigned last_pte, i; | |
1d2a314c | 950 | |
b35b380e | 951 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 952 | |
7bddb01f DV |
953 | while (num_entries) { |
954 | last_pte = first_pte + num_entries; | |
955 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
956 | last_pte = I915_PPGTT_PT_ENTRIES; | |
957 | ||
a15326a5 | 958 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 959 | |
7bddb01f DV |
960 | for (i = first_pte; i < last_pte; i++) |
961 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
962 | |
963 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 964 | |
7bddb01f DV |
965 | num_entries -= last_pte - first_pte; |
966 | first_pte = 0; | |
a15326a5 | 967 | act_pt++; |
7bddb01f | 968 | } |
1d2a314c DV |
969 | } |
970 | ||
853ba5d2 | 971 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 972 | struct sg_table *pages, |
782f1495 | 973 | uint64_t start, |
def886c3 DV |
974 | enum i915_cache_level cache_level) |
975 | { | |
853ba5d2 BW |
976 | struct i915_hw_ppgtt *ppgtt = |
977 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 978 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 979 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 980 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
981 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
982 | struct sg_page_iter sg_iter; | |
983 | ||
cc79714f | 984 | pt_vaddr = NULL; |
6e995e23 | 985 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
986 | if (pt_vaddr == NULL) |
987 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 988 | |
cc79714f CW |
989 | pt_vaddr[act_pte] = |
990 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
991 | cache_level, true); | |
6e995e23 ID |
992 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
993 | kunmap_atomic(pt_vaddr); | |
cc79714f | 994 | pt_vaddr = NULL; |
a15326a5 | 995 | act_pt++; |
6e995e23 | 996 | act_pte = 0; |
def886c3 | 997 | } |
def886c3 | 998 | } |
cc79714f CW |
999 | if (pt_vaddr) |
1000 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1001 | } |
1002 | ||
853ba5d2 | 1003 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 1004 | { |
853ba5d2 BW |
1005 | struct i915_hw_ppgtt *ppgtt = |
1006 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
1007 | int i; |
1008 | ||
7e0d96bc | 1009 | list_del(&vm->global_link); |
93bd8649 | 1010 | drm_mm_takedown(&ppgtt->base.mm); |
c8d4c0d6 | 1011 | drm_mm_remove_node(&ppgtt->node); |
93bd8649 | 1012 | |
3440d265 DV |
1013 | if (ppgtt->pt_dma_addr) { |
1014 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 1015 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
1016 | ppgtt->pt_dma_addr[i], |
1017 | 4096, PCI_DMA_BIDIRECTIONAL); | |
1018 | } | |
1019 | ||
1020 | kfree(ppgtt->pt_dma_addr); | |
1021 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
1022 | __free_page(ppgtt->pt_pages[i]); | |
1023 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
1024 | } |
1025 | ||
1026 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1027 | { | |
c8d4c0d6 BW |
1028 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
1029 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) | |
853ba5d2 | 1030 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1031 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1032 | bool retried = false; |
c8d4c0d6 | 1033 | int i, ret; |
1d2a314c | 1034 | |
c8d4c0d6 BW |
1035 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1036 | * allocator works in address space sizes, so it's multiplied by page | |
1037 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1038 | */ | |
1039 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1040 | alloc: |
c8d4c0d6 BW |
1041 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1042 | &ppgtt->node, GEN6_PD_SIZE, | |
1043 | GEN6_PD_ALIGN, 0, | |
1044 | 0, dev_priv->gtt.base.total, | |
1045 | DRM_MM_SEARCH_DEFAULT); | |
e3cc1995 BW |
1046 | if (ret == -ENOSPC && !retried) { |
1047 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1048 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d47c3ea2 | 1049 | I915_CACHE_NONE, 0); |
e3cc1995 BW |
1050 | if (ret) |
1051 | return ret; | |
1052 | ||
1053 | retried = true; | |
1054 | goto alloc; | |
1055 | } | |
c8d4c0d6 BW |
1056 | |
1057 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1058 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1059 | |
08c45263 | 1060 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 1061 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
48a10389 | 1062 | if (IS_GEN6(dev)) { |
b4a74e3a | 1063 | ppgtt->enable = gen6_ppgtt_enable; |
48a10389 | 1064 | ppgtt->switch_mm = gen6_mm_switch; |
90252e5c BW |
1065 | } else if (IS_HASWELL(dev)) { |
1066 | ppgtt->enable = gen7_ppgtt_enable; | |
1067 | ppgtt->switch_mm = hsw_mm_switch; | |
48a10389 | 1068 | } else if (IS_GEN7(dev)) { |
b4a74e3a | 1069 | ppgtt->enable = gen7_ppgtt_enable; |
48a10389 BW |
1070 | ppgtt->switch_mm = gen7_mm_switch; |
1071 | } else | |
b4a74e3a | 1072 | BUG(); |
853ba5d2 BW |
1073 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1074 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1075 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
1076 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
686e1f6f BW |
1077 | ppgtt->base.start = 0; |
1078 | ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; | |
a1e22653 | 1079 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1080 | GFP_KERNEL); |
c8d4c0d6 BW |
1081 | if (!ppgtt->pt_pages) { |
1082 | drm_mm_remove_node(&ppgtt->node); | |
3440d265 | 1083 | return -ENOMEM; |
c8d4c0d6 | 1084 | } |
1d2a314c DV |
1085 | |
1086 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1087 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
1088 | if (!ppgtt->pt_pages[i]) | |
1089 | goto err_pt_alloc; | |
1090 | } | |
1091 | ||
a1e22653 | 1092 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
1093 | GFP_KERNEL); |
1094 | if (!ppgtt->pt_dma_addr) | |
1095 | goto err_pt_alloc; | |
1d2a314c | 1096 | |
8d2e6308 BW |
1097 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1098 | dma_addr_t pt_addr; | |
211c568b | 1099 | |
8d2e6308 BW |
1100 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1101 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1102 | |
8d2e6308 BW |
1103 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
1104 | ret = -EIO; | |
1105 | goto err_pd_pin; | |
1d2a314c | 1106 | |
211c568b | 1107 | } |
8d2e6308 | 1108 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1109 | } |
1d2a314c | 1110 | |
782f1495 | 1111 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
87d60b63 | 1112 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1113 | |
c8d4c0d6 BW |
1114 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1115 | ppgtt->node.size >> 20, | |
1116 | ppgtt->node.start / PAGE_SIZE); | |
1117 | ppgtt->pd_offset = | |
1118 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1119 | |
1d2a314c DV |
1120 | return 0; |
1121 | ||
1122 | err_pd_pin: | |
1123 | if (ppgtt->pt_dma_addr) { | |
1124 | for (i--; i >= 0; i--) | |
1125 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
1126 | 4096, PCI_DMA_BIDIRECTIONAL); | |
1127 | } | |
1128 | err_pt_alloc: | |
1129 | kfree(ppgtt->pt_dma_addr); | |
1130 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1131 | if (ppgtt->pt_pages[i]) | |
1132 | __free_page(ppgtt->pt_pages[i]); | |
1133 | } | |
1134 | kfree(ppgtt->pt_pages); | |
c8d4c0d6 | 1135 | drm_mm_remove_node(&ppgtt->node); |
3440d265 DV |
1136 | |
1137 | return ret; | |
1138 | } | |
1139 | ||
246cbfb5 | 1140 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1141 | { |
1142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 1143 | int ret = 0; |
3440d265 | 1144 | |
853ba5d2 | 1145 | ppgtt->base.dev = dev; |
3440d265 | 1146 | |
3ed124b2 BW |
1147 | if (INTEL_INFO(dev)->gen < 8) |
1148 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 1149 | else if (IS_GEN8(dev)) |
37aca44a | 1150 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1151 | else |
1152 | BUG(); | |
1153 | ||
c7c48dfd | 1154 | if (!ret) { |
7e0d96bc | 1155 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 1156 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1157 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1158 | ppgtt->base.total); | |
7e0d96bc BW |
1159 | i915_init_vm(dev_priv, &ppgtt->base); |
1160 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 1161 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
1162 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
1163 | ppgtt->pd_offset << 10); | |
1164 | } | |
93bd8649 | 1165 | } |
1d2a314c DV |
1166 | |
1167 | return ret; | |
1168 | } | |
1169 | ||
7e0d96bc | 1170 | static void |
6f65e29a BW |
1171 | ppgtt_bind_vma(struct i915_vma *vma, |
1172 | enum i915_cache_level cache_level, | |
1173 | u32 flags) | |
1d2a314c | 1174 | { |
6f65e29a | 1175 | WARN_ON(flags); |
1d2a314c | 1176 | |
782f1495 BW |
1177 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
1178 | cache_level); | |
1d2a314c DV |
1179 | } |
1180 | ||
7e0d96bc | 1181 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1182 | { |
6f65e29a | 1183 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1184 | vma->node.start, |
1185 | vma->obj->base.size, | |
6f65e29a | 1186 | true); |
7bddb01f DV |
1187 | } |
1188 | ||
a81cc00c BW |
1189 | extern int intel_iommu_gfx_mapped; |
1190 | /* Certain Gen5 chipsets require require idling the GPU before | |
1191 | * unmapping anything from the GTT when VT-d is enabled. | |
1192 | */ | |
1193 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1194 | { | |
1195 | #ifdef CONFIG_INTEL_IOMMU | |
1196 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1197 | * was loaded first. | |
1198 | */ | |
1199 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1200 | return true; | |
1201 | #endif | |
1202 | return false; | |
1203 | } | |
1204 | ||
5c042287 BW |
1205 | static bool do_idling(struct drm_i915_private *dev_priv) |
1206 | { | |
1207 | bool ret = dev_priv->mm.interruptible; | |
1208 | ||
a81cc00c | 1209 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1210 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1211 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1212 | DRM_ERROR("Couldn't idle GPU\n"); |
1213 | /* Wait a bit, in hopes it avoids the hang */ | |
1214 | udelay(10); | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | return ret; | |
1219 | } | |
1220 | ||
1221 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1222 | { | |
a81cc00c | 1223 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1224 | dev_priv->mm.interruptible = interruptible; |
1225 | } | |
1226 | ||
828c7908 BW |
1227 | void i915_check_and_clear_faults(struct drm_device *dev) |
1228 | { | |
1229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1230 | struct intel_ring_buffer *ring; | |
1231 | int i; | |
1232 | ||
1233 | if (INTEL_INFO(dev)->gen < 6) | |
1234 | return; | |
1235 | ||
1236 | for_each_ring(ring, dev_priv, i) { | |
1237 | u32 fault_reg; | |
1238 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1239 | if (fault_reg & RING_FAULT_VALID) { | |
1240 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1241 | "\tAddr: 0x%08lx\\n" | |
1242 | "\tAddress space: %s\n" | |
1243 | "\tSource ID: %d\n" | |
1244 | "\tType: %d\n", | |
1245 | fault_reg & PAGE_MASK, | |
1246 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1247 | RING_FAULT_SRCID(fault_reg), | |
1248 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1249 | I915_WRITE(RING_FAULT_REG(ring), | |
1250 | fault_reg & ~RING_FAULT_VALID); | |
1251 | } | |
1252 | } | |
1253 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1254 | } | |
1255 | ||
1256 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1257 | { | |
1258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1259 | ||
1260 | /* Don't bother messing with faults pre GEN6 as we have little | |
1261 | * documentation supporting that it's a good idea. | |
1262 | */ | |
1263 | if (INTEL_INFO(dev)->gen < 6) | |
1264 | return; | |
1265 | ||
1266 | i915_check_and_clear_faults(dev); | |
1267 | ||
1268 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1269 | dev_priv->gtt.base.start, |
1270 | dev_priv->gtt.base.total, | |
828c7908 BW |
1271 | false); |
1272 | } | |
1273 | ||
76aaf220 DV |
1274 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1275 | { | |
1276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1277 | struct drm_i915_gem_object *obj; |
80da2161 | 1278 | struct i915_address_space *vm; |
76aaf220 | 1279 | |
828c7908 BW |
1280 | i915_check_and_clear_faults(dev); |
1281 | ||
bee4a186 | 1282 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1283 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1284 | dev_priv->gtt.base.start, |
1285 | dev_priv->gtt.base.total, | |
828c7908 | 1286 | true); |
bee4a186 | 1287 | |
35c20a60 | 1288 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1289 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1290 | &dev_priv->gtt.base); | |
1291 | if (!vma) | |
1292 | continue; | |
1293 | ||
2c22569b | 1294 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1295 | /* The bind_vma code tries to be smart about tracking mappings. |
1296 | * Unfortunately above, we've just wiped out the mappings | |
1297 | * without telling our object about it. So we need to fake it. | |
1298 | */ | |
1299 | obj->has_global_gtt_mapping = 0; | |
1300 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1301 | } |
1302 | ||
80da2161 BW |
1303 | |
1304 | if (INTEL_INFO(dev)->gen >= 8) | |
1305 | return; | |
1306 | ||
1307 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1308 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1309 | if (i915_is_ggtt(vm)) { | |
1310 | if (dev_priv->mm.aliasing_ppgtt) | |
1311 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1312 | continue; | |
1313 | } | |
1314 | ||
1315 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1316 | } |
1317 | ||
e76e9aeb | 1318 | i915_gem_chipset_flush(dev); |
76aaf220 | 1319 | } |
7c2e6fdf | 1320 | |
74163907 | 1321 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1322 | { |
9da3da66 | 1323 | if (obj->has_dma_mapping) |
74163907 | 1324 | return 0; |
9da3da66 CW |
1325 | |
1326 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1327 | obj->pages->sgl, obj->pages->nents, | |
1328 | PCI_DMA_BIDIRECTIONAL)) | |
1329 | return -ENOSPC; | |
1330 | ||
1331 | return 0; | |
7c2e6fdf DV |
1332 | } |
1333 | ||
94ec8f61 BW |
1334 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1335 | { | |
1336 | #ifdef writeq | |
1337 | writeq(pte, addr); | |
1338 | #else | |
1339 | iowrite32((u32)pte, addr); | |
1340 | iowrite32(pte >> 32, addr + 4); | |
1341 | #endif | |
1342 | } | |
1343 | ||
1344 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1345 | struct sg_table *st, | |
782f1495 | 1346 | uint64_t start, |
94ec8f61 BW |
1347 | enum i915_cache_level level) |
1348 | { | |
1349 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1350 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1351 | gen8_gtt_pte_t __iomem *gtt_entries = |
1352 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1353 | int i = 0; | |
1354 | struct sg_page_iter sg_iter; | |
1355 | dma_addr_t addr; | |
1356 | ||
1357 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1358 | addr = sg_dma_address(sg_iter.sg) + | |
1359 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1360 | gen8_set_pte(>t_entries[i], | |
1361 | gen8_pte_encode(addr, level, true)); | |
1362 | i++; | |
1363 | } | |
1364 | ||
1365 | /* | |
1366 | * XXX: This serves as a posting read to make sure that the PTE has | |
1367 | * actually been updated. There is some concern that even though | |
1368 | * registers and PTEs are within the same BAR that they are potentially | |
1369 | * of NUMA access patterns. Therefore, even with the way we assume | |
1370 | * hardware should work, we must keep this posting read for paranoia. | |
1371 | */ | |
1372 | if (i != 0) | |
1373 | WARN_ON(readq(>t_entries[i-1]) | |
1374 | != gen8_pte_encode(addr, level, true)); | |
1375 | ||
94ec8f61 BW |
1376 | /* This next bit makes the above posting read even more important. We |
1377 | * want to flush the TLBs only after we're certain all the PTE updates | |
1378 | * have finished. | |
1379 | */ | |
1380 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1381 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1382 | } |
1383 | ||
e76e9aeb BW |
1384 | /* |
1385 | * Binds an object into the global gtt with the specified cache level. The object | |
1386 | * will be accessible to the GPU via commands whose operands reference offsets | |
1387 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1388 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1389 | */ | |
853ba5d2 | 1390 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1391 | struct sg_table *st, |
782f1495 | 1392 | uint64_t start, |
7faf1ab2 | 1393 | enum i915_cache_level level) |
e76e9aeb | 1394 | { |
853ba5d2 | 1395 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1396 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1397 | gen6_gtt_pte_t __iomem *gtt_entries = |
1398 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1399 | int i = 0; |
1400 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1401 | dma_addr_t addr; |
1402 | ||
6e995e23 | 1403 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1404 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1405 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1406 | i++; |
e76e9aeb BW |
1407 | } |
1408 | ||
e76e9aeb BW |
1409 | /* XXX: This serves as a posting read to make sure that the PTE has |
1410 | * actually been updated. There is some concern that even though | |
1411 | * registers and PTEs are within the same BAR that they are potentially | |
1412 | * of NUMA access patterns. Therefore, even with the way we assume | |
1413 | * hardware should work, we must keep this posting read for paranoia. | |
1414 | */ | |
1415 | if (i != 0) | |
853ba5d2 | 1416 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1417 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1418 | |
1419 | /* This next bit makes the above posting read even more important. We | |
1420 | * want to flush the TLBs only after we're certain all the PTE updates | |
1421 | * have finished. | |
1422 | */ | |
1423 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1424 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1425 | } |
1426 | ||
94ec8f61 | 1427 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1428 | uint64_t start, |
1429 | uint64_t length, | |
94ec8f61 BW |
1430 | bool use_scratch) |
1431 | { | |
1432 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1433 | unsigned first_entry = start >> PAGE_SHIFT; |
1434 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1435 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1436 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1437 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1438 | int i; | |
1439 | ||
1440 | if (WARN(num_entries > max_entries, | |
1441 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1442 | first_entry, num_entries, max_entries)) | |
1443 | num_entries = max_entries; | |
1444 | ||
1445 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1446 | I915_CACHE_LLC, | |
1447 | use_scratch); | |
1448 | for (i = 0; i < num_entries; i++) | |
1449 | gen8_set_pte(>t_base[i], scratch_pte); | |
1450 | readl(gtt_base); | |
1451 | } | |
1452 | ||
853ba5d2 | 1453 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1454 | uint64_t start, |
1455 | uint64_t length, | |
828c7908 | 1456 | bool use_scratch) |
7faf1ab2 | 1457 | { |
853ba5d2 | 1458 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1459 | unsigned first_entry = start >> PAGE_SHIFT; |
1460 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1461 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1462 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1463 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1464 | int i; |
1465 | ||
1466 | if (WARN(num_entries > max_entries, | |
1467 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1468 | first_entry, num_entries, max_entries)) | |
1469 | num_entries = max_entries; | |
1470 | ||
828c7908 BW |
1471 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1472 | ||
7faf1ab2 DV |
1473 | for (i = 0; i < num_entries; i++) |
1474 | iowrite32(scratch_pte, >t_base[i]); | |
1475 | readl(gtt_base); | |
1476 | } | |
1477 | ||
6f65e29a BW |
1478 | |
1479 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1480 | enum i915_cache_level cache_level, | |
1481 | u32 unused) | |
7faf1ab2 | 1482 | { |
6f65e29a | 1483 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1484 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1485 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1486 | ||
6f65e29a BW |
1487 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1488 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1489 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1490 | } |
1491 | ||
853ba5d2 | 1492 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1493 | uint64_t start, |
1494 | uint64_t length, | |
828c7908 | 1495 | bool unused) |
7faf1ab2 | 1496 | { |
782f1495 BW |
1497 | unsigned first_entry = start >> PAGE_SHIFT; |
1498 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1499 | intel_gtt_clear_range(first_entry, num_entries); |
1500 | } | |
1501 | ||
6f65e29a BW |
1502 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1503 | { | |
1504 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1505 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1506 | |
6f65e29a BW |
1507 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1508 | vma->obj->has_global_gtt_mapping = 0; | |
1509 | intel_gtt_clear_range(first, size); | |
1510 | } | |
7faf1ab2 | 1511 | |
6f65e29a BW |
1512 | static void ggtt_bind_vma(struct i915_vma *vma, |
1513 | enum i915_cache_level cache_level, | |
1514 | u32 flags) | |
d5bd1449 | 1515 | { |
6f65e29a | 1516 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1517 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1518 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1519 | |
6f65e29a BW |
1520 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1521 | * or we have a global mapping already but the cacheability flags have | |
1522 | * changed, set the global PTEs. | |
1523 | * | |
1524 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1525 | * instead if none of the above hold true. | |
1526 | * | |
1527 | * NB: A global mapping should only be needed for special regions like | |
1528 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1529 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1530 | */ | |
1531 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1532 | if (!obj->has_global_gtt_mapping || | |
1533 | (cache_level != obj->cache_level)) { | |
782f1495 BW |
1534 | vma->vm->insert_entries(vma->vm, obj->pages, |
1535 | vma->node.start, | |
6f65e29a BW |
1536 | cache_level); |
1537 | obj->has_global_gtt_mapping = 1; | |
1538 | } | |
1539 | } | |
d5bd1449 | 1540 | |
6f65e29a BW |
1541 | if (dev_priv->mm.aliasing_ppgtt && |
1542 | (!obj->has_aliasing_ppgtt_mapping || | |
1543 | (cache_level != obj->cache_level))) { | |
1544 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1545 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1546 | vma->obj->pages, |
1547 | vma->node.start, | |
1548 | cache_level); | |
6f65e29a BW |
1549 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
1550 | } | |
d5bd1449 CW |
1551 | } |
1552 | ||
6f65e29a | 1553 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1554 | { |
6f65e29a | 1555 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1556 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1557 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a BW |
1558 | |
1559 | if (obj->has_global_gtt_mapping) { | |
782f1495 BW |
1560 | vma->vm->clear_range(vma->vm, |
1561 | vma->node.start, | |
1562 | obj->base.size, | |
6f65e29a BW |
1563 | true); |
1564 | obj->has_global_gtt_mapping = 0; | |
1565 | } | |
74898d7e | 1566 | |
6f65e29a BW |
1567 | if (obj->has_aliasing_ppgtt_mapping) { |
1568 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1569 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1570 | vma->node.start, |
1571 | obj->base.size, | |
6f65e29a BW |
1572 | true); |
1573 | obj->has_aliasing_ppgtt_mapping = 0; | |
1574 | } | |
74163907 DV |
1575 | } |
1576 | ||
1577 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1578 | { |
5c042287 BW |
1579 | struct drm_device *dev = obj->base.dev; |
1580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1581 | bool interruptible; | |
1582 | ||
1583 | interruptible = do_idling(dev_priv); | |
1584 | ||
9da3da66 CW |
1585 | if (!obj->has_dma_mapping) |
1586 | dma_unmap_sg(&dev->pdev->dev, | |
1587 | obj->pages->sgl, obj->pages->nents, | |
1588 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1589 | |
1590 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1591 | } |
644ec02b | 1592 | |
42d6ab48 CW |
1593 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1594 | unsigned long color, | |
1595 | unsigned long *start, | |
1596 | unsigned long *end) | |
1597 | { | |
1598 | if (node->color != color) | |
1599 | *start += 4096; | |
1600 | ||
1601 | if (!list_empty(&node->node_list)) { | |
1602 | node = list_entry(node->node_list.next, | |
1603 | struct drm_mm_node, | |
1604 | node_list); | |
1605 | if (node->allocated && node->color != color) | |
1606 | *end -= 4096; | |
1607 | } | |
1608 | } | |
fbe5d36e | 1609 | |
d7e5008f BW |
1610 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1611 | unsigned long start, | |
1612 | unsigned long mappable_end, | |
1613 | unsigned long end) | |
644ec02b | 1614 | { |
e78891ca BW |
1615 | /* Let GEM Manage all of the aperture. |
1616 | * | |
1617 | * However, leave one page at the end still bound to the scratch page. | |
1618 | * There are a number of places where the hardware apparently prefetches | |
1619 | * past the end of the object, and we've seen multiple hangs with the | |
1620 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1621 | * aperture. One page should be enough to keep any prefetching inside | |
1622 | * of the aperture. | |
1623 | */ | |
40d74980 BW |
1624 | struct drm_i915_private *dev_priv = dev->dev_private; |
1625 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1626 | struct drm_mm_node *entry; |
1627 | struct drm_i915_gem_object *obj; | |
1628 | unsigned long hole_start, hole_end; | |
644ec02b | 1629 | |
35451cb6 BW |
1630 | BUG_ON(mappable_end > end); |
1631 | ||
ed2f3452 | 1632 | /* Subtract the guard page ... */ |
40d74980 | 1633 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1634 | if (!HAS_LLC(dev)) |
93bd8649 | 1635 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1636 | |
ed2f3452 | 1637 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1638 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1639 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1640 | int ret; |
edd41a87 | 1641 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1642 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1643 | ||
1644 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1645 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1646 | if (ret) |
b3a070cc | 1647 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1648 | obj->has_global_gtt_mapping = 1; |
1649 | } | |
1650 | ||
853ba5d2 BW |
1651 | dev_priv->gtt.base.start = start; |
1652 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1653 | |
ed2f3452 | 1654 | /* Clear any non-preallocated blocks */ |
40d74980 | 1655 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1656 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1657 | hole_start, hole_end); | |
782f1495 BW |
1658 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1659 | hole_end - hole_start, true); | |
ed2f3452 CW |
1660 | } |
1661 | ||
1662 | /* And finally clear the reserved guard page */ | |
782f1495 | 1663 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
e76e9aeb BW |
1664 | } |
1665 | ||
d7e5008f BW |
1666 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1667 | { | |
1668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1669 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1670 | |
853ba5d2 | 1671 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1672 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1673 | |
e78891ca | 1674 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1675 | } |
1676 | ||
1677 | static int setup_scratch_page(struct drm_device *dev) | |
1678 | { | |
1679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1680 | struct page *page; | |
1681 | dma_addr_t dma_addr; | |
1682 | ||
1683 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1684 | if (page == NULL) | |
1685 | return -ENOMEM; | |
1686 | get_page(page); | |
1687 | set_pages_uc(page, 1); | |
1688 | ||
1689 | #ifdef CONFIG_INTEL_IOMMU | |
1690 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1691 | PCI_DMA_BIDIRECTIONAL); | |
1692 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1693 | return -EINVAL; | |
1694 | #else | |
1695 | dma_addr = page_to_phys(page); | |
1696 | #endif | |
853ba5d2 BW |
1697 | dev_priv->gtt.base.scratch.page = page; |
1698 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1699 | |
1700 | return 0; | |
1701 | } | |
1702 | ||
1703 | static void teardown_scratch_page(struct drm_device *dev) | |
1704 | { | |
1705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1706 | struct page *page = dev_priv->gtt.base.scratch.page; |
1707 | ||
1708 | set_pages_wb(page, 1); | |
1709 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1710 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1711 | put_page(page); |
1712 | __free_page(page); | |
e76e9aeb BW |
1713 | } |
1714 | ||
1715 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1716 | { | |
1717 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1718 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1719 | return snb_gmch_ctl << 20; | |
1720 | } | |
1721 | ||
9459d252 BW |
1722 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1723 | { | |
1724 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1725 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1726 | if (bdw_gmch_ctl) | |
1727 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
1728 | return bdw_gmch_ctl << 20; | |
1729 | } | |
1730 | ||
baa09f5f | 1731 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1732 | { |
1733 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1734 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1735 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1736 | } | |
1737 | ||
9459d252 BW |
1738 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1739 | { | |
1740 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1741 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1742 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1743 | } | |
1744 | ||
63340133 BW |
1745 | static int ggtt_probe_common(struct drm_device *dev, |
1746 | size_t gtt_size) | |
1747 | { | |
1748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1749 | phys_addr_t gtt_bus_addr; | |
1750 | int ret; | |
1751 | ||
1752 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1753 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1754 | (pci_resource_len(dev->pdev, 0) / 2); | |
1755 | ||
1756 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1757 | if (!dev_priv->gtt.gsm) { | |
1758 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1759 | return -ENOMEM; | |
1760 | } | |
1761 | ||
1762 | ret = setup_scratch_page(dev); | |
1763 | if (ret) { | |
1764 | DRM_ERROR("Scratch setup failed\n"); | |
1765 | /* iounmap will also get called at remove, but meh */ | |
1766 | iounmap(dev_priv->gtt.gsm); | |
1767 | } | |
1768 | ||
1769 | return ret; | |
1770 | } | |
1771 | ||
fbe5d36e BW |
1772 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1773 | * bits. When using advanced contexts each context stores its own PAT, but | |
1774 | * writing this data shouldn't be harmful even in those cases. */ | |
1775 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1776 | { | |
1777 | #define GEN8_PPAT_UC (0<<0) | |
1778 | #define GEN8_PPAT_WC (1<<0) | |
1779 | #define GEN8_PPAT_WT (2<<0) | |
1780 | #define GEN8_PPAT_WB (3<<0) | |
1781 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1782 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1783 | #define GEN8_PPAT_LLC (1<<2) | |
1784 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1785 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1786 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1787 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1788 | uint64_t pat; | |
1789 | ||
1790 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1791 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1792 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1793 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1794 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1795 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1796 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1797 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1798 | ||
1799 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1800 | * write would work. */ | |
1801 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1802 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1803 | } | |
1804 | ||
63340133 BW |
1805 | static int gen8_gmch_probe(struct drm_device *dev, |
1806 | size_t *gtt_total, | |
1807 | size_t *stolen, | |
1808 | phys_addr_t *mappable_base, | |
1809 | unsigned long *mappable_end) | |
1810 | { | |
1811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1812 | unsigned int gtt_size; | |
1813 | u16 snb_gmch_ctl; | |
1814 | int ret; | |
1815 | ||
1816 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1817 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1818 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1819 | ||
1820 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1821 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1822 | ||
1823 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1824 | ||
1825 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1826 | ||
1827 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1828 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1829 | |
fbe5d36e BW |
1830 | gen8_setup_private_ppat(dev_priv); |
1831 | ||
63340133 BW |
1832 | ret = ggtt_probe_common(dev, gtt_size); |
1833 | ||
94ec8f61 BW |
1834 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1835 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1836 | |
1837 | return ret; | |
1838 | } | |
1839 | ||
baa09f5f BW |
1840 | static int gen6_gmch_probe(struct drm_device *dev, |
1841 | size_t *gtt_total, | |
41907ddc BW |
1842 | size_t *stolen, |
1843 | phys_addr_t *mappable_base, | |
1844 | unsigned long *mappable_end) | |
e76e9aeb BW |
1845 | { |
1846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1847 | unsigned int gtt_size; |
e76e9aeb | 1848 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1849 | int ret; |
1850 | ||
41907ddc BW |
1851 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1852 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1853 | ||
baa09f5f BW |
1854 | /* 64/512MB is the current min/max we actually know of, but this is just |
1855 | * a coarse sanity check. | |
e76e9aeb | 1856 | */ |
41907ddc | 1857 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1858 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1859 | dev_priv->gtt.mappable_end); | |
1860 | return -ENXIO; | |
e76e9aeb BW |
1861 | } |
1862 | ||
e76e9aeb BW |
1863 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1864 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1865 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1866 | |
c4ae25ec | 1867 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1868 | |
63340133 BW |
1869 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1870 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1871 | |
63340133 | 1872 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1873 | |
853ba5d2 BW |
1874 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1875 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1876 | |
e76e9aeb BW |
1877 | return ret; |
1878 | } | |
1879 | ||
853ba5d2 | 1880 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1881 | { |
853ba5d2 BW |
1882 | |
1883 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1884 | |
1885 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1886 | iounmap(gtt->gsm); |
1887 | teardown_scratch_page(vm->dev); | |
644ec02b | 1888 | } |
baa09f5f BW |
1889 | |
1890 | static int i915_gmch_probe(struct drm_device *dev, | |
1891 | size_t *gtt_total, | |
41907ddc BW |
1892 | size_t *stolen, |
1893 | phys_addr_t *mappable_base, | |
1894 | unsigned long *mappable_end) | |
baa09f5f BW |
1895 | { |
1896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1897 | int ret; | |
1898 | ||
baa09f5f BW |
1899 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1900 | if (!ret) { | |
1901 | DRM_ERROR("failed to set up gmch\n"); | |
1902 | return -EIO; | |
1903 | } | |
1904 | ||
41907ddc | 1905 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1906 | |
1907 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1908 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 1909 | |
c0a7f818 CW |
1910 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
1911 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
1912 | ||
baa09f5f BW |
1913 | return 0; |
1914 | } | |
1915 | ||
853ba5d2 | 1916 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1917 | { |
1918 | intel_gmch_remove(); | |
1919 | } | |
1920 | ||
1921 | int i915_gem_gtt_init(struct drm_device *dev) | |
1922 | { | |
1923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1924 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1925 | int ret; |
1926 | ||
baa09f5f | 1927 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1928 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1929 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1930 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1931 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1932 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1933 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1934 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1935 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1936 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1937 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1938 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1939 | else if (INTEL_INFO(dev)->gen >= 7) |
1940 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1941 | else |
350ec881 | 1942 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1943 | } else { |
1944 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1945 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1946 | } |
1947 | ||
853ba5d2 | 1948 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1949 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1950 | if (ret) |
baa09f5f | 1951 | return ret; |
baa09f5f | 1952 | |
853ba5d2 BW |
1953 | gtt->base.dev = dev; |
1954 | ||
baa09f5f | 1955 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1956 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1957 | gtt->base.total >> 20); | |
b2f21b4d BW |
1958 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1959 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1960 | |
1961 | return 0; | |
1962 | } | |
6f65e29a BW |
1963 | |
1964 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
1965 | struct i915_address_space *vm) | |
1966 | { | |
1967 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
1968 | if (vma == NULL) | |
1969 | return ERR_PTR(-ENOMEM); | |
1970 | ||
1971 | INIT_LIST_HEAD(&vma->vma_link); | |
1972 | INIT_LIST_HEAD(&vma->mm_list); | |
1973 | INIT_LIST_HEAD(&vma->exec_list); | |
1974 | vma->vm = vm; | |
1975 | vma->obj = obj; | |
1976 | ||
1977 | switch (INTEL_INFO(vm->dev)->gen) { | |
1978 | case 8: | |
1979 | case 7: | |
1980 | case 6: | |
7e0d96bc BW |
1981 | if (i915_is_ggtt(vm)) { |
1982 | vma->unbind_vma = ggtt_unbind_vma; | |
1983 | vma->bind_vma = ggtt_bind_vma; | |
1984 | } else { | |
1985 | vma->unbind_vma = ppgtt_unbind_vma; | |
1986 | vma->bind_vma = ppgtt_bind_vma; | |
1987 | } | |
6f65e29a BW |
1988 | break; |
1989 | case 5: | |
1990 | case 4: | |
1991 | case 3: | |
1992 | case 2: | |
1993 | BUG_ON(!i915_is_ggtt(vm)); | |
1994 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
1995 | vma->bind_vma = i915_ggtt_bind_vma; | |
1996 | break; | |
1997 | default: | |
1998 | BUG(); | |
1999 | } | |
2000 | ||
2001 | /* Keep GGTT vmas first to make debug easier */ | |
2002 | if (i915_is_ggtt(vm)) | |
2003 | list_add(&vma->vma_link, &obj->vma_list); | |
2004 | else | |
2005 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
2006 | ||
2007 | return vma; | |
2008 | } | |
2009 | ||
2010 | struct i915_vma * | |
2011 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2012 | struct i915_address_space *vm) | |
2013 | { | |
2014 | struct i915_vma *vma; | |
2015 | ||
2016 | vma = i915_gem_obj_to_vma(obj, vm); | |
2017 | if (!vma) | |
2018 | vma = __i915_gem_vma_create(obj, vm); | |
2019 | ||
2020 | return vma; | |
2021 | } |