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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
93a25a9e DV |
33 | bool intel_enable_ppgtt(struct drm_device *dev, bool full) |
34 | { | |
35 | if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | |
36 | return false; | |
37 | ||
38 | if (i915.enable_ppgtt == 1 && full) | |
39 | return false; | |
40 | ||
41 | #ifdef CONFIG_INTEL_IOMMU | |
42 | /* Disable ppgtt on SNB if VT-d is on. */ | |
43 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
44 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
45 | return false; | |
46 | } | |
47 | #endif | |
48 | ||
49 | /* Full ppgtt disabled by default for now due to issues. */ | |
50 | if (full) | |
51 | return false; /* HAS_PPGTT(dev) */ | |
52 | else | |
53 | return HAS_ALIASING_PPGTT(dev); | |
54 | } | |
55 | ||
6670a5a5 BW |
56 | #define GEN6_PPGTT_PD_ENTRIES 512 |
57 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 58 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 59 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 60 | |
26b1ff35 BW |
61 | /* PPGTT stuff */ |
62 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 63 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
64 | |
65 | #define GEN6_PDE_VALID (1 << 0) | |
66 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
67 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
68 | ||
69 | #define GEN6_PTE_VALID (1 << 0) | |
70 | #define GEN6_PTE_UNCACHED (1 << 1) | |
71 | #define HSW_PTE_UNCACHED (0) | |
72 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 73 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 74 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
75 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
76 | ||
77 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
78 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
79 | */ | |
80 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
81 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 82 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 83 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 84 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
c51e9701 | 85 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
651d794f | 86 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
c51e9701 | 87 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
26b1ff35 | 88 | |
459108b8 | 89 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a | 90 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
7ad47cf2 BW |
91 | |
92 | /* GEN8 legacy style addressis defined as a 3 level page table: | |
93 | * 31:30 | 29:21 | 20:12 | 11:0 | |
94 | * PDPE | PDE | PTE | offset | |
95 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
96 | * programmed via register. | |
97 | */ | |
98 | #define GEN8_PDPE_SHIFT 30 | |
99 | #define GEN8_PDPE_MASK 0x3 | |
100 | #define GEN8_PDE_SHIFT 21 | |
101 | #define GEN8_PDE_MASK 0x1ff | |
102 | #define GEN8_PTE_SHIFT 12 | |
103 | #define GEN8_PTE_MASK 0x1ff | |
37aca44a | 104 | |
fbe5d36e BW |
105 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
106 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
107 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
108 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
109 | ||
6f65e29a BW |
110 | static void ppgtt_bind_vma(struct i915_vma *vma, |
111 | enum i915_cache_level cache_level, | |
112 | u32 flags); | |
113 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 114 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 115 | |
94ec8f61 BW |
116 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
117 | enum i915_cache_level level, | |
118 | bool valid) | |
119 | { | |
120 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
121 | pte |= addr; | |
fbe5d36e BW |
122 | if (level != I915_CACHE_NONE) |
123 | pte |= PPAT_CACHED_INDEX; | |
124 | else | |
125 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
126 | return pte; |
127 | } | |
128 | ||
b1fe6673 BW |
129 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
130 | dma_addr_t addr, | |
131 | enum i915_cache_level level) | |
132 | { | |
133 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
134 | pde |= addr; | |
135 | if (level != I915_CACHE_NONE) | |
136 | pde |= PPAT_CACHED_PDE_INDEX; | |
137 | else | |
138 | pde |= PPAT_UNCACHED_INDEX; | |
139 | return pde; | |
140 | } | |
141 | ||
350ec881 | 142 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
143 | enum i915_cache_level level, |
144 | bool valid) | |
54d12527 | 145 | { |
b35b380e | 146 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 147 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
148 | |
149 | switch (level) { | |
350ec881 CW |
150 | case I915_CACHE_L3_LLC: |
151 | case I915_CACHE_LLC: | |
152 | pte |= GEN6_PTE_CACHE_LLC; | |
153 | break; | |
154 | case I915_CACHE_NONE: | |
155 | pte |= GEN6_PTE_UNCACHED; | |
156 | break; | |
157 | default: | |
158 | WARN_ON(1); | |
159 | } | |
160 | ||
161 | return pte; | |
162 | } | |
163 | ||
164 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
165 | enum i915_cache_level level, |
166 | bool valid) | |
350ec881 | 167 | { |
b35b380e | 168 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
169 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
170 | ||
171 | switch (level) { | |
172 | case I915_CACHE_L3_LLC: | |
173 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
174 | break; |
175 | case I915_CACHE_LLC: | |
176 | pte |= GEN6_PTE_CACHE_LLC; | |
177 | break; | |
178 | case I915_CACHE_NONE: | |
9119708c | 179 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
180 | break; |
181 | default: | |
350ec881 | 182 | WARN_ON(1); |
e7210c3c BW |
183 | } |
184 | ||
54d12527 BW |
185 | return pte; |
186 | } | |
187 | ||
93c34e70 KG |
188 | #define BYT_PTE_WRITEABLE (1 << 1) |
189 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
190 | ||
80a74f7f | 191 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
192 | enum i915_cache_level level, |
193 | bool valid) | |
93c34e70 | 194 | { |
b35b380e | 195 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
196 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
197 | ||
198 | /* Mark the page as writeable. Other platforms don't have a | |
199 | * setting for read-only/writable, so this matches that behavior. | |
200 | */ | |
201 | pte |= BYT_PTE_WRITEABLE; | |
202 | ||
203 | if (level != I915_CACHE_NONE) | |
204 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
205 | ||
206 | return pte; | |
207 | } | |
208 | ||
80a74f7f | 209 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
210 | enum i915_cache_level level, |
211 | bool valid) | |
9119708c | 212 | { |
b35b380e | 213 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 214 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
215 | |
216 | if (level != I915_CACHE_NONE) | |
87a6b688 | 217 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
218 | |
219 | return pte; | |
220 | } | |
221 | ||
4d15c145 | 222 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
223 | enum i915_cache_level level, |
224 | bool valid) | |
4d15c145 | 225 | { |
b35b380e | 226 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
227 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
228 | ||
651d794f CW |
229 | switch (level) { |
230 | case I915_CACHE_NONE: | |
231 | break; | |
232 | case I915_CACHE_WT: | |
c51e9701 | 233 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
234 | break; |
235 | default: | |
c51e9701 | 236 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
237 | break; |
238 | } | |
4d15c145 BW |
239 | |
240 | return pte; | |
241 | } | |
242 | ||
94e409c1 BW |
243 | /* Broadwell Page Directory Pointer Descriptors */ |
244 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 245 | uint64_t val, bool synchronous) |
94e409c1 | 246 | { |
e178f705 | 247 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
248 | int ret; |
249 | ||
250 | BUG_ON(entry >= 4); | |
251 | ||
e178f705 BW |
252 | if (synchronous) { |
253 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
254 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
255 | return 0; | |
256 | } | |
257 | ||
94e409c1 BW |
258 | ret = intel_ring_begin(ring, 6); |
259 | if (ret) | |
260 | return ret; | |
261 | ||
262 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
263 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
264 | intel_ring_emit(ring, (u32)(val >> 32)); | |
265 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
266 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
267 | intel_ring_emit(ring, (u32)(val)); | |
268 | intel_ring_advance(ring); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
eeb9488e BW |
273 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
274 | struct intel_ring_buffer *ring, | |
275 | bool synchronous) | |
94e409c1 | 276 | { |
eeb9488e | 277 | int i, ret; |
94e409c1 BW |
278 | |
279 | /* bit of a hack to find the actual last used pd */ | |
280 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
281 | ||
94e409c1 BW |
282 | for (i = used_pd - 1; i >= 0; i--) { |
283 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
284 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
285 | if (ret) | |
286 | return ret; | |
94e409c1 | 287 | } |
d595bd4b | 288 | |
eeb9488e | 289 | return 0; |
94e409c1 BW |
290 | } |
291 | ||
459108b8 | 292 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
293 | uint64_t start, |
294 | uint64_t length, | |
459108b8 BW |
295 | bool use_scratch) |
296 | { | |
297 | struct i915_hw_ppgtt *ppgtt = | |
298 | container_of(vm, struct i915_hw_ppgtt, base); | |
299 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
300 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
301 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
302 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 303 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
304 | unsigned last_pte, i; |
305 | ||
306 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
307 | I915_CACHE_LLC, use_scratch); | |
308 | ||
309 | while (num_entries) { | |
7ad47cf2 | 310 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 311 | |
7ad47cf2 | 312 | last_pte = pte + num_entries; |
459108b8 BW |
313 | if (last_pte > GEN8_PTES_PER_PAGE) |
314 | last_pte = GEN8_PTES_PER_PAGE; | |
315 | ||
316 | pt_vaddr = kmap_atomic(page_table); | |
317 | ||
7ad47cf2 | 318 | for (i = pte; i < last_pte; i++) { |
459108b8 | 319 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
320 | num_entries--; |
321 | } | |
459108b8 BW |
322 | |
323 | kunmap_atomic(pt_vaddr); | |
324 | ||
7ad47cf2 BW |
325 | pte = 0; |
326 | if (++pde == GEN8_PDES_PER_PAGE) { | |
327 | pdpe++; | |
328 | pde = 0; | |
329 | } | |
459108b8 BW |
330 | } |
331 | } | |
332 | ||
9df15b49 BW |
333 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
334 | struct sg_table *pages, | |
782f1495 | 335 | uint64_t start, |
9df15b49 BW |
336 | enum i915_cache_level cache_level) |
337 | { | |
338 | struct i915_hw_ppgtt *ppgtt = | |
339 | container_of(vm, struct i915_hw_ppgtt, base); | |
340 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
341 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
342 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
343 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
344 | struct sg_page_iter sg_iter; |
345 | ||
6f1cc993 | 346 | pt_vaddr = NULL; |
7ad47cf2 | 347 | |
9df15b49 | 348 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
349 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
350 | break; | |
351 | ||
6f1cc993 | 352 | if (pt_vaddr == NULL) |
7ad47cf2 | 353 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 354 | |
7ad47cf2 | 355 | pt_vaddr[pte] = |
6f1cc993 CW |
356 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
357 | cache_level, true); | |
7ad47cf2 | 358 | if (++pte == GEN8_PTES_PER_PAGE) { |
9df15b49 | 359 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 360 | pt_vaddr = NULL; |
7ad47cf2 BW |
361 | if (++pde == GEN8_PDES_PER_PAGE) { |
362 | pdpe++; | |
363 | pde = 0; | |
364 | } | |
365 | pte = 0; | |
9df15b49 BW |
366 | } |
367 | } | |
6f1cc993 CW |
368 | if (pt_vaddr) |
369 | kunmap_atomic(pt_vaddr); | |
9df15b49 BW |
370 | } |
371 | ||
7ad47cf2 BW |
372 | static void gen8_free_page_tables(struct page **pt_pages) |
373 | { | |
374 | int i; | |
375 | ||
376 | if (pt_pages == NULL) | |
377 | return; | |
378 | ||
379 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
380 | if (pt_pages[i]) | |
381 | __free_pages(pt_pages[i], 0); | |
382 | } | |
383 | ||
384 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
385 | { |
386 | int i; | |
387 | ||
7ad47cf2 BW |
388 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
389 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
390 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 391 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 392 | } |
b45a6715 | 393 | |
b45a6715 BW |
394 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
395 | } | |
396 | ||
397 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
398 | { | |
f3a964b9 | 399 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
400 | int i, j; |
401 | ||
402 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
403 | /* TODO: In the future we'll support sparse mappings, so this | |
404 | * will have to change. */ | |
405 | if (!ppgtt->pd_dma_addr[i]) | |
406 | continue; | |
407 | ||
f3a964b9 BW |
408 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
409 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
410 | |
411 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
412 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
413 | if (addr) | |
f3a964b9 BW |
414 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
415 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
416 | } |
417 | } | |
418 | } | |
419 | ||
37aca44a BW |
420 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
421 | { | |
422 | struct i915_hw_ppgtt *ppgtt = | |
423 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 424 | |
7e0d96bc | 425 | list_del(&vm->global_link); |
686e1f6f BW |
426 | drm_mm_takedown(&vm->mm); |
427 | ||
b45a6715 BW |
428 | gen8_ppgtt_unmap_pages(ppgtt); |
429 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
430 | } |
431 | ||
7ad47cf2 BW |
432 | static struct page **__gen8_alloc_page_tables(void) |
433 | { | |
434 | struct page **pt_pages; | |
435 | int i; | |
436 | ||
437 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
438 | if (!pt_pages) | |
439 | return ERR_PTR(-ENOMEM); | |
440 | ||
441 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
442 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
443 | if (!pt_pages[i]) | |
444 | goto bail; | |
445 | } | |
446 | ||
447 | return pt_pages; | |
448 | ||
449 | bail: | |
450 | gen8_free_page_tables(pt_pages); | |
451 | kfree(pt_pages); | |
452 | return ERR_PTR(-ENOMEM); | |
453 | } | |
454 | ||
bf2b4ed2 BW |
455 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
456 | const int max_pdp) | |
457 | { | |
7ad47cf2 | 458 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 459 | int i, ret; |
bf2b4ed2 | 460 | |
7ad47cf2 BW |
461 | for (i = 0; i < max_pdp; i++) { |
462 | pt_pages[i] = __gen8_alloc_page_tables(); | |
463 | if (IS_ERR(pt_pages[i])) { | |
464 | ret = PTR_ERR(pt_pages[i]); | |
465 | goto unwind_out; | |
466 | } | |
467 | } | |
468 | ||
469 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
470 | * "atomic" - for cleanup purposes. | |
471 | */ | |
472 | for (i = 0; i < max_pdp; i++) | |
473 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 474 | |
bf2b4ed2 | 475 | return 0; |
7ad47cf2 BW |
476 | |
477 | unwind_out: | |
478 | while (i--) { | |
479 | gen8_free_page_tables(pt_pages[i]); | |
480 | kfree(pt_pages[i]); | |
481 | } | |
482 | ||
483 | return ret; | |
bf2b4ed2 BW |
484 | } |
485 | ||
486 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
487 | { | |
488 | int i; | |
489 | ||
490 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
491 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
492 | sizeof(dma_addr_t), | |
493 | GFP_KERNEL); | |
494 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
495 | return -ENOMEM; | |
496 | } | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
502 | const int max_pdp) | |
503 | { | |
504 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
505 | if (!ppgtt->pd_pages) | |
506 | return -ENOMEM; | |
507 | ||
508 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
509 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
515 | const int max_pdp) | |
516 | { | |
517 | int ret; | |
518 | ||
519 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
520 | if (ret) | |
521 | return ret; | |
522 | ||
523 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
524 | if (ret) { | |
525 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
526 | return ret; | |
527 | } | |
528 | ||
529 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
530 | ||
531 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
532 | if (ret) | |
533 | gen8_ppgtt_free(ppgtt); | |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
538 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
539 | const int pd) | |
540 | { | |
541 | dma_addr_t pd_addr; | |
542 | int ret; | |
543 | ||
544 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
545 | &ppgtt->pd_pages[pd], 0, | |
546 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
547 | ||
548 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
549 | if (ret) | |
550 | return ret; | |
551 | ||
552 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
558 | const int pd, | |
559 | const int pt) | |
560 | { | |
561 | dma_addr_t pt_addr; | |
562 | struct page *p; | |
563 | int ret; | |
564 | ||
7ad47cf2 | 565 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
566 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
567 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
568 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
569 | if (ret) | |
570 | return ret; | |
571 | ||
572 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
573 | ||
574 | return 0; | |
575 | } | |
576 | ||
37aca44a | 577 | /** |
f3a964b9 BW |
578 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
579 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
580 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
581 | * space. | |
37aca44a | 582 | * |
f3a964b9 BW |
583 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
584 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 585 | * TODO: Do something with the size parameter |
f3a964b9 | 586 | */ |
37aca44a BW |
587 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
588 | { | |
37aca44a | 589 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 590 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 591 | int i, j, ret; |
37aca44a BW |
592 | |
593 | if (size % (1<<30)) | |
594 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
595 | ||
bf2b4ed2 BW |
596 | /* 1. Do all our allocations for page directories and page tables. */ |
597 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
598 | if (ret) | |
599 | return ret; | |
f3a964b9 | 600 | |
37aca44a | 601 | /* |
bf2b4ed2 | 602 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
603 | */ |
604 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 605 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
606 | if (ret) |
607 | goto bail; | |
37aca44a | 608 | |
37aca44a | 609 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 610 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
611 | if (ret) |
612 | goto bail; | |
37aca44a BW |
613 | } |
614 | } | |
615 | ||
f3a964b9 BW |
616 | /* |
617 | * 3. Map all the page directory entires to point to the page tables | |
618 | * we've allocated. | |
619 | * | |
620 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 621 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
622 | * will never need to touch the PDEs again. |
623 | */ | |
b1fe6673 BW |
624 | for (i = 0; i < max_pdp; i++) { |
625 | gen8_ppgtt_pde_t *pd_vaddr; | |
626 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
627 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
628 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
629 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
630 | I915_CACHE_LLC); | |
631 | } | |
632 | kunmap_atomic(pd_vaddr); | |
633 | } | |
634 | ||
f3a964b9 BW |
635 | ppgtt->enable = gen8_ppgtt_enable; |
636 | ppgtt->switch_mm = gen8_mm_switch; | |
637 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
638 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
639 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
640 | ppgtt->base.start = 0; | |
5abbcca3 | 641 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 642 | |
5abbcca3 | 643 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 644 | |
37aca44a BW |
645 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
646 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
647 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
648 | ppgtt->num_pd_entries, |
649 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 650 | return 0; |
37aca44a | 651 | |
f3a964b9 BW |
652 | bail: |
653 | gen8_ppgtt_unmap_pages(ppgtt); | |
654 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
655 | return ret; |
656 | } | |
657 | ||
87d60b63 BW |
658 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
659 | { | |
660 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
661 | struct i915_address_space *vm = &ppgtt->base; | |
662 | gen6_gtt_pte_t __iomem *pd_addr; | |
663 | gen6_gtt_pte_t scratch_pte; | |
664 | uint32_t pd_entry; | |
665 | int pte, pde; | |
666 | ||
667 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); | |
668 | ||
669 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
670 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
671 | ||
672 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
673 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
674 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
675 | u32 expected; | |
676 | gen6_gtt_pte_t *pt_vaddr; | |
677 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
678 | pd_entry = readl(pd_addr + pde); | |
679 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
680 | ||
681 | if (pd_entry != expected) | |
682 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
683 | pde, | |
684 | pd_entry, | |
685 | expected); | |
686 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
687 | ||
688 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
689 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
690 | unsigned long va = | |
691 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
692 | (pte * PAGE_SIZE); | |
693 | int i; | |
694 | bool found = false; | |
695 | for (i = 0; i < 4; i++) | |
696 | if (pt_vaddr[pte + i] != scratch_pte) | |
697 | found = true; | |
698 | if (!found) | |
699 | continue; | |
700 | ||
701 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
702 | for (i = 0; i < 4; i++) { | |
703 | if (pt_vaddr[pte + i] != scratch_pte) | |
704 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
705 | else | |
706 | seq_puts(m, " SCRATCH "); | |
707 | } | |
708 | seq_puts(m, "\n"); | |
709 | } | |
710 | kunmap_atomic(pt_vaddr); | |
711 | } | |
712 | } | |
713 | ||
3e302542 | 714 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 715 | { |
853ba5d2 | 716 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
717 | gen6_gtt_pte_t __iomem *pd_addr; |
718 | uint32_t pd_entry; | |
719 | int i; | |
720 | ||
0a732870 | 721 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
722 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
723 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
724 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
725 | dma_addr_t pt_addr; | |
726 | ||
727 | pt_addr = ppgtt->pt_dma_addr[i]; | |
728 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
729 | pd_entry |= GEN6_PDE_VALID; | |
730 | ||
731 | writel(pd_entry, pd_addr + i); | |
732 | } | |
733 | readl(pd_addr); | |
3e302542 BW |
734 | } |
735 | ||
b4a74e3a | 736 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 737 | { |
b4a74e3a BW |
738 | BUG_ON(ppgtt->pd_offset & 0x3f); |
739 | ||
740 | return (ppgtt->pd_offset / 64) << 16; | |
741 | } | |
742 | ||
90252e5c BW |
743 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
744 | struct intel_ring_buffer *ring, | |
745 | bool synchronous) | |
746 | { | |
747 | struct drm_device *dev = ppgtt->base.dev; | |
748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
749 | int ret; | |
750 | ||
751 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
752 | * manually frob these bits. Ideally we could use the ring functions, | |
753 | * except our error handling makes it quite difficult (can't use | |
754 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
755 | * | |
756 | * FIXME: We should try not to special case reset | |
757 | */ | |
758 | if (synchronous || | |
759 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
760 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
761 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
762 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
763 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
764 | return 0; | |
765 | } | |
766 | ||
767 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
768 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
769 | if (ret) | |
770 | return ret; | |
771 | ||
772 | ret = intel_ring_begin(ring, 6); | |
773 | if (ret) | |
774 | return ret; | |
775 | ||
776 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
777 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
778 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
779 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
780 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
781 | intel_ring_emit(ring, MI_NOOP); | |
782 | intel_ring_advance(ring); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
48a10389 BW |
787 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
788 | struct intel_ring_buffer *ring, | |
789 | bool synchronous) | |
790 | { | |
791 | struct drm_device *dev = ppgtt->base.dev; | |
792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
793 | int ret; | |
794 | ||
795 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
796 | * manually frob these bits. Ideally we could use the ring functions, | |
797 | * except our error handling makes it quite difficult (can't use | |
798 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
799 | * | |
800 | * FIXME: We should try not to special case reset | |
801 | */ | |
802 | if (synchronous || | |
803 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
804 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
805 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
806 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
807 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
808 | return 0; | |
809 | } | |
810 | ||
811 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
812 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
813 | if (ret) | |
814 | return ret; | |
815 | ||
816 | ret = intel_ring_begin(ring, 6); | |
817 | if (ret) | |
818 | return ret; | |
819 | ||
820 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
821 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
822 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
823 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
824 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
825 | intel_ring_emit(ring, MI_NOOP); | |
826 | intel_ring_advance(ring); | |
827 | ||
90252e5c BW |
828 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
829 | if (ring->id != RCS) { | |
830 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
831 | if (ret) | |
832 | return ret; | |
833 | } | |
834 | ||
48a10389 BW |
835 | return 0; |
836 | } | |
837 | ||
eeb9488e BW |
838 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
839 | struct intel_ring_buffer *ring, | |
840 | bool synchronous) | |
841 | { | |
842 | struct drm_device *dev = ppgtt->base.dev; | |
843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
844 | ||
48a10389 BW |
845 | if (!synchronous) |
846 | return 0; | |
847 | ||
eeb9488e BW |
848 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
849 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
850 | ||
851 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
856 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
857 | { | |
858 | struct drm_device *dev = ppgtt->base.dev; | |
859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3e302542 | 860 | struct intel_ring_buffer *ring; |
eeb9488e | 861 | int j, ret; |
3e302542 | 862 | |
eeb9488e BW |
863 | for_each_ring(ring, dev_priv, j) { |
864 | I915_WRITE(RING_MODE_GEN7(ring), | |
865 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
3e302542 | 866 | |
d2ff7192 BW |
867 | /* We promise to do a switch later with FULL PPGTT. If this is |
868 | * aliasing, this is the one and only switch we'll do */ | |
869 | if (USES_FULL_PPGTT(dev)) | |
870 | continue; | |
6197349b | 871 | |
eeb9488e BW |
872 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
873 | if (ret) | |
874 | goto err_out; | |
875 | } | |
6197349b | 876 | |
eeb9488e | 877 | return 0; |
6197349b | 878 | |
eeb9488e BW |
879 | err_out: |
880 | for_each_ring(ring, dev_priv, j) | |
881 | I915_WRITE(RING_MODE_GEN7(ring), | |
882 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
883 | return ret; | |
884 | } | |
6197349b | 885 | |
b4a74e3a | 886 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 887 | { |
a3d67d23 | 888 | struct drm_device *dev = ppgtt->base.dev; |
3e302542 | 889 | drm_i915_private_t *dev_priv = dev->dev_private; |
3e302542 | 890 | struct intel_ring_buffer *ring; |
b4a74e3a | 891 | uint32_t ecochk, ecobits; |
3e302542 | 892 | int i; |
6197349b | 893 | |
b4a74e3a BW |
894 | ecobits = I915_READ(GAC_ECO_BITS); |
895 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 896 | |
b4a74e3a BW |
897 | ecochk = I915_READ(GAM_ECOCHK); |
898 | if (IS_HASWELL(dev)) { | |
899 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
900 | } else { | |
901 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
902 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
903 | } | |
904 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 905 | |
b4a74e3a | 906 | for_each_ring(ring, dev_priv, i) { |
eeb9488e | 907 | int ret; |
6197349b | 908 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
909 | I915_WRITE(RING_MODE_GEN7(ring), |
910 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
911 | |
912 | /* We promise to do a switch later with FULL PPGTT. If this is | |
913 | * aliasing, this is the one and only switch we'll do */ | |
914 | if (USES_FULL_PPGTT(dev)) | |
915 | continue; | |
916 | ||
eeb9488e BW |
917 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
918 | if (ret) | |
919 | return ret; | |
6197349b BW |
920 | } |
921 | ||
b4a74e3a BW |
922 | return 0; |
923 | } | |
6197349b | 924 | |
b4a74e3a BW |
925 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
926 | { | |
927 | struct drm_device *dev = ppgtt->base.dev; | |
928 | drm_i915_private_t *dev_priv = dev->dev_private; | |
929 | struct intel_ring_buffer *ring; | |
930 | uint32_t ecochk, gab_ctl, ecobits; | |
931 | int i; | |
a65c2fcd | 932 | |
b4a74e3a BW |
933 | ecobits = I915_READ(GAC_ECO_BITS); |
934 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
935 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 936 | |
b4a74e3a BW |
937 | gab_ctl = I915_READ(GAB_CTL); |
938 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
939 | ||
940 | ecochk = I915_READ(GAM_ECOCHK); | |
941 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
942 | ||
943 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 944 | |
b4a74e3a | 945 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
946 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
947 | if (ret) | |
948 | return ret; | |
6197349b | 949 | } |
b4a74e3a | 950 | |
b7c36d25 | 951 | return 0; |
6197349b BW |
952 | } |
953 | ||
1d2a314c | 954 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 955 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
956 | uint64_t start, |
957 | uint64_t length, | |
828c7908 | 958 | bool use_scratch) |
1d2a314c | 959 | { |
853ba5d2 BW |
960 | struct i915_hw_ppgtt *ppgtt = |
961 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 962 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
963 | unsigned first_entry = start >> PAGE_SHIFT; |
964 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 965 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
966 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
967 | unsigned last_pte, i; | |
1d2a314c | 968 | |
b35b380e | 969 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 970 | |
7bddb01f DV |
971 | while (num_entries) { |
972 | last_pte = first_pte + num_entries; | |
973 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
974 | last_pte = I915_PPGTT_PT_ENTRIES; | |
975 | ||
a15326a5 | 976 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 977 | |
7bddb01f DV |
978 | for (i = first_pte; i < last_pte; i++) |
979 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
980 | |
981 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 982 | |
7bddb01f DV |
983 | num_entries -= last_pte - first_pte; |
984 | first_pte = 0; | |
a15326a5 | 985 | act_pt++; |
7bddb01f | 986 | } |
1d2a314c DV |
987 | } |
988 | ||
853ba5d2 | 989 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 990 | struct sg_table *pages, |
782f1495 | 991 | uint64_t start, |
def886c3 DV |
992 | enum i915_cache_level cache_level) |
993 | { | |
853ba5d2 BW |
994 | struct i915_hw_ppgtt *ppgtt = |
995 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 996 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 997 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 998 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
999 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
1000 | struct sg_page_iter sg_iter; | |
1001 | ||
cc79714f | 1002 | pt_vaddr = NULL; |
6e995e23 | 1003 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
1004 | if (pt_vaddr == NULL) |
1005 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 1006 | |
cc79714f CW |
1007 | pt_vaddr[act_pte] = |
1008 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
1009 | cache_level, true); | |
6e995e23 ID |
1010 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
1011 | kunmap_atomic(pt_vaddr); | |
cc79714f | 1012 | pt_vaddr = NULL; |
a15326a5 | 1013 | act_pt++; |
6e995e23 | 1014 | act_pte = 0; |
def886c3 | 1015 | } |
def886c3 | 1016 | } |
cc79714f CW |
1017 | if (pt_vaddr) |
1018 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1019 | } |
1020 | ||
a00d825d | 1021 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 1022 | { |
3440d265 DV |
1023 | int i; |
1024 | ||
1025 | if (ppgtt->pt_dma_addr) { | |
1026 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 1027 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
1028 | ppgtt->pt_dma_addr[i], |
1029 | 4096, PCI_DMA_BIDIRECTIONAL); | |
1030 | } | |
a00d825d BW |
1031 | } |
1032 | ||
1033 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
1034 | { | |
1035 | int i; | |
3440d265 DV |
1036 | |
1037 | kfree(ppgtt->pt_dma_addr); | |
1038 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
1039 | __free_page(ppgtt->pt_pages[i]); | |
1040 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
1041 | } |
1042 | ||
a00d825d BW |
1043 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1044 | { | |
1045 | struct i915_hw_ppgtt *ppgtt = | |
1046 | container_of(vm, struct i915_hw_ppgtt, base); | |
1047 | ||
1048 | list_del(&vm->global_link); | |
1049 | drm_mm_takedown(&ppgtt->base.mm); | |
1050 | drm_mm_remove_node(&ppgtt->node); | |
1051 | ||
1052 | gen6_ppgtt_unmap_pages(ppgtt); | |
1053 | gen6_ppgtt_free(ppgtt); | |
1054 | } | |
1055 | ||
b146520f | 1056 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1057 | { |
c8d4c0d6 BW |
1058 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
1059 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) | |
853ba5d2 | 1060 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1061 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1062 | bool retried = false; |
b146520f | 1063 | int ret; |
1d2a314c | 1064 | |
c8d4c0d6 BW |
1065 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1066 | * allocator works in address space sizes, so it's multiplied by page | |
1067 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1068 | */ | |
1069 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1070 | alloc: |
c8d4c0d6 BW |
1071 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1072 | &ppgtt->node, GEN6_PD_SIZE, | |
1073 | GEN6_PD_ALIGN, 0, | |
1074 | 0, dev_priv->gtt.base.total, | |
1075 | DRM_MM_SEARCH_DEFAULT); | |
e3cc1995 BW |
1076 | if (ret == -ENOSPC && !retried) { |
1077 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1078 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d47c3ea2 | 1079 | I915_CACHE_NONE, 0); |
e3cc1995 BW |
1080 | if (ret) |
1081 | return ret; | |
1082 | ||
1083 | retried = true; | |
1084 | goto alloc; | |
1085 | } | |
c8d4c0d6 BW |
1086 | |
1087 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1088 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1089 | |
6670a5a5 | 1090 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
1091 | return ret; |
1092 | } | |
1093 | ||
1094 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1095 | { | |
1096 | int i; | |
1097 | ||
a1e22653 | 1098 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1099 | GFP_KERNEL); |
b146520f BW |
1100 | |
1101 | if (!ppgtt->pt_pages) | |
3440d265 | 1102 | return -ENOMEM; |
1d2a314c DV |
1103 | |
1104 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1105 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
1106 | if (!ppgtt->pt_pages[i]) { |
1107 | gen6_ppgtt_free(ppgtt); | |
1108 | return -ENOMEM; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1116 | { | |
1117 | int ret; | |
1118 | ||
1119 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1120 | if (ret) | |
1121 | return ret; | |
1122 | ||
1123 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1124 | if (ret) { | |
1125 | drm_mm_remove_node(&ppgtt->node); | |
1126 | return ret; | |
1d2a314c DV |
1127 | } |
1128 | ||
a1e22653 | 1129 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1130 | GFP_KERNEL); |
b146520f BW |
1131 | if (!ppgtt->pt_dma_addr) { |
1132 | drm_mm_remove_node(&ppgtt->node); | |
1133 | gen6_ppgtt_free(ppgtt); | |
1134 | return -ENOMEM; | |
1135 | } | |
1136 | ||
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1141 | { | |
1142 | struct drm_device *dev = ppgtt->base.dev; | |
1143 | int i; | |
1d2a314c | 1144 | |
8d2e6308 BW |
1145 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1146 | dma_addr_t pt_addr; | |
211c568b | 1147 | |
8d2e6308 BW |
1148 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1149 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1150 | |
8d2e6308 | 1151 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1152 | gen6_ppgtt_unmap_pages(ppgtt); |
1153 | return -EIO; | |
211c568b | 1154 | } |
b146520f | 1155 | |
8d2e6308 | 1156 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1157 | } |
1d2a314c | 1158 | |
b146520f BW |
1159 | return 0; |
1160 | } | |
1161 | ||
1162 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1163 | { | |
1164 | struct drm_device *dev = ppgtt->base.dev; | |
1165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1166 | int ret; | |
1167 | ||
1168 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1169 | if (IS_GEN6(dev)) { | |
1170 | ppgtt->enable = gen6_ppgtt_enable; | |
1171 | ppgtt->switch_mm = gen6_mm_switch; | |
1172 | } else if (IS_HASWELL(dev)) { | |
1173 | ppgtt->enable = gen7_ppgtt_enable; | |
1174 | ppgtt->switch_mm = hsw_mm_switch; | |
1175 | } else if (IS_GEN7(dev)) { | |
1176 | ppgtt->enable = gen7_ppgtt_enable; | |
1177 | ppgtt->switch_mm = gen7_mm_switch; | |
1178 | } else | |
1179 | BUG(); | |
1180 | ||
1181 | ret = gen6_ppgtt_alloc(ppgtt); | |
1182 | if (ret) | |
1183 | return ret; | |
1184 | ||
1185 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1186 | if (ret) { | |
1187 | gen6_ppgtt_free(ppgtt); | |
1188 | return ret; | |
1189 | } | |
1190 | ||
1191 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1192 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1193 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1194 | ppgtt->base.start = 0; |
5a6c93fe | 1195 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1196 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1197 | |
c8d4c0d6 BW |
1198 | ppgtt->pd_offset = |
1199 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1200 | |
b146520f | 1201 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1202 | |
b146520f BW |
1203 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1204 | ppgtt->node.size >> 20, | |
1205 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1206 | |
b146520f | 1207 | return 0; |
3440d265 DV |
1208 | } |
1209 | ||
246cbfb5 | 1210 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1211 | { |
1212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 1213 | int ret = 0; |
3440d265 | 1214 | |
853ba5d2 | 1215 | ppgtt->base.dev = dev; |
8407bb91 | 1216 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1217 | |
3ed124b2 BW |
1218 | if (INTEL_INFO(dev)->gen < 8) |
1219 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 1220 | else if (IS_GEN8(dev)) |
37aca44a | 1221 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1222 | else |
1223 | BUG(); | |
1224 | ||
c7c48dfd | 1225 | if (!ret) { |
7e0d96bc | 1226 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 1227 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1228 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1229 | ppgtt->base.total); | |
7e0d96bc BW |
1230 | i915_init_vm(dev_priv, &ppgtt->base); |
1231 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 1232 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
1233 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
1234 | ppgtt->pd_offset << 10); | |
1235 | } | |
93bd8649 | 1236 | } |
1d2a314c DV |
1237 | |
1238 | return ret; | |
1239 | } | |
1240 | ||
7e0d96bc | 1241 | static void |
6f65e29a BW |
1242 | ppgtt_bind_vma(struct i915_vma *vma, |
1243 | enum i915_cache_level cache_level, | |
1244 | u32 flags) | |
1d2a314c | 1245 | { |
782f1495 BW |
1246 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
1247 | cache_level); | |
1d2a314c DV |
1248 | } |
1249 | ||
7e0d96bc | 1250 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1251 | { |
6f65e29a | 1252 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1253 | vma->node.start, |
1254 | vma->obj->base.size, | |
6f65e29a | 1255 | true); |
7bddb01f DV |
1256 | } |
1257 | ||
a81cc00c BW |
1258 | extern int intel_iommu_gfx_mapped; |
1259 | /* Certain Gen5 chipsets require require idling the GPU before | |
1260 | * unmapping anything from the GTT when VT-d is enabled. | |
1261 | */ | |
1262 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1263 | { | |
1264 | #ifdef CONFIG_INTEL_IOMMU | |
1265 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1266 | * was loaded first. | |
1267 | */ | |
1268 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1269 | return true; | |
1270 | #endif | |
1271 | return false; | |
1272 | } | |
1273 | ||
5c042287 BW |
1274 | static bool do_idling(struct drm_i915_private *dev_priv) |
1275 | { | |
1276 | bool ret = dev_priv->mm.interruptible; | |
1277 | ||
a81cc00c | 1278 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1279 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1280 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1281 | DRM_ERROR("Couldn't idle GPU\n"); |
1282 | /* Wait a bit, in hopes it avoids the hang */ | |
1283 | udelay(10); | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | return ret; | |
1288 | } | |
1289 | ||
1290 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1291 | { | |
a81cc00c | 1292 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1293 | dev_priv->mm.interruptible = interruptible; |
1294 | } | |
1295 | ||
828c7908 BW |
1296 | void i915_check_and_clear_faults(struct drm_device *dev) |
1297 | { | |
1298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1299 | struct intel_ring_buffer *ring; | |
1300 | int i; | |
1301 | ||
1302 | if (INTEL_INFO(dev)->gen < 6) | |
1303 | return; | |
1304 | ||
1305 | for_each_ring(ring, dev_priv, i) { | |
1306 | u32 fault_reg; | |
1307 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1308 | if (fault_reg & RING_FAULT_VALID) { | |
1309 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1310 | "\tAddr: 0x%08lx\\n" | |
1311 | "\tAddress space: %s\n" | |
1312 | "\tSource ID: %d\n" | |
1313 | "\tType: %d\n", | |
1314 | fault_reg & PAGE_MASK, | |
1315 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1316 | RING_FAULT_SRCID(fault_reg), | |
1317 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1318 | I915_WRITE(RING_FAULT_REG(ring), | |
1319 | fault_reg & ~RING_FAULT_VALID); | |
1320 | } | |
1321 | } | |
1322 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1323 | } | |
1324 | ||
1325 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1326 | { | |
1327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1328 | ||
1329 | /* Don't bother messing with faults pre GEN6 as we have little | |
1330 | * documentation supporting that it's a good idea. | |
1331 | */ | |
1332 | if (INTEL_INFO(dev)->gen < 6) | |
1333 | return; | |
1334 | ||
1335 | i915_check_and_clear_faults(dev); | |
1336 | ||
1337 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1338 | dev_priv->gtt.base.start, |
1339 | dev_priv->gtt.base.total, | |
828c7908 BW |
1340 | false); |
1341 | } | |
1342 | ||
76aaf220 DV |
1343 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1344 | { | |
1345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1346 | struct drm_i915_gem_object *obj; |
80da2161 | 1347 | struct i915_address_space *vm; |
76aaf220 | 1348 | |
828c7908 BW |
1349 | i915_check_and_clear_faults(dev); |
1350 | ||
bee4a186 | 1351 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1352 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1353 | dev_priv->gtt.base.start, |
1354 | dev_priv->gtt.base.total, | |
828c7908 | 1355 | true); |
bee4a186 | 1356 | |
35c20a60 | 1357 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1358 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1359 | &dev_priv->gtt.base); | |
1360 | if (!vma) | |
1361 | continue; | |
1362 | ||
2c22569b | 1363 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1364 | /* The bind_vma code tries to be smart about tracking mappings. |
1365 | * Unfortunately above, we've just wiped out the mappings | |
1366 | * without telling our object about it. So we need to fake it. | |
1367 | */ | |
1368 | obj->has_global_gtt_mapping = 0; | |
1369 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1370 | } |
1371 | ||
80da2161 BW |
1372 | |
1373 | if (INTEL_INFO(dev)->gen >= 8) | |
1374 | return; | |
1375 | ||
1376 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1377 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1378 | if (i915_is_ggtt(vm)) { | |
1379 | if (dev_priv->mm.aliasing_ppgtt) | |
1380 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1381 | continue; | |
1382 | } | |
1383 | ||
1384 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1385 | } |
1386 | ||
e76e9aeb | 1387 | i915_gem_chipset_flush(dev); |
76aaf220 | 1388 | } |
7c2e6fdf | 1389 | |
74163907 | 1390 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1391 | { |
9da3da66 | 1392 | if (obj->has_dma_mapping) |
74163907 | 1393 | return 0; |
9da3da66 CW |
1394 | |
1395 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1396 | obj->pages->sgl, obj->pages->nents, | |
1397 | PCI_DMA_BIDIRECTIONAL)) | |
1398 | return -ENOSPC; | |
1399 | ||
1400 | return 0; | |
7c2e6fdf DV |
1401 | } |
1402 | ||
94ec8f61 BW |
1403 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1404 | { | |
1405 | #ifdef writeq | |
1406 | writeq(pte, addr); | |
1407 | #else | |
1408 | iowrite32((u32)pte, addr); | |
1409 | iowrite32(pte >> 32, addr + 4); | |
1410 | #endif | |
1411 | } | |
1412 | ||
1413 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1414 | struct sg_table *st, | |
782f1495 | 1415 | uint64_t start, |
94ec8f61 BW |
1416 | enum i915_cache_level level) |
1417 | { | |
1418 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1419 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1420 | gen8_gtt_pte_t __iomem *gtt_entries = |
1421 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1422 | int i = 0; | |
1423 | struct sg_page_iter sg_iter; | |
1424 | dma_addr_t addr; | |
1425 | ||
1426 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1427 | addr = sg_dma_address(sg_iter.sg) + | |
1428 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1429 | gen8_set_pte(>t_entries[i], | |
1430 | gen8_pte_encode(addr, level, true)); | |
1431 | i++; | |
1432 | } | |
1433 | ||
1434 | /* | |
1435 | * XXX: This serves as a posting read to make sure that the PTE has | |
1436 | * actually been updated. There is some concern that even though | |
1437 | * registers and PTEs are within the same BAR that they are potentially | |
1438 | * of NUMA access patterns. Therefore, even with the way we assume | |
1439 | * hardware should work, we must keep this posting read for paranoia. | |
1440 | */ | |
1441 | if (i != 0) | |
1442 | WARN_ON(readq(>t_entries[i-1]) | |
1443 | != gen8_pte_encode(addr, level, true)); | |
1444 | ||
94ec8f61 BW |
1445 | /* This next bit makes the above posting read even more important. We |
1446 | * want to flush the TLBs only after we're certain all the PTE updates | |
1447 | * have finished. | |
1448 | */ | |
1449 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1450 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1451 | } |
1452 | ||
e76e9aeb BW |
1453 | /* |
1454 | * Binds an object into the global gtt with the specified cache level. The object | |
1455 | * will be accessible to the GPU via commands whose operands reference offsets | |
1456 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1457 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1458 | */ | |
853ba5d2 | 1459 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1460 | struct sg_table *st, |
782f1495 | 1461 | uint64_t start, |
7faf1ab2 | 1462 | enum i915_cache_level level) |
e76e9aeb | 1463 | { |
853ba5d2 | 1464 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1465 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1466 | gen6_gtt_pte_t __iomem *gtt_entries = |
1467 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1468 | int i = 0; |
1469 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1470 | dma_addr_t addr; |
1471 | ||
6e995e23 | 1472 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1473 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1474 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1475 | i++; |
e76e9aeb BW |
1476 | } |
1477 | ||
e76e9aeb BW |
1478 | /* XXX: This serves as a posting read to make sure that the PTE has |
1479 | * actually been updated. There is some concern that even though | |
1480 | * registers and PTEs are within the same BAR that they are potentially | |
1481 | * of NUMA access patterns. Therefore, even with the way we assume | |
1482 | * hardware should work, we must keep this posting read for paranoia. | |
1483 | */ | |
1484 | if (i != 0) | |
853ba5d2 | 1485 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1486 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1487 | |
1488 | /* This next bit makes the above posting read even more important. We | |
1489 | * want to flush the TLBs only after we're certain all the PTE updates | |
1490 | * have finished. | |
1491 | */ | |
1492 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1493 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1494 | } |
1495 | ||
94ec8f61 | 1496 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1497 | uint64_t start, |
1498 | uint64_t length, | |
94ec8f61 BW |
1499 | bool use_scratch) |
1500 | { | |
1501 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1502 | unsigned first_entry = start >> PAGE_SHIFT; |
1503 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1504 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1505 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1506 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1507 | int i; | |
1508 | ||
1509 | if (WARN(num_entries > max_entries, | |
1510 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1511 | first_entry, num_entries, max_entries)) | |
1512 | num_entries = max_entries; | |
1513 | ||
1514 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1515 | I915_CACHE_LLC, | |
1516 | use_scratch); | |
1517 | for (i = 0; i < num_entries; i++) | |
1518 | gen8_set_pte(>t_base[i], scratch_pte); | |
1519 | readl(gtt_base); | |
1520 | } | |
1521 | ||
853ba5d2 | 1522 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1523 | uint64_t start, |
1524 | uint64_t length, | |
828c7908 | 1525 | bool use_scratch) |
7faf1ab2 | 1526 | { |
853ba5d2 | 1527 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1528 | unsigned first_entry = start >> PAGE_SHIFT; |
1529 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1530 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1531 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1532 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1533 | int i; |
1534 | ||
1535 | if (WARN(num_entries > max_entries, | |
1536 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1537 | first_entry, num_entries, max_entries)) | |
1538 | num_entries = max_entries; | |
1539 | ||
828c7908 BW |
1540 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1541 | ||
7faf1ab2 DV |
1542 | for (i = 0; i < num_entries; i++) |
1543 | iowrite32(scratch_pte, >t_base[i]); | |
1544 | readl(gtt_base); | |
1545 | } | |
1546 | ||
6f65e29a BW |
1547 | |
1548 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1549 | enum i915_cache_level cache_level, | |
1550 | u32 unused) | |
7faf1ab2 | 1551 | { |
6f65e29a | 1552 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1553 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1554 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1555 | ||
6f65e29a BW |
1556 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1557 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1558 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1559 | } |
1560 | ||
853ba5d2 | 1561 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1562 | uint64_t start, |
1563 | uint64_t length, | |
828c7908 | 1564 | bool unused) |
7faf1ab2 | 1565 | { |
782f1495 BW |
1566 | unsigned first_entry = start >> PAGE_SHIFT; |
1567 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1568 | intel_gtt_clear_range(first_entry, num_entries); |
1569 | } | |
1570 | ||
6f65e29a BW |
1571 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1572 | { | |
1573 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1574 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1575 | |
6f65e29a BW |
1576 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1577 | vma->obj->has_global_gtt_mapping = 0; | |
1578 | intel_gtt_clear_range(first, size); | |
1579 | } | |
7faf1ab2 | 1580 | |
6f65e29a BW |
1581 | static void ggtt_bind_vma(struct i915_vma *vma, |
1582 | enum i915_cache_level cache_level, | |
1583 | u32 flags) | |
d5bd1449 | 1584 | { |
6f65e29a | 1585 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1586 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1587 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1588 | |
6f65e29a BW |
1589 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1590 | * or we have a global mapping already but the cacheability flags have | |
1591 | * changed, set the global PTEs. | |
1592 | * | |
1593 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1594 | * instead if none of the above hold true. | |
1595 | * | |
1596 | * NB: A global mapping should only be needed for special regions like | |
1597 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1598 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1599 | */ | |
1600 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1601 | if (!obj->has_global_gtt_mapping || | |
1602 | (cache_level != obj->cache_level)) { | |
782f1495 BW |
1603 | vma->vm->insert_entries(vma->vm, obj->pages, |
1604 | vma->node.start, | |
6f65e29a BW |
1605 | cache_level); |
1606 | obj->has_global_gtt_mapping = 1; | |
1607 | } | |
1608 | } | |
d5bd1449 | 1609 | |
6f65e29a BW |
1610 | if (dev_priv->mm.aliasing_ppgtt && |
1611 | (!obj->has_aliasing_ppgtt_mapping || | |
1612 | (cache_level != obj->cache_level))) { | |
1613 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1614 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1615 | vma->obj->pages, |
1616 | vma->node.start, | |
1617 | cache_level); | |
6f65e29a BW |
1618 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
1619 | } | |
d5bd1449 CW |
1620 | } |
1621 | ||
6f65e29a | 1622 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1623 | { |
6f65e29a | 1624 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1625 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1626 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a BW |
1627 | |
1628 | if (obj->has_global_gtt_mapping) { | |
782f1495 BW |
1629 | vma->vm->clear_range(vma->vm, |
1630 | vma->node.start, | |
1631 | obj->base.size, | |
6f65e29a BW |
1632 | true); |
1633 | obj->has_global_gtt_mapping = 0; | |
1634 | } | |
74898d7e | 1635 | |
6f65e29a BW |
1636 | if (obj->has_aliasing_ppgtt_mapping) { |
1637 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1638 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1639 | vma->node.start, |
1640 | obj->base.size, | |
6f65e29a BW |
1641 | true); |
1642 | obj->has_aliasing_ppgtt_mapping = 0; | |
1643 | } | |
74163907 DV |
1644 | } |
1645 | ||
1646 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1647 | { |
5c042287 BW |
1648 | struct drm_device *dev = obj->base.dev; |
1649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1650 | bool interruptible; | |
1651 | ||
1652 | interruptible = do_idling(dev_priv); | |
1653 | ||
9da3da66 CW |
1654 | if (!obj->has_dma_mapping) |
1655 | dma_unmap_sg(&dev->pdev->dev, | |
1656 | obj->pages->sgl, obj->pages->nents, | |
1657 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1658 | |
1659 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1660 | } |
644ec02b | 1661 | |
42d6ab48 CW |
1662 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1663 | unsigned long color, | |
1664 | unsigned long *start, | |
1665 | unsigned long *end) | |
1666 | { | |
1667 | if (node->color != color) | |
1668 | *start += 4096; | |
1669 | ||
1670 | if (!list_empty(&node->node_list)) { | |
1671 | node = list_entry(node->node_list.next, | |
1672 | struct drm_mm_node, | |
1673 | node_list); | |
1674 | if (node->allocated && node->color != color) | |
1675 | *end -= 4096; | |
1676 | } | |
1677 | } | |
fbe5d36e | 1678 | |
d7e5008f BW |
1679 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1680 | unsigned long start, | |
1681 | unsigned long mappable_end, | |
1682 | unsigned long end) | |
644ec02b | 1683 | { |
e78891ca BW |
1684 | /* Let GEM Manage all of the aperture. |
1685 | * | |
1686 | * However, leave one page at the end still bound to the scratch page. | |
1687 | * There are a number of places where the hardware apparently prefetches | |
1688 | * past the end of the object, and we've seen multiple hangs with the | |
1689 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1690 | * aperture. One page should be enough to keep any prefetching inside | |
1691 | * of the aperture. | |
1692 | */ | |
40d74980 BW |
1693 | struct drm_i915_private *dev_priv = dev->dev_private; |
1694 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1695 | struct drm_mm_node *entry; |
1696 | struct drm_i915_gem_object *obj; | |
1697 | unsigned long hole_start, hole_end; | |
644ec02b | 1698 | |
35451cb6 BW |
1699 | BUG_ON(mappable_end > end); |
1700 | ||
ed2f3452 | 1701 | /* Subtract the guard page ... */ |
40d74980 | 1702 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1703 | if (!HAS_LLC(dev)) |
93bd8649 | 1704 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1705 | |
ed2f3452 | 1706 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1707 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1708 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1709 | int ret; |
edd41a87 | 1710 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1711 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1712 | ||
1713 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1714 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1715 | if (ret) |
b3a070cc | 1716 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1717 | obj->has_global_gtt_mapping = 1; |
1718 | } | |
1719 | ||
853ba5d2 BW |
1720 | dev_priv->gtt.base.start = start; |
1721 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1722 | |
ed2f3452 | 1723 | /* Clear any non-preallocated blocks */ |
40d74980 | 1724 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1725 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1726 | hole_start, hole_end); | |
782f1495 BW |
1727 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1728 | hole_end - hole_start, true); | |
ed2f3452 CW |
1729 | } |
1730 | ||
1731 | /* And finally clear the reserved guard page */ | |
782f1495 | 1732 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
e76e9aeb BW |
1733 | } |
1734 | ||
d7e5008f BW |
1735 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1736 | { | |
1737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1738 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1739 | |
853ba5d2 | 1740 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1741 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1742 | |
e78891ca | 1743 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1744 | } |
1745 | ||
1746 | static int setup_scratch_page(struct drm_device *dev) | |
1747 | { | |
1748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1749 | struct page *page; | |
1750 | dma_addr_t dma_addr; | |
1751 | ||
1752 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1753 | if (page == NULL) | |
1754 | return -ENOMEM; | |
1755 | get_page(page); | |
1756 | set_pages_uc(page, 1); | |
1757 | ||
1758 | #ifdef CONFIG_INTEL_IOMMU | |
1759 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1760 | PCI_DMA_BIDIRECTIONAL); | |
1761 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1762 | return -EINVAL; | |
1763 | #else | |
1764 | dma_addr = page_to_phys(page); | |
1765 | #endif | |
853ba5d2 BW |
1766 | dev_priv->gtt.base.scratch.page = page; |
1767 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1768 | |
1769 | return 0; | |
1770 | } | |
1771 | ||
1772 | static void teardown_scratch_page(struct drm_device *dev) | |
1773 | { | |
1774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1775 | struct page *page = dev_priv->gtt.base.scratch.page; |
1776 | ||
1777 | set_pages_wb(page, 1); | |
1778 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1779 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1780 | put_page(page); |
1781 | __free_page(page); | |
e76e9aeb BW |
1782 | } |
1783 | ||
1784 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1785 | { | |
1786 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1787 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1788 | return snb_gmch_ctl << 20; | |
1789 | } | |
1790 | ||
9459d252 BW |
1791 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1792 | { | |
1793 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1794 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1795 | if (bdw_gmch_ctl) | |
1796 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
1797 | return bdw_gmch_ctl << 20; | |
1798 | } | |
1799 | ||
baa09f5f | 1800 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1801 | { |
1802 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1803 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1804 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1805 | } | |
1806 | ||
9459d252 BW |
1807 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1808 | { | |
1809 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1810 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1811 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1812 | } | |
1813 | ||
63340133 BW |
1814 | static int ggtt_probe_common(struct drm_device *dev, |
1815 | size_t gtt_size) | |
1816 | { | |
1817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1818 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1819 | int ret; |
1820 | ||
1821 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1822 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1823 | (pci_resource_len(dev->pdev, 0) / 2); |
1824 | ||
21c34607 | 1825 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1826 | if (!dev_priv->gtt.gsm) { |
1827 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1828 | return -ENOMEM; | |
1829 | } | |
1830 | ||
1831 | ret = setup_scratch_page(dev); | |
1832 | if (ret) { | |
1833 | DRM_ERROR("Scratch setup failed\n"); | |
1834 | /* iounmap will also get called at remove, but meh */ | |
1835 | iounmap(dev_priv->gtt.gsm); | |
1836 | } | |
1837 | ||
1838 | return ret; | |
1839 | } | |
1840 | ||
fbe5d36e BW |
1841 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1842 | * bits. When using advanced contexts each context stores its own PAT, but | |
1843 | * writing this data shouldn't be harmful even in those cases. */ | |
1844 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1845 | { | |
1846 | #define GEN8_PPAT_UC (0<<0) | |
1847 | #define GEN8_PPAT_WC (1<<0) | |
1848 | #define GEN8_PPAT_WT (2<<0) | |
1849 | #define GEN8_PPAT_WB (3<<0) | |
1850 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1851 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1852 | #define GEN8_PPAT_LLC (1<<2) | |
1853 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1854 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1855 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1856 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1857 | uint64_t pat; | |
1858 | ||
1859 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1860 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1861 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1862 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1863 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1864 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1865 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1866 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1867 | ||
1868 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1869 | * write would work. */ | |
1870 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1871 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1872 | } | |
1873 | ||
63340133 BW |
1874 | static int gen8_gmch_probe(struct drm_device *dev, |
1875 | size_t *gtt_total, | |
1876 | size_t *stolen, | |
1877 | phys_addr_t *mappable_base, | |
1878 | unsigned long *mappable_end) | |
1879 | { | |
1880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1881 | unsigned int gtt_size; | |
1882 | u16 snb_gmch_ctl; | |
1883 | int ret; | |
1884 | ||
1885 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1886 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1887 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1888 | ||
1889 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1890 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1891 | ||
1892 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1893 | ||
1894 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1895 | ||
1896 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1897 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1898 | |
fbe5d36e BW |
1899 | gen8_setup_private_ppat(dev_priv); |
1900 | ||
63340133 BW |
1901 | ret = ggtt_probe_common(dev, gtt_size); |
1902 | ||
94ec8f61 BW |
1903 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1904 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1905 | |
1906 | return ret; | |
1907 | } | |
1908 | ||
baa09f5f BW |
1909 | static int gen6_gmch_probe(struct drm_device *dev, |
1910 | size_t *gtt_total, | |
41907ddc BW |
1911 | size_t *stolen, |
1912 | phys_addr_t *mappable_base, | |
1913 | unsigned long *mappable_end) | |
e76e9aeb BW |
1914 | { |
1915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1916 | unsigned int gtt_size; |
e76e9aeb | 1917 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1918 | int ret; |
1919 | ||
41907ddc BW |
1920 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1921 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1922 | ||
baa09f5f BW |
1923 | /* 64/512MB is the current min/max we actually know of, but this is just |
1924 | * a coarse sanity check. | |
e76e9aeb | 1925 | */ |
41907ddc | 1926 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1927 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1928 | dev_priv->gtt.mappable_end); | |
1929 | return -ENXIO; | |
e76e9aeb BW |
1930 | } |
1931 | ||
e76e9aeb BW |
1932 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1933 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1934 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1935 | |
c4ae25ec | 1936 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1937 | |
63340133 BW |
1938 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1939 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1940 | |
63340133 | 1941 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1942 | |
853ba5d2 BW |
1943 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1944 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1945 | |
e76e9aeb BW |
1946 | return ret; |
1947 | } | |
1948 | ||
853ba5d2 | 1949 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1950 | { |
853ba5d2 BW |
1951 | |
1952 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1953 | |
1954 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1955 | iounmap(gtt->gsm); |
1956 | teardown_scratch_page(vm->dev); | |
644ec02b | 1957 | } |
baa09f5f BW |
1958 | |
1959 | static int i915_gmch_probe(struct drm_device *dev, | |
1960 | size_t *gtt_total, | |
41907ddc BW |
1961 | size_t *stolen, |
1962 | phys_addr_t *mappable_base, | |
1963 | unsigned long *mappable_end) | |
baa09f5f BW |
1964 | { |
1965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1966 | int ret; | |
1967 | ||
baa09f5f BW |
1968 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1969 | if (!ret) { | |
1970 | DRM_ERROR("failed to set up gmch\n"); | |
1971 | return -EIO; | |
1972 | } | |
1973 | ||
41907ddc | 1974 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1975 | |
1976 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1977 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 1978 | |
c0a7f818 CW |
1979 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
1980 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
1981 | ||
baa09f5f BW |
1982 | return 0; |
1983 | } | |
1984 | ||
853ba5d2 | 1985 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1986 | { |
1987 | intel_gmch_remove(); | |
1988 | } | |
1989 | ||
1990 | int i915_gem_gtt_init(struct drm_device *dev) | |
1991 | { | |
1992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1993 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1994 | int ret; |
1995 | ||
baa09f5f | 1996 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1997 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1998 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1999 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2000 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2001 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2002 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2003 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2004 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2005 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2006 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2007 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2008 | else if (INTEL_INFO(dev)->gen >= 7) |
2009 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2010 | else |
350ec881 | 2011 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2012 | } else { |
2013 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2014 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2015 | } |
2016 | ||
853ba5d2 | 2017 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2018 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2019 | if (ret) |
baa09f5f | 2020 | return ret; |
baa09f5f | 2021 | |
853ba5d2 BW |
2022 | gtt->base.dev = dev; |
2023 | ||
baa09f5f | 2024 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2025 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2026 | gtt->base.total >> 20); | |
b2f21b4d BW |
2027 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2028 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
2029 | |
2030 | return 0; | |
2031 | } | |
6f65e29a BW |
2032 | |
2033 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2034 | struct i915_address_space *vm) | |
2035 | { | |
2036 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2037 | if (vma == NULL) | |
2038 | return ERR_PTR(-ENOMEM); | |
2039 | ||
2040 | INIT_LIST_HEAD(&vma->vma_link); | |
2041 | INIT_LIST_HEAD(&vma->mm_list); | |
2042 | INIT_LIST_HEAD(&vma->exec_list); | |
2043 | vma->vm = vm; | |
2044 | vma->obj = obj; | |
2045 | ||
2046 | switch (INTEL_INFO(vm->dev)->gen) { | |
2047 | case 8: | |
2048 | case 7: | |
2049 | case 6: | |
7e0d96bc BW |
2050 | if (i915_is_ggtt(vm)) { |
2051 | vma->unbind_vma = ggtt_unbind_vma; | |
2052 | vma->bind_vma = ggtt_bind_vma; | |
2053 | } else { | |
2054 | vma->unbind_vma = ppgtt_unbind_vma; | |
2055 | vma->bind_vma = ppgtt_bind_vma; | |
2056 | } | |
6f65e29a BW |
2057 | break; |
2058 | case 5: | |
2059 | case 4: | |
2060 | case 3: | |
2061 | case 2: | |
2062 | BUG_ON(!i915_is_ggtt(vm)); | |
2063 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2064 | vma->bind_vma = i915_ggtt_bind_vma; | |
2065 | break; | |
2066 | default: | |
2067 | BUG(); | |
2068 | } | |
2069 | ||
2070 | /* Keep GGTT vmas first to make debug easier */ | |
2071 | if (i915_is_ggtt(vm)) | |
2072 | list_add(&vma->vma_link, &obj->vma_list); | |
2073 | else | |
2074 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
2075 | ||
2076 | return vma; | |
2077 | } | |
2078 | ||
2079 | struct i915_vma * | |
2080 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2081 | struct i915_address_space *vm) | |
2082 | { | |
2083 | struct i915_vma *vma; | |
2084 | ||
2085 | vma = i915_gem_obj_to_vma(obj, vm); | |
2086 | if (!vma) | |
2087 | vma = __i915_gem_vma_create(obj, vm); | |
2088 | ||
2089 | return vma; | |
2090 | } |