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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
45f8f69a TU |
33 | /** |
34 | * DOC: Global GTT views | |
35 | * | |
36 | * Background and previous state | |
37 | * | |
38 | * Historically objects could exists (be bound) in global GTT space only as | |
39 | * singular instances with a view representing all of the object's backing pages | |
40 | * in a linear fashion. This view will be called a normal view. | |
41 | * | |
42 | * To support multiple views of the same object, where the number of mapped | |
43 | * pages is not equal to the backing store, or where the layout of the pages | |
44 | * is not linear, concept of a GGTT view was added. | |
45 | * | |
46 | * One example of an alternative view is a stereo display driven by a single | |
47 | * image. In this case we would have a framebuffer looking like this | |
48 | * (2x2 pages): | |
49 | * | |
50 | * 12 | |
51 | * 34 | |
52 | * | |
53 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
54 | * rendering. In contrast, fed to the display engine would be an alternative | |
55 | * view which could look something like this: | |
56 | * | |
57 | * 1212 | |
58 | * 3434 | |
59 | * | |
60 | * In this example both the size and layout of pages in the alternative view is | |
61 | * different from the normal view. | |
62 | * | |
63 | * Implementation and usage | |
64 | * | |
65 | * GGTT views are implemented using VMAs and are distinguished via enum | |
66 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
67 | * | |
68 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
69 | * added with the _view suffix. They take the struct i915_ggtt_view parameter | |
70 | * encapsulating all metadata required to implement a view. | |
71 | * | |
72 | * As a helper for callers which are only interested in the normal view, | |
73 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
74 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
75 | * or with the normal GGTT view. | |
76 | * | |
77 | * Code wanting to add or use a new GGTT view needs to: | |
78 | * | |
79 | * 1. Add a new enum with a suitable name. | |
80 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
81 | * 3. Add support to i915_get_vma_pages(). | |
82 | * | |
83 | * New views are required to build a scatter-gather table from within the | |
84 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
85 | * exists for the lifetime of an VMA. | |
86 | * | |
87 | * Core API is designed to have copy semantics which means that passed in | |
88 | * struct i915_ggtt_view does not need to be persistent (left around after | |
89 | * calling the core API functions). | |
90 | * | |
91 | */ | |
92 | ||
fe14d5f4 TU |
93 | const struct i915_ggtt_view i915_ggtt_view_normal; |
94 | ||
ee0ce478 VS |
95 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
96 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 97 | |
cfa7c862 DV |
98 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
99 | { | |
1893a71b CW |
100 | bool has_aliasing_ppgtt; |
101 | bool has_full_ppgtt; | |
102 | ||
103 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
104 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
105 | if (IS_GEN8(dev)) | |
106 | has_full_ppgtt = false; /* XXX why? */ | |
107 | ||
70ee45e1 DL |
108 | /* |
109 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
110 | * execlists, the sole mechanism available to submit work. | |
111 | */ | |
112 | if (INTEL_INFO(dev)->gen < 9 && | |
113 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
114 | return 0; |
115 | ||
116 | if (enable_ppgtt == 1) | |
117 | return 1; | |
118 | ||
1893a71b | 119 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
120 | return 2; |
121 | ||
93a25a9e DV |
122 | #ifdef CONFIG_INTEL_IOMMU |
123 | /* Disable ppgtt on SNB if VT-d is on. */ | |
124 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
125 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 126 | return 0; |
93a25a9e DV |
127 | } |
128 | #endif | |
129 | ||
62942ed7 | 130 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
131 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
132 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
133 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
134 | return 0; | |
135 | } | |
136 | ||
cacc6c83 | 137 | return has_aliasing_ppgtt ? 1 : 0; |
93a25a9e DV |
138 | } |
139 | ||
fbe5d36e | 140 | |
6f65e29a BW |
141 | static void ppgtt_bind_vma(struct i915_vma *vma, |
142 | enum i915_cache_level cache_level, | |
143 | u32 flags); | |
144 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
145 | ||
94ec8f61 BW |
146 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
147 | enum i915_cache_level level, | |
148 | bool valid) | |
149 | { | |
150 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
151 | pte |= addr; | |
63c42e56 BW |
152 | |
153 | switch (level) { | |
154 | case I915_CACHE_NONE: | |
fbe5d36e | 155 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
156 | break; |
157 | case I915_CACHE_WT: | |
158 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
159 | break; | |
160 | default: | |
161 | pte |= PPAT_CACHED_INDEX; | |
162 | break; | |
163 | } | |
164 | ||
94ec8f61 BW |
165 | return pte; |
166 | } | |
167 | ||
b1fe6673 BW |
168 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
169 | dma_addr_t addr, | |
170 | enum i915_cache_level level) | |
171 | { | |
172 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
173 | pde |= addr; | |
174 | if (level != I915_CACHE_NONE) | |
175 | pde |= PPAT_CACHED_PDE_INDEX; | |
176 | else | |
177 | pde |= PPAT_UNCACHED_INDEX; | |
178 | return pde; | |
179 | } | |
180 | ||
350ec881 | 181 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e | 182 | enum i915_cache_level level, |
24f3a8cf | 183 | bool valid, u32 unused) |
54d12527 | 184 | { |
b35b380e | 185 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 186 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
187 | |
188 | switch (level) { | |
350ec881 CW |
189 | case I915_CACHE_L3_LLC: |
190 | case I915_CACHE_LLC: | |
191 | pte |= GEN6_PTE_CACHE_LLC; | |
192 | break; | |
193 | case I915_CACHE_NONE: | |
194 | pte |= GEN6_PTE_UNCACHED; | |
195 | break; | |
196 | default: | |
5f77eeb0 | 197 | MISSING_CASE(level); |
350ec881 CW |
198 | } |
199 | ||
200 | return pte; | |
201 | } | |
202 | ||
203 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e | 204 | enum i915_cache_level level, |
24f3a8cf | 205 | bool valid, u32 unused) |
350ec881 | 206 | { |
b35b380e | 207 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
208 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
209 | ||
210 | switch (level) { | |
211 | case I915_CACHE_L3_LLC: | |
212 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
213 | break; |
214 | case I915_CACHE_LLC: | |
215 | pte |= GEN6_PTE_CACHE_LLC; | |
216 | break; | |
217 | case I915_CACHE_NONE: | |
9119708c | 218 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
219 | break; |
220 | default: | |
5f77eeb0 | 221 | MISSING_CASE(level); |
e7210c3c BW |
222 | } |
223 | ||
54d12527 BW |
224 | return pte; |
225 | } | |
226 | ||
80a74f7f | 227 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e | 228 | enum i915_cache_level level, |
24f3a8cf | 229 | bool valid, u32 flags) |
93c34e70 | 230 | { |
b35b380e | 231 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
232 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
233 | ||
24f3a8cf AG |
234 | if (!(flags & PTE_READ_ONLY)) |
235 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
236 | |
237 | if (level != I915_CACHE_NONE) | |
238 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
239 | ||
240 | return pte; | |
241 | } | |
242 | ||
80a74f7f | 243 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e | 244 | enum i915_cache_level level, |
24f3a8cf | 245 | bool valid, u32 unused) |
9119708c | 246 | { |
b35b380e | 247 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 248 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
249 | |
250 | if (level != I915_CACHE_NONE) | |
87a6b688 | 251 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
252 | |
253 | return pte; | |
254 | } | |
255 | ||
4d15c145 | 256 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e | 257 | enum i915_cache_level level, |
24f3a8cf | 258 | bool valid, u32 unused) |
4d15c145 | 259 | { |
b35b380e | 260 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
261 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
262 | ||
651d794f CW |
263 | switch (level) { |
264 | case I915_CACHE_NONE: | |
265 | break; | |
266 | case I915_CACHE_WT: | |
c51e9701 | 267 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
268 | break; |
269 | default: | |
c51e9701 | 270 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
271 | break; |
272 | } | |
4d15c145 BW |
273 | |
274 | return pte; | |
275 | } | |
276 | ||
94e409c1 | 277 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 278 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
6689c167 | 279 | uint64_t val) |
94e409c1 BW |
280 | { |
281 | int ret; | |
282 | ||
283 | BUG_ON(entry >= 4); | |
284 | ||
285 | ret = intel_ring_begin(ring, 6); | |
286 | if (ret) | |
287 | return ret; | |
288 | ||
289 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
290 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
291 | intel_ring_emit(ring, (u32)(val >> 32)); | |
292 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
293 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
294 | intel_ring_emit(ring, (u32)(val)); | |
295 | intel_ring_advance(ring); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
eeb9488e | 300 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 301 | struct intel_engine_cs *ring) |
94e409c1 | 302 | { |
eeb9488e | 303 | int i, ret; |
94e409c1 BW |
304 | |
305 | /* bit of a hack to find the actual last used pd */ | |
306 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
307 | ||
94e409c1 BW |
308 | for (i = used_pd - 1; i >= 0; i--) { |
309 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
6689c167 | 310 | ret = gen8_write_pdp(ring, i, addr); |
eeb9488e BW |
311 | if (ret) |
312 | return ret; | |
94e409c1 | 313 | } |
d595bd4b | 314 | |
eeb9488e | 315 | return 0; |
94e409c1 BW |
316 | } |
317 | ||
459108b8 | 318 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
319 | uint64_t start, |
320 | uint64_t length, | |
459108b8 BW |
321 | bool use_scratch) |
322 | { | |
323 | struct i915_hw_ppgtt *ppgtt = | |
324 | container_of(vm, struct i915_hw_ppgtt, base); | |
325 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
326 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
327 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
328 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 329 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
330 | unsigned last_pte, i; |
331 | ||
332 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
333 | I915_CACHE_LLC, use_scratch); | |
334 | ||
335 | while (num_entries) { | |
7ad47cf2 | 336 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 337 | |
7ad47cf2 | 338 | last_pte = pte + num_entries; |
459108b8 BW |
339 | if (last_pte > GEN8_PTES_PER_PAGE) |
340 | last_pte = GEN8_PTES_PER_PAGE; | |
341 | ||
342 | pt_vaddr = kmap_atomic(page_table); | |
343 | ||
7ad47cf2 | 344 | for (i = pte; i < last_pte; i++) { |
459108b8 | 345 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
346 | num_entries--; |
347 | } | |
459108b8 | 348 | |
fd1ab8f4 RB |
349 | if (!HAS_LLC(ppgtt->base.dev)) |
350 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
351 | kunmap_atomic(pt_vaddr); |
352 | ||
7ad47cf2 BW |
353 | pte = 0; |
354 | if (++pde == GEN8_PDES_PER_PAGE) { | |
355 | pdpe++; | |
356 | pde = 0; | |
357 | } | |
459108b8 BW |
358 | } |
359 | } | |
360 | ||
9df15b49 BW |
361 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
362 | struct sg_table *pages, | |
782f1495 | 363 | uint64_t start, |
24f3a8cf | 364 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
365 | { |
366 | struct i915_hw_ppgtt *ppgtt = | |
367 | container_of(vm, struct i915_hw_ppgtt, base); | |
368 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
369 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
370 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
371 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
372 | struct sg_page_iter sg_iter; |
373 | ||
6f1cc993 | 374 | pt_vaddr = NULL; |
7ad47cf2 | 375 | |
9df15b49 | 376 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
377 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
378 | break; | |
379 | ||
6f1cc993 | 380 | if (pt_vaddr == NULL) |
7ad47cf2 | 381 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 382 | |
7ad47cf2 | 383 | pt_vaddr[pte] = |
6f1cc993 CW |
384 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
385 | cache_level, true); | |
7ad47cf2 | 386 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
387 | if (!HAS_LLC(ppgtt->base.dev)) |
388 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 389 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 390 | pt_vaddr = NULL; |
7ad47cf2 BW |
391 | if (++pde == GEN8_PDES_PER_PAGE) { |
392 | pdpe++; | |
393 | pde = 0; | |
394 | } | |
395 | pte = 0; | |
9df15b49 BW |
396 | } |
397 | } | |
fd1ab8f4 RB |
398 | if (pt_vaddr) { |
399 | if (!HAS_LLC(ppgtt->base.dev)) | |
400 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 401 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 402 | } |
9df15b49 BW |
403 | } |
404 | ||
7ad47cf2 BW |
405 | static void gen8_free_page_tables(struct page **pt_pages) |
406 | { | |
407 | int i; | |
408 | ||
409 | if (pt_pages == NULL) | |
410 | return; | |
411 | ||
412 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
413 | if (pt_pages[i]) | |
414 | __free_pages(pt_pages[i], 0); | |
415 | } | |
416 | ||
417 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
418 | { |
419 | int i; | |
420 | ||
7ad47cf2 BW |
421 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
422 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
423 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 424 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 425 | } |
b45a6715 | 426 | |
b45a6715 BW |
427 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
428 | } | |
429 | ||
430 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
431 | { | |
f3a964b9 | 432 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
433 | int i, j; |
434 | ||
435 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
436 | /* TODO: In the future we'll support sparse mappings, so this | |
437 | * will have to change. */ | |
438 | if (!ppgtt->pd_dma_addr[i]) | |
439 | continue; | |
440 | ||
f3a964b9 BW |
441 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
442 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
443 | |
444 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
445 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
446 | if (addr) | |
f3a964b9 BW |
447 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
448 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
449 | } |
450 | } | |
451 | } | |
452 | ||
37aca44a BW |
453 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
454 | { | |
455 | struct i915_hw_ppgtt *ppgtt = | |
456 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 457 | |
b45a6715 BW |
458 | gen8_ppgtt_unmap_pages(ppgtt); |
459 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
460 | } |
461 | ||
7ad47cf2 BW |
462 | static struct page **__gen8_alloc_page_tables(void) |
463 | { | |
464 | struct page **pt_pages; | |
465 | int i; | |
466 | ||
467 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
468 | if (!pt_pages) | |
469 | return ERR_PTR(-ENOMEM); | |
470 | ||
471 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
472 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
473 | if (!pt_pages[i]) | |
474 | goto bail; | |
475 | } | |
476 | ||
477 | return pt_pages; | |
478 | ||
479 | bail: | |
480 | gen8_free_page_tables(pt_pages); | |
481 | kfree(pt_pages); | |
482 | return ERR_PTR(-ENOMEM); | |
483 | } | |
484 | ||
bf2b4ed2 BW |
485 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
486 | const int max_pdp) | |
487 | { | |
7ad47cf2 | 488 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 489 | int i, ret; |
bf2b4ed2 | 490 | |
7ad47cf2 BW |
491 | for (i = 0; i < max_pdp; i++) { |
492 | pt_pages[i] = __gen8_alloc_page_tables(); | |
493 | if (IS_ERR(pt_pages[i])) { | |
494 | ret = PTR_ERR(pt_pages[i]); | |
495 | goto unwind_out; | |
496 | } | |
497 | } | |
498 | ||
499 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
500 | * "atomic" - for cleanup purposes. | |
501 | */ | |
502 | for (i = 0; i < max_pdp; i++) | |
503 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 504 | |
bf2b4ed2 | 505 | return 0; |
7ad47cf2 BW |
506 | |
507 | unwind_out: | |
508 | while (i--) { | |
509 | gen8_free_page_tables(pt_pages[i]); | |
510 | kfree(pt_pages[i]); | |
511 | } | |
512 | ||
513 | return ret; | |
bf2b4ed2 BW |
514 | } |
515 | ||
516 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
517 | { | |
518 | int i; | |
519 | ||
520 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
521 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
522 | sizeof(dma_addr_t), | |
523 | GFP_KERNEL); | |
524 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
525 | return -ENOMEM; | |
526 | } | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
531 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
532 | const int max_pdp) | |
533 | { | |
534 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
535 | if (!ppgtt->pd_pages) | |
536 | return -ENOMEM; | |
537 | ||
538 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
539 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
545 | const int max_pdp) | |
546 | { | |
547 | int ret; | |
548 | ||
549 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
550 | if (ret) | |
551 | return ret; | |
552 | ||
553 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
554 | if (ret) { | |
555 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
556 | return ret; | |
557 | } | |
558 | ||
559 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
560 | ||
561 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
562 | if (ret) | |
563 | gen8_ppgtt_free(ppgtt); | |
564 | ||
565 | return ret; | |
566 | } | |
567 | ||
568 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
569 | const int pd) | |
570 | { | |
571 | dma_addr_t pd_addr; | |
572 | int ret; | |
573 | ||
574 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
575 | &ppgtt->pd_pages[pd], 0, | |
576 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
577 | ||
578 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
579 | if (ret) | |
580 | return ret; | |
581 | ||
582 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
588 | const int pd, | |
589 | const int pt) | |
590 | { | |
591 | dma_addr_t pt_addr; | |
592 | struct page *p; | |
593 | int ret; | |
594 | ||
7ad47cf2 | 595 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
596 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
597 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
598 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
599 | if (ret) | |
600 | return ret; | |
601 | ||
602 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
37aca44a | 607 | /** |
f3a964b9 BW |
608 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
609 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
610 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
611 | * space. | |
37aca44a | 612 | * |
f3a964b9 BW |
613 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
614 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 615 | * TODO: Do something with the size parameter |
f3a964b9 | 616 | */ |
37aca44a BW |
617 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
618 | { | |
37aca44a | 619 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 620 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 621 | int i, j, ret; |
37aca44a BW |
622 | |
623 | if (size % (1<<30)) | |
624 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
625 | ||
bf2b4ed2 BW |
626 | /* 1. Do all our allocations for page directories and page tables. */ |
627 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
628 | if (ret) | |
629 | return ret; | |
f3a964b9 | 630 | |
37aca44a | 631 | /* |
bf2b4ed2 | 632 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
633 | */ |
634 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 635 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
636 | if (ret) |
637 | goto bail; | |
37aca44a | 638 | |
37aca44a | 639 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 640 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
641 | if (ret) |
642 | goto bail; | |
37aca44a BW |
643 | } |
644 | } | |
645 | ||
f3a964b9 BW |
646 | /* |
647 | * 3. Map all the page directory entires to point to the page tables | |
648 | * we've allocated. | |
649 | * | |
650 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 651 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
652 | * will never need to touch the PDEs again. |
653 | */ | |
b1fe6673 BW |
654 | for (i = 0; i < max_pdp; i++) { |
655 | gen8_ppgtt_pde_t *pd_vaddr; | |
656 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
657 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
658 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
659 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
660 | I915_CACHE_LLC); | |
661 | } | |
fd1ab8f4 RB |
662 | if (!HAS_LLC(ppgtt->base.dev)) |
663 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
664 | kunmap_atomic(pd_vaddr); |
665 | } | |
666 | ||
f3a964b9 BW |
667 | ppgtt->switch_mm = gen8_mm_switch; |
668 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
669 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
670 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
671 | ppgtt->base.start = 0; | |
5abbcca3 | 672 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 673 | |
5abbcca3 | 674 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 675 | |
37aca44a BW |
676 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
677 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
678 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
679 | ppgtt->num_pd_entries, |
680 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 681 | return 0; |
37aca44a | 682 | |
f3a964b9 BW |
683 | bail: |
684 | gen8_ppgtt_unmap_pages(ppgtt); | |
685 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
686 | return ret; |
687 | } | |
688 | ||
87d60b63 BW |
689 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
690 | { | |
691 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
692 | struct i915_address_space *vm = &ppgtt->base; | |
693 | gen6_gtt_pte_t __iomem *pd_addr; | |
694 | gen6_gtt_pte_t scratch_pte; | |
695 | uint32_t pd_entry; | |
696 | int pte, pde; | |
697 | ||
24f3a8cf | 698 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 BW |
699 | |
700 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
701 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
702 | ||
703 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
704 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
705 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
706 | u32 expected; | |
707 | gen6_gtt_pte_t *pt_vaddr; | |
708 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
709 | pd_entry = readl(pd_addr + pde); | |
710 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
711 | ||
712 | if (pd_entry != expected) | |
713 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
714 | pde, | |
715 | pd_entry, | |
716 | expected); | |
717 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
718 | ||
719 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
720 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
721 | unsigned long va = | |
722 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
723 | (pte * PAGE_SIZE); | |
724 | int i; | |
725 | bool found = false; | |
726 | for (i = 0; i < 4; i++) | |
727 | if (pt_vaddr[pte + i] != scratch_pte) | |
728 | found = true; | |
729 | if (!found) | |
730 | continue; | |
731 | ||
732 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
733 | for (i = 0; i < 4; i++) { | |
734 | if (pt_vaddr[pte + i] != scratch_pte) | |
735 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
736 | else | |
737 | seq_puts(m, " SCRATCH "); | |
738 | } | |
739 | seq_puts(m, "\n"); | |
740 | } | |
741 | kunmap_atomic(pt_vaddr); | |
742 | } | |
743 | } | |
744 | ||
3e302542 | 745 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 746 | { |
853ba5d2 | 747 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
748 | gen6_gtt_pte_t __iomem *pd_addr; |
749 | uint32_t pd_entry; | |
750 | int i; | |
751 | ||
0a732870 | 752 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
753 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
754 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
755 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
756 | dma_addr_t pt_addr; | |
757 | ||
758 | pt_addr = ppgtt->pt_dma_addr[i]; | |
759 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
760 | pd_entry |= GEN6_PDE_VALID; | |
761 | ||
762 | writel(pd_entry, pd_addr + i); | |
763 | } | |
764 | readl(pd_addr); | |
3e302542 BW |
765 | } |
766 | ||
b4a74e3a | 767 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 768 | { |
b4a74e3a BW |
769 | BUG_ON(ppgtt->pd_offset & 0x3f); |
770 | ||
771 | return (ppgtt->pd_offset / 64) << 16; | |
772 | } | |
773 | ||
90252e5c | 774 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 775 | struct intel_engine_cs *ring) |
90252e5c | 776 | { |
90252e5c BW |
777 | int ret; |
778 | ||
90252e5c BW |
779 | /* NB: TLBs must be flushed and invalidated before a switch */ |
780 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
781 | if (ret) | |
782 | return ret; | |
783 | ||
784 | ret = intel_ring_begin(ring, 6); | |
785 | if (ret) | |
786 | return ret; | |
787 | ||
788 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
789 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
790 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
791 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
792 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
793 | intel_ring_emit(ring, MI_NOOP); | |
794 | intel_ring_advance(ring); | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
48a10389 | 799 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 800 | struct intel_engine_cs *ring) |
48a10389 | 801 | { |
48a10389 BW |
802 | int ret; |
803 | ||
48a10389 BW |
804 | /* NB: TLBs must be flushed and invalidated before a switch */ |
805 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
806 | if (ret) | |
807 | return ret; | |
808 | ||
809 | ret = intel_ring_begin(ring, 6); | |
810 | if (ret) | |
811 | return ret; | |
812 | ||
813 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
814 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
815 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
816 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
817 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
818 | intel_ring_emit(ring, MI_NOOP); | |
819 | intel_ring_advance(ring); | |
820 | ||
90252e5c BW |
821 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
822 | if (ring->id != RCS) { | |
823 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
824 | if (ret) | |
825 | return ret; | |
826 | } | |
827 | ||
48a10389 BW |
828 | return 0; |
829 | } | |
830 | ||
eeb9488e | 831 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 832 | struct intel_engine_cs *ring) |
eeb9488e BW |
833 | { |
834 | struct drm_device *dev = ppgtt->base.dev; | |
835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
836 | ||
48a10389 | 837 | |
eeb9488e BW |
838 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
839 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
840 | ||
841 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
82460d97 | 846 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 847 | { |
eeb9488e | 848 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 849 | struct intel_engine_cs *ring; |
82460d97 | 850 | int j; |
3e302542 | 851 | |
eeb9488e BW |
852 | for_each_ring(ring, dev_priv, j) { |
853 | I915_WRITE(RING_MODE_GEN7(ring), | |
854 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 855 | } |
eeb9488e | 856 | } |
6197349b | 857 | |
82460d97 | 858 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 859 | { |
50227e1c | 860 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 861 | struct intel_engine_cs *ring; |
b4a74e3a | 862 | uint32_t ecochk, ecobits; |
3e302542 | 863 | int i; |
6197349b | 864 | |
b4a74e3a BW |
865 | ecobits = I915_READ(GAC_ECO_BITS); |
866 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 867 | |
b4a74e3a BW |
868 | ecochk = I915_READ(GAM_ECOCHK); |
869 | if (IS_HASWELL(dev)) { | |
870 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
871 | } else { | |
872 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
873 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
874 | } | |
875 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 876 | |
b4a74e3a | 877 | for_each_ring(ring, dev_priv, i) { |
6197349b | 878 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
879 | I915_WRITE(RING_MODE_GEN7(ring), |
880 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 881 | } |
b4a74e3a | 882 | } |
6197349b | 883 | |
82460d97 | 884 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 885 | { |
50227e1c | 886 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 887 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 888 | |
b4a74e3a BW |
889 | ecobits = I915_READ(GAC_ECO_BITS); |
890 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
891 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 892 | |
b4a74e3a BW |
893 | gab_ctl = I915_READ(GAB_CTL); |
894 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
895 | ||
896 | ecochk = I915_READ(GAM_ECOCHK); | |
897 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
898 | ||
899 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
900 | } |
901 | ||
1d2a314c | 902 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 903 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
904 | uint64_t start, |
905 | uint64_t length, | |
828c7908 | 906 | bool use_scratch) |
1d2a314c | 907 | { |
853ba5d2 BW |
908 | struct i915_hw_ppgtt *ppgtt = |
909 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 910 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
911 | unsigned first_entry = start >> PAGE_SHIFT; |
912 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 913 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
914 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
915 | unsigned last_pte, i; | |
1d2a314c | 916 | |
24f3a8cf | 917 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 918 | |
7bddb01f DV |
919 | while (num_entries) { |
920 | last_pte = first_pte + num_entries; | |
921 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
922 | last_pte = I915_PPGTT_PT_ENTRIES; | |
923 | ||
a15326a5 | 924 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 925 | |
7bddb01f DV |
926 | for (i = first_pte; i < last_pte; i++) |
927 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
928 | |
929 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 930 | |
7bddb01f DV |
931 | num_entries -= last_pte - first_pte; |
932 | first_pte = 0; | |
a15326a5 | 933 | act_pt++; |
7bddb01f | 934 | } |
1d2a314c DV |
935 | } |
936 | ||
853ba5d2 | 937 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 938 | struct sg_table *pages, |
782f1495 | 939 | uint64_t start, |
24f3a8cf | 940 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 941 | { |
853ba5d2 BW |
942 | struct i915_hw_ppgtt *ppgtt = |
943 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 944 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 945 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 946 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
947 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
948 | struct sg_page_iter sg_iter; | |
949 | ||
cc79714f | 950 | pt_vaddr = NULL; |
6e995e23 | 951 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
952 | if (pt_vaddr == NULL) |
953 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 954 | |
cc79714f CW |
955 | pt_vaddr[act_pte] = |
956 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
957 | cache_level, true, flags); |
958 | ||
6e995e23 ID |
959 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
960 | kunmap_atomic(pt_vaddr); | |
cc79714f | 961 | pt_vaddr = NULL; |
a15326a5 | 962 | act_pt++; |
6e995e23 | 963 | act_pte = 0; |
def886c3 | 964 | } |
def886c3 | 965 | } |
cc79714f CW |
966 | if (pt_vaddr) |
967 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
968 | } |
969 | ||
a00d825d | 970 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 971 | { |
3440d265 DV |
972 | int i; |
973 | ||
974 | if (ppgtt->pt_dma_addr) { | |
975 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 976 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
977 | ppgtt->pt_dma_addr[i], |
978 | 4096, PCI_DMA_BIDIRECTIONAL); | |
979 | } | |
a00d825d BW |
980 | } |
981 | ||
982 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
983 | { | |
984 | int i; | |
3440d265 DV |
985 | |
986 | kfree(ppgtt->pt_dma_addr); | |
987 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
988 | __free_page(ppgtt->pt_pages[i]); | |
989 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
990 | } |
991 | ||
a00d825d BW |
992 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
993 | { | |
994 | struct i915_hw_ppgtt *ppgtt = | |
995 | container_of(vm, struct i915_hw_ppgtt, base); | |
996 | ||
a00d825d BW |
997 | drm_mm_remove_node(&ppgtt->node); |
998 | ||
999 | gen6_ppgtt_unmap_pages(ppgtt); | |
1000 | gen6_ppgtt_free(ppgtt); | |
1001 | } | |
1002 | ||
b146520f | 1003 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1004 | { |
853ba5d2 | 1005 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1006 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1007 | bool retried = false; |
b146520f | 1008 | int ret; |
1d2a314c | 1009 | |
c8d4c0d6 BW |
1010 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1011 | * allocator works in address space sizes, so it's multiplied by page | |
1012 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1013 | */ | |
1014 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1015 | alloc: |
c8d4c0d6 BW |
1016 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1017 | &ppgtt->node, GEN6_PD_SIZE, | |
1018 | GEN6_PD_ALIGN, 0, | |
1019 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1020 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1021 | if (ret == -ENOSPC && !retried) { |
1022 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1023 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1024 | I915_CACHE_NONE, |
1025 | 0, dev_priv->gtt.base.total, | |
1026 | 0); | |
e3cc1995 BW |
1027 | if (ret) |
1028 | return ret; | |
1029 | ||
1030 | retried = true; | |
1031 | goto alloc; | |
1032 | } | |
c8d4c0d6 BW |
1033 | |
1034 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1035 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1036 | |
6670a5a5 | 1037 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
1038 | return ret; |
1039 | } | |
1040 | ||
1041 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1042 | { | |
1043 | int i; | |
1044 | ||
a1e22653 | 1045 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1046 | GFP_KERNEL); |
b146520f BW |
1047 | |
1048 | if (!ppgtt->pt_pages) | |
3440d265 | 1049 | return -ENOMEM; |
1d2a314c DV |
1050 | |
1051 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1052 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
1053 | if (!ppgtt->pt_pages[i]) { |
1054 | gen6_ppgtt_free(ppgtt); | |
1055 | return -ENOMEM; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1063 | { | |
1064 | int ret; | |
1065 | ||
1066 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1067 | if (ret) | |
1068 | return ret; | |
1069 | ||
1070 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1071 | if (ret) { | |
1072 | drm_mm_remove_node(&ppgtt->node); | |
1073 | return ret; | |
1d2a314c DV |
1074 | } |
1075 | ||
a1e22653 | 1076 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1077 | GFP_KERNEL); |
b146520f BW |
1078 | if (!ppgtt->pt_dma_addr) { |
1079 | drm_mm_remove_node(&ppgtt->node); | |
1080 | gen6_ppgtt_free(ppgtt); | |
1081 | return -ENOMEM; | |
1082 | } | |
1083 | ||
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1088 | { | |
1089 | struct drm_device *dev = ppgtt->base.dev; | |
1090 | int i; | |
1d2a314c | 1091 | |
8d2e6308 BW |
1092 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1093 | dma_addr_t pt_addr; | |
211c568b | 1094 | |
8d2e6308 BW |
1095 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1096 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1097 | |
8d2e6308 | 1098 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1099 | gen6_ppgtt_unmap_pages(ppgtt); |
1100 | return -EIO; | |
211c568b | 1101 | } |
b146520f | 1102 | |
8d2e6308 | 1103 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1104 | } |
1d2a314c | 1105 | |
b146520f BW |
1106 | return 0; |
1107 | } | |
1108 | ||
1109 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1110 | { | |
1111 | struct drm_device *dev = ppgtt->base.dev; | |
1112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1113 | int ret; | |
1114 | ||
1115 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1116 | if (IS_GEN6(dev)) { | |
b146520f BW |
1117 | ppgtt->switch_mm = gen6_mm_switch; |
1118 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1119 | ppgtt->switch_mm = hsw_mm_switch; |
1120 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1121 | ppgtt->switch_mm = gen7_mm_switch; |
1122 | } else | |
1123 | BUG(); | |
1124 | ||
1125 | ret = gen6_ppgtt_alloc(ppgtt); | |
1126 | if (ret) | |
1127 | return ret; | |
1128 | ||
1129 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1130 | if (ret) { | |
1131 | gen6_ppgtt_free(ppgtt); | |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1136 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1137 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1138 | ppgtt->base.start = 0; |
5a6c93fe | 1139 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1140 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1141 | |
c8d4c0d6 BW |
1142 | ppgtt->pd_offset = |
1143 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1144 | |
b146520f | 1145 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1146 | |
b146520f BW |
1147 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1148 | ppgtt->node.size >> 20, | |
1149 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1150 | |
fa76da34 DV |
1151 | gen6_write_pdes(ppgtt); |
1152 | DRM_DEBUG("Adding PPGTT at offset %x\n", | |
1153 | ppgtt->pd_offset << 10); | |
1154 | ||
b146520f | 1155 | return 0; |
3440d265 DV |
1156 | } |
1157 | ||
fa76da34 | 1158 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1159 | { |
1160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1161 | |
853ba5d2 | 1162 | ppgtt->base.dev = dev; |
8407bb91 | 1163 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1164 | |
3ed124b2 | 1165 | if (INTEL_INFO(dev)->gen < 8) |
fa76da34 | 1166 | return gen6_ppgtt_init(ppgtt); |
3fdcf80f | 1167 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
fa76da34 | 1168 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1169 | else |
1170 | BUG(); | |
fa76da34 DV |
1171 | } |
1172 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1173 | { | |
1174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1175 | int ret = 0; | |
3ed124b2 | 1176 | |
fa76da34 DV |
1177 | ret = __hw_ppgtt_init(dev, ppgtt); |
1178 | if (ret == 0) { | |
c7c48dfd | 1179 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1180 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1181 | ppgtt->base.total); | |
7e0d96bc | 1182 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1183 | } |
1d2a314c DV |
1184 | |
1185 | return ret; | |
1186 | } | |
1187 | ||
82460d97 DV |
1188 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1189 | { | |
1190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1191 | struct intel_engine_cs *ring; | |
1192 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1193 | int i, ret = 0; | |
1194 | ||
671b5013 TD |
1195 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1196 | * and the PDPs are contained within the context itself. We don't | |
1197 | * need to do anything here. */ | |
1198 | if (i915.enable_execlists) | |
1199 | return 0; | |
1200 | ||
82460d97 DV |
1201 | if (!USES_PPGTT(dev)) |
1202 | return 0; | |
1203 | ||
1204 | if (IS_GEN6(dev)) | |
1205 | gen6_ppgtt_enable(dev); | |
1206 | else if (IS_GEN7(dev)) | |
1207 | gen7_ppgtt_enable(dev); | |
1208 | else if (INTEL_INFO(dev)->gen >= 8) | |
1209 | gen8_ppgtt_enable(dev); | |
1210 | else | |
5f77eeb0 | 1211 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 DV |
1212 | |
1213 | if (ppgtt) { | |
1214 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1215 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1216 | if (ret != 0) |
1217 | return ret; | |
7e0d96bc | 1218 | } |
93bd8649 | 1219 | } |
1d2a314c DV |
1220 | |
1221 | return ret; | |
1222 | } | |
4d884705 DV |
1223 | struct i915_hw_ppgtt * |
1224 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1225 | { | |
1226 | struct i915_hw_ppgtt *ppgtt; | |
1227 | int ret; | |
1228 | ||
1229 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1230 | if (!ppgtt) | |
1231 | return ERR_PTR(-ENOMEM); | |
1232 | ||
1233 | ret = i915_ppgtt_init(dev, ppgtt); | |
1234 | if (ret) { | |
1235 | kfree(ppgtt); | |
1236 | return ERR_PTR(ret); | |
1237 | } | |
1238 | ||
1239 | ppgtt->file_priv = fpriv; | |
1240 | ||
198c974d DCS |
1241 | trace_i915_ppgtt_create(&ppgtt->base); |
1242 | ||
4d884705 DV |
1243 | return ppgtt; |
1244 | } | |
1245 | ||
ee960be7 DV |
1246 | void i915_ppgtt_release(struct kref *kref) |
1247 | { | |
1248 | struct i915_hw_ppgtt *ppgtt = | |
1249 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1250 | ||
198c974d DCS |
1251 | trace_i915_ppgtt_release(&ppgtt->base); |
1252 | ||
ee960be7 DV |
1253 | /* vmas should already be unbound */ |
1254 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1255 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1256 | ||
19dd120c DV |
1257 | list_del(&ppgtt->base.global_link); |
1258 | drm_mm_takedown(&ppgtt->base.mm); | |
1259 | ||
ee960be7 DV |
1260 | ppgtt->base.cleanup(&ppgtt->base); |
1261 | kfree(ppgtt); | |
1262 | } | |
1d2a314c | 1263 | |
7e0d96bc | 1264 | static void |
6f65e29a BW |
1265 | ppgtt_bind_vma(struct i915_vma *vma, |
1266 | enum i915_cache_level cache_level, | |
1267 | u32 flags) | |
1d2a314c | 1268 | { |
24f3a8cf AG |
1269 | /* Currently applicable only to VLV */ |
1270 | if (vma->obj->gt_ro) | |
1271 | flags |= PTE_READ_ONLY; | |
1272 | ||
782f1495 | 1273 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1274 | cache_level, flags); |
1d2a314c DV |
1275 | } |
1276 | ||
7e0d96bc | 1277 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1278 | { |
6f65e29a | 1279 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1280 | vma->node.start, |
1281 | vma->obj->base.size, | |
6f65e29a | 1282 | true); |
7bddb01f DV |
1283 | } |
1284 | ||
a81cc00c BW |
1285 | extern int intel_iommu_gfx_mapped; |
1286 | /* Certain Gen5 chipsets require require idling the GPU before | |
1287 | * unmapping anything from the GTT when VT-d is enabled. | |
1288 | */ | |
1289 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1290 | { | |
1291 | #ifdef CONFIG_INTEL_IOMMU | |
1292 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1293 | * was loaded first. | |
1294 | */ | |
1295 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1296 | return true; | |
1297 | #endif | |
1298 | return false; | |
1299 | } | |
1300 | ||
5c042287 BW |
1301 | static bool do_idling(struct drm_i915_private *dev_priv) |
1302 | { | |
1303 | bool ret = dev_priv->mm.interruptible; | |
1304 | ||
a81cc00c | 1305 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1306 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1307 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1308 | DRM_ERROR("Couldn't idle GPU\n"); |
1309 | /* Wait a bit, in hopes it avoids the hang */ | |
1310 | udelay(10); | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | return ret; | |
1315 | } | |
1316 | ||
1317 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1318 | { | |
a81cc00c | 1319 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1320 | dev_priv->mm.interruptible = interruptible; |
1321 | } | |
1322 | ||
828c7908 BW |
1323 | void i915_check_and_clear_faults(struct drm_device *dev) |
1324 | { | |
1325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1326 | struct intel_engine_cs *ring; |
828c7908 BW |
1327 | int i; |
1328 | ||
1329 | if (INTEL_INFO(dev)->gen < 6) | |
1330 | return; | |
1331 | ||
1332 | for_each_ring(ring, dev_priv, i) { | |
1333 | u32 fault_reg; | |
1334 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1335 | if (fault_reg & RING_FAULT_VALID) { | |
1336 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1337 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1338 | "\tAddress space: %s\n" |
1339 | "\tSource ID: %d\n" | |
1340 | "\tType: %d\n", | |
1341 | fault_reg & PAGE_MASK, | |
1342 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1343 | RING_FAULT_SRCID(fault_reg), | |
1344 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1345 | I915_WRITE(RING_FAULT_REG(ring), | |
1346 | fault_reg & ~RING_FAULT_VALID); | |
1347 | } | |
1348 | } | |
1349 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1350 | } | |
1351 | ||
91e56499 CW |
1352 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1353 | { | |
1354 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1355 | intel_gtt_chipset_flush(); | |
1356 | } else { | |
1357 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1358 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1359 | } | |
1360 | } | |
1361 | ||
828c7908 BW |
1362 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1363 | { | |
1364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1365 | ||
1366 | /* Don't bother messing with faults pre GEN6 as we have little | |
1367 | * documentation supporting that it's a good idea. | |
1368 | */ | |
1369 | if (INTEL_INFO(dev)->gen < 6) | |
1370 | return; | |
1371 | ||
1372 | i915_check_and_clear_faults(dev); | |
1373 | ||
1374 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1375 | dev_priv->gtt.base.start, |
1376 | dev_priv->gtt.base.total, | |
e568af1c | 1377 | true); |
91e56499 CW |
1378 | |
1379 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1380 | } |
1381 | ||
76aaf220 DV |
1382 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1383 | { | |
1384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1385 | struct drm_i915_gem_object *obj; |
80da2161 | 1386 | struct i915_address_space *vm; |
76aaf220 | 1387 | |
828c7908 BW |
1388 | i915_check_and_clear_faults(dev); |
1389 | ||
bee4a186 | 1390 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1391 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1392 | dev_priv->gtt.base.start, |
1393 | dev_priv->gtt.base.total, | |
828c7908 | 1394 | true); |
bee4a186 | 1395 | |
35c20a60 | 1396 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1397 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1398 | &dev_priv->gtt.base); | |
1399 | if (!vma) | |
1400 | continue; | |
1401 | ||
2c22569b | 1402 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1403 | /* The bind_vma code tries to be smart about tracking mappings. |
1404 | * Unfortunately above, we've just wiped out the mappings | |
1405 | * without telling our object about it. So we need to fake it. | |
fe14d5f4 TU |
1406 | * |
1407 | * Bind is not expected to fail since this is only called on | |
1408 | * resume and assumption is all requirements exist already. | |
6f65e29a | 1409 | */ |
aff43766 | 1410 | vma->bound &= ~GLOBAL_BIND; |
fe14d5f4 | 1411 | WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); |
76aaf220 DV |
1412 | } |
1413 | ||
80da2161 | 1414 | |
a2319c08 | 1415 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1416 | if (IS_CHERRYVIEW(dev)) |
1417 | chv_setup_private_ppat(dev_priv); | |
1418 | else | |
1419 | bdw_setup_private_ppat(dev_priv); | |
1420 | ||
80da2161 | 1421 | return; |
a2319c08 | 1422 | } |
80da2161 BW |
1423 | |
1424 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1425 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1426 | if (i915_is_ggtt(vm)) { | |
1427 | if (dev_priv->mm.aliasing_ppgtt) | |
1428 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1429 | continue; | |
1430 | } | |
1431 | ||
1432 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1433 | } |
1434 | ||
91e56499 | 1435 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1436 | } |
7c2e6fdf | 1437 | |
74163907 | 1438 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1439 | { |
9da3da66 | 1440 | if (obj->has_dma_mapping) |
74163907 | 1441 | return 0; |
9da3da66 CW |
1442 | |
1443 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1444 | obj->pages->sgl, obj->pages->nents, | |
1445 | PCI_DMA_BIDIRECTIONAL)) | |
1446 | return -ENOSPC; | |
1447 | ||
1448 | return 0; | |
7c2e6fdf DV |
1449 | } |
1450 | ||
94ec8f61 BW |
1451 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1452 | { | |
1453 | #ifdef writeq | |
1454 | writeq(pte, addr); | |
1455 | #else | |
1456 | iowrite32((u32)pte, addr); | |
1457 | iowrite32(pte >> 32, addr + 4); | |
1458 | #endif | |
1459 | } | |
1460 | ||
1461 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1462 | struct sg_table *st, | |
782f1495 | 1463 | uint64_t start, |
24f3a8cf | 1464 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1465 | { |
1466 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1467 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1468 | gen8_gtt_pte_t __iomem *gtt_entries = |
1469 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1470 | int i = 0; | |
1471 | struct sg_page_iter sg_iter; | |
57007df7 | 1472 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1473 | |
1474 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1475 | addr = sg_dma_address(sg_iter.sg) + | |
1476 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1477 | gen8_set_pte(>t_entries[i], | |
1478 | gen8_pte_encode(addr, level, true)); | |
1479 | i++; | |
1480 | } | |
1481 | ||
1482 | /* | |
1483 | * XXX: This serves as a posting read to make sure that the PTE has | |
1484 | * actually been updated. There is some concern that even though | |
1485 | * registers and PTEs are within the same BAR that they are potentially | |
1486 | * of NUMA access patterns. Therefore, even with the way we assume | |
1487 | * hardware should work, we must keep this posting read for paranoia. | |
1488 | */ | |
1489 | if (i != 0) | |
1490 | WARN_ON(readq(>t_entries[i-1]) | |
1491 | != gen8_pte_encode(addr, level, true)); | |
1492 | ||
94ec8f61 BW |
1493 | /* This next bit makes the above posting read even more important. We |
1494 | * want to flush the TLBs only after we're certain all the PTE updates | |
1495 | * have finished. | |
1496 | */ | |
1497 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1498 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1499 | } |
1500 | ||
e76e9aeb BW |
1501 | /* |
1502 | * Binds an object into the global gtt with the specified cache level. The object | |
1503 | * will be accessible to the GPU via commands whose operands reference offsets | |
1504 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1505 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1506 | */ | |
853ba5d2 | 1507 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1508 | struct sg_table *st, |
782f1495 | 1509 | uint64_t start, |
24f3a8cf | 1510 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1511 | { |
853ba5d2 | 1512 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1513 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1514 | gen6_gtt_pte_t __iomem *gtt_entries = |
1515 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1516 | int i = 0; |
1517 | struct sg_page_iter sg_iter; | |
57007df7 | 1518 | dma_addr_t addr = 0; |
e76e9aeb | 1519 | |
6e995e23 | 1520 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1521 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1522 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1523 | i++; |
e76e9aeb BW |
1524 | } |
1525 | ||
e76e9aeb BW |
1526 | /* XXX: This serves as a posting read to make sure that the PTE has |
1527 | * actually been updated. There is some concern that even though | |
1528 | * registers and PTEs are within the same BAR that they are potentially | |
1529 | * of NUMA access patterns. Therefore, even with the way we assume | |
1530 | * hardware should work, we must keep this posting read for paranoia. | |
1531 | */ | |
57007df7 PM |
1532 | if (i != 0) { |
1533 | unsigned long gtt = readl(>t_entries[i-1]); | |
1534 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1535 | } | |
0f9b91c7 BW |
1536 | |
1537 | /* This next bit makes the above posting read even more important. We | |
1538 | * want to flush the TLBs only after we're certain all the PTE updates | |
1539 | * have finished. | |
1540 | */ | |
1541 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1542 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1543 | } |
1544 | ||
94ec8f61 | 1545 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1546 | uint64_t start, |
1547 | uint64_t length, | |
94ec8f61 BW |
1548 | bool use_scratch) |
1549 | { | |
1550 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1551 | unsigned first_entry = start >> PAGE_SHIFT; |
1552 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1553 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1554 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1555 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1556 | int i; | |
1557 | ||
1558 | if (WARN(num_entries > max_entries, | |
1559 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1560 | first_entry, num_entries, max_entries)) | |
1561 | num_entries = max_entries; | |
1562 | ||
1563 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1564 | I915_CACHE_LLC, | |
1565 | use_scratch); | |
1566 | for (i = 0; i < num_entries; i++) | |
1567 | gen8_set_pte(>t_base[i], scratch_pte); | |
1568 | readl(gtt_base); | |
1569 | } | |
1570 | ||
853ba5d2 | 1571 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1572 | uint64_t start, |
1573 | uint64_t length, | |
828c7908 | 1574 | bool use_scratch) |
7faf1ab2 | 1575 | { |
853ba5d2 | 1576 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1577 | unsigned first_entry = start >> PAGE_SHIFT; |
1578 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1579 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1580 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1581 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1582 | int i; |
1583 | ||
1584 | if (WARN(num_entries > max_entries, | |
1585 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1586 | first_entry, num_entries, max_entries)) | |
1587 | num_entries = max_entries; | |
1588 | ||
24f3a8cf | 1589 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1590 | |
7faf1ab2 DV |
1591 | for (i = 0; i < num_entries; i++) |
1592 | iowrite32(scratch_pte, >t_base[i]); | |
1593 | readl(gtt_base); | |
1594 | } | |
1595 | ||
6f65e29a BW |
1596 | |
1597 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1598 | enum i915_cache_level cache_level, | |
1599 | u32 unused) | |
7faf1ab2 | 1600 | { |
6f65e29a | 1601 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1602 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1603 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1604 | ||
6f65e29a | 1605 | BUG_ON(!i915_is_ggtt(vma->vm)); |
fe14d5f4 | 1606 | intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); |
aff43766 | 1607 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1608 | } |
1609 | ||
853ba5d2 | 1610 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1611 | uint64_t start, |
1612 | uint64_t length, | |
828c7908 | 1613 | bool unused) |
7faf1ab2 | 1614 | { |
782f1495 BW |
1615 | unsigned first_entry = start >> PAGE_SHIFT; |
1616 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1617 | intel_gtt_clear_range(first_entry, num_entries); |
1618 | } | |
1619 | ||
6f65e29a BW |
1620 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1621 | { | |
1622 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1623 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1624 | |
6f65e29a | 1625 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1626 | vma->bound = 0; |
6f65e29a BW |
1627 | intel_gtt_clear_range(first, size); |
1628 | } | |
7faf1ab2 | 1629 | |
6f65e29a BW |
1630 | static void ggtt_bind_vma(struct i915_vma *vma, |
1631 | enum i915_cache_level cache_level, | |
1632 | u32 flags) | |
d5bd1449 | 1633 | { |
6f65e29a | 1634 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1635 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1636 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1637 | |
24f3a8cf AG |
1638 | /* Currently applicable only to VLV */ |
1639 | if (obj->gt_ro) | |
1640 | flags |= PTE_READ_ONLY; | |
1641 | ||
6f65e29a BW |
1642 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1643 | * or we have a global mapping already but the cacheability flags have | |
1644 | * changed, set the global PTEs. | |
1645 | * | |
1646 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1647 | * instead if none of the above hold true. | |
1648 | * | |
1649 | * NB: A global mapping should only be needed for special regions like | |
1650 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1651 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1652 | */ | |
1653 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 1654 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 1655 | (cache_level != obj->cache_level)) { |
fe14d5f4 | 1656 | vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages, |
782f1495 | 1657 | vma->node.start, |
24f3a8cf | 1658 | cache_level, flags); |
aff43766 | 1659 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
1660 | } |
1661 | } | |
d5bd1449 | 1662 | |
6f65e29a | 1663 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 1664 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
1665 | (cache_level != obj->cache_level))) { |
1666 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1667 | appgtt->base.insert_entries(&appgtt->base, | |
fe14d5f4 | 1668 | vma->ggtt_view.pages, |
782f1495 | 1669 | vma->node.start, |
24f3a8cf | 1670 | cache_level, flags); |
aff43766 | 1671 | vma->bound |= LOCAL_BIND; |
6f65e29a | 1672 | } |
d5bd1449 CW |
1673 | } |
1674 | ||
6f65e29a | 1675 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1676 | { |
6f65e29a | 1677 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1678 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1679 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1680 | |
aff43766 | 1681 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1682 | vma->vm->clear_range(vma->vm, |
1683 | vma->node.start, | |
1684 | obj->base.size, | |
6f65e29a | 1685 | true); |
aff43766 | 1686 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1687 | } |
74898d7e | 1688 | |
aff43766 | 1689 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1690 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1691 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1692 | vma->node.start, |
1693 | obj->base.size, | |
6f65e29a | 1694 | true); |
aff43766 | 1695 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 1696 | } |
74163907 DV |
1697 | } |
1698 | ||
1699 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1700 | { |
5c042287 BW |
1701 | struct drm_device *dev = obj->base.dev; |
1702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1703 | bool interruptible; | |
1704 | ||
1705 | interruptible = do_idling(dev_priv); | |
1706 | ||
9da3da66 CW |
1707 | if (!obj->has_dma_mapping) |
1708 | dma_unmap_sg(&dev->pdev->dev, | |
1709 | obj->pages->sgl, obj->pages->nents, | |
1710 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1711 | |
1712 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1713 | } |
644ec02b | 1714 | |
42d6ab48 CW |
1715 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1716 | unsigned long color, | |
1717 | unsigned long *start, | |
1718 | unsigned long *end) | |
1719 | { | |
1720 | if (node->color != color) | |
1721 | *start += 4096; | |
1722 | ||
1723 | if (!list_empty(&node->node_list)) { | |
1724 | node = list_entry(node->node_list.next, | |
1725 | struct drm_mm_node, | |
1726 | node_list); | |
1727 | if (node->allocated && node->color != color) | |
1728 | *end -= 4096; | |
1729 | } | |
1730 | } | |
fbe5d36e | 1731 | |
f548c0e9 DV |
1732 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1733 | unsigned long start, | |
1734 | unsigned long mappable_end, | |
1735 | unsigned long end) | |
644ec02b | 1736 | { |
e78891ca BW |
1737 | /* Let GEM Manage all of the aperture. |
1738 | * | |
1739 | * However, leave one page at the end still bound to the scratch page. | |
1740 | * There are a number of places where the hardware apparently prefetches | |
1741 | * past the end of the object, and we've seen multiple hangs with the | |
1742 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1743 | * aperture. One page should be enough to keep any prefetching inside | |
1744 | * of the aperture. | |
1745 | */ | |
40d74980 BW |
1746 | struct drm_i915_private *dev_priv = dev->dev_private; |
1747 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1748 | struct drm_mm_node *entry; |
1749 | struct drm_i915_gem_object *obj; | |
1750 | unsigned long hole_start, hole_end; | |
fa76da34 | 1751 | int ret; |
644ec02b | 1752 | |
35451cb6 BW |
1753 | BUG_ON(mappable_end > end); |
1754 | ||
ed2f3452 | 1755 | /* Subtract the guard page ... */ |
40d74980 | 1756 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1757 | if (!HAS_LLC(dev)) |
93bd8649 | 1758 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1759 | |
ed2f3452 | 1760 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1761 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1762 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 1763 | |
edd41a87 | 1764 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1765 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1766 | ||
1767 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1768 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
1769 | if (ret) { |
1770 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
1771 | return ret; | |
1772 | } | |
aff43766 | 1773 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
1774 | } |
1775 | ||
853ba5d2 BW |
1776 | dev_priv->gtt.base.start = start; |
1777 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1778 | |
ed2f3452 | 1779 | /* Clear any non-preallocated blocks */ |
40d74980 | 1780 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1781 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1782 | hole_start, hole_end); | |
782f1495 BW |
1783 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1784 | hole_end - hole_start, true); | |
ed2f3452 CW |
1785 | } |
1786 | ||
1787 | /* And finally clear the reserved guard page */ | |
782f1495 | 1788 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 1789 | |
fa76da34 DV |
1790 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
1791 | struct i915_hw_ppgtt *ppgtt; | |
1792 | ||
1793 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1794 | if (!ppgtt) | |
1795 | return -ENOMEM; | |
1796 | ||
1797 | ret = __hw_ppgtt_init(dev, ppgtt); | |
1798 | if (ret != 0) | |
1799 | return ret; | |
1800 | ||
1801 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1802 | } | |
1803 | ||
6c5566a8 | 1804 | return 0; |
e76e9aeb BW |
1805 | } |
1806 | ||
d7e5008f BW |
1807 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1808 | { | |
1809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1810 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1811 | |
853ba5d2 | 1812 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1813 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1814 | |
e78891ca | 1815 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1816 | } |
1817 | ||
90d0a0e8 DV |
1818 | void i915_global_gtt_cleanup(struct drm_device *dev) |
1819 | { | |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1821 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
1822 | ||
70e32544 DV |
1823 | if (dev_priv->mm.aliasing_ppgtt) { |
1824 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1825 | ||
1826 | ppgtt->base.cleanup(&ppgtt->base); | |
1827 | } | |
1828 | ||
90d0a0e8 DV |
1829 | if (drm_mm_initialized(&vm->mm)) { |
1830 | drm_mm_takedown(&vm->mm); | |
1831 | list_del(&vm->global_link); | |
1832 | } | |
1833 | ||
1834 | vm->cleanup(vm); | |
1835 | } | |
70e32544 | 1836 | |
e76e9aeb BW |
1837 | static int setup_scratch_page(struct drm_device *dev) |
1838 | { | |
1839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1840 | struct page *page; | |
1841 | dma_addr_t dma_addr; | |
1842 | ||
1843 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1844 | if (page == NULL) | |
1845 | return -ENOMEM; | |
e76e9aeb BW |
1846 | set_pages_uc(page, 1); |
1847 | ||
1848 | #ifdef CONFIG_INTEL_IOMMU | |
1849 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1850 | PCI_DMA_BIDIRECTIONAL); | |
1851 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1852 | return -EINVAL; | |
1853 | #else | |
1854 | dma_addr = page_to_phys(page); | |
1855 | #endif | |
853ba5d2 BW |
1856 | dev_priv->gtt.base.scratch.page = page; |
1857 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1858 | |
1859 | return 0; | |
1860 | } | |
1861 | ||
1862 | static void teardown_scratch_page(struct drm_device *dev) | |
1863 | { | |
1864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1865 | struct page *page = dev_priv->gtt.base.scratch.page; |
1866 | ||
1867 | set_pages_wb(page, 1); | |
1868 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1869 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 1870 | __free_page(page); |
e76e9aeb BW |
1871 | } |
1872 | ||
1873 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1874 | { | |
1875 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1876 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1877 | return snb_gmch_ctl << 20; | |
1878 | } | |
1879 | ||
9459d252 BW |
1880 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1881 | { | |
1882 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1883 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1884 | if (bdw_gmch_ctl) | |
1885 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
1886 | |
1887 | #ifdef CONFIG_X86_32 | |
1888 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
1889 | if (bdw_gmch_ctl > 4) | |
1890 | bdw_gmch_ctl = 4; | |
1891 | #endif | |
1892 | ||
9459d252 BW |
1893 | return bdw_gmch_ctl << 20; |
1894 | } | |
1895 | ||
d7f25f23 DL |
1896 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1897 | { | |
1898 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
1899 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
1900 | ||
1901 | if (gmch_ctrl) | |
1902 | return 1 << (20 + gmch_ctrl); | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | ||
baa09f5f | 1907 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1908 | { |
1909 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1910 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1911 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1912 | } | |
1913 | ||
9459d252 BW |
1914 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1915 | { | |
1916 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1917 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1918 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1919 | } | |
1920 | ||
d7f25f23 DL |
1921 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1922 | { | |
1923 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
1924 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
1925 | ||
1926 | /* | |
1927 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
1928 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
1929 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
1930 | */ | |
1931 | if (gmch_ctrl < 0x11) | |
1932 | return gmch_ctrl << 25; | |
1933 | else if (gmch_ctrl < 0x17) | |
1934 | return (gmch_ctrl - 0x11 + 2) << 22; | |
1935 | else | |
1936 | return (gmch_ctrl - 0x17 + 9) << 22; | |
1937 | } | |
1938 | ||
66375014 DL |
1939 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
1940 | { | |
1941 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1942 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1943 | ||
1944 | if (gen9_gmch_ctl < 0xf0) | |
1945 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
1946 | else | |
1947 | /* 4MB increments starting at 0xf0 for 4MB */ | |
1948 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
1949 | } | |
1950 | ||
63340133 BW |
1951 | static int ggtt_probe_common(struct drm_device *dev, |
1952 | size_t gtt_size) | |
1953 | { | |
1954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1955 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1956 | int ret; |
1957 | ||
1958 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1959 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1960 | (pci_resource_len(dev->pdev, 0) / 2); |
1961 | ||
21c34607 | 1962 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1963 | if (!dev_priv->gtt.gsm) { |
1964 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1965 | return -ENOMEM; | |
1966 | } | |
1967 | ||
1968 | ret = setup_scratch_page(dev); | |
1969 | if (ret) { | |
1970 | DRM_ERROR("Scratch setup failed\n"); | |
1971 | /* iounmap will also get called at remove, but meh */ | |
1972 | iounmap(dev_priv->gtt.gsm); | |
1973 | } | |
1974 | ||
1975 | return ret; | |
1976 | } | |
1977 | ||
fbe5d36e BW |
1978 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1979 | * bits. When using advanced contexts each context stores its own PAT, but | |
1980 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1981 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1982 | { |
fbe5d36e BW |
1983 | uint64_t pat; |
1984 | ||
1985 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1986 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1987 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1988 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1989 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1990 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1991 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1992 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1993 | ||
d6a8b72e RV |
1994 | if (!USES_PPGTT(dev_priv->dev)) |
1995 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
1996 | * so RTL will always use the value corresponding to | |
1997 | * pat_sel = 000". | |
1998 | * So let's disable cache for GGTT to avoid screen corruptions. | |
1999 | * MOCS still can be used though. | |
2000 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2001 | * before this patch, i.e. the same uncached + snooping access | |
2002 | * like on gen6/7 seems to be in effect. | |
2003 | * - So this just fixes blitter/render access. Again it looks | |
2004 | * like it's not just uncached access, but uncached + snooping. | |
2005 | * So we can still hold onto all our assumptions wrt cpu | |
2006 | * clflushing on LLC machines. | |
2007 | */ | |
2008 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2009 | ||
fbe5d36e BW |
2010 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2011 | * write would work. */ | |
2012 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2013 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2014 | } | |
2015 | ||
ee0ce478 VS |
2016 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2017 | { | |
2018 | uint64_t pat; | |
2019 | ||
2020 | /* | |
2021 | * Map WB on BDW to snooped on CHV. | |
2022 | * | |
2023 | * Only the snoop bit has meaning for CHV, the rest is | |
2024 | * ignored. | |
2025 | * | |
cf3d262e VS |
2026 | * The hardware will never snoop for certain types of accesses: |
2027 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2028 | * - PPGTT page tables | |
2029 | * - some other special cycles | |
2030 | * | |
2031 | * As with BDW, we also need to consider the following for GT accesses: | |
2032 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2033 | * so RTL will always use the value corresponding to | |
2034 | * pat_sel = 000". | |
2035 | * Which means we must set the snoop bit in PAT entry 0 | |
2036 | * in order to keep the global status page working. | |
ee0ce478 VS |
2037 | */ |
2038 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2039 | GEN8_PPAT(1, 0) | | |
2040 | GEN8_PPAT(2, 0) | | |
2041 | GEN8_PPAT(3, 0) | | |
2042 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2043 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2044 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2045 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2046 | ||
2047 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2048 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2049 | } | |
2050 | ||
63340133 BW |
2051 | static int gen8_gmch_probe(struct drm_device *dev, |
2052 | size_t *gtt_total, | |
2053 | size_t *stolen, | |
2054 | phys_addr_t *mappable_base, | |
2055 | unsigned long *mappable_end) | |
2056 | { | |
2057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2058 | unsigned int gtt_size; | |
2059 | u16 snb_gmch_ctl; | |
2060 | int ret; | |
2061 | ||
2062 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2063 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2064 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2065 | ||
2066 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2067 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2068 | ||
2069 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2070 | ||
66375014 DL |
2071 | if (INTEL_INFO(dev)->gen >= 9) { |
2072 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2073 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2074 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2075 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2076 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2077 | } else { | |
2078 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2079 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2080 | } | |
63340133 | 2081 | |
d31eb10e | 2082 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 2083 | |
ee0ce478 VS |
2084 | if (IS_CHERRYVIEW(dev)) |
2085 | chv_setup_private_ppat(dev_priv); | |
2086 | else | |
2087 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2088 | |
63340133 BW |
2089 | ret = ggtt_probe_common(dev, gtt_size); |
2090 | ||
94ec8f61 BW |
2091 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2092 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
2093 | |
2094 | return ret; | |
2095 | } | |
2096 | ||
baa09f5f BW |
2097 | static int gen6_gmch_probe(struct drm_device *dev, |
2098 | size_t *gtt_total, | |
41907ddc BW |
2099 | size_t *stolen, |
2100 | phys_addr_t *mappable_base, | |
2101 | unsigned long *mappable_end) | |
e76e9aeb BW |
2102 | { |
2103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2104 | unsigned int gtt_size; |
e76e9aeb | 2105 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2106 | int ret; |
2107 | ||
41907ddc BW |
2108 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2109 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2110 | ||
baa09f5f BW |
2111 | /* 64/512MB is the current min/max we actually know of, but this is just |
2112 | * a coarse sanity check. | |
e76e9aeb | 2113 | */ |
41907ddc | 2114 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2115 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2116 | dev_priv->gtt.mappable_end); | |
2117 | return -ENXIO; | |
e76e9aeb BW |
2118 | } |
2119 | ||
e76e9aeb BW |
2120 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2121 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2122 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2123 | |
c4ae25ec | 2124 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2125 | |
63340133 BW |
2126 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
2127 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 2128 | |
63340133 | 2129 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2130 | |
853ba5d2 BW |
2131 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2132 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2133 | |
e76e9aeb BW |
2134 | return ret; |
2135 | } | |
2136 | ||
853ba5d2 | 2137 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2138 | { |
853ba5d2 BW |
2139 | |
2140 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2141 | |
853ba5d2 BW |
2142 | iounmap(gtt->gsm); |
2143 | teardown_scratch_page(vm->dev); | |
644ec02b | 2144 | } |
baa09f5f BW |
2145 | |
2146 | static int i915_gmch_probe(struct drm_device *dev, | |
2147 | size_t *gtt_total, | |
41907ddc BW |
2148 | size_t *stolen, |
2149 | phys_addr_t *mappable_base, | |
2150 | unsigned long *mappable_end) | |
baa09f5f BW |
2151 | { |
2152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2153 | int ret; | |
2154 | ||
baa09f5f BW |
2155 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2156 | if (!ret) { | |
2157 | DRM_ERROR("failed to set up gmch\n"); | |
2158 | return -EIO; | |
2159 | } | |
2160 | ||
41907ddc | 2161 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2162 | |
2163 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2164 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2165 | |
c0a7f818 CW |
2166 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2167 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2168 | ||
baa09f5f BW |
2169 | return 0; |
2170 | } | |
2171 | ||
853ba5d2 | 2172 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2173 | { |
2174 | intel_gmch_remove(); | |
2175 | } | |
2176 | ||
2177 | int i915_gem_gtt_init(struct drm_device *dev) | |
2178 | { | |
2179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2180 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2181 | int ret; |
2182 | ||
baa09f5f | 2183 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2184 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2185 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2186 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2187 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2188 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2189 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2190 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2191 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2192 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2193 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2194 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2195 | else if (INTEL_INFO(dev)->gen >= 7) |
2196 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2197 | else |
350ec881 | 2198 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2199 | } else { |
2200 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2201 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2202 | } |
2203 | ||
853ba5d2 | 2204 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2205 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2206 | if (ret) |
baa09f5f | 2207 | return ret; |
baa09f5f | 2208 | |
853ba5d2 BW |
2209 | gtt->base.dev = dev; |
2210 | ||
baa09f5f | 2211 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2212 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2213 | gtt->base.total >> 20); | |
b2f21b4d BW |
2214 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2215 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2216 | #ifdef CONFIG_INTEL_IOMMU |
2217 | if (intel_iommu_gfx_mapped) | |
2218 | DRM_INFO("VT-d active for gfx access\n"); | |
2219 | #endif | |
cfa7c862 DV |
2220 | /* |
2221 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2222 | * user's requested state against the hardware/driver capabilities. We | |
2223 | * do this now so that we can print out any log messages once rather | |
2224 | * than every time we check intel_enable_ppgtt(). | |
2225 | */ | |
2226 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2227 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2228 | |
2229 | return 0; | |
2230 | } | |
6f65e29a BW |
2231 | |
2232 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
fe14d5f4 TU |
2233 | struct i915_address_space *vm, |
2234 | const struct i915_ggtt_view *view) | |
6f65e29a BW |
2235 | { |
2236 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2237 | if (vma == NULL) | |
2238 | return ERR_PTR(-ENOMEM); | |
2239 | ||
2240 | INIT_LIST_HEAD(&vma->vma_link); | |
2241 | INIT_LIST_HEAD(&vma->mm_list); | |
2242 | INIT_LIST_HEAD(&vma->exec_list); | |
2243 | vma->vm = vm; | |
2244 | vma->obj = obj; | |
fe14d5f4 | 2245 | vma->ggtt_view = *view; |
6f65e29a BW |
2246 | |
2247 | switch (INTEL_INFO(vm->dev)->gen) { | |
fb8aad4b | 2248 | case 9: |
6f65e29a BW |
2249 | case 8: |
2250 | case 7: | |
2251 | case 6: | |
7e0d96bc BW |
2252 | if (i915_is_ggtt(vm)) { |
2253 | vma->unbind_vma = ggtt_unbind_vma; | |
2254 | vma->bind_vma = ggtt_bind_vma; | |
2255 | } else { | |
2256 | vma->unbind_vma = ppgtt_unbind_vma; | |
2257 | vma->bind_vma = ppgtt_bind_vma; | |
2258 | } | |
6f65e29a BW |
2259 | break; |
2260 | case 5: | |
2261 | case 4: | |
2262 | case 3: | |
2263 | case 2: | |
2264 | BUG_ON(!i915_is_ggtt(vm)); | |
2265 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2266 | vma->bind_vma = i915_ggtt_bind_vma; | |
2267 | break; | |
2268 | default: | |
2269 | BUG(); | |
2270 | } | |
2271 | ||
f7635669 TU |
2272 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2273 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2274 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2275 | |
2276 | return vma; | |
2277 | } | |
2278 | ||
2279 | struct i915_vma * | |
fe14d5f4 TU |
2280 | i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj, |
2281 | struct i915_address_space *vm, | |
2282 | const struct i915_ggtt_view *view) | |
6f65e29a BW |
2283 | { |
2284 | struct i915_vma *vma; | |
2285 | ||
fe14d5f4 | 2286 | vma = i915_gem_obj_to_vma_view(obj, vm, view); |
6f65e29a | 2287 | if (!vma) |
fe14d5f4 | 2288 | vma = __i915_gem_vma_create(obj, vm, view); |
6f65e29a BW |
2289 | |
2290 | return vma; | |
2291 | } | |
fe14d5f4 TU |
2292 | |
2293 | static inline | |
2294 | int i915_get_vma_pages(struct i915_vma *vma) | |
2295 | { | |
2296 | if (vma->ggtt_view.pages) | |
2297 | return 0; | |
2298 | ||
2299 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2300 | vma->ggtt_view.pages = vma->obj->pages; | |
2301 | else | |
2302 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2303 | vma->ggtt_view.type); | |
2304 | ||
2305 | if (!vma->ggtt_view.pages) { | |
2306 | DRM_ERROR("Failed to get pages for VMA view type %u!\n", | |
2307 | vma->ggtt_view.type); | |
2308 | return -EINVAL; | |
2309 | } | |
2310 | ||
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | /** | |
2315 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2316 | * @vma: VMA to map | |
2317 | * @cache_level: mapping cache level | |
2318 | * @flags: flags like global or local mapping | |
2319 | * | |
2320 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2321 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2322 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2323 | */ | |
2324 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2325 | u32 flags) | |
2326 | { | |
2327 | int ret = i915_get_vma_pages(vma); | |
2328 | ||
2329 | if (ret) | |
2330 | return ret; | |
2331 | ||
2332 | vma->bind_vma(vma, cache_level, flags); | |
2333 | ||
2334 | return 0; | |
2335 | } |