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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 33 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 34 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 35 | |
26b1ff35 BW |
36 | /* PPGTT stuff */ |
37 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 38 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
39 | |
40 | #define GEN6_PDE_VALID (1 << 0) | |
41 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
42 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
43 | ||
44 | #define GEN6_PTE_VALID (1 << 0) | |
45 | #define GEN6_PTE_UNCACHED (1 << 1) | |
46 | #define HSW_PTE_UNCACHED (0) | |
47 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 48 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 49 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
50 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
51 | ||
52 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
53 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
54 | */ | |
55 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
56 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
c51e9701 | 60 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
651d794f | 61 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
c51e9701 | 62 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
26b1ff35 | 63 | |
459108b8 | 64 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a BW |
65 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
66 | #define GEN8_LEGACY_PDPS 4 | |
67 | ||
fbe5d36e BW |
68 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
69 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
70 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
71 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
72 | ||
6f65e29a BW |
73 | static void ppgtt_bind_vma(struct i915_vma *vma, |
74 | enum i915_cache_level cache_level, | |
75 | u32 flags); | |
76 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 77 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 78 | |
94ec8f61 BW |
79 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
80 | enum i915_cache_level level, | |
81 | bool valid) | |
82 | { | |
83 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
84 | pte |= addr; | |
fbe5d36e BW |
85 | if (level != I915_CACHE_NONE) |
86 | pte |= PPAT_CACHED_INDEX; | |
87 | else | |
88 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
89 | return pte; |
90 | } | |
91 | ||
b1fe6673 BW |
92 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
93 | dma_addr_t addr, | |
94 | enum i915_cache_level level) | |
95 | { | |
96 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
97 | pde |= addr; | |
98 | if (level != I915_CACHE_NONE) | |
99 | pde |= PPAT_CACHED_PDE_INDEX; | |
100 | else | |
101 | pde |= PPAT_UNCACHED_INDEX; | |
102 | return pde; | |
103 | } | |
104 | ||
350ec881 | 105 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
106 | enum i915_cache_level level, |
107 | bool valid) | |
54d12527 | 108 | { |
b35b380e | 109 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 110 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
111 | |
112 | switch (level) { | |
350ec881 CW |
113 | case I915_CACHE_L3_LLC: |
114 | case I915_CACHE_LLC: | |
115 | pte |= GEN6_PTE_CACHE_LLC; | |
116 | break; | |
117 | case I915_CACHE_NONE: | |
118 | pte |= GEN6_PTE_UNCACHED; | |
119 | break; | |
120 | default: | |
121 | WARN_ON(1); | |
122 | } | |
123 | ||
124 | return pte; | |
125 | } | |
126 | ||
127 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
128 | enum i915_cache_level level, |
129 | bool valid) | |
350ec881 | 130 | { |
b35b380e | 131 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
132 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
133 | ||
134 | switch (level) { | |
135 | case I915_CACHE_L3_LLC: | |
136 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
137 | break; |
138 | case I915_CACHE_LLC: | |
139 | pte |= GEN6_PTE_CACHE_LLC; | |
140 | break; | |
141 | case I915_CACHE_NONE: | |
9119708c | 142 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
143 | break; |
144 | default: | |
350ec881 | 145 | WARN_ON(1); |
e7210c3c BW |
146 | } |
147 | ||
54d12527 BW |
148 | return pte; |
149 | } | |
150 | ||
93c34e70 KG |
151 | #define BYT_PTE_WRITEABLE (1 << 1) |
152 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
153 | ||
80a74f7f | 154 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
155 | enum i915_cache_level level, |
156 | bool valid) | |
93c34e70 | 157 | { |
b35b380e | 158 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
159 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
160 | ||
161 | /* Mark the page as writeable. Other platforms don't have a | |
162 | * setting for read-only/writable, so this matches that behavior. | |
163 | */ | |
164 | pte |= BYT_PTE_WRITEABLE; | |
165 | ||
166 | if (level != I915_CACHE_NONE) | |
167 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
168 | ||
169 | return pte; | |
170 | } | |
171 | ||
80a74f7f | 172 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
173 | enum i915_cache_level level, |
174 | bool valid) | |
9119708c | 175 | { |
b35b380e | 176 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 177 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
178 | |
179 | if (level != I915_CACHE_NONE) | |
87a6b688 | 180 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
181 | |
182 | return pte; | |
183 | } | |
184 | ||
4d15c145 | 185 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
186 | enum i915_cache_level level, |
187 | bool valid) | |
4d15c145 | 188 | { |
b35b380e | 189 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
190 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
191 | ||
651d794f CW |
192 | switch (level) { |
193 | case I915_CACHE_NONE: | |
194 | break; | |
195 | case I915_CACHE_WT: | |
c51e9701 | 196 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
197 | break; |
198 | default: | |
c51e9701 | 199 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
200 | break; |
201 | } | |
4d15c145 BW |
202 | |
203 | return pte; | |
204 | } | |
205 | ||
94e409c1 BW |
206 | /* Broadwell Page Directory Pointer Descriptors */ |
207 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 208 | uint64_t val, bool synchronous) |
94e409c1 | 209 | { |
e178f705 | 210 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
211 | int ret; |
212 | ||
213 | BUG_ON(entry >= 4); | |
214 | ||
e178f705 BW |
215 | if (synchronous) { |
216 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
217 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
218 | return 0; | |
219 | } | |
220 | ||
94e409c1 BW |
221 | ret = intel_ring_begin(ring, 6); |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
226 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
227 | intel_ring_emit(ring, (u32)(val >> 32)); | |
228 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
229 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
230 | intel_ring_emit(ring, (u32)(val)); | |
231 | intel_ring_advance(ring); | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
eeb9488e BW |
236 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
237 | struct intel_ring_buffer *ring, | |
238 | bool synchronous) | |
94e409c1 | 239 | { |
eeb9488e | 240 | int i, ret; |
94e409c1 BW |
241 | |
242 | /* bit of a hack to find the actual last used pd */ | |
243 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
244 | ||
94e409c1 BW |
245 | for (i = used_pd - 1; i >= 0; i--) { |
246 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
247 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
248 | if (ret) | |
249 | return ret; | |
94e409c1 | 250 | } |
d595bd4b | 251 | |
eeb9488e | 252 | return 0; |
94e409c1 BW |
253 | } |
254 | ||
459108b8 BW |
255 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
256 | unsigned first_entry, | |
257 | unsigned num_entries, | |
258 | bool use_scratch) | |
259 | { | |
260 | struct i915_hw_ppgtt *ppgtt = | |
261 | container_of(vm, struct i915_hw_ppgtt, base); | |
262 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
263 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
264 | unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE; | |
265 | unsigned last_pte, i; | |
266 | ||
267 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
268 | I915_CACHE_LLC, use_scratch); | |
269 | ||
270 | while (num_entries) { | |
271 | struct page *page_table = &ppgtt->gen8_pt_pages[act_pt]; | |
272 | ||
273 | last_pte = first_pte + num_entries; | |
274 | if (last_pte > GEN8_PTES_PER_PAGE) | |
275 | last_pte = GEN8_PTES_PER_PAGE; | |
276 | ||
277 | pt_vaddr = kmap_atomic(page_table); | |
278 | ||
279 | for (i = first_pte; i < last_pte; i++) | |
280 | pt_vaddr[i] = scratch_pte; | |
281 | ||
282 | kunmap_atomic(pt_vaddr); | |
283 | ||
284 | num_entries -= last_pte - first_pte; | |
285 | first_pte = 0; | |
286 | act_pt++; | |
287 | } | |
288 | } | |
289 | ||
9df15b49 BW |
290 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
291 | struct sg_table *pages, | |
292 | unsigned first_entry, | |
293 | enum i915_cache_level cache_level) | |
294 | { | |
295 | struct i915_hw_ppgtt *ppgtt = | |
296 | container_of(vm, struct i915_hw_ppgtt, base); | |
297 | gen8_gtt_pte_t *pt_vaddr; | |
298 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
299 | unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE; | |
300 | struct sg_page_iter sg_iter; | |
301 | ||
302 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
303 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { | |
304 | dma_addr_t page_addr; | |
305 | ||
306 | page_addr = sg_dma_address(sg_iter.sg) + | |
307 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
308 | pt_vaddr[act_pte] = gen8_pte_encode(page_addr, cache_level, | |
309 | true); | |
310 | if (++act_pte == GEN8_PTES_PER_PAGE) { | |
311 | kunmap_atomic(pt_vaddr); | |
312 | act_pt++; | |
313 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
314 | act_pte = 0; | |
315 | ||
316 | } | |
317 | } | |
318 | kunmap_atomic(pt_vaddr); | |
319 | } | |
320 | ||
37aca44a BW |
321 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
322 | { | |
323 | struct i915_hw_ppgtt *ppgtt = | |
324 | container_of(vm, struct i915_hw_ppgtt, base); | |
325 | int i, j; | |
326 | ||
7e0d96bc | 327 | list_del(&vm->global_link); |
686e1f6f BW |
328 | drm_mm_takedown(&vm->mm); |
329 | ||
37aca44a BW |
330 | for (i = 0; i < ppgtt->num_pd_pages ; i++) { |
331 | if (ppgtt->pd_dma_addr[i]) { | |
332 | pci_unmap_page(ppgtt->base.dev->pdev, | |
333 | ppgtt->pd_dma_addr[i], | |
334 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
335 | ||
336 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
337 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
338 | if (addr) | |
339 | pci_unmap_page(ppgtt->base.dev->pdev, | |
340 | addr, | |
341 | PAGE_SIZE, | |
342 | PCI_DMA_BIDIRECTIONAL); | |
343 | ||
344 | } | |
345 | } | |
346 | kfree(ppgtt->gen8_pt_dma_addr[i]); | |
347 | } | |
348 | ||
230f955f BW |
349 | __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); |
350 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); | |
37aca44a BW |
351 | } |
352 | ||
353 | /** | |
354 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a | |
355 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP | |
356 | * represents 1GB of memory | |
357 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. | |
358 | * | |
359 | * TODO: Do something with the size parameter | |
360 | **/ | |
361 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) | |
362 | { | |
363 | struct page *pt_pages; | |
364 | int i, j, ret = -ENOMEM; | |
365 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); | |
366 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; | |
367 | ||
368 | if (size % (1<<30)) | |
369 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
370 | ||
371 | /* FIXME: split allocation into smaller pieces. For now we only ever do | |
372 | * this once, but with full PPGTT, the multiple contiguous allocations | |
373 | * will be bad. | |
374 | */ | |
375 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
376 | if (!ppgtt->pd_pages) | |
377 | return -ENOMEM; | |
378 | ||
379 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); | |
380 | if (!pt_pages) { | |
381 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
382 | return -ENOMEM; | |
383 | } | |
384 | ||
385 | ppgtt->gen8_pt_pages = pt_pages; | |
386 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
387 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); | |
388 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
94e409c1 | 389 | ppgtt->enable = gen8_ppgtt_enable; |
eeb9488e | 390 | ppgtt->switch_mm = gen8_mm_switch; |
459108b8 | 391 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
9df15b49 | 392 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
37aca44a | 393 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
686e1f6f BW |
394 | ppgtt->base.start = 0; |
395 | ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; | |
37aca44a BW |
396 | |
397 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
398 | ||
399 | /* | |
400 | * - Create a mapping for the page directories. | |
401 | * - For each page directory: | |
402 | * allocate space for page table mappings. | |
403 | * map each page table | |
404 | */ | |
405 | for (i = 0; i < max_pdp; i++) { | |
406 | dma_addr_t temp; | |
407 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
408 | &ppgtt->pd_pages[i], 0, | |
409 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
410 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
411 | goto err_out; | |
412 | ||
413 | ppgtt->pd_dma_addr[i] = temp; | |
414 | ||
415 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); | |
416 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
417 | goto err_out; | |
418 | ||
419 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
420 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; | |
421 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
422 | p, 0, PAGE_SIZE, | |
423 | PCI_DMA_BIDIRECTIONAL); | |
424 | ||
425 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
426 | goto err_out; | |
427 | ||
428 | ppgtt->gen8_pt_dma_addr[i][j] = temp; | |
429 | } | |
430 | } | |
431 | ||
b1fe6673 BW |
432 | /* For now, the PPGTT helper functions all require that the PDEs are |
433 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we | |
434 | * will never need to touch the PDEs again */ | |
435 | for (i = 0; i < max_pdp; i++) { | |
436 | gen8_ppgtt_pde_t *pd_vaddr; | |
437 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
438 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
439 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
440 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
441 | I915_CACHE_LLC); | |
442 | } | |
443 | kunmap_atomic(pd_vaddr); | |
444 | } | |
445 | ||
459108b8 BW |
446 | ppgtt->base.clear_range(&ppgtt->base, 0, |
447 | ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE, | |
448 | true); | |
449 | ||
37aca44a BW |
450 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
451 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
452 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
453 | ppgtt->num_pt_pages, | |
454 | (ppgtt->num_pt_pages - num_pt_pages) + | |
455 | size % (1<<30)); | |
28cf5415 | 456 | return 0; |
37aca44a BW |
457 | |
458 | err_out: | |
459 | ppgtt->base.cleanup(&ppgtt->base); | |
460 | return ret; | |
461 | } | |
462 | ||
3e302542 | 463 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 464 | { |
853ba5d2 | 465 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
466 | gen6_gtt_pte_t __iomem *pd_addr; |
467 | uint32_t pd_entry; | |
468 | int i; | |
469 | ||
0a732870 | 470 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
471 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
472 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
473 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
474 | dma_addr_t pt_addr; | |
475 | ||
476 | pt_addr = ppgtt->pt_dma_addr[i]; | |
477 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
478 | pd_entry |= GEN6_PDE_VALID; | |
479 | ||
480 | writel(pd_entry, pd_addr + i); | |
481 | } | |
482 | readl(pd_addr); | |
3e302542 BW |
483 | } |
484 | ||
b4a74e3a BW |
485 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
486 | { | |
487 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
488 | ||
489 | return (ppgtt->pd_offset / 64) << 16; | |
490 | } | |
491 | ||
90252e5c BW |
492 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
493 | struct intel_ring_buffer *ring, | |
494 | bool synchronous) | |
495 | { | |
496 | struct drm_device *dev = ppgtt->base.dev; | |
497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498 | int ret; | |
499 | ||
500 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
501 | * manually frob these bits. Ideally we could use the ring functions, | |
502 | * except our error handling makes it quite difficult (can't use | |
503 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
504 | * | |
505 | * FIXME: We should try not to special case reset | |
506 | */ | |
507 | if (synchronous || | |
508 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
509 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
510 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
511 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
512 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
513 | return 0; | |
514 | } | |
515 | ||
516 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
517 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
518 | if (ret) | |
519 | return ret; | |
520 | ||
521 | ret = intel_ring_begin(ring, 6); | |
522 | if (ret) | |
523 | return ret; | |
524 | ||
525 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
526 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
527 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
528 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
529 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
530 | intel_ring_emit(ring, MI_NOOP); | |
531 | intel_ring_advance(ring); | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
48a10389 BW |
536 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
537 | struct intel_ring_buffer *ring, | |
538 | bool synchronous) | |
539 | { | |
540 | struct drm_device *dev = ppgtt->base.dev; | |
541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
542 | int ret; | |
543 | ||
544 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
545 | * manually frob these bits. Ideally we could use the ring functions, | |
546 | * except our error handling makes it quite difficult (can't use | |
547 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
548 | * | |
549 | * FIXME: We should try not to special case reset | |
550 | */ | |
551 | if (synchronous || | |
552 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
553 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
554 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
555 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
556 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
557 | return 0; | |
558 | } | |
559 | ||
560 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
561 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
562 | if (ret) | |
563 | return ret; | |
564 | ||
565 | ret = intel_ring_begin(ring, 6); | |
566 | if (ret) | |
567 | return ret; | |
568 | ||
569 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
570 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
571 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
572 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
573 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
574 | intel_ring_emit(ring, MI_NOOP); | |
575 | intel_ring_advance(ring); | |
576 | ||
90252e5c BW |
577 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
578 | if (ring->id != RCS) { | |
579 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
580 | if (ret) | |
581 | return ret; | |
582 | } | |
583 | ||
48a10389 BW |
584 | return 0; |
585 | } | |
586 | ||
eeb9488e BW |
587 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
588 | struct intel_ring_buffer *ring, | |
589 | bool synchronous) | |
590 | { | |
591 | struct drm_device *dev = ppgtt->base.dev; | |
592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
593 | ||
48a10389 BW |
594 | if (!synchronous) |
595 | return 0; | |
596 | ||
eeb9488e BW |
597 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
598 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
599 | ||
600 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
606 | { | |
607 | struct drm_device *dev = ppgtt->base.dev; | |
608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
609 | struct intel_ring_buffer *ring; | |
610 | int j, ret; | |
611 | ||
612 | for_each_ring(ring, dev_priv, j) { | |
613 | I915_WRITE(RING_MODE_GEN7(ring), | |
614 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
615 | |
616 | /* We promise to do a switch later with FULL PPGTT. If this is | |
617 | * aliasing, this is the one and only switch we'll do */ | |
618 | if (USES_FULL_PPGTT(dev)) | |
619 | continue; | |
620 | ||
eeb9488e BW |
621 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
622 | if (ret) | |
623 | goto err_out; | |
624 | } | |
625 | ||
626 | return 0; | |
627 | ||
628 | err_out: | |
629 | for_each_ring(ring, dev_priv, j) | |
630 | I915_WRITE(RING_MODE_GEN7(ring), | |
631 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
632 | return ret; | |
633 | } | |
634 | ||
b4a74e3a | 635 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 636 | { |
a3d67d23 | 637 | struct drm_device *dev = ppgtt->base.dev; |
3e302542 | 638 | drm_i915_private_t *dev_priv = dev->dev_private; |
3e302542 | 639 | struct intel_ring_buffer *ring; |
b4a74e3a | 640 | uint32_t ecochk, ecobits; |
3e302542 BW |
641 | int i; |
642 | ||
b4a74e3a BW |
643 | ecobits = I915_READ(GAC_ECO_BITS); |
644 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 645 | |
b4a74e3a BW |
646 | ecochk = I915_READ(GAM_ECOCHK); |
647 | if (IS_HASWELL(dev)) { | |
648 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
649 | } else { | |
650 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
651 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
652 | } | |
653 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b | 654 | |
b4a74e3a | 655 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
656 | int ret; |
657 | /* GFX_MODE is per-ring on gen7+ */ | |
b4a74e3a BW |
658 | I915_WRITE(RING_MODE_GEN7(ring), |
659 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
660 | |
661 | /* We promise to do a switch later with FULL PPGTT. If this is | |
662 | * aliasing, this is the one and only switch we'll do */ | |
663 | if (USES_FULL_PPGTT(dev)) | |
664 | continue; | |
665 | ||
eeb9488e BW |
666 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
667 | if (ret) | |
668 | return ret; | |
b4a74e3a | 669 | } |
d2ff7192 | 670 | |
b4a74e3a BW |
671 | return 0; |
672 | } | |
6197349b | 673 | |
b4a74e3a BW |
674 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
675 | { | |
676 | struct drm_device *dev = ppgtt->base.dev; | |
677 | drm_i915_private_t *dev_priv = dev->dev_private; | |
678 | struct intel_ring_buffer *ring; | |
679 | uint32_t ecochk, gab_ctl, ecobits; | |
680 | int i; | |
a65c2fcd | 681 | |
b4a74e3a BW |
682 | ecobits = I915_READ(GAC_ECO_BITS); |
683 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
684 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 685 | |
b4a74e3a BW |
686 | gab_ctl = I915_READ(GAB_CTL); |
687 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
688 | ||
689 | ecochk = I915_READ(GAM_ECOCHK); | |
690 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
691 | ||
692 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 693 | |
b4a74e3a | 694 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
695 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
696 | if (ret) | |
697 | return ret; | |
6197349b | 698 | } |
b4a74e3a | 699 | |
b7c36d25 | 700 | return 0; |
6197349b BW |
701 | } |
702 | ||
1d2a314c | 703 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 704 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 705 | unsigned first_entry, |
828c7908 BW |
706 | unsigned num_entries, |
707 | bool use_scratch) | |
1d2a314c | 708 | { |
853ba5d2 BW |
709 | struct i915_hw_ppgtt *ppgtt = |
710 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 711 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 712 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
713 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
714 | unsigned last_pte, i; | |
1d2a314c | 715 | |
b35b380e | 716 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 717 | |
7bddb01f DV |
718 | while (num_entries) { |
719 | last_pte = first_pte + num_entries; | |
720 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
721 | last_pte = I915_PPGTT_PT_ENTRIES; | |
722 | ||
a15326a5 | 723 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 724 | |
7bddb01f DV |
725 | for (i = first_pte; i < last_pte; i++) |
726 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
727 | |
728 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 729 | |
7bddb01f DV |
730 | num_entries -= last_pte - first_pte; |
731 | first_pte = 0; | |
a15326a5 | 732 | act_pt++; |
7bddb01f | 733 | } |
1d2a314c DV |
734 | } |
735 | ||
853ba5d2 | 736 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
737 | struct sg_table *pages, |
738 | unsigned first_entry, | |
739 | enum i915_cache_level cache_level) | |
740 | { | |
853ba5d2 BW |
741 | struct i915_hw_ppgtt *ppgtt = |
742 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 743 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 744 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
745 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
746 | struct sg_page_iter sg_iter; | |
747 | ||
a15326a5 | 748 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
749 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
750 | dma_addr_t page_addr; | |
751 | ||
2db76d7c | 752 | page_addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 753 | pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true); |
6e995e23 ID |
754 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
755 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
756 | act_pt++; |
757 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 758 | act_pte = 0; |
def886c3 | 759 | |
def886c3 | 760 | } |
def886c3 | 761 | } |
6e995e23 | 762 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
763 | } |
764 | ||
853ba5d2 | 765 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 766 | { |
853ba5d2 BW |
767 | struct i915_hw_ppgtt *ppgtt = |
768 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
769 | int i; |
770 | ||
7e0d96bc | 771 | list_del(&vm->global_link); |
93bd8649 | 772 | drm_mm_takedown(&ppgtt->base.mm); |
c8d4c0d6 | 773 | drm_mm_remove_node(&ppgtt->node); |
93bd8649 | 774 | |
3440d265 DV |
775 | if (ppgtt->pt_dma_addr) { |
776 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 777 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
778 | ppgtt->pt_dma_addr[i], |
779 | 4096, PCI_DMA_BIDIRECTIONAL); | |
780 | } | |
781 | ||
782 | kfree(ppgtt->pt_dma_addr); | |
783 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
784 | __free_page(ppgtt->pt_pages[i]); | |
785 | kfree(ppgtt->pt_pages); | |
786 | kfree(ppgtt); | |
787 | } | |
788 | ||
789 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
790 | { | |
c8d4c0d6 BW |
791 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
792 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) | |
853ba5d2 | 793 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 794 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 795 | bool retried = false; |
c8d4c0d6 | 796 | int i, ret; |
1d2a314c | 797 | |
c8d4c0d6 BW |
798 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
799 | * allocator works in address space sizes, so it's multiplied by page | |
800 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
801 | */ | |
802 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 803 | alloc: |
c8d4c0d6 BW |
804 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
805 | &ppgtt->node, GEN6_PD_SIZE, | |
806 | GEN6_PD_ALIGN, 0, | |
807 | 0, dev_priv->gtt.base.total, | |
808 | DRM_MM_SEARCH_DEFAULT); | |
e3cc1995 BW |
809 | if (ret == -ENOSPC && !retried) { |
810 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
811 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
812 | I915_CACHE_NONE, false, true); | |
813 | if (ret) | |
814 | return ret; | |
815 | ||
816 | retried = true; | |
817 | goto alloc; | |
818 | } | |
c8d4c0d6 BW |
819 | |
820 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
821 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 822 | |
08c45263 | 823 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 824 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
48a10389 | 825 | if (IS_GEN6(dev)) { |
b4a74e3a | 826 | ppgtt->enable = gen6_ppgtt_enable; |
48a10389 | 827 | ppgtt->switch_mm = gen6_mm_switch; |
90252e5c BW |
828 | } else if (IS_HASWELL(dev)) { |
829 | ppgtt->enable = gen7_ppgtt_enable; | |
830 | ppgtt->switch_mm = hsw_mm_switch; | |
48a10389 | 831 | } else if (IS_GEN7(dev)) { |
b4a74e3a | 832 | ppgtt->enable = gen7_ppgtt_enable; |
48a10389 BW |
833 | ppgtt->switch_mm = gen7_mm_switch; |
834 | } else | |
b4a74e3a | 835 | BUG(); |
853ba5d2 BW |
836 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
837 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
838 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
839 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
686e1f6f BW |
840 | ppgtt->base.start = 0; |
841 | ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; | |
a1e22653 | 842 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 843 | GFP_KERNEL); |
c8d4c0d6 BW |
844 | if (!ppgtt->pt_pages) { |
845 | drm_mm_remove_node(&ppgtt->node); | |
3440d265 | 846 | return -ENOMEM; |
c8d4c0d6 | 847 | } |
1d2a314c DV |
848 | |
849 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
850 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
851 | if (!ppgtt->pt_pages[i]) | |
852 | goto err_pt_alloc; | |
853 | } | |
854 | ||
a1e22653 | 855 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
856 | GFP_KERNEL); |
857 | if (!ppgtt->pt_dma_addr) | |
858 | goto err_pt_alloc; | |
1d2a314c | 859 | |
8d2e6308 BW |
860 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
861 | dma_addr_t pt_addr; | |
211c568b | 862 | |
8d2e6308 BW |
863 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
864 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 865 | |
8d2e6308 BW |
866 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
867 | ret = -EIO; | |
868 | goto err_pd_pin; | |
1d2a314c | 869 | |
211c568b | 870 | } |
8d2e6308 | 871 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 872 | } |
1d2a314c | 873 | |
853ba5d2 | 874 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 875 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
1d2a314c | 876 | |
c8d4c0d6 BW |
877 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
878 | ppgtt->node.size >> 20, | |
879 | ppgtt->node.start / PAGE_SIZE); | |
880 | ppgtt->pd_offset = | |
881 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 882 | |
1d2a314c DV |
883 | return 0; |
884 | ||
885 | err_pd_pin: | |
886 | if (ppgtt->pt_dma_addr) { | |
887 | for (i--; i >= 0; i--) | |
888 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
889 | 4096, PCI_DMA_BIDIRECTIONAL); | |
890 | } | |
891 | err_pt_alloc: | |
892 | kfree(ppgtt->pt_dma_addr); | |
893 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
894 | if (ppgtt->pt_pages[i]) | |
895 | __free_page(ppgtt->pt_pages[i]); | |
896 | } | |
897 | kfree(ppgtt->pt_pages); | |
c8d4c0d6 | 898 | drm_mm_remove_node(&ppgtt->node); |
3440d265 DV |
899 | |
900 | return ret; | |
901 | } | |
902 | ||
246cbfb5 | 903 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
904 | { |
905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 906 | int ret = 0; |
3440d265 | 907 | |
853ba5d2 | 908 | ppgtt->base.dev = dev; |
3440d265 | 909 | |
3ed124b2 BW |
910 | if (INTEL_INFO(dev)->gen < 8) |
911 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 912 | else if (IS_GEN8(dev)) |
37aca44a | 913 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
914 | else |
915 | BUG(); | |
916 | ||
c7c48dfd | 917 | if (!ret) { |
7e0d96bc | 918 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 919 | kref_init(&ppgtt->ref); |
93bd8649 BW |
920 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
921 | ppgtt->base.total); | |
7e0d96bc BW |
922 | i915_init_vm(dev_priv, &ppgtt->base); |
923 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 924 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
925 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
926 | ppgtt->pd_offset << 10); | |
927 | } | |
c7c48dfd | 928 | } |
1d2a314c DV |
929 | |
930 | return ret; | |
931 | } | |
932 | ||
7e0d96bc | 933 | static void |
6f65e29a BW |
934 | ppgtt_bind_vma(struct i915_vma *vma, |
935 | enum i915_cache_level cache_level, | |
936 | u32 flags) | |
7bddb01f | 937 | { |
6f65e29a BW |
938 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
939 | ||
940 | WARN_ON(flags); | |
941 | ||
942 | vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level); | |
7bddb01f DV |
943 | } |
944 | ||
7e0d96bc | 945 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 946 | { |
6f65e29a BW |
947 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
948 | ||
949 | vma->vm->clear_range(vma->vm, | |
950 | entry, | |
951 | vma->obj->base.size >> PAGE_SHIFT, | |
952 | true); | |
7bddb01f DV |
953 | } |
954 | ||
a81cc00c BW |
955 | extern int intel_iommu_gfx_mapped; |
956 | /* Certain Gen5 chipsets require require idling the GPU before | |
957 | * unmapping anything from the GTT when VT-d is enabled. | |
958 | */ | |
959 | static inline bool needs_idle_maps(struct drm_device *dev) | |
960 | { | |
961 | #ifdef CONFIG_INTEL_IOMMU | |
962 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
963 | * was loaded first. | |
964 | */ | |
965 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
966 | return true; | |
967 | #endif | |
968 | return false; | |
969 | } | |
970 | ||
5c042287 BW |
971 | static bool do_idling(struct drm_i915_private *dev_priv) |
972 | { | |
973 | bool ret = dev_priv->mm.interruptible; | |
974 | ||
a81cc00c | 975 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 976 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 977 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
978 | DRM_ERROR("Couldn't idle GPU\n"); |
979 | /* Wait a bit, in hopes it avoids the hang */ | |
980 | udelay(10); | |
981 | } | |
982 | } | |
983 | ||
984 | return ret; | |
985 | } | |
986 | ||
987 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
988 | { | |
a81cc00c | 989 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
990 | dev_priv->mm.interruptible = interruptible; |
991 | } | |
992 | ||
828c7908 BW |
993 | void i915_check_and_clear_faults(struct drm_device *dev) |
994 | { | |
995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
996 | struct intel_ring_buffer *ring; | |
997 | int i; | |
998 | ||
999 | if (INTEL_INFO(dev)->gen < 6) | |
1000 | return; | |
1001 | ||
1002 | for_each_ring(ring, dev_priv, i) { | |
1003 | u32 fault_reg; | |
1004 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1005 | if (fault_reg & RING_FAULT_VALID) { | |
1006 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1007 | "\tAddr: 0x%08lx\\n" | |
1008 | "\tAddress space: %s\n" | |
1009 | "\tSource ID: %d\n" | |
1010 | "\tType: %d\n", | |
1011 | fault_reg & PAGE_MASK, | |
1012 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1013 | RING_FAULT_SRCID(fault_reg), | |
1014 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1015 | I915_WRITE(RING_FAULT_REG(ring), | |
1016 | fault_reg & ~RING_FAULT_VALID); | |
1017 | } | |
1018 | } | |
1019 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1020 | } | |
1021 | ||
1022 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1023 | { | |
1024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1025 | ||
1026 | /* Don't bother messing with faults pre GEN6 as we have little | |
1027 | * documentation supporting that it's a good idea. | |
1028 | */ | |
1029 | if (INTEL_INFO(dev)->gen < 6) | |
1030 | return; | |
1031 | ||
1032 | i915_check_and_clear_faults(dev); | |
1033 | ||
1034 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
1035 | dev_priv->gtt.base.start / PAGE_SIZE, | |
1036 | dev_priv->gtt.base.total / PAGE_SIZE, | |
1037 | false); | |
1038 | } | |
1039 | ||
76aaf220 DV |
1040 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1041 | { | |
1042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1043 | struct drm_i915_gem_object *obj; |
80da2161 | 1044 | struct i915_address_space *vm; |
76aaf220 | 1045 | |
828c7908 BW |
1046 | i915_check_and_clear_faults(dev); |
1047 | ||
bee4a186 | 1048 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
1049 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
1050 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
1051 | dev_priv->gtt.base.total / PAGE_SIZE, |
1052 | true); | |
bee4a186 | 1053 | |
35c20a60 | 1054 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1055 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1056 | &dev_priv->gtt.base); | |
1057 | if (!vma) | |
1058 | continue; | |
1059 | ||
2c22569b | 1060 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1061 | /* The bind_vma code tries to be smart about tracking mappings. |
1062 | * Unfortunately above, we've just wiped out the mappings | |
1063 | * without telling our object about it. So we need to fake it. | |
1064 | */ | |
1065 | obj->has_global_gtt_mapping = 0; | |
1066 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1067 | } |
1068 | ||
80da2161 BW |
1069 | |
1070 | if (INTEL_INFO(dev)->gen >= 8) | |
1071 | return; | |
1072 | ||
1073 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1074 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1075 | if (i915_is_ggtt(vm)) { | |
1076 | if (dev_priv->mm.aliasing_ppgtt) | |
1077 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1078 | continue; | |
1079 | } | |
1080 | ||
1081 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
1082 | } | |
9f273d48 | 1083 | |
e76e9aeb | 1084 | i915_gem_chipset_flush(dev); |
76aaf220 | 1085 | } |
7c2e6fdf | 1086 | |
74163907 | 1087 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1088 | { |
9da3da66 | 1089 | if (obj->has_dma_mapping) |
74163907 | 1090 | return 0; |
9da3da66 CW |
1091 | |
1092 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1093 | obj->pages->sgl, obj->pages->nents, | |
1094 | PCI_DMA_BIDIRECTIONAL)) | |
1095 | return -ENOSPC; | |
1096 | ||
1097 | return 0; | |
7c2e6fdf DV |
1098 | } |
1099 | ||
94ec8f61 BW |
1100 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1101 | { | |
1102 | #ifdef writeq | |
1103 | writeq(pte, addr); | |
1104 | #else | |
1105 | iowrite32((u32)pte, addr); | |
1106 | iowrite32(pte >> 32, addr + 4); | |
1107 | #endif | |
1108 | } | |
1109 | ||
1110 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1111 | struct sg_table *st, | |
1112 | unsigned int first_entry, | |
1113 | enum i915_cache_level level) | |
1114 | { | |
1115 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
1116 | gen8_gtt_pte_t __iomem *gtt_entries = | |
1117 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1118 | int i = 0; | |
1119 | struct sg_page_iter sg_iter; | |
1120 | dma_addr_t addr; | |
1121 | ||
1122 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1123 | addr = sg_dma_address(sg_iter.sg) + | |
1124 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1125 | gen8_set_pte(>t_entries[i], | |
1126 | gen8_pte_encode(addr, level, true)); | |
1127 | i++; | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * XXX: This serves as a posting read to make sure that the PTE has | |
1132 | * actually been updated. There is some concern that even though | |
1133 | * registers and PTEs are within the same BAR that they are potentially | |
1134 | * of NUMA access patterns. Therefore, even with the way we assume | |
1135 | * hardware should work, we must keep this posting read for paranoia. | |
1136 | */ | |
1137 | if (i != 0) | |
1138 | WARN_ON(readq(>t_entries[i-1]) | |
1139 | != gen8_pte_encode(addr, level, true)); | |
1140 | ||
1141 | #if 0 /* TODO: Still needed on GEN8? */ | |
1142 | /* This next bit makes the above posting read even more important. We | |
1143 | * want to flush the TLBs only after we're certain all the PTE updates | |
1144 | * have finished. | |
1145 | */ | |
1146 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1147 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1148 | #endif | |
1149 | } | |
1150 | ||
e76e9aeb BW |
1151 | /* |
1152 | * Binds an object into the global gtt with the specified cache level. The object | |
1153 | * will be accessible to the GPU via commands whose operands reference offsets | |
1154 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1155 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1156 | */ | |
853ba5d2 | 1157 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
1158 | struct sg_table *st, |
1159 | unsigned int first_entry, | |
1160 | enum i915_cache_level level) | |
e76e9aeb | 1161 | { |
853ba5d2 | 1162 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1163 | gen6_gtt_pte_t __iomem *gtt_entries = |
1164 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1165 | int i = 0; |
1166 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1167 | dma_addr_t addr; |
1168 | ||
6e995e23 | 1169 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1170 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1171 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1172 | i++; |
e76e9aeb BW |
1173 | } |
1174 | ||
e76e9aeb BW |
1175 | /* XXX: This serves as a posting read to make sure that the PTE has |
1176 | * actually been updated. There is some concern that even though | |
1177 | * registers and PTEs are within the same BAR that they are potentially | |
1178 | * of NUMA access patterns. Therefore, even with the way we assume | |
1179 | * hardware should work, we must keep this posting read for paranoia. | |
1180 | */ | |
1181 | if (i != 0) | |
853ba5d2 | 1182 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1183 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1184 | |
1185 | /* This next bit makes the above posting read even more important. We | |
1186 | * want to flush the TLBs only after we're certain all the PTE updates | |
1187 | * have finished. | |
1188 | */ | |
1189 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1190 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1191 | } |
1192 | ||
94ec8f61 BW |
1193 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
1194 | unsigned int first_entry, | |
1195 | unsigned int num_entries, | |
1196 | bool use_scratch) | |
1197 | { | |
1198 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
1199 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
1200 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1201 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1202 | int i; | |
1203 | ||
1204 | if (WARN(num_entries > max_entries, | |
1205 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1206 | first_entry, num_entries, max_entries)) | |
1207 | num_entries = max_entries; | |
1208 | ||
1209 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1210 | I915_CACHE_LLC, | |
1211 | use_scratch); | |
1212 | for (i = 0; i < num_entries; i++) | |
1213 | gen8_set_pte(>t_base[i], scratch_pte); | |
1214 | readl(gtt_base); | |
1215 | } | |
1216 | ||
853ba5d2 | 1217 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1218 | unsigned int first_entry, |
828c7908 BW |
1219 | unsigned int num_entries, |
1220 | bool use_scratch) | |
7faf1ab2 | 1221 | { |
853ba5d2 | 1222 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1223 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1224 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1225 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1226 | int i; |
1227 | ||
1228 | if (WARN(num_entries > max_entries, | |
1229 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1230 | first_entry, num_entries, max_entries)) | |
1231 | num_entries = max_entries; | |
1232 | ||
828c7908 BW |
1233 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1234 | ||
7faf1ab2 DV |
1235 | for (i = 0; i < num_entries; i++) |
1236 | iowrite32(scratch_pte, >t_base[i]); | |
1237 | readl(gtt_base); | |
1238 | } | |
1239 | ||
6f65e29a BW |
1240 | |
1241 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1242 | enum i915_cache_level cache_level, | |
1243 | u32 unused) | |
7faf1ab2 | 1244 | { |
6f65e29a | 1245 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1246 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1247 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1248 | ||
6f65e29a BW |
1249 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1250 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1251 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1252 | } |
1253 | ||
853ba5d2 | 1254 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1255 | unsigned int first_entry, |
828c7908 BW |
1256 | unsigned int num_entries, |
1257 | bool unused) | |
7faf1ab2 DV |
1258 | { |
1259 | intel_gtt_clear_range(first_entry, num_entries); | |
1260 | } | |
1261 | ||
6f65e29a BW |
1262 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1263 | { | |
1264 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1265 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1266 | |
6f65e29a BW |
1267 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1268 | vma->obj->has_global_gtt_mapping = 0; | |
1269 | intel_gtt_clear_range(first, size); | |
1270 | } | |
1271 | ||
1272 | static void ggtt_bind_vma(struct i915_vma *vma, | |
1273 | enum i915_cache_level cache_level, | |
1274 | u32 flags) | |
d5bd1449 | 1275 | { |
6f65e29a | 1276 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1277 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1278 | struct drm_i915_gem_object *obj = vma->obj; |
1279 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
7faf1ab2 | 1280 | |
6f65e29a BW |
1281 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1282 | * or we have a global mapping already but the cacheability flags have | |
1283 | * changed, set the global PTEs. | |
1284 | * | |
1285 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1286 | * instead if none of the above hold true. | |
1287 | * | |
1288 | * NB: A global mapping should only be needed for special regions like | |
1289 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1290 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1291 | */ | |
1292 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1293 | if (!obj->has_global_gtt_mapping || | |
1294 | (cache_level != obj->cache_level)) { | |
1295 | vma->vm->insert_entries(vma->vm, obj->pages, entry, | |
1296 | cache_level); | |
1297 | obj->has_global_gtt_mapping = 1; | |
1298 | } | |
1299 | } | |
d5bd1449 | 1300 | |
6f65e29a BW |
1301 | if (dev_priv->mm.aliasing_ppgtt && |
1302 | (!obj->has_aliasing_ppgtt_mapping || | |
1303 | (cache_level != obj->cache_level))) { | |
1304 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1305 | appgtt->base.insert_entries(&appgtt->base, | |
1306 | vma->obj->pages, entry, cache_level); | |
1307 | vma->obj->has_aliasing_ppgtt_mapping = 1; | |
1308 | } | |
d5bd1449 CW |
1309 | } |
1310 | ||
6f65e29a | 1311 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1312 | { |
6f65e29a | 1313 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1314 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1315 | struct drm_i915_gem_object *obj = vma->obj; |
1316 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
1317 | ||
1318 | if (obj->has_global_gtt_mapping) { | |
1319 | vma->vm->clear_range(vma->vm, entry, | |
1320 | vma->obj->base.size >> PAGE_SHIFT, | |
1321 | true); | |
1322 | obj->has_global_gtt_mapping = 0; | |
1323 | } | |
74898d7e | 1324 | |
6f65e29a BW |
1325 | if (obj->has_aliasing_ppgtt_mapping) { |
1326 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1327 | appgtt->base.clear_range(&appgtt->base, | |
1328 | entry, | |
1329 | obj->base.size >> PAGE_SHIFT, | |
1330 | true); | |
1331 | obj->has_aliasing_ppgtt_mapping = 0; | |
1332 | } | |
74163907 DV |
1333 | } |
1334 | ||
1335 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1336 | { |
5c042287 BW |
1337 | struct drm_device *dev = obj->base.dev; |
1338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1339 | bool interruptible; | |
1340 | ||
1341 | interruptible = do_idling(dev_priv); | |
1342 | ||
9da3da66 CW |
1343 | if (!obj->has_dma_mapping) |
1344 | dma_unmap_sg(&dev->pdev->dev, | |
1345 | obj->pages->sgl, obj->pages->nents, | |
1346 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1347 | |
1348 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1349 | } |
644ec02b | 1350 | |
42d6ab48 CW |
1351 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1352 | unsigned long color, | |
1353 | unsigned long *start, | |
1354 | unsigned long *end) | |
1355 | { | |
1356 | if (node->color != color) | |
1357 | *start += 4096; | |
1358 | ||
1359 | if (!list_empty(&node->node_list)) { | |
1360 | node = list_entry(node->node_list.next, | |
1361 | struct drm_mm_node, | |
1362 | node_list); | |
1363 | if (node->allocated && node->color != color) | |
1364 | *end -= 4096; | |
1365 | } | |
1366 | } | |
fbe5d36e | 1367 | |
d7e5008f BW |
1368 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1369 | unsigned long start, | |
1370 | unsigned long mappable_end, | |
1371 | unsigned long end) | |
644ec02b | 1372 | { |
e78891ca BW |
1373 | /* Let GEM Manage all of the aperture. |
1374 | * | |
1375 | * However, leave one page at the end still bound to the scratch page. | |
1376 | * There are a number of places where the hardware apparently prefetches | |
1377 | * past the end of the object, and we've seen multiple hangs with the | |
1378 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1379 | * aperture. One page should be enough to keep any prefetching inside | |
1380 | * of the aperture. | |
1381 | */ | |
40d74980 BW |
1382 | struct drm_i915_private *dev_priv = dev->dev_private; |
1383 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1384 | struct drm_mm_node *entry; |
1385 | struct drm_i915_gem_object *obj; | |
1386 | unsigned long hole_start, hole_end; | |
644ec02b | 1387 | |
35451cb6 BW |
1388 | BUG_ON(mappable_end > end); |
1389 | ||
ed2f3452 | 1390 | /* Subtract the guard page ... */ |
40d74980 | 1391 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1392 | if (!HAS_LLC(dev)) |
93bd8649 | 1393 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1394 | |
ed2f3452 | 1395 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1396 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1397 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1398 | int ret; |
edd41a87 | 1399 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1400 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1401 | ||
1402 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1403 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1404 | if (ret) |
b3a070cc | 1405 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1406 | obj->has_global_gtt_mapping = 1; |
1407 | } | |
1408 | ||
853ba5d2 BW |
1409 | dev_priv->gtt.base.start = start; |
1410 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1411 | |
ed2f3452 | 1412 | /* Clear any non-preallocated blocks */ |
40d74980 | 1413 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 1414 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
1415 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1416 | hole_start, hole_end); | |
828c7908 | 1417 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
1418 | } |
1419 | ||
1420 | /* And finally clear the reserved guard page */ | |
828c7908 | 1421 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
1422 | } |
1423 | ||
d7e5008f BW |
1424 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1425 | { | |
1426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1427 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1428 | |
853ba5d2 | 1429 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1430 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1431 | |
c8d4c0d6 | 1432 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1433 | } |
1434 | ||
1435 | static int setup_scratch_page(struct drm_device *dev) | |
1436 | { | |
1437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1438 | struct page *page; | |
1439 | dma_addr_t dma_addr; | |
1440 | ||
1441 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1442 | if (page == NULL) | |
1443 | return -ENOMEM; | |
1444 | get_page(page); | |
1445 | set_pages_uc(page, 1); | |
1446 | ||
1447 | #ifdef CONFIG_INTEL_IOMMU | |
1448 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1449 | PCI_DMA_BIDIRECTIONAL); | |
1450 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1451 | return -EINVAL; | |
1452 | #else | |
1453 | dma_addr = page_to_phys(page); | |
1454 | #endif | |
853ba5d2 BW |
1455 | dev_priv->gtt.base.scratch.page = page; |
1456 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1457 | |
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | static void teardown_scratch_page(struct drm_device *dev) | |
1462 | { | |
1463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1464 | struct page *page = dev_priv->gtt.base.scratch.page; |
1465 | ||
1466 | set_pages_wb(page, 1); | |
1467 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1468 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1469 | put_page(page); |
1470 | __free_page(page); | |
e76e9aeb BW |
1471 | } |
1472 | ||
1473 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1474 | { | |
1475 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1476 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1477 | return snb_gmch_ctl << 20; | |
1478 | } | |
1479 | ||
9459d252 BW |
1480 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1481 | { | |
1482 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1483 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1484 | if (bdw_gmch_ctl) | |
1485 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
3a2ffb65 BW |
1486 | if (bdw_gmch_ctl > 4) { |
1487 | WARN_ON(!i915_preliminary_hw_support); | |
1488 | return 4<<20; | |
1489 | } | |
1490 | ||
9459d252 BW |
1491 | return bdw_gmch_ctl << 20; |
1492 | } | |
1493 | ||
baa09f5f | 1494 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1495 | { |
1496 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1497 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1498 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1499 | } | |
1500 | ||
9459d252 BW |
1501 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1502 | { | |
1503 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1504 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1505 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1506 | } | |
1507 | ||
63340133 BW |
1508 | static int ggtt_probe_common(struct drm_device *dev, |
1509 | size_t gtt_size) | |
1510 | { | |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | phys_addr_t gtt_bus_addr; | |
1513 | int ret; | |
1514 | ||
1515 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1516 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1517 | (pci_resource_len(dev->pdev, 0) / 2); | |
1518 | ||
1519 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1520 | if (!dev_priv->gtt.gsm) { | |
1521 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1522 | return -ENOMEM; | |
1523 | } | |
1524 | ||
1525 | ret = setup_scratch_page(dev); | |
1526 | if (ret) { | |
1527 | DRM_ERROR("Scratch setup failed\n"); | |
1528 | /* iounmap will also get called at remove, but meh */ | |
1529 | iounmap(dev_priv->gtt.gsm); | |
1530 | } | |
1531 | ||
1532 | return ret; | |
1533 | } | |
1534 | ||
fbe5d36e BW |
1535 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1536 | * bits. When using advanced contexts each context stores its own PAT, but | |
1537 | * writing this data shouldn't be harmful even in those cases. */ | |
1538 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1539 | { | |
1540 | #define GEN8_PPAT_UC (0<<0) | |
1541 | #define GEN8_PPAT_WC (1<<0) | |
1542 | #define GEN8_PPAT_WT (2<<0) | |
1543 | #define GEN8_PPAT_WB (3<<0) | |
1544 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1545 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1546 | #define GEN8_PPAT_LLC (1<<2) | |
1547 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1548 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1549 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1550 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1551 | uint64_t pat; | |
1552 | ||
1553 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1554 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1555 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1556 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1557 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1558 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1559 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1560 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1561 | ||
1562 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1563 | * write would work. */ | |
1564 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1565 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1566 | } | |
1567 | ||
63340133 BW |
1568 | static int gen8_gmch_probe(struct drm_device *dev, |
1569 | size_t *gtt_total, | |
1570 | size_t *stolen, | |
1571 | phys_addr_t *mappable_base, | |
1572 | unsigned long *mappable_end) | |
1573 | { | |
1574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1575 | unsigned int gtt_size; | |
1576 | u16 snb_gmch_ctl; | |
1577 | int ret; | |
1578 | ||
1579 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1580 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1581 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1582 | ||
1583 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1584 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1585 | ||
1586 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1587 | ||
1588 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1589 | ||
1590 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1591 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1592 | |
fbe5d36e BW |
1593 | gen8_setup_private_ppat(dev_priv); |
1594 | ||
63340133 BW |
1595 | ret = ggtt_probe_common(dev, gtt_size); |
1596 | ||
94ec8f61 BW |
1597 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1598 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1599 | |
1600 | return ret; | |
1601 | } | |
1602 | ||
baa09f5f BW |
1603 | static int gen6_gmch_probe(struct drm_device *dev, |
1604 | size_t *gtt_total, | |
41907ddc BW |
1605 | size_t *stolen, |
1606 | phys_addr_t *mappable_base, | |
1607 | unsigned long *mappable_end) | |
e76e9aeb BW |
1608 | { |
1609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1610 | unsigned int gtt_size; |
e76e9aeb | 1611 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1612 | int ret; |
1613 | ||
41907ddc BW |
1614 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1615 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1616 | ||
baa09f5f BW |
1617 | /* 64/512MB is the current min/max we actually know of, but this is just |
1618 | * a coarse sanity check. | |
e76e9aeb | 1619 | */ |
41907ddc | 1620 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1621 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1622 | dev_priv->gtt.mappable_end); | |
1623 | return -ENXIO; | |
e76e9aeb BW |
1624 | } |
1625 | ||
e76e9aeb BW |
1626 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1627 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1628 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1629 | |
c4ae25ec | 1630 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1631 | |
63340133 BW |
1632 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1633 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1634 | |
63340133 | 1635 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1636 | |
853ba5d2 BW |
1637 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1638 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1639 | |
e76e9aeb BW |
1640 | return ret; |
1641 | } | |
1642 | ||
853ba5d2 | 1643 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1644 | { |
853ba5d2 BW |
1645 | |
1646 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1647 | |
1648 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1649 | iounmap(gtt->gsm); |
1650 | teardown_scratch_page(vm->dev); | |
644ec02b | 1651 | } |
baa09f5f BW |
1652 | |
1653 | static int i915_gmch_probe(struct drm_device *dev, | |
1654 | size_t *gtt_total, | |
41907ddc BW |
1655 | size_t *stolen, |
1656 | phys_addr_t *mappable_base, | |
1657 | unsigned long *mappable_end) | |
baa09f5f BW |
1658 | { |
1659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1660 | int ret; | |
1661 | ||
baa09f5f BW |
1662 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1663 | if (!ret) { | |
1664 | DRM_ERROR("failed to set up gmch\n"); | |
1665 | return -EIO; | |
1666 | } | |
1667 | ||
41907ddc | 1668 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1669 | |
1670 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1671 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f BW |
1672 | |
1673 | return 0; | |
1674 | } | |
1675 | ||
853ba5d2 | 1676 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1677 | { |
1678 | intel_gmch_remove(); | |
1679 | } | |
1680 | ||
1681 | int i915_gem_gtt_init(struct drm_device *dev) | |
1682 | { | |
1683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1684 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1685 | int ret; |
1686 | ||
baa09f5f | 1687 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1688 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1689 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1690 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1691 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1692 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1693 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1694 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1695 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1696 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1697 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1698 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1699 | else if (INTEL_INFO(dev)->gen >= 7) |
1700 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1701 | else |
350ec881 | 1702 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1703 | } else { |
1704 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1705 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1706 | } |
1707 | ||
853ba5d2 | 1708 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1709 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1710 | if (ret) |
baa09f5f | 1711 | return ret; |
baa09f5f | 1712 | |
853ba5d2 BW |
1713 | gtt->base.dev = dev; |
1714 | ||
baa09f5f | 1715 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1716 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1717 | gtt->base.total >> 20); | |
b2f21b4d BW |
1718 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1719 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1720 | |
1721 | return 0; | |
1722 | } | |
6f65e29a BW |
1723 | |
1724 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
1725 | struct i915_address_space *vm) | |
1726 | { | |
1727 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
1728 | if (vma == NULL) | |
1729 | return ERR_PTR(-ENOMEM); | |
1730 | ||
1731 | INIT_LIST_HEAD(&vma->vma_link); | |
1732 | INIT_LIST_HEAD(&vma->mm_list); | |
1733 | INIT_LIST_HEAD(&vma->exec_list); | |
1734 | vma->vm = vm; | |
1735 | vma->obj = obj; | |
1736 | ||
1737 | switch (INTEL_INFO(vm->dev)->gen) { | |
1738 | case 8: | |
1739 | case 7: | |
1740 | case 6: | |
7e0d96bc BW |
1741 | if (i915_is_ggtt(vm)) { |
1742 | vma->unbind_vma = ggtt_unbind_vma; | |
1743 | vma->bind_vma = ggtt_bind_vma; | |
1744 | } else { | |
1745 | vma->unbind_vma = ppgtt_unbind_vma; | |
1746 | vma->bind_vma = ppgtt_bind_vma; | |
1747 | } | |
6f65e29a BW |
1748 | break; |
1749 | case 5: | |
1750 | case 4: | |
1751 | case 3: | |
1752 | case 2: | |
1753 | BUG_ON(!i915_is_ggtt(vm)); | |
1754 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
1755 | vma->bind_vma = i915_ggtt_bind_vma; | |
1756 | break; | |
1757 | default: | |
1758 | BUG(); | |
1759 | } | |
1760 | ||
1761 | /* Keep GGTT vmas first to make debug easier */ | |
1762 | if (i915_is_ggtt(vm)) | |
1763 | list_add(&vma->vma_link, &obj->vma_list); | |
1764 | else | |
1765 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
1766 | ||
1767 | return vma; | |
1768 | } | |
1769 | ||
1770 | struct i915_vma * | |
1771 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
1772 | struct i915_address_space *vm) | |
1773 | { | |
1774 | struct i915_vma *vma; | |
1775 | ||
1776 | vma = i915_gem_obj_to_vma(obj, vm); | |
1777 | if (!vma) | |
1778 | vma = __i915_gem_vma_create(obj, vm); | |
1779 | ||
1780 | return vma; | |
1781 | } |