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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
10122051 JN |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ | |
33 | u32 trans2; /* vref sel, vswing */ | |
f8896f5d | 34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
10122051 JN |
35 | }; |
36 | ||
97eeb872 VS |
37 | static const u8 index_to_dp_signal_levels[] = { |
38 | [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
39 | [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
40 | [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, | |
41 | [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, | |
42 | [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
43 | [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
44 | [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, | |
45 | [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
46 | [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, | |
47 | [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, | |
48 | }; | |
49 | ||
45244b87 ED |
50 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
51 | * them for both DP and FDI transports, allowing those ports to | |
52 | * automatically adapt to HDMI connections as well | |
53 | */ | |
10122051 | 54 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
f8896f5d DW |
55 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
56 | { 0x00D75FFF, 0x0005000A, 0x0 }, | |
57 | { 0x00C30FFF, 0x00040006, 0x0 }, | |
58 | { 0x80AAAFFF, 0x000B0000, 0x0 }, | |
59 | { 0x00FFFFFF, 0x0005000A, 0x0 }, | |
60 | { 0x00D75FFF, 0x000C0004, 0x0 }, | |
61 | { 0x80C30FFF, 0x000B0000, 0x0 }, | |
62 | { 0x00FFFFFF, 0x00040006, 0x0 }, | |
63 | { 0x80D75FFF, 0x000B0000, 0x0 }, | |
45244b87 ED |
64 | }; |
65 | ||
10122051 | 66 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
f8896f5d DW |
67 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
68 | { 0x00D75FFF, 0x000F000A, 0x0 }, | |
69 | { 0x00C30FFF, 0x00060006, 0x0 }, | |
70 | { 0x00AAAFFF, 0x001E0000, 0x0 }, | |
71 | { 0x00FFFFFF, 0x000F000A, 0x0 }, | |
72 | { 0x00D75FFF, 0x00160004, 0x0 }, | |
73 | { 0x00C30FFF, 0x001E0000, 0x0 }, | |
74 | { 0x00FFFFFF, 0x00060006, 0x0 }, | |
75 | { 0x00D75FFF, 0x001E0000, 0x0 }, | |
6acab15a PZ |
76 | }; |
77 | ||
10122051 JN |
78 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
79 | /* Idx NT mV d T mV d db */ | |
f8896f5d DW |
80 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
81 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ | |
82 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ | |
83 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ | |
84 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ | |
85 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ | |
86 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ | |
87 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ | |
88 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ | |
89 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ | |
90 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ | |
91 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ | |
45244b87 ED |
92 | }; |
93 | ||
10122051 | 94 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
f8896f5d DW |
95 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
96 | { 0x00EBAFFF, 0x00020011, 0x0 }, | |
97 | { 0x00C71FFF, 0x0006000F, 0x0 }, | |
98 | { 0x00AAAFFF, 0x000E000A, 0x0 }, | |
99 | { 0x00FFFFFF, 0x00020011, 0x0 }, | |
100 | { 0x00DB6FFF, 0x0005000F, 0x0 }, | |
101 | { 0x00BEEFFF, 0x000A000C, 0x0 }, | |
102 | { 0x00FFFFFF, 0x0005000F, 0x0 }, | |
103 | { 0x00DB6FFF, 0x000A000C, 0x0 }, | |
300644c7 PZ |
104 | }; |
105 | ||
10122051 | 106 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
f8896f5d DW |
107 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
108 | { 0x00D75FFF, 0x000E000A, 0x0 }, | |
109 | { 0x00BEFFFF, 0x00140006, 0x0 }, | |
110 | { 0x80B2CFFF, 0x001B0002, 0x0 }, | |
111 | { 0x00FFFFFF, 0x000E000A, 0x0 }, | |
112 | { 0x00DB6FFF, 0x00160005, 0x0 }, | |
113 | { 0x80C71FFF, 0x001A0002, 0x0 }, | |
114 | { 0x00F7DFFF, 0x00180004, 0x0 }, | |
115 | { 0x80D75FFF, 0x001B0002, 0x0 }, | |
e58623cb AR |
116 | }; |
117 | ||
10122051 | 118 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
f8896f5d DW |
119 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
120 | { 0x00D75FFF, 0x0004000A, 0x0 }, | |
121 | { 0x00C30FFF, 0x00070006, 0x0 }, | |
122 | { 0x00AAAFFF, 0x000C0000, 0x0 }, | |
123 | { 0x00FFFFFF, 0x0004000A, 0x0 }, | |
124 | { 0x00D75FFF, 0x00090004, 0x0 }, | |
125 | { 0x00C30FFF, 0x000C0000, 0x0 }, | |
126 | { 0x00FFFFFF, 0x00070006, 0x0 }, | |
127 | { 0x00D75FFF, 0x000C0000, 0x0 }, | |
e58623cb AR |
128 | }; |
129 | ||
10122051 JN |
130 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
131 | /* Idx NT mV d T mV df db */ | |
f8896f5d DW |
132 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
133 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ | |
134 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ | |
135 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ | |
136 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ | |
137 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ | |
138 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ | |
139 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ | |
140 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ | |
141 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ | |
a26aa8ba DL |
142 | }; |
143 | ||
5f8b2531 | 144 | /* Skylake H and S */ |
7f88e3af | 145 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
f8896f5d DW |
146 | { 0x00002016, 0x000000A0, 0x0 }, |
147 | { 0x00005012, 0x0000009B, 0x0 }, | |
148 | { 0x00007011, 0x00000088, 0x0 }, | |
d7097cff | 149 | { 0x80009010, 0x000000C0, 0x1 }, |
f8896f5d DW |
150 | { 0x00002016, 0x0000009B, 0x0 }, |
151 | { 0x00005012, 0x00000088, 0x0 }, | |
d7097cff | 152 | { 0x80007011, 0x000000C0, 0x1 }, |
f8896f5d | 153 | { 0x00002016, 0x000000DF, 0x0 }, |
d7097cff | 154 | { 0x80005012, 0x000000C0, 0x1 }, |
7f88e3af DL |
155 | }; |
156 | ||
f8896f5d DW |
157 | /* Skylake U */ |
158 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { | |
5f8b2531 | 159 | { 0x0000201B, 0x000000A2, 0x0 }, |
f8896f5d | 160 | { 0x00005012, 0x00000088, 0x0 }, |
5ac90567 | 161 | { 0x80007011, 0x000000CD, 0x1 }, |
d7097cff | 162 | { 0x80009010, 0x000000C0, 0x1 }, |
5f8b2531 | 163 | { 0x0000201B, 0x0000009D, 0x0 }, |
d7097cff RV |
164 | { 0x80005012, 0x000000C0, 0x1 }, |
165 | { 0x80007011, 0x000000C0, 0x1 }, | |
f8896f5d | 166 | { 0x00002016, 0x00000088, 0x0 }, |
d7097cff | 167 | { 0x80005012, 0x000000C0, 0x1 }, |
f8896f5d DW |
168 | }; |
169 | ||
5f8b2531 RV |
170 | /* Skylake Y */ |
171 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { | |
f8896f5d DW |
172 | { 0x00000018, 0x000000A2, 0x0 }, |
173 | { 0x00005012, 0x00000088, 0x0 }, | |
5ac90567 | 174 | { 0x80007011, 0x000000CD, 0x3 }, |
d7097cff | 175 | { 0x80009010, 0x000000C0, 0x3 }, |
f8896f5d | 176 | { 0x00000018, 0x0000009D, 0x0 }, |
d7097cff RV |
177 | { 0x80005012, 0x000000C0, 0x3 }, |
178 | { 0x80007011, 0x000000C0, 0x3 }, | |
f8896f5d | 179 | { 0x00000018, 0x00000088, 0x0 }, |
d7097cff | 180 | { 0x80005012, 0x000000C0, 0x3 }, |
f8896f5d DW |
181 | }; |
182 | ||
0fdd4918 RV |
183 | /* Kabylake H and S */ |
184 | static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { | |
185 | { 0x00002016, 0x000000A0, 0x0 }, | |
186 | { 0x00005012, 0x0000009B, 0x0 }, | |
187 | { 0x00007011, 0x00000088, 0x0 }, | |
188 | { 0x80009010, 0x000000C0, 0x1 }, | |
189 | { 0x00002016, 0x0000009B, 0x0 }, | |
190 | { 0x00005012, 0x00000088, 0x0 }, | |
191 | { 0x80007011, 0x000000C0, 0x1 }, | |
192 | { 0x00002016, 0x00000097, 0x0 }, | |
193 | { 0x80005012, 0x000000C0, 0x1 }, | |
194 | }; | |
195 | ||
196 | /* Kabylake U */ | |
197 | static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { | |
198 | { 0x0000201B, 0x000000A1, 0x0 }, | |
199 | { 0x00005012, 0x00000088, 0x0 }, | |
200 | { 0x80007011, 0x000000CD, 0x3 }, | |
201 | { 0x80009010, 0x000000C0, 0x3 }, | |
202 | { 0x0000201B, 0x0000009D, 0x0 }, | |
203 | { 0x80005012, 0x000000C0, 0x3 }, | |
204 | { 0x80007011, 0x000000C0, 0x3 }, | |
205 | { 0x00002016, 0x0000004F, 0x0 }, | |
206 | { 0x80005012, 0x000000C0, 0x3 }, | |
207 | }; | |
208 | ||
209 | /* Kabylake Y */ | |
210 | static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { | |
211 | { 0x00001017, 0x000000A1, 0x0 }, | |
212 | { 0x00005012, 0x00000088, 0x0 }, | |
213 | { 0x80007011, 0x000000CD, 0x3 }, | |
214 | { 0x8000800F, 0x000000C0, 0x3 }, | |
215 | { 0x00001017, 0x0000009D, 0x0 }, | |
216 | { 0x80005012, 0x000000C0, 0x3 }, | |
217 | { 0x80007011, 0x000000C0, 0x3 }, | |
218 | { 0x00001017, 0x0000004C, 0x0 }, | |
219 | { 0x80005012, 0x000000C0, 0x3 }, | |
220 | }; | |
221 | ||
f8896f5d | 222 | /* |
0fdd4918 | 223 | * Skylake/Kabylake H and S |
f8896f5d DW |
224 | * eDP 1.4 low vswing translation parameters |
225 | */ | |
7ad14a29 | 226 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
f8896f5d DW |
227 | { 0x00000018, 0x000000A8, 0x0 }, |
228 | { 0x00004013, 0x000000A9, 0x0 }, | |
229 | { 0x00007011, 0x000000A2, 0x0 }, | |
230 | { 0x00009010, 0x0000009C, 0x0 }, | |
231 | { 0x00000018, 0x000000A9, 0x0 }, | |
232 | { 0x00006013, 0x000000A2, 0x0 }, | |
233 | { 0x00007011, 0x000000A6, 0x0 }, | |
234 | { 0x00000018, 0x000000AB, 0x0 }, | |
235 | { 0x00007013, 0x0000009F, 0x0 }, | |
236 | { 0x00000018, 0x000000DF, 0x0 }, | |
237 | }; | |
238 | ||
239 | /* | |
0fdd4918 | 240 | * Skylake/Kabylake U |
f8896f5d DW |
241 | * eDP 1.4 low vswing translation parameters |
242 | */ | |
243 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { | |
244 | { 0x00000018, 0x000000A8, 0x0 }, | |
245 | { 0x00004013, 0x000000A9, 0x0 }, | |
246 | { 0x00007011, 0x000000A2, 0x0 }, | |
247 | { 0x00009010, 0x0000009C, 0x0 }, | |
248 | { 0x00000018, 0x000000A9, 0x0 }, | |
249 | { 0x00006013, 0x000000A2, 0x0 }, | |
250 | { 0x00007011, 0x000000A6, 0x0 }, | |
251 | { 0x00002016, 0x000000AB, 0x0 }, | |
252 | { 0x00005013, 0x0000009F, 0x0 }, | |
253 | { 0x00000018, 0x000000DF, 0x0 }, | |
7ad14a29 SJ |
254 | }; |
255 | ||
f8896f5d | 256 | /* |
0fdd4918 | 257 | * Skylake/Kabylake Y |
f8896f5d DW |
258 | * eDP 1.4 low vswing translation parameters |
259 | */ | |
5f8b2531 | 260 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
f8896f5d DW |
261 | { 0x00000018, 0x000000A8, 0x0 }, |
262 | { 0x00004013, 0x000000AB, 0x0 }, | |
263 | { 0x00007011, 0x000000A4, 0x0 }, | |
264 | { 0x00009010, 0x000000DF, 0x0 }, | |
265 | { 0x00000018, 0x000000AA, 0x0 }, | |
266 | { 0x00006013, 0x000000A4, 0x0 }, | |
267 | { 0x00007011, 0x0000009D, 0x0 }, | |
268 | { 0x00000018, 0x000000A0, 0x0 }, | |
269 | { 0x00006012, 0x000000DF, 0x0 }, | |
270 | { 0x00000018, 0x0000008A, 0x0 }, | |
271 | }; | |
7ad14a29 | 272 | |
0fdd4918 | 273 | /* Skylake/Kabylake U, H and S */ |
7f88e3af | 274 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
f8896f5d DW |
275 | { 0x00000018, 0x000000AC, 0x0 }, |
276 | { 0x00005012, 0x0000009D, 0x0 }, | |
277 | { 0x00007011, 0x00000088, 0x0 }, | |
278 | { 0x00000018, 0x000000A1, 0x0 }, | |
279 | { 0x00000018, 0x00000098, 0x0 }, | |
280 | { 0x00004013, 0x00000088, 0x0 }, | |
2e78416e | 281 | { 0x80006012, 0x000000CD, 0x1 }, |
f8896f5d | 282 | { 0x00000018, 0x000000DF, 0x0 }, |
2e78416e RV |
283 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
284 | { 0x80003015, 0x000000C0, 0x1 }, | |
285 | { 0x80000018, 0x000000C0, 0x1 }, | |
f8896f5d DW |
286 | }; |
287 | ||
0fdd4918 | 288 | /* Skylake/Kabylake Y */ |
5f8b2531 | 289 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
f8896f5d DW |
290 | { 0x00000018, 0x000000A1, 0x0 }, |
291 | { 0x00005012, 0x000000DF, 0x0 }, | |
2e78416e | 292 | { 0x80007011, 0x000000CB, 0x3 }, |
f8896f5d DW |
293 | { 0x00000018, 0x000000A4, 0x0 }, |
294 | { 0x00000018, 0x0000009D, 0x0 }, | |
295 | { 0x00004013, 0x00000080, 0x0 }, | |
2e78416e | 296 | { 0x80006013, 0x000000C0, 0x3 }, |
f8896f5d | 297 | { 0x00000018, 0x0000008A, 0x0 }, |
2e78416e RV |
298 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
299 | { 0x80003015, 0x000000C0, 0x3 }, | |
300 | { 0x80000018, 0x000000C0, 0x3 }, | |
7f88e3af DL |
301 | }; |
302 | ||
96fb9f9b | 303 | struct bxt_ddi_buf_trans { |
ac3ad6c6 VS |
304 | u8 margin; /* swing value */ |
305 | u8 scale; /* scale value */ | |
306 | u8 enable; /* scale enable */ | |
307 | u8 deemphasis; | |
96fb9f9b VK |
308 | }; |
309 | ||
96fb9f9b VK |
310 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
311 | /* Idx NT mV diff db */ | |
043eaf36 VS |
312 | { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ |
313 | { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ | |
314 | { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ | |
315 | { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ | |
316 | { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ | |
317 | { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ | |
318 | { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ | |
319 | { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ | |
320 | { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ | |
321 | { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ | |
96fb9f9b VK |
322 | }; |
323 | ||
d9d7000d SJ |
324 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
325 | /* Idx NT mV diff db */ | |
043eaf36 VS |
326 | { 26, 0, 0, 128, }, /* 0: 200 0 */ |
327 | { 38, 0, 0, 112, }, /* 1: 200 1.5 */ | |
328 | { 48, 0, 0, 96, }, /* 2: 200 4 */ | |
329 | { 54, 0, 0, 69, }, /* 3: 200 6 */ | |
330 | { 32, 0, 0, 128, }, /* 4: 250 0 */ | |
331 | { 48, 0, 0, 104, }, /* 5: 250 1.5 */ | |
332 | { 54, 0, 0, 85, }, /* 6: 250 4 */ | |
333 | { 43, 0, 0, 128, }, /* 7: 300 0 */ | |
334 | { 54, 0, 0, 101, }, /* 8: 300 1.5 */ | |
335 | { 48, 0, 0, 128, }, /* 9: 300 0 */ | |
d9d7000d SJ |
336 | }; |
337 | ||
96fb9f9b VK |
338 | /* BSpec has 2 recommended values - entries 0 and 8. |
339 | * Using the entry with higher vswing. | |
340 | */ | |
341 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { | |
342 | /* Idx NT mV diff db */ | |
043eaf36 VS |
343 | { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ |
344 | { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ | |
345 | { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ | |
346 | { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ | |
347 | { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ | |
348 | { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ | |
349 | { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ | |
350 | { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ | |
351 | { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ | |
352 | { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ | |
96fb9f9b VK |
353 | }; |
354 | ||
83fb7ab4 | 355 | struct cnl_ddi_buf_trans { |
fb5f4e96 VS |
356 | u8 dw2_swing_sel; |
357 | u8 dw7_n_scalar; | |
358 | u8 dw4_cursor_coeff; | |
359 | u8 dw4_post_cursor_2; | |
360 | u8 dw4_post_cursor_1; | |
83fb7ab4 RV |
361 | }; |
362 | ||
363 | /* Voltage Swing Programming for VccIO 0.85V for DP */ | |
364 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { | |
365 | /* NT mV Trans mV db */ | |
366 | { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ | |
367 | { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ | |
368 | { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ | |
369 | { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ | |
370 | { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ | |
371 | { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ | |
372 | { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ | |
373 | { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ | |
374 | { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ | |
375 | { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ | |
376 | }; | |
377 | ||
378 | /* Voltage Swing Programming for VccIO 0.85V for HDMI */ | |
379 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { | |
380 | /* NT mV Trans mV db */ | |
381 | { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ | |
382 | { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ | |
383 | { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ | |
384 | { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ | |
385 | { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ | |
386 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ | |
387 | { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
388 | }; | |
389 | ||
390 | /* Voltage Swing Programming for VccIO 0.85V for eDP */ | |
391 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { | |
392 | /* NT mV Trans mV db */ | |
393 | { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ | |
394 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ | |
395 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ | |
396 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ | |
397 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ | |
398 | { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ | |
399 | { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ | |
400 | { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ | |
401 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
402 | }; | |
403 | ||
404 | /* Voltage Swing Programming for VccIO 0.95V for DP */ | |
405 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { | |
406 | /* NT mV Trans mV db */ | |
407 | { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ | |
408 | { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ | |
409 | { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ | |
410 | { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ | |
411 | { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ | |
412 | { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ | |
413 | { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ | |
414 | { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ | |
415 | { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ | |
416 | { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ | |
417 | }; | |
418 | ||
419 | /* Voltage Swing Programming for VccIO 0.95V for HDMI */ | |
420 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { | |
421 | /* NT mV Trans mV db */ | |
422 | { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
423 | { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ | |
424 | { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ | |
425 | { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ | |
426 | { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ | |
427 | { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
428 | { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ | |
429 | { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ | |
430 | { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ | |
431 | { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ | |
432 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ | |
433 | }; | |
434 | ||
435 | /* Voltage Swing Programming for VccIO 0.95V for eDP */ | |
436 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { | |
437 | /* NT mV Trans mV db */ | |
438 | { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ | |
439 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ | |
440 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ | |
441 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ | |
442 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ | |
443 | { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ | |
444 | { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ | |
445 | { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ | |
446 | { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ | |
447 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
448 | }; | |
449 | ||
450 | /* Voltage Swing Programming for VccIO 1.05V for DP */ | |
451 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { | |
452 | /* NT mV Trans mV db */ | |
453 | { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
454 | { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ | |
455 | { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ | |
456 | { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ | |
457 | { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ | |
458 | { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
459 | { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ | |
460 | { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ | |
461 | { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ | |
462 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ | |
463 | }; | |
464 | ||
465 | /* Voltage Swing Programming for VccIO 1.05V for HDMI */ | |
466 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { | |
467 | /* NT mV Trans mV db */ | |
468 | { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
469 | { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ | |
470 | { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ | |
471 | { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ | |
472 | { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ | |
473 | { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ | |
474 | { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ | |
475 | { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ | |
476 | { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ | |
477 | { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ | |
478 | { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ | |
479 | }; | |
480 | ||
481 | /* Voltage Swing Programming for VccIO 1.05V for eDP */ | |
482 | static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { | |
483 | /* NT mV Trans mV db */ | |
484 | { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ | |
485 | { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ | |
486 | { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ | |
487 | { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ | |
488 | { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ | |
489 | { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ | |
490 | { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ | |
491 | { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ | |
492 | { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ | |
493 | }; | |
494 | ||
5a5d24dc | 495 | enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder) |
fc914639 | 496 | { |
5a5d24dc | 497 | switch (encoder->type) { |
8cd21b7f | 498 | case INTEL_OUTPUT_DP_MST: |
5a5d24dc | 499 | return enc_to_mst(&encoder->base)->primary->port; |
cca0502b | 500 | case INTEL_OUTPUT_DP: |
8cd21b7f JN |
501 | case INTEL_OUTPUT_EDP: |
502 | case INTEL_OUTPUT_HDMI: | |
503 | case INTEL_OUTPUT_UNKNOWN: | |
5a5d24dc | 504 | return enc_to_dig_port(&encoder->base)->port; |
8cd21b7f | 505 | case INTEL_OUTPUT_ANALOG: |
5a5d24dc VS |
506 | return PORT_E; |
507 | default: | |
508 | MISSING_CASE(encoder->type); | |
509 | return PORT_A; | |
fc914639 PZ |
510 | } |
511 | } | |
512 | ||
a930acd9 VS |
513 | static const struct ddi_buf_trans * |
514 | bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
515 | { | |
516 | if (dev_priv->vbt.edp.low_vswing) { | |
517 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); | |
518 | return bdw_ddi_translations_edp; | |
519 | } else { | |
520 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
521 | return bdw_ddi_translations_dp; | |
522 | } | |
523 | } | |
524 | ||
acee2998 | 525 | static const struct ddi_buf_trans * |
78ab0bae | 526 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 527 | { |
0fdd4918 | 528 | if (IS_SKL_ULX(dev_priv)) { |
5f8b2531 | 529 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
acee2998 | 530 | return skl_y_ddi_translations_dp; |
0fdd4918 | 531 | } else if (IS_SKL_ULT(dev_priv)) { |
f8896f5d | 532 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
acee2998 | 533 | return skl_u_ddi_translations_dp; |
f8896f5d | 534 | } else { |
f8896f5d | 535 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
acee2998 | 536 | return skl_ddi_translations_dp; |
f8896f5d | 537 | } |
f8896f5d DW |
538 | } |
539 | ||
0fdd4918 RV |
540 | static const struct ddi_buf_trans * |
541 | kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
542 | { | |
543 | if (IS_KBL_ULX(dev_priv)) { | |
544 | *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); | |
545 | return kbl_y_ddi_translations_dp; | |
da411a48 | 546 | } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { |
0fdd4918 RV |
547 | *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); |
548 | return kbl_u_ddi_translations_dp; | |
549 | } else { | |
550 | *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); | |
551 | return kbl_ddi_translations_dp; | |
552 | } | |
553 | } | |
554 | ||
acee2998 | 555 | static const struct ddi_buf_trans * |
78ab0bae | 556 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 557 | { |
06411f08 | 558 | if (dev_priv->vbt.edp.low_vswing) { |
78ab0bae | 559 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 560 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
acee2998 | 561 | return skl_y_ddi_translations_edp; |
da411a48 RV |
562 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || |
563 | IS_CFL_ULT(dev_priv)) { | |
f8896f5d | 564 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
acee2998 | 565 | return skl_u_ddi_translations_edp; |
f8896f5d | 566 | } else { |
f8896f5d | 567 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
acee2998 | 568 | return skl_ddi_translations_edp; |
f8896f5d DW |
569 | } |
570 | } | |
cd1101cb | 571 | |
da411a48 | 572 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) |
0fdd4918 RV |
573 | return kbl_get_buf_trans_dp(dev_priv, n_entries); |
574 | else | |
575 | return skl_get_buf_trans_dp(dev_priv, n_entries); | |
f8896f5d DW |
576 | } |
577 | ||
578 | static const struct ddi_buf_trans * | |
78ab0bae | 579 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 580 | { |
78ab0bae | 581 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 582 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
acee2998 | 583 | return skl_y_ddi_translations_hdmi; |
f8896f5d | 584 | } else { |
f8896f5d | 585 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
acee2998 | 586 | return skl_ddi_translations_hdmi; |
f8896f5d | 587 | } |
f8896f5d DW |
588 | } |
589 | ||
edba48fd VS |
590 | static int skl_buf_trans_num_entries(enum port port, int n_entries) |
591 | { | |
592 | /* Only DDIA and DDIE can select the 10th register with DP */ | |
593 | if (port == PORT_A || port == PORT_E) | |
594 | return min(n_entries, 10); | |
595 | else | |
596 | return min(n_entries, 9); | |
597 | } | |
598 | ||
d8fe2c7f VS |
599 | static const struct ddi_buf_trans * |
600 | intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, | |
edba48fd | 601 | enum port port, int *n_entries) |
d8fe2c7f VS |
602 | { |
603 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { | |
edba48fd VS |
604 | const struct ddi_buf_trans *ddi_translations = |
605 | kbl_get_buf_trans_dp(dev_priv, n_entries); | |
606 | *n_entries = skl_buf_trans_num_entries(port, *n_entries); | |
607 | return ddi_translations; | |
d8fe2c7f | 608 | } else if (IS_SKYLAKE(dev_priv)) { |
edba48fd VS |
609 | const struct ddi_buf_trans *ddi_translations = |
610 | skl_get_buf_trans_dp(dev_priv, n_entries); | |
611 | *n_entries = skl_buf_trans_num_entries(port, *n_entries); | |
612 | return ddi_translations; | |
d8fe2c7f VS |
613 | } else if (IS_BROADWELL(dev_priv)) { |
614 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
615 | return bdw_ddi_translations_dp; | |
616 | } else if (IS_HASWELL(dev_priv)) { | |
617 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); | |
618 | return hsw_ddi_translations_dp; | |
619 | } | |
620 | ||
621 | *n_entries = 0; | |
622 | return NULL; | |
623 | } | |
624 | ||
625 | static const struct ddi_buf_trans * | |
626 | intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, | |
edba48fd | 627 | enum port port, int *n_entries) |
d8fe2c7f VS |
628 | { |
629 | if (IS_GEN9_BC(dev_priv)) { | |
edba48fd VS |
630 | const struct ddi_buf_trans *ddi_translations = |
631 | skl_get_buf_trans_edp(dev_priv, n_entries); | |
632 | *n_entries = skl_buf_trans_num_entries(port, *n_entries); | |
633 | return ddi_translations; | |
d8fe2c7f VS |
634 | } else if (IS_BROADWELL(dev_priv)) { |
635 | return bdw_get_buf_trans_edp(dev_priv, n_entries); | |
636 | } else if (IS_HASWELL(dev_priv)) { | |
637 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); | |
638 | return hsw_ddi_translations_dp; | |
639 | } | |
640 | ||
641 | *n_entries = 0; | |
642 | return NULL; | |
643 | } | |
644 | ||
645 | static const struct ddi_buf_trans * | |
646 | intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, | |
647 | int *n_entries) | |
648 | { | |
649 | if (IS_BROADWELL(dev_priv)) { | |
650 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); | |
651 | return bdw_ddi_translations_fdi; | |
652 | } else if (IS_HASWELL(dev_priv)) { | |
653 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); | |
654 | return hsw_ddi_translations_fdi; | |
655 | } | |
656 | ||
657 | *n_entries = 0; | |
658 | return NULL; | |
659 | } | |
660 | ||
975786ee VS |
661 | static const struct ddi_buf_trans * |
662 | intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, | |
663 | int *n_entries) | |
664 | { | |
665 | if (IS_GEN9_BC(dev_priv)) { | |
666 | return skl_get_buf_trans_hdmi(dev_priv, n_entries); | |
667 | } else if (IS_BROADWELL(dev_priv)) { | |
668 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
669 | return bdw_ddi_translations_hdmi; | |
670 | } else if (IS_HASWELL(dev_priv)) { | |
671 | *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
672 | return hsw_ddi_translations_hdmi; | |
673 | } | |
674 | ||
675 | *n_entries = 0; | |
676 | return NULL; | |
677 | } | |
678 | ||
7d4f37b5 VS |
679 | static const struct bxt_ddi_buf_trans * |
680 | bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
681 | { | |
682 | *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); | |
683 | return bxt_ddi_translations_dp; | |
684 | } | |
685 | ||
686 | static const struct bxt_ddi_buf_trans * | |
687 | bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
688 | { | |
689 | if (dev_priv->vbt.edp.low_vswing) { | |
690 | *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); | |
691 | return bxt_ddi_translations_edp; | |
692 | } | |
693 | ||
694 | return bxt_get_buf_trans_dp(dev_priv, n_entries); | |
695 | } | |
696 | ||
697 | static const struct bxt_ddi_buf_trans * | |
698 | bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) | |
699 | { | |
700 | *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); | |
701 | return bxt_ddi_translations_hdmi; | |
702 | } | |
703 | ||
cf3e0fb4 RV |
704 | static const struct cnl_ddi_buf_trans * |
705 | cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) | |
706 | { | |
707 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
708 | ||
709 | if (voltage == VOLTAGE_INFO_0_85V) { | |
710 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); | |
711 | return cnl_ddi_translations_hdmi_0_85V; | |
712 | } else if (voltage == VOLTAGE_INFO_0_95V) { | |
713 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); | |
714 | return cnl_ddi_translations_hdmi_0_95V; | |
715 | } else if (voltage == VOLTAGE_INFO_1_05V) { | |
716 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); | |
717 | return cnl_ddi_translations_hdmi_1_05V; | |
83482ca3 AB |
718 | } else { |
719 | *n_entries = 1; /* shut up gcc */ | |
cf3e0fb4 | 720 | MISSING_CASE(voltage); |
83482ca3 | 721 | } |
cf3e0fb4 RV |
722 | return NULL; |
723 | } | |
724 | ||
725 | static const struct cnl_ddi_buf_trans * | |
726 | cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
727 | { | |
728 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
729 | ||
730 | if (voltage == VOLTAGE_INFO_0_85V) { | |
731 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); | |
732 | return cnl_ddi_translations_dp_0_85V; | |
733 | } else if (voltage == VOLTAGE_INFO_0_95V) { | |
734 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); | |
735 | return cnl_ddi_translations_dp_0_95V; | |
736 | } else if (voltage == VOLTAGE_INFO_1_05V) { | |
737 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); | |
738 | return cnl_ddi_translations_dp_1_05V; | |
83482ca3 AB |
739 | } else { |
740 | *n_entries = 1; /* shut up gcc */ | |
cf3e0fb4 | 741 | MISSING_CASE(voltage); |
83482ca3 | 742 | } |
cf3e0fb4 RV |
743 | return NULL; |
744 | } | |
745 | ||
746 | static const struct cnl_ddi_buf_trans * | |
747 | cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
748 | { | |
749 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
750 | ||
751 | if (dev_priv->vbt.edp.low_vswing) { | |
752 | if (voltage == VOLTAGE_INFO_0_85V) { | |
753 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); | |
754 | return cnl_ddi_translations_edp_0_85V; | |
755 | } else if (voltage == VOLTAGE_INFO_0_95V) { | |
756 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); | |
757 | return cnl_ddi_translations_edp_0_95V; | |
758 | } else if (voltage == VOLTAGE_INFO_1_05V) { | |
759 | *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); | |
760 | return cnl_ddi_translations_edp_1_05V; | |
83482ca3 AB |
761 | } else { |
762 | *n_entries = 1; /* shut up gcc */ | |
cf3e0fb4 | 763 | MISSING_CASE(voltage); |
83482ca3 | 764 | } |
cf3e0fb4 RV |
765 | return NULL; |
766 | } else { | |
767 | return cnl_get_buf_trans_dp(dev_priv, n_entries); | |
768 | } | |
769 | } | |
770 | ||
8d8bb85e VS |
771 | static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) |
772 | { | |
d02ace87 | 773 | int n_entries, level, default_entry; |
8d8bb85e | 774 | |
d02ace87 | 775 | level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
8d8bb85e | 776 | |
bf503556 | 777 | if (IS_CANNONLAKE(dev_priv)) { |
d02ace87 VS |
778 | cnl_get_buf_trans_hdmi(dev_priv, &n_entries); |
779 | default_entry = n_entries - 1; | |
043eaf36 | 780 | } else if (IS_GEN9_LP(dev_priv)) { |
d02ace87 VS |
781 | bxt_get_buf_trans_hdmi(dev_priv, &n_entries); |
782 | default_entry = n_entries - 1; | |
bf503556 | 783 | } else if (IS_GEN9_BC(dev_priv)) { |
d02ace87 VS |
784 | intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
785 | default_entry = 8; | |
8d8bb85e | 786 | } else if (IS_BROADWELL(dev_priv)) { |
d02ace87 VS |
787 | intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
788 | default_entry = 7; | |
8d8bb85e | 789 | } else if (IS_HASWELL(dev_priv)) { |
d02ace87 VS |
790 | intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
791 | default_entry = 6; | |
8d8bb85e VS |
792 | } else { |
793 | WARN(1, "ddi translation table missing\n"); | |
975786ee | 794 | return 0; |
8d8bb85e VS |
795 | } |
796 | ||
797 | /* Choose a good default if VBT is badly populated */ | |
d02ace87 VS |
798 | if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries) |
799 | level = default_entry; | |
8d8bb85e | 800 | |
d02ace87 | 801 | if (WARN_ON_ONCE(n_entries == 0)) |
21b39d2a | 802 | return 0; |
d02ace87 VS |
803 | if (WARN_ON_ONCE(level >= n_entries)) |
804 | level = n_entries - 1; | |
21b39d2a | 805 | |
d02ace87 | 806 | return level; |
8d8bb85e VS |
807 | } |
808 | ||
e58623cb AR |
809 | /* |
810 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
32bdc400 VS |
811 | * values in advance. This function programs the correct values for |
812 | * DP/eDP/FDI use cases. | |
45244b87 | 813 | */ |
d7c530b2 | 814 | static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) |
45244b87 | 815 | { |
6a7e4f99 | 816 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
75067dde | 817 | u32 iboost_bit = 0; |
7d1c42e6 | 818 | int i, n_entries; |
32bdc400 | 819 | enum port port = intel_ddi_get_encoder_port(encoder); |
10122051 | 820 | const struct ddi_buf_trans *ddi_translations; |
e58623cb | 821 | |
7d1c42e6 VS |
822 | switch (encoder->type) { |
823 | case INTEL_OUTPUT_EDP: | |
edba48fd | 824 | ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, |
7d1c42e6 VS |
825 | &n_entries); |
826 | break; | |
827 | case INTEL_OUTPUT_DP: | |
edba48fd | 828 | ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, |
7d1c42e6 VS |
829 | &n_entries); |
830 | break; | |
831 | case INTEL_OUTPUT_ANALOG: | |
832 | ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, | |
833 | &n_entries); | |
834 | break; | |
835 | default: | |
836 | MISSING_CASE(encoder->type); | |
837 | return; | |
e58623cb AR |
838 | } |
839 | ||
edba48fd VS |
840 | /* If we're boosting the current, set bit 31 of trans1 */ |
841 | if (IS_GEN9_BC(dev_priv) && | |
842 | dev_priv->vbt.ddi_port_info[port].dp_boost_level) | |
843 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; | |
45244b87 | 844 | |
7d1c42e6 | 845 | for (i = 0; i < n_entries; i++) { |
9712e688 VS |
846 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), |
847 | ddi_translations[i].trans1 | iboost_bit); | |
848 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), | |
849 | ddi_translations[i].trans2); | |
45244b87 | 850 | } |
32bdc400 VS |
851 | } |
852 | ||
853 | /* | |
854 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
855 | * values in advance. This function programs the correct values for | |
856 | * HDMI/DVI use cases. | |
857 | */ | |
7ea79333 | 858 | static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, |
d02ace87 | 859 | int level) |
32bdc400 VS |
860 | { |
861 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
862 | u32 iboost_bit = 0; | |
d02ace87 | 863 | int n_entries; |
32bdc400 | 864 | enum port port = intel_ddi_get_encoder_port(encoder); |
d02ace87 | 865 | const struct ddi_buf_trans *ddi_translations; |
ce4dd49e | 866 | |
d02ace87 | 867 | ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); |
1edaaa2f | 868 | |
d02ace87 | 869 | if (WARN_ON_ONCE(!ddi_translations)) |
21b39d2a | 870 | return; |
d02ace87 VS |
871 | if (WARN_ON_ONCE(level >= n_entries)) |
872 | level = n_entries - 1; | |
21b39d2a | 873 | |
975786ee VS |
874 | /* If we're boosting the current, set bit 31 of trans1 */ |
875 | if (IS_GEN9_BC(dev_priv) && | |
876 | dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) | |
877 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; | |
32bdc400 | 878 | |
6acab15a | 879 | /* Entry 9 is for HDMI: */ |
ed9c77d2 | 880 | I915_WRITE(DDI_BUF_TRANS_LO(port, 9), |
d02ace87 | 881 | ddi_translations[level].trans1 | iboost_bit); |
ed9c77d2 | 882 | I915_WRITE(DDI_BUF_TRANS_HI(port, 9), |
d02ace87 | 883 | ddi_translations[level].trans2); |
45244b87 ED |
884 | } |
885 | ||
248138b5 PZ |
886 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
887 | enum port port) | |
888 | { | |
f0f59a00 | 889 | i915_reg_t reg = DDI_BUF_CTL(port); |
248138b5 PZ |
890 | int i; |
891 | ||
3449ca85 | 892 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
893 | udelay(1); |
894 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
895 | return; | |
896 | } | |
897 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
898 | } | |
c82e4d26 | 899 | |
5f88a9c6 | 900 | static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) |
c856052a ACO |
901 | { |
902 | switch (pll->id) { | |
903 | case DPLL_ID_WRPLL1: | |
904 | return PORT_CLK_SEL_WRPLL1; | |
905 | case DPLL_ID_WRPLL2: | |
906 | return PORT_CLK_SEL_WRPLL2; | |
907 | case DPLL_ID_SPLL: | |
908 | return PORT_CLK_SEL_SPLL; | |
909 | case DPLL_ID_LCPLL_810: | |
910 | return PORT_CLK_SEL_LCPLL_810; | |
911 | case DPLL_ID_LCPLL_1350: | |
912 | return PORT_CLK_SEL_LCPLL_1350; | |
913 | case DPLL_ID_LCPLL_2700: | |
914 | return PORT_CLK_SEL_LCPLL_2700; | |
915 | default: | |
916 | MISSING_CASE(pll->id); | |
917 | return PORT_CLK_SEL_NONE; | |
918 | } | |
919 | } | |
920 | ||
c82e4d26 ED |
921 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
922 | * connection to the PCH-located connectors. For this, it is necessary to train | |
923 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
924 | * | |
925 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
926 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
927 | * DDI A (which is used for eDP) | |
928 | */ | |
929 | ||
dc4a1094 ACO |
930 | void hsw_fdi_link_train(struct intel_crtc *crtc, |
931 | const struct intel_crtc_state *crtc_state) | |
c82e4d26 | 932 | { |
4cbe4b2b | 933 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 934 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a7e4f99 | 935 | struct intel_encoder *encoder; |
c856052a | 936 | u32 temp, i, rx_ctl_val, ddi_pll_sel; |
c82e4d26 | 937 | |
4cbe4b2b | 938 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
6a7e4f99 | 939 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); |
32bdc400 | 940 | intel_prepare_dp_ddi_buffers(encoder); |
6a7e4f99 VS |
941 | } |
942 | ||
04945641 PZ |
943 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
944 | * mode set "sequence for CRT port" document: | |
945 | * - TP1 to TP2 time with the default value | |
946 | * - FDI delay to 90h | |
8693a824 DL |
947 | * |
948 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 | 949 | */ |
eede3b53 | 950 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
04945641 PZ |
951 | FDI_RX_PWRDN_LANE0_VAL(2) | |
952 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
953 | ||
954 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 955 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 956 | FDI_RX_PLL_ENABLE | |
dc4a1094 | 957 | FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
eede3b53 VS |
958 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
959 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
960 | udelay(220); |
961 | ||
962 | /* Switch from Rawclk to PCDclk */ | |
963 | rx_ctl_val |= FDI_PCDCLK; | |
eede3b53 | 964 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
04945641 PZ |
965 | |
966 | /* Configure Port Clock Select */ | |
dc4a1094 | 967 | ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); |
c856052a ACO |
968 | I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); |
969 | WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
970 | |
971 | /* Start the training iterating through available voltages and emphasis, | |
972 | * testing each value twice. */ | |
10122051 | 973 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
974 | /* Configure DP_TP_CTL with auto-training */ |
975 | I915_WRITE(DP_TP_CTL(PORT_E), | |
976 | DP_TP_CTL_FDI_AUTOTRAIN | | |
977 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
978 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
979 | DP_TP_CTL_ENABLE); | |
980 | ||
876a8cdf DL |
981 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
982 | * DDI E does not support port reversal, the functionality is | |
983 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
984 | * port reversal bit */ | |
c82e4d26 | 985 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 986 | DDI_BUF_CTL_ENABLE | |
dc4a1094 | 987 | ((crtc_state->fdi_lanes - 1) << 1) | |
c5fe6a06 | 988 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 989 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
990 | |
991 | udelay(600); | |
992 | ||
04945641 | 993 | /* Program PCH FDI Receiver TU */ |
eede3b53 | 994 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
04945641 PZ |
995 | |
996 | /* Enable PCH FDI Receiver with auto-training */ | |
997 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
eede3b53 VS |
998 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
999 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
1000 | |
1001 | /* Wait for FDI receiver lane calibration */ | |
1002 | udelay(30); | |
1003 | ||
1004 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
eede3b53 | 1005 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 | 1006 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
eede3b53 VS |
1007 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
1008 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
04945641 PZ |
1009 | |
1010 | /* Wait for FDI auto training time */ | |
1011 | udelay(5); | |
c82e4d26 ED |
1012 | |
1013 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
1014 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 1015 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
a308ccb3 VS |
1016 | break; |
1017 | } | |
c82e4d26 | 1018 | |
a308ccb3 VS |
1019 | /* |
1020 | * Leave things enabled even if we failed to train FDI. | |
1021 | * Results in less fireworks from the state checker. | |
1022 | */ | |
1023 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { | |
1024 | DRM_ERROR("FDI link training failed!\n"); | |
1025 | break; | |
c82e4d26 | 1026 | } |
04945641 | 1027 | |
5b421c57 VS |
1028 | rx_ctl_val &= ~FDI_RX_ENABLE; |
1029 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); | |
1030 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
1031 | ||
248138b5 PZ |
1032 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
1033 | temp &= ~DDI_BUF_CTL_ENABLE; | |
1034 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
1035 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
1036 | ||
04945641 | 1037 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
1038 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
1039 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1040 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1041 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
1042 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
1043 | ||
1044 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 | 1045 | |
04945641 | 1046 | /* Reset FDI_RX_MISC pwrdn lanes */ |
eede3b53 | 1047 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 PZ |
1048 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
1049 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 VS |
1050 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
1051 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
c82e4d26 ED |
1052 | } |
1053 | ||
a308ccb3 VS |
1054 | /* Enable normal pixel sending for FDI */ |
1055 | I915_WRITE(DP_TP_CTL(PORT_E), | |
1056 | DP_TP_CTL_FDI_AUTOTRAIN | | |
1057 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
1058 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
1059 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 1060 | } |
0e72a5b5 | 1061 | |
d7c530b2 | 1062 | static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
44905a27 DA |
1063 | { |
1064 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1065 | struct intel_digital_port *intel_dig_port = | |
1066 | enc_to_dig_port(&encoder->base); | |
1067 | ||
1068 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 1069 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
901c2daf | 1070 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
44905a27 DA |
1071 | } |
1072 | ||
8d9ddbcb | 1073 | static struct intel_encoder * |
e9ce1a62 | 1074 | intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) |
8d9ddbcb | 1075 | { |
e9ce1a62 | 1076 | struct drm_device *dev = crtc->base.dev; |
1524e93e | 1077 | struct intel_encoder *encoder, *ret = NULL; |
8d9ddbcb PZ |
1078 | int num_encoders = 0; |
1079 | ||
1524e93e SS |
1080 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
1081 | ret = encoder; | |
8d9ddbcb PZ |
1082 | num_encoders++; |
1083 | } | |
1084 | ||
1085 | if (num_encoders != 1) | |
84f44ce7 | 1086 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
e9ce1a62 | 1087 | pipe_name(crtc->pipe)); |
8d9ddbcb PZ |
1088 | |
1089 | BUG_ON(ret == NULL); | |
1090 | return ret; | |
1091 | } | |
1092 | ||
44a126ba PZ |
1093 | /* Finds the only possible encoder associated with the given CRTC. */ |
1094 | struct intel_encoder * | |
3165c074 | 1095 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
d0737e1d | 1096 | { |
3165c074 ACO |
1097 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
1098 | struct intel_encoder *ret = NULL; | |
1099 | struct drm_atomic_state *state; | |
da3ced29 ACO |
1100 | struct drm_connector *connector; |
1101 | struct drm_connector_state *connector_state; | |
d0737e1d | 1102 | int num_encoders = 0; |
3165c074 | 1103 | int i; |
d0737e1d | 1104 | |
3165c074 ACO |
1105 | state = crtc_state->base.state; |
1106 | ||
b77c7a90 | 1107 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 1108 | if (connector_state->crtc != crtc_state->base.crtc) |
3165c074 ACO |
1109 | continue; |
1110 | ||
da3ced29 | 1111 | ret = to_intel_encoder(connector_state->best_encoder); |
3165c074 | 1112 | num_encoders++; |
d0737e1d ACO |
1113 | } |
1114 | ||
1115 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, | |
1116 | pipe_name(crtc->pipe)); | |
1117 | ||
1118 | BUG_ON(ret == NULL); | |
1119 | return ret; | |
1120 | } | |
1121 | ||
1c0b85c5 | 1122 | #define LC_FREQ 2700 |
1c0b85c5 | 1123 | |
f0f59a00 VS |
1124 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
1125 | i915_reg_t reg) | |
11578553 JB |
1126 | { |
1127 | int refclk = LC_FREQ; | |
1128 | int n, p, r; | |
1129 | u32 wrpll; | |
1130 | ||
1131 | wrpll = I915_READ(reg); | |
114fe488 DV |
1132 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
1133 | case WRPLL_PLL_SSC: | |
1134 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
1135 | /* |
1136 | * We could calculate spread here, but our checking | |
1137 | * code only cares about 5% accuracy, and spread is a max of | |
1138 | * 0.5% downspread. | |
1139 | */ | |
1140 | refclk = 135; | |
1141 | break; | |
114fe488 | 1142 | case WRPLL_PLL_LCPLL: |
11578553 JB |
1143 | refclk = LC_FREQ; |
1144 | break; | |
1145 | default: | |
1146 | WARN(1, "bad wrpll refclk\n"); | |
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
1151 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
1152 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
1153 | ||
20f0ec16 JB |
1154 | /* Convert to KHz, p & r have a fixed point portion */ |
1155 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
1156 | } |
1157 | ||
540e732c | 1158 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
2952cd6f | 1159 | enum intel_dpll_id pll_id) |
540e732c | 1160 | { |
f0f59a00 | 1161 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
540e732c S |
1162 | uint32_t cfgcr1_val, cfgcr2_val; |
1163 | uint32_t p0, p1, p2, dco_freq; | |
1164 | ||
2952cd6f RV |
1165 | cfgcr1_reg = DPLL_CFGCR1(pll_id); |
1166 | cfgcr2_reg = DPLL_CFGCR2(pll_id); | |
540e732c S |
1167 | |
1168 | cfgcr1_val = I915_READ(cfgcr1_reg); | |
1169 | cfgcr2_val = I915_READ(cfgcr2_reg); | |
1170 | ||
1171 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; | |
1172 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; | |
1173 | ||
1174 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) | |
1175 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
1176 | else | |
1177 | p1 = 1; | |
1178 | ||
1179 | ||
1180 | switch (p0) { | |
1181 | case DPLL_CFGCR2_PDIV_1: | |
1182 | p0 = 1; | |
1183 | break; | |
1184 | case DPLL_CFGCR2_PDIV_2: | |
1185 | p0 = 2; | |
1186 | break; | |
1187 | case DPLL_CFGCR2_PDIV_3: | |
1188 | p0 = 3; | |
1189 | break; | |
1190 | case DPLL_CFGCR2_PDIV_7: | |
1191 | p0 = 7; | |
1192 | break; | |
1193 | } | |
1194 | ||
1195 | switch (p2) { | |
1196 | case DPLL_CFGCR2_KDIV_5: | |
1197 | p2 = 5; | |
1198 | break; | |
1199 | case DPLL_CFGCR2_KDIV_2: | |
1200 | p2 = 2; | |
1201 | break; | |
1202 | case DPLL_CFGCR2_KDIV_3: | |
1203 | p2 = 3; | |
1204 | break; | |
1205 | case DPLL_CFGCR2_KDIV_1: | |
1206 | p2 = 1; | |
1207 | break; | |
1208 | } | |
1209 | ||
1210 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; | |
1211 | ||
1212 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * | |
1213 | 1000) / 0x8000; | |
1214 | ||
1215 | return dco_freq / (p0 * p1 * p2 * 5); | |
1216 | } | |
1217 | ||
a9701a89 | 1218 | static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
2952cd6f | 1219 | enum intel_dpll_id pll_id) |
a9701a89 RV |
1220 | { |
1221 | uint32_t cfgcr0, cfgcr1; | |
1222 | uint32_t p0, p1, p2, dco_freq, ref_clock; | |
1223 | ||
1224 | cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); | |
1225 | cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); | |
1226 | ||
1227 | p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK; | |
1228 | p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK; | |
1229 | ||
1230 | if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) | |
1231 | p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> | |
1232 | DPLL_CFGCR1_QDIV_RATIO_SHIFT; | |
1233 | else | |
1234 | p1 = 1; | |
1235 | ||
1236 | ||
1237 | switch (p0) { | |
1238 | case DPLL_CFGCR1_PDIV_2: | |
1239 | p0 = 2; | |
1240 | break; | |
1241 | case DPLL_CFGCR1_PDIV_3: | |
1242 | p0 = 3; | |
1243 | break; | |
1244 | case DPLL_CFGCR1_PDIV_5: | |
1245 | p0 = 5; | |
1246 | break; | |
1247 | case DPLL_CFGCR1_PDIV_7: | |
1248 | p0 = 7; | |
1249 | break; | |
1250 | } | |
1251 | ||
1252 | switch (p2) { | |
1253 | case DPLL_CFGCR1_KDIV_1: | |
1254 | p2 = 1; | |
1255 | break; | |
1256 | case DPLL_CFGCR1_KDIV_2: | |
1257 | p2 = 2; | |
1258 | break; | |
1259 | case DPLL_CFGCR1_KDIV_4: | |
1260 | p2 = 4; | |
1261 | break; | |
1262 | } | |
1263 | ||
1264 | ref_clock = dev_priv->cdclk.hw.ref; | |
1265 | ||
1266 | dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock; | |
1267 | ||
1268 | dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> | |
442aa277 | 1269 | DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; |
a9701a89 | 1270 | |
0e005888 PZ |
1271 | if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) |
1272 | return 0; | |
1273 | ||
a9701a89 RV |
1274 | return dco_freq / (p0 * p1 * p2 * 5); |
1275 | } | |
1276 | ||
398a017e VS |
1277 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
1278 | { | |
1279 | int dotclock; | |
1280 | ||
1281 | if (pipe_config->has_pch_encoder) | |
1282 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
1283 | &pipe_config->fdi_m_n); | |
37a5650b | 1284 | else if (intel_crtc_has_dp_encoder(pipe_config)) |
398a017e VS |
1285 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
1286 | &pipe_config->dp_m_n); | |
1287 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) | |
1288 | dotclock = pipe_config->port_clock * 2 / 3; | |
1289 | else | |
1290 | dotclock = pipe_config->port_clock; | |
1291 | ||
b22ca995 SS |
1292 | if (pipe_config->ycbcr420) |
1293 | dotclock *= 2; | |
1294 | ||
398a017e VS |
1295 | if (pipe_config->pixel_multiplier) |
1296 | dotclock /= pipe_config->pixel_multiplier; | |
1297 | ||
1298 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; | |
1299 | } | |
540e732c | 1300 | |
a9701a89 RV |
1301 | static void cnl_ddi_clock_get(struct intel_encoder *encoder, |
1302 | struct intel_crtc_state *pipe_config) | |
1303 | { | |
1304 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1305 | int link_clock = 0; | |
2952cd6f RV |
1306 | uint32_t cfgcr0; |
1307 | enum intel_dpll_id pll_id; | |
a9701a89 RV |
1308 | |
1309 | pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); | |
1310 | ||
1311 | cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); | |
1312 | ||
1313 | if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { | |
1314 | link_clock = cnl_calc_wrpll_link(dev_priv, pll_id); | |
1315 | } else { | |
1316 | link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; | |
1317 | ||
1318 | switch (link_clock) { | |
1319 | case DPLL_CFGCR0_LINK_RATE_810: | |
1320 | link_clock = 81000; | |
1321 | break; | |
1322 | case DPLL_CFGCR0_LINK_RATE_1080: | |
1323 | link_clock = 108000; | |
1324 | break; | |
1325 | case DPLL_CFGCR0_LINK_RATE_1350: | |
1326 | link_clock = 135000; | |
1327 | break; | |
1328 | case DPLL_CFGCR0_LINK_RATE_1620: | |
1329 | link_clock = 162000; | |
1330 | break; | |
1331 | case DPLL_CFGCR0_LINK_RATE_2160: | |
1332 | link_clock = 216000; | |
1333 | break; | |
1334 | case DPLL_CFGCR0_LINK_RATE_2700: | |
1335 | link_clock = 270000; | |
1336 | break; | |
1337 | case DPLL_CFGCR0_LINK_RATE_3240: | |
1338 | link_clock = 324000; | |
1339 | break; | |
1340 | case DPLL_CFGCR0_LINK_RATE_4050: | |
1341 | link_clock = 405000; | |
1342 | break; | |
1343 | default: | |
1344 | WARN(1, "Unsupported link rate\n"); | |
1345 | break; | |
1346 | } | |
1347 | link_clock *= 2; | |
1348 | } | |
1349 | ||
1350 | pipe_config->port_clock = link_clock; | |
1351 | ||
1352 | ddi_dotclock_get(pipe_config); | |
1353 | } | |
1354 | ||
540e732c | 1355 | static void skl_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1356 | struct intel_crtc_state *pipe_config) |
540e732c | 1357 | { |
fac5e23e | 1358 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
540e732c | 1359 | int link_clock = 0; |
2952cd6f RV |
1360 | uint32_t dpll_ctl1; |
1361 | enum intel_dpll_id pll_id; | |
540e732c | 1362 | |
2952cd6f | 1363 | pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); |
540e732c S |
1364 | |
1365 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
1366 | ||
2952cd6f RV |
1367 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) { |
1368 | link_clock = skl_calc_wrpll_link(dev_priv, pll_id); | |
540e732c | 1369 | } else { |
2952cd6f RV |
1370 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id); |
1371 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id); | |
540e732c S |
1372 | |
1373 | switch (link_clock) { | |
71cd8423 | 1374 | case DPLL_CTRL1_LINK_RATE_810: |
540e732c S |
1375 | link_clock = 81000; |
1376 | break; | |
71cd8423 | 1377 | case DPLL_CTRL1_LINK_RATE_1080: |
a8f3ef61 SJ |
1378 | link_clock = 108000; |
1379 | break; | |
71cd8423 | 1380 | case DPLL_CTRL1_LINK_RATE_1350: |
540e732c S |
1381 | link_clock = 135000; |
1382 | break; | |
71cd8423 | 1383 | case DPLL_CTRL1_LINK_RATE_1620: |
a8f3ef61 SJ |
1384 | link_clock = 162000; |
1385 | break; | |
71cd8423 | 1386 | case DPLL_CTRL1_LINK_RATE_2160: |
a8f3ef61 SJ |
1387 | link_clock = 216000; |
1388 | break; | |
71cd8423 | 1389 | case DPLL_CTRL1_LINK_RATE_2700: |
540e732c S |
1390 | link_clock = 270000; |
1391 | break; | |
1392 | default: | |
1393 | WARN(1, "Unsupported link rate\n"); | |
1394 | break; | |
1395 | } | |
1396 | link_clock *= 2; | |
1397 | } | |
1398 | ||
1399 | pipe_config->port_clock = link_clock; | |
1400 | ||
398a017e | 1401 | ddi_dotclock_get(pipe_config); |
540e732c S |
1402 | } |
1403 | ||
3d51278a | 1404 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1405 | struct intel_crtc_state *pipe_config) |
11578553 | 1406 | { |
fac5e23e | 1407 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
11578553 JB |
1408 | int link_clock = 0; |
1409 | u32 val, pll; | |
1410 | ||
c856052a | 1411 | val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); |
11578553 JB |
1412 | switch (val & PORT_CLK_SEL_MASK) { |
1413 | case PORT_CLK_SEL_LCPLL_810: | |
1414 | link_clock = 81000; | |
1415 | break; | |
1416 | case PORT_CLK_SEL_LCPLL_1350: | |
1417 | link_clock = 135000; | |
1418 | break; | |
1419 | case PORT_CLK_SEL_LCPLL_2700: | |
1420 | link_clock = 270000; | |
1421 | break; | |
1422 | case PORT_CLK_SEL_WRPLL1: | |
01403de3 | 1423 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
11578553 JB |
1424 | break; |
1425 | case PORT_CLK_SEL_WRPLL2: | |
01403de3 | 1426 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
11578553 JB |
1427 | break; |
1428 | case PORT_CLK_SEL_SPLL: | |
1429 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
1430 | if (pll == SPLL_PLL_FREQ_810MHz) | |
1431 | link_clock = 81000; | |
1432 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
1433 | link_clock = 135000; | |
1434 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
1435 | link_clock = 270000; | |
1436 | else { | |
1437 | WARN(1, "bad spll freq\n"); | |
1438 | return; | |
1439 | } | |
1440 | break; | |
1441 | default: | |
1442 | WARN(1, "bad port clock sel\n"); | |
1443 | return; | |
1444 | } | |
1445 | ||
1446 | pipe_config->port_clock = link_clock * 2; | |
1447 | ||
398a017e | 1448 | ddi_dotclock_get(pipe_config); |
11578553 JB |
1449 | } |
1450 | ||
977bb38d | 1451 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
2952cd6f | 1452 | enum intel_dpll_id pll_id) |
977bb38d | 1453 | { |
aa610dcb ID |
1454 | struct intel_shared_dpll *pll; |
1455 | struct intel_dpll_hw_state *state; | |
9e2c8475 | 1456 | struct dpll clock; |
aa610dcb ID |
1457 | |
1458 | /* For DDI ports we always use a shared PLL. */ | |
2952cd6f | 1459 | if (WARN_ON(pll_id == DPLL_ID_PRIVATE)) |
aa610dcb ID |
1460 | return 0; |
1461 | ||
2952cd6f | 1462 | pll = &dev_priv->shared_dplls[pll_id]; |
2c42e535 | 1463 | state = &pll->state.hw_state; |
aa610dcb ID |
1464 | |
1465 | clock.m1 = 2; | |
1466 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; | |
1467 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) | |
1468 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; | |
1469 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; | |
1470 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; | |
1471 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; | |
1472 | ||
1473 | return chv_calc_dpll_params(100000, &clock); | |
977bb38d S |
1474 | } |
1475 | ||
1476 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
1477 | struct intel_crtc_state *pipe_config) | |
1478 | { | |
fac5e23e | 1479 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
977bb38d | 1480 | enum port port = intel_ddi_get_encoder_port(encoder); |
2952cd6f | 1481 | enum intel_dpll_id pll_id = port; |
977bb38d | 1482 | |
2952cd6f | 1483 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, pll_id); |
977bb38d | 1484 | |
398a017e | 1485 | ddi_dotclock_get(pipe_config); |
977bb38d S |
1486 | } |
1487 | ||
3d51278a | 1488 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1489 | struct intel_crtc_state *pipe_config) |
3d51278a | 1490 | { |
0853723b | 1491 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22606a18 | 1492 | |
0853723b | 1493 | if (INTEL_GEN(dev_priv) <= 8) |
22606a18 | 1494 | hsw_ddi_clock_get(encoder, pipe_config); |
b976dc53 | 1495 | else if (IS_GEN9_BC(dev_priv)) |
22606a18 | 1496 | skl_ddi_clock_get(encoder, pipe_config); |
cc3f90f0 | 1497 | else if (IS_GEN9_LP(dev_priv)) |
977bb38d | 1498 | bxt_ddi_clock_get(encoder, pipe_config); |
a9701a89 RV |
1499 | else if (IS_CANNONLAKE(dev_priv)) |
1500 | cnl_ddi_clock_get(encoder, pipe_config); | |
3d51278a DV |
1501 | } |
1502 | ||
3dc38eea | 1503 | void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) |
dae84799 | 1504 | { |
3dc38eea | 1505 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
e9ce1a62 | 1506 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1524e93e | 1507 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
3dc38eea | 1508 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1524e93e | 1509 | int type = encoder->type; |
dae84799 PZ |
1510 | uint32_t temp; |
1511 | ||
cca0502b | 1512 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
4d1de975 JN |
1513 | WARN_ON(transcoder_is_dsi(cpu_transcoder)); |
1514 | ||
c9809791 | 1515 | temp = TRANS_MSA_SYNC_CLK; |
3dc38eea | 1516 | switch (crtc_state->pipe_bpp) { |
dae84799 | 1517 | case 18: |
c9809791 | 1518 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
1519 | break; |
1520 | case 24: | |
c9809791 | 1521 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
1522 | break; |
1523 | case 30: | |
c9809791 | 1524 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
1525 | break; |
1526 | case 36: | |
c9809791 | 1527 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
1528 | break; |
1529 | default: | |
4e53c2e0 | 1530 | BUG(); |
dae84799 | 1531 | } |
c9809791 | 1532 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1533 | } |
1534 | } | |
1535 | ||
3dc38eea ACO |
1536 | void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, |
1537 | bool state) | |
0e32b39c | 1538 | { |
3dc38eea | 1539 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
e9ce1a62 | 1540 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
3dc38eea | 1541 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
0e32b39c DA |
1542 | uint32_t temp; |
1543 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1544 | if (state == true) | |
1545 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1546 | else | |
1547 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1548 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1549 | } | |
1550 | ||
3dc38eea | 1551 | void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) |
8d9ddbcb | 1552 | { |
3dc38eea | 1553 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
1524e93e | 1554 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
e9ce1a62 ACO |
1555 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1556 | enum pipe pipe = crtc->pipe; | |
3dc38eea | 1557 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1524e93e SS |
1558 | enum port port = intel_ddi_get_encoder_port(encoder); |
1559 | int type = encoder->type; | |
8d9ddbcb PZ |
1560 | uint32_t temp; |
1561 | ||
ad80a810 PZ |
1562 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1563 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 1564 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 1565 | |
3dc38eea | 1566 | switch (crtc_state->pipe_bpp) { |
dfcef252 | 1567 | case 18: |
ad80a810 | 1568 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1569 | break; |
1570 | case 24: | |
ad80a810 | 1571 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1572 | break; |
1573 | case 30: | |
ad80a810 | 1574 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1575 | break; |
1576 | case 36: | |
ad80a810 | 1577 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1578 | break; |
1579 | default: | |
4e53c2e0 | 1580 | BUG(); |
dfcef252 | 1581 | } |
72662e10 | 1582 | |
3dc38eea | 1583 | if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1584 | temp |= TRANS_DDI_PVSYNC; |
3dc38eea | 1585 | if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1586 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1587 | |
e6f0bfc4 PZ |
1588 | if (cpu_transcoder == TRANSCODER_EDP) { |
1589 | switch (pipe) { | |
1590 | case PIPE_A: | |
c7670b10 PZ |
1591 | /* On Haswell, can only use the always-on power well for |
1592 | * eDP when not using the panel fitter, and when not | |
1593 | * using motion blur mitigation (which we don't | |
1594 | * support). */ | |
772c2a51 | 1595 | if (IS_HASWELL(dev_priv) && |
3dc38eea ACO |
1596 | (crtc_state->pch_pfit.enabled || |
1597 | crtc_state->pch_pfit.force_thru)) | |
d6dd9eb1 DV |
1598 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1599 | else | |
1600 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1601 | break; |
1602 | case PIPE_B: | |
1603 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1604 | break; | |
1605 | case PIPE_C: | |
1606 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1607 | break; | |
1608 | default: | |
1609 | BUG(); | |
1610 | break; | |
1611 | } | |
1612 | } | |
1613 | ||
7739c33b | 1614 | if (type == INTEL_OUTPUT_HDMI) { |
3dc38eea | 1615 | if (crtc_state->has_hdmi_sink) |
ad80a810 | 1616 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1617 | else |
ad80a810 | 1618 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
15953637 SS |
1619 | |
1620 | if (crtc_state->hdmi_scrambling) | |
1621 | temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK; | |
1622 | if (crtc_state->hdmi_high_tmds_clock_ratio) | |
1623 | temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; | |
7739c33b | 1624 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1625 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
3dc38eea | 1626 | temp |= (crtc_state->fdi_lanes - 1) << 1; |
cca0502b | 1627 | } else if (type == INTEL_OUTPUT_DP || |
7739c33b | 1628 | type == INTEL_OUTPUT_EDP) { |
64ee2fd2 | 1629 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
3dc38eea | 1630 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count); |
0e32b39c | 1631 | } else if (type == INTEL_OUTPUT_DP_MST) { |
64ee2fd2 | 1632 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
3dc38eea | 1633 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count); |
8d9ddbcb | 1634 | } else { |
84f44ce7 | 1635 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1524e93e | 1636 | encoder->type, pipe_name(pipe)); |
8d9ddbcb PZ |
1637 | } |
1638 | ||
ad80a810 | 1639 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1640 | } |
72662e10 | 1641 | |
ad80a810 PZ |
1642 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1643 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1644 | { |
f0f59a00 | 1645 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1646 | uint32_t val = I915_READ(reg); |
1647 | ||
0e32b39c | 1648 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 1649 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 1650 | I915_WRITE(reg, val); |
72662e10 ED |
1651 | } |
1652 | ||
bcbc889b PZ |
1653 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1654 | { | |
1655 | struct drm_device *dev = intel_connector->base.dev; | |
fac5e23e | 1656 | struct drm_i915_private *dev_priv = to_i915(dev); |
1524e93e | 1657 | struct intel_encoder *encoder = intel_connector->encoder; |
bcbc889b | 1658 | int type = intel_connector->base.connector_type; |
1524e93e | 1659 | enum port port = intel_ddi_get_encoder_port(encoder); |
bcbc889b PZ |
1660 | enum pipe pipe = 0; |
1661 | enum transcoder cpu_transcoder; | |
1662 | uint32_t tmp; | |
e27daab4 | 1663 | bool ret; |
bcbc889b | 1664 | |
79f255a0 | 1665 | if (!intel_display_power_get_if_enabled(dev_priv, |
1524e93e | 1666 | encoder->power_domain)) |
882244a3 PZ |
1667 | return false; |
1668 | ||
1524e93e | 1669 | if (!encoder->get_hw_state(encoder, &pipe)) { |
e27daab4 ID |
1670 | ret = false; |
1671 | goto out; | |
1672 | } | |
bcbc889b PZ |
1673 | |
1674 | if (port == PORT_A) | |
1675 | cpu_transcoder = TRANSCODER_EDP; | |
1676 | else | |
1a240d4d | 1677 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1678 | |
1679 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1680 | ||
1681 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1682 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1683 | case TRANS_DDI_MODE_SELECT_DVI: | |
e27daab4 ID |
1684 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
1685 | break; | |
bcbc889b PZ |
1686 | |
1687 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
e27daab4 ID |
1688 | ret = type == DRM_MODE_CONNECTOR_eDP || |
1689 | type == DRM_MODE_CONNECTOR_DisplayPort; | |
1690 | break; | |
1691 | ||
0e32b39c DA |
1692 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1693 | /* if the transcoder is in MST state then | |
1694 | * connector isn't connected */ | |
e27daab4 ID |
1695 | ret = false; |
1696 | break; | |
bcbc889b PZ |
1697 | |
1698 | case TRANS_DDI_MODE_SELECT_FDI: | |
e27daab4 ID |
1699 | ret = type == DRM_MODE_CONNECTOR_VGA; |
1700 | break; | |
bcbc889b PZ |
1701 | |
1702 | default: | |
e27daab4 ID |
1703 | ret = false; |
1704 | break; | |
bcbc889b | 1705 | } |
e27daab4 ID |
1706 | |
1707 | out: | |
1524e93e | 1708 | intel_display_power_put(dev_priv, encoder->power_domain); |
e27daab4 ID |
1709 | |
1710 | return ret; | |
bcbc889b PZ |
1711 | } |
1712 | ||
85234cdc DV |
1713 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1714 | enum pipe *pipe) | |
1715 | { | |
1716 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1717 | struct drm_i915_private *dev_priv = to_i915(dev); |
fe43d3f5 | 1718 | enum port port = intel_ddi_get_encoder_port(encoder); |
85234cdc DV |
1719 | u32 tmp; |
1720 | int i; | |
e27daab4 | 1721 | bool ret; |
85234cdc | 1722 | |
79f255a0 ACO |
1723 | if (!intel_display_power_get_if_enabled(dev_priv, |
1724 | encoder->power_domain)) | |
6d129bea ID |
1725 | return false; |
1726 | ||
e27daab4 ID |
1727 | ret = false; |
1728 | ||
fe43d3f5 | 1729 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1730 | |
1731 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
e27daab4 | 1732 | goto out; |
85234cdc | 1733 | |
ad80a810 PZ |
1734 | if (port == PORT_A) { |
1735 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1736 | |
ad80a810 PZ |
1737 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1738 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1739 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1740 | *pipe = PIPE_A; | |
1741 | break; | |
1742 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1743 | *pipe = PIPE_B; | |
1744 | break; | |
1745 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1746 | *pipe = PIPE_C; | |
1747 | break; | |
1748 | } | |
1749 | ||
e27daab4 | 1750 | ret = true; |
ad80a810 | 1751 | |
e27daab4 ID |
1752 | goto out; |
1753 | } | |
0e32b39c | 1754 | |
e27daab4 ID |
1755 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
1756 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1757 | ||
1758 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { | |
1759 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == | |
1760 | TRANS_DDI_MODE_SELECT_DP_MST) | |
1761 | goto out; | |
1762 | ||
1763 | *pipe = i; | |
1764 | ret = true; | |
1765 | ||
1766 | goto out; | |
85234cdc DV |
1767 | } |
1768 | } | |
1769 | ||
84f44ce7 | 1770 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1771 | |
e27daab4 | 1772 | out: |
cc3f90f0 | 1773 | if (ret && IS_GEN9_LP(dev_priv)) { |
e93da0a0 | 1774 | tmp = I915_READ(BXT_PHY_CTL(port)); |
e19c1eb8 ID |
1775 | if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | |
1776 | BXT_PHY_LANE_POWERDOWN_ACK | | |
e93da0a0 ID |
1777 | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) |
1778 | DRM_ERROR("Port %c enabled but PHY powered down? " | |
1779 | "(PHY_CTL %08x)\n", port_name(port), tmp); | |
1780 | } | |
1781 | ||
79f255a0 | 1782 | intel_display_power_put(dev_priv, encoder->power_domain); |
e27daab4 ID |
1783 | |
1784 | return ret; | |
85234cdc DV |
1785 | } |
1786 | ||
62b69566 ACO |
1787 | static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder) |
1788 | { | |
1789 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
1790 | enum pipe pipe; | |
1791 | ||
1792 | if (intel_ddi_get_hw_state(encoder, &pipe)) | |
1793 | return BIT_ULL(dig_port->ddi_io_power_domain); | |
1794 | ||
1795 | return 0; | |
1796 | } | |
1797 | ||
3dc38eea | 1798 | void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) |
fc914639 | 1799 | { |
3dc38eea | 1800 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
e9ce1a62 | 1801 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1524e93e SS |
1802 | struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); |
1803 | enum port port = intel_ddi_get_encoder_port(encoder); | |
3dc38eea | 1804 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc914639 | 1805 | |
bb523fc0 PZ |
1806 | if (cpu_transcoder != TRANSCODER_EDP) |
1807 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1808 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1809 | } |
1810 | ||
3dc38eea | 1811 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) |
fc914639 | 1812 | { |
3dc38eea ACO |
1813 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
1814 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
fc914639 | 1815 | |
bb523fc0 PZ |
1816 | if (cpu_transcoder != TRANSCODER_EDP) |
1817 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1818 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1819 | } |
1820 | ||
a7d8dbc0 VS |
1821 | static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
1822 | enum port port, uint8_t iboost) | |
f8896f5d | 1823 | { |
a7d8dbc0 VS |
1824 | u32 tmp; |
1825 | ||
1826 | tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); | |
1827 | tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); | |
1828 | if (iboost) | |
1829 | tmp |= iboost << BALANCE_LEG_SHIFT(port); | |
1830 | else | |
1831 | tmp |= BALANCE_LEG_DISABLE(port); | |
1832 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); | |
1833 | } | |
1834 | ||
081dfcfa VS |
1835 | static void skl_ddi_set_iboost(struct intel_encoder *encoder, |
1836 | int level, enum intel_output_type type) | |
a7d8dbc0 VS |
1837 | { |
1838 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
1839 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); | |
1840 | enum port port = intel_dig_port->port; | |
f8896f5d | 1841 | uint8_t iboost; |
f8896f5d | 1842 | |
081dfcfa VS |
1843 | if (type == INTEL_OUTPUT_HDMI) |
1844 | iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; | |
1845 | else | |
1846 | iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; | |
75067dde | 1847 | |
081dfcfa VS |
1848 | if (iboost == 0) { |
1849 | const struct ddi_buf_trans *ddi_translations; | |
1850 | int n_entries; | |
1851 | ||
1852 | if (type == INTEL_OUTPUT_HDMI) | |
1853 | ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); | |
1854 | else if (type == INTEL_OUTPUT_EDP) | |
edba48fd | 1855 | ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); |
081dfcfa | 1856 | else |
edba48fd | 1857 | ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); |
10afa0b6 | 1858 | |
21b39d2a VS |
1859 | if (WARN_ON_ONCE(!ddi_translations)) |
1860 | return; | |
1861 | if (WARN_ON_ONCE(level >= n_entries)) | |
1862 | level = n_entries - 1; | |
1863 | ||
081dfcfa | 1864 | iboost = ddi_translations[level].i_boost; |
f8896f5d DW |
1865 | } |
1866 | ||
1867 | /* Make sure that the requested I_boost is valid */ | |
1868 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { | |
1869 | DRM_ERROR("Invalid I_boost value %u\n", iboost); | |
1870 | return; | |
1871 | } | |
1872 | ||
a7d8dbc0 | 1873 | _skl_ddi_set_iboost(dev_priv, port, iboost); |
f8896f5d | 1874 | |
a7d8dbc0 VS |
1875 | if (port == PORT_A && intel_dig_port->max_lanes == 4) |
1876 | _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); | |
f8896f5d DW |
1877 | } |
1878 | ||
7d4f37b5 VS |
1879 | static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, |
1880 | int level, enum intel_output_type type) | |
96fb9f9b | 1881 | { |
7d4f37b5 | 1882 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
96fb9f9b | 1883 | const struct bxt_ddi_buf_trans *ddi_translations; |
7d4f37b5 | 1884 | enum port port = encoder->port; |
043eaf36 | 1885 | int n_entries; |
7d4f37b5 VS |
1886 | |
1887 | if (type == INTEL_OUTPUT_HDMI) | |
1888 | ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); | |
1889 | else if (type == INTEL_OUTPUT_EDP) | |
1890 | ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); | |
1891 | else | |
1892 | ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); | |
96fb9f9b | 1893 | |
21b39d2a VS |
1894 | if (WARN_ON_ONCE(!ddi_translations)) |
1895 | return; | |
1896 | if (WARN_ON_ONCE(level >= n_entries)) | |
1897 | level = n_entries - 1; | |
1898 | ||
b6e08203 ACO |
1899 | bxt_ddi_phy_set_signal_level(dev_priv, port, |
1900 | ddi_translations[level].margin, | |
1901 | ddi_translations[level].scale, | |
1902 | ddi_translations[level].enable, | |
1903 | ddi_translations[level].deemphasis); | |
96fb9f9b VK |
1904 | } |
1905 | ||
ffe5111e VS |
1906 | u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) |
1907 | { | |
1908 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
edba48fd | 1909 | enum port port = encoder->port; |
ffe5111e VS |
1910 | int n_entries; |
1911 | ||
5fcf34b1 RV |
1912 | if (IS_CANNONLAKE(dev_priv)) { |
1913 | if (encoder->type == INTEL_OUTPUT_EDP) | |
1914 | cnl_get_buf_trans_edp(dev_priv, &n_entries); | |
1915 | else | |
1916 | cnl_get_buf_trans_dp(dev_priv, &n_entries); | |
7d4f37b5 VS |
1917 | } else if (IS_GEN9_LP(dev_priv)) { |
1918 | if (encoder->type == INTEL_OUTPUT_EDP) | |
1919 | bxt_get_buf_trans_edp(dev_priv, &n_entries); | |
1920 | else | |
1921 | bxt_get_buf_trans_dp(dev_priv, &n_entries); | |
5fcf34b1 RV |
1922 | } else { |
1923 | if (encoder->type == INTEL_OUTPUT_EDP) | |
edba48fd | 1924 | intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); |
5fcf34b1 | 1925 | else |
edba48fd | 1926 | intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); |
5fcf34b1 | 1927 | } |
ffe5111e VS |
1928 | |
1929 | if (WARN_ON(n_entries < 1)) | |
1930 | n_entries = 1; | |
1931 | if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) | |
1932 | n_entries = ARRAY_SIZE(index_to_dp_signal_levels); | |
1933 | ||
1934 | return index_to_dp_signal_levels[n_entries - 1] & | |
1935 | DP_TRAIN_VOLTAGE_SWING_MASK; | |
1936 | } | |
1937 | ||
f3cf4ba4 VS |
1938 | static void cnl_ddi_vswing_program(struct intel_encoder *encoder, |
1939 | int level, enum intel_output_type type) | |
cf54ca8b | 1940 | { |
f3cf4ba4 VS |
1941 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1942 | enum port port = intel_ddi_get_encoder_port(encoder); | |
1943 | const struct cnl_ddi_buf_trans *ddi_translations; | |
1944 | int n_entries, ln; | |
1945 | u32 val; | |
cf54ca8b | 1946 | |
f3cf4ba4 | 1947 | if (type == INTEL_OUTPUT_HDMI) |
cc9cabfd | 1948 | ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); |
f3cf4ba4 | 1949 | else if (type == INTEL_OUTPUT_EDP) |
cc9cabfd | 1950 | ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); |
f3cf4ba4 VS |
1951 | else |
1952 | ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); | |
cf54ca8b | 1953 | |
21b39d2a | 1954 | if (WARN_ON_ONCE(!ddi_translations)) |
cf54ca8b | 1955 | return; |
21b39d2a | 1956 | if (WARN_ON_ONCE(level >= n_entries)) |
cf54ca8b | 1957 | level = n_entries - 1; |
cf54ca8b RV |
1958 | |
1959 | /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ | |
1960 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
1f588aeb | 1961 | val &= ~SCALING_MODE_SEL_MASK; |
cf54ca8b RV |
1962 | val |= SCALING_MODE_SEL(2); |
1963 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
1964 | ||
1965 | /* Program PORT_TX_DW2 */ | |
1966 | val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); | |
1f588aeb RV |
1967 | val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | |
1968 | RCOMP_SCALAR_MASK); | |
cf54ca8b RV |
1969 | val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); |
1970 | val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); | |
1971 | /* Rcomp scalar is fixed as 0x98 for every table entry */ | |
1972 | val |= RCOMP_SCALAR(0x98); | |
1973 | I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); | |
1974 | ||
20303eb4 | 1975 | /* Program PORT_TX_DW4 */ |
cf54ca8b RV |
1976 | /* We cannot write to GRP. It would overrite individual loadgen */ |
1977 | for (ln = 0; ln < 4; ln++) { | |
1978 | val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); | |
1f588aeb RV |
1979 | val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | |
1980 | CURSOR_COEFF_MASK); | |
cf54ca8b RV |
1981 | val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); |
1982 | val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); | |
1983 | val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); | |
1984 | I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); | |
1985 | } | |
1986 | ||
20303eb4 | 1987 | /* Program PORT_TX_DW5 */ |
cf54ca8b RV |
1988 | /* All DW5 values are fixed for every table entry */ |
1989 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
1f588aeb | 1990 | val &= ~RTERM_SELECT_MASK; |
cf54ca8b RV |
1991 | val |= RTERM_SELECT(6); |
1992 | val |= TAP3_DISABLE; | |
1993 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
1994 | ||
20303eb4 | 1995 | /* Program PORT_TX_DW7 */ |
cf54ca8b | 1996 | val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); |
1f588aeb | 1997 | val &= ~N_SCALAR_MASK; |
cf54ca8b RV |
1998 | val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); |
1999 | I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); | |
2000 | } | |
2001 | ||
f3cf4ba4 VS |
2002 | static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, |
2003 | int level, enum intel_output_type type) | |
cf54ca8b | 2004 | { |
0091abc3 | 2005 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0091abc3 | 2006 | enum port port = intel_ddi_get_encoder_port(encoder); |
f3cf4ba4 | 2007 | int width, rate, ln; |
cf54ca8b | 2008 | u32 val; |
0091abc3 | 2009 | |
f3cf4ba4 | 2010 | if (type == INTEL_OUTPUT_HDMI) { |
0091abc3 | 2011 | width = 4; |
f3cf4ba4 | 2012 | rate = 0; /* Rate is always < than 6GHz for HDMI */ |
61f3e770 | 2013 | } else { |
f3cf4ba4 VS |
2014 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2015 | ||
2016 | width = intel_dp->lane_count; | |
2017 | rate = intel_dp->link_rate; | |
0091abc3 | 2018 | } |
cf54ca8b RV |
2019 | |
2020 | /* | |
2021 | * 1. If port type is eDP or DP, | |
2022 | * set PORT_PCS_DW1 cmnkeeper_enable to 1b, | |
2023 | * else clear to 0b. | |
2024 | */ | |
2025 | val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); | |
f3cf4ba4 | 2026 | if (type != INTEL_OUTPUT_HDMI) |
cf54ca8b RV |
2027 | val |= COMMON_KEEPER_EN; |
2028 | else | |
2029 | val &= ~COMMON_KEEPER_EN; | |
2030 | I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); | |
2031 | ||
2032 | /* 2. Program loadgen select */ | |
2033 | /* | |
0091abc3 CT |
2034 | * Program PORT_TX_DW4_LN depending on Bit rate and used lanes |
2035 | * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) | |
2036 | * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) | |
2037 | * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) | |
cf54ca8b | 2038 | */ |
0091abc3 CT |
2039 | for (ln = 0; ln <= 3; ln++) { |
2040 | val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); | |
2041 | val &= ~LOADGEN_SELECT; | |
2042 | ||
a8e45a1c NM |
2043 | if ((rate <= 600000 && width == 4 && ln >= 1) || |
2044 | (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { | |
0091abc3 CT |
2045 | val |= LOADGEN_SELECT; |
2046 | } | |
2047 | I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); | |
2048 | } | |
cf54ca8b RV |
2049 | |
2050 | /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ | |
2051 | val = I915_READ(CNL_PORT_CL1CM_DW5); | |
2052 | val |= SUS_CLOCK_CONFIG; | |
2053 | I915_WRITE(CNL_PORT_CL1CM_DW5, val); | |
2054 | ||
2055 | /* 4. Clear training enable to change swing values */ | |
2056 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
2057 | val &= ~TX_TRAINING_EN; | |
2058 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
2059 | ||
2060 | /* 5. Program swing and de-emphasis */ | |
f3cf4ba4 | 2061 | cnl_ddi_vswing_program(encoder, level, type); |
cf54ca8b RV |
2062 | |
2063 | /* 6. Set training enable to trigger update */ | |
2064 | val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); | |
2065 | val |= TX_TRAINING_EN; | |
2066 | I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); | |
2067 | } | |
2068 | ||
f8896f5d DW |
2069 | static uint32_t translate_signal_level(int signal_levels) |
2070 | { | |
97eeb872 | 2071 | int i; |
f8896f5d | 2072 | |
97eeb872 VS |
2073 | for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { |
2074 | if (index_to_dp_signal_levels[i] == signal_levels) | |
2075 | return i; | |
f8896f5d DW |
2076 | } |
2077 | ||
97eeb872 VS |
2078 | WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", |
2079 | signal_levels); | |
2080 | ||
2081 | return 0; | |
f8896f5d DW |
2082 | } |
2083 | ||
1b6e2fd2 RV |
2084 | static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp) |
2085 | { | |
2086 | uint8_t train_set = intel_dp->train_set[0]; | |
2087 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2088 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2089 | ||
2090 | return translate_signal_level(signal_levels); | |
2091 | } | |
2092 | ||
d509af6c | 2093 | u32 bxt_signal_levels(struct intel_dp *intel_dp) |
f8896f5d DW |
2094 | { |
2095 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
78ab0bae | 2096 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
f8896f5d | 2097 | struct intel_encoder *encoder = &dport->base; |
d02ace87 | 2098 | int level = intel_ddi_dp_level(intel_dp); |
d509af6c RV |
2099 | |
2100 | if (IS_CANNONLAKE(dev_priv)) | |
f3cf4ba4 | 2101 | cnl_ddi_vswing_sequence(encoder, level, encoder->type); |
d509af6c | 2102 | else |
7d4f37b5 | 2103 | bxt_ddi_vswing_sequence(encoder, level, encoder->type); |
d509af6c RV |
2104 | |
2105 | return 0; | |
2106 | } | |
2107 | ||
2108 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) | |
2109 | { | |
2110 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2111 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
2112 | struct intel_encoder *encoder = &dport->base; | |
d02ace87 | 2113 | int level = intel_ddi_dp_level(intel_dp); |
f8896f5d | 2114 | |
b976dc53 | 2115 | if (IS_GEN9_BC(dev_priv)) |
081dfcfa | 2116 | skl_ddi_set_iboost(encoder, level, encoder->type); |
d509af6c | 2117 | |
f8896f5d DW |
2118 | return DDI_BUF_TRANS_SELECT(level); |
2119 | } | |
2120 | ||
d7c530b2 | 2121 | static void intel_ddi_clk_select(struct intel_encoder *encoder, |
5f88a9c6 | 2122 | const struct intel_shared_dpll *pll) |
6441ab5f | 2123 | { |
e404ba8d VS |
2124 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2125 | enum port port = intel_ddi_get_encoder_port(encoder); | |
555e38d2 | 2126 | uint32_t val; |
6441ab5f | 2127 | |
c856052a ACO |
2128 | if (WARN_ON(!pll)) |
2129 | return; | |
2130 | ||
a4ffdc2b RV |
2131 | mutex_lock(&dev_priv->dpll_lock); |
2132 | ||
555e38d2 RV |
2133 | if (IS_CANNONLAKE(dev_priv)) { |
2134 | /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ | |
2135 | val = I915_READ(DPCLKA_CFGCR0); | |
46442bee | 2136 | val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); |
555e38d2 RV |
2137 | val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port); |
2138 | I915_WRITE(DPCLKA_CFGCR0, val); | |
efa80add | 2139 | |
555e38d2 RV |
2140 | /* |
2141 | * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. | |
2142 | * This step and the step before must be done with separate | |
2143 | * register writes. | |
2144 | */ | |
2145 | val = I915_READ(DPCLKA_CFGCR0); | |
87145d95 | 2146 | val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); |
555e38d2 RV |
2147 | I915_WRITE(DPCLKA_CFGCR0, val); |
2148 | } else if (IS_GEN9_BC(dev_priv)) { | |
5416d871 | 2149 | /* DDI -> PLL mapping */ |
efa80add S |
2150 | val = I915_READ(DPLL_CTRL2); |
2151 | ||
2152 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
2153 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); | |
c856052a | 2154 | val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) | |
efa80add S |
2155 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
2156 | ||
2157 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 2158 | |
e404ba8d | 2159 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
c856052a | 2160 | I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); |
efa80add | 2161 | } |
a4ffdc2b RV |
2162 | |
2163 | mutex_unlock(&dev_priv->dpll_lock); | |
e404ba8d VS |
2164 | } |
2165 | ||
6b8506d5 VS |
2166 | static void intel_ddi_clk_disable(struct intel_encoder *encoder) |
2167 | { | |
2168 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2169 | enum port port = intel_ddi_get_encoder_port(encoder); | |
2170 | ||
2171 | if (IS_CANNONLAKE(dev_priv)) | |
2172 | I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | | |
2173 | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); | |
2174 | else if (IS_GEN9_BC(dev_priv)) | |
2175 | I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | | |
2176 | DPLL_CTRL2_DDI_CLK_OFF(port)); | |
2177 | else if (INTEL_GEN(dev_priv) < 9) | |
2178 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); | |
2179 | } | |
2180 | ||
ba88d153 | 2181 | static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, |
45e0327e VS |
2182 | const struct intel_crtc_state *crtc_state, |
2183 | const struct drm_connector_state *conn_state) | |
e404ba8d | 2184 | { |
ba88d153 MN |
2185 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2186 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2187 | enum port port = intel_ddi_get_encoder_port(encoder); | |
62b69566 | 2188 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
45e0327e | 2189 | bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); |
d02ace87 | 2190 | int level = intel_ddi_dp_level(intel_dp); |
b2ccb822 | 2191 | |
45e0327e | 2192 | WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); |
e081c846 | 2193 | |
45e0327e VS |
2194 | intel_dp_set_link_params(intel_dp, crtc_state->port_clock, |
2195 | crtc_state->lane_count, is_mst); | |
680b71c2 VS |
2196 | |
2197 | intel_edp_panel_on(intel_dp); | |
32bdc400 | 2198 | |
45e0327e | 2199 | intel_ddi_clk_select(encoder, crtc_state->shared_dpll); |
62b69566 ACO |
2200 | |
2201 | intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); | |
2202 | ||
381f9570 | 2203 | if (IS_CANNONLAKE(dev_priv)) |
f3cf4ba4 | 2204 | cnl_ddi_vswing_sequence(encoder, level, encoder->type); |
381f9570 | 2205 | else if (IS_GEN9_LP(dev_priv)) |
7d4f37b5 | 2206 | bxt_ddi_vswing_sequence(encoder, level, encoder->type); |
381f9570 | 2207 | else |
2f7460a7 RV |
2208 | intel_prepare_dp_ddi_buffers(encoder); |
2209 | ||
ba88d153 | 2210 | intel_ddi_init_dp_buf_reg(encoder); |
45e0327e | 2211 | if (!is_mst) |
5ea2355a | 2212 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
ba88d153 MN |
2213 | intel_dp_start_link_train(intel_dp); |
2214 | if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) | |
2215 | intel_dp_stop_link_train(intel_dp); | |
2216 | } | |
901c2daf | 2217 | |
ba88d153 | 2218 | static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, |
ac240288 | 2219 | const struct intel_crtc_state *crtc_state, |
45e0327e | 2220 | const struct drm_connector_state *conn_state) |
ba88d153 | 2221 | { |
f99be1b3 VS |
2222 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
2223 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
ba88d153 | 2224 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ba88d153 MN |
2225 | enum port port = intel_ddi_get_encoder_port(encoder); |
2226 | int level = intel_ddi_hdmi_level(dev_priv, port); | |
62b69566 | 2227 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); |
c19b0669 | 2228 | |
ba88d153 | 2229 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
45e0327e | 2230 | intel_ddi_clk_select(encoder, crtc_state->shared_dpll); |
62b69566 ACO |
2231 | |
2232 | intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); | |
2233 | ||
2f7460a7 | 2234 | if (IS_CANNONLAKE(dev_priv)) |
f3cf4ba4 | 2235 | cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); |
cc3f90f0 | 2236 | else if (IS_GEN9_LP(dev_priv)) |
7d4f37b5 | 2237 | bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); |
2f7460a7 | 2238 | else |
7ea79333 | 2239 | intel_prepare_hdmi_ddi_buffers(encoder, level); |
2f7460a7 RV |
2240 | |
2241 | if (IS_GEN9_BC(dev_priv)) | |
081dfcfa | 2242 | skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); |
8d8bb85e | 2243 | |
f99be1b3 | 2244 | intel_dig_port->set_infoframes(&encoder->base, |
45e0327e | 2245 | crtc_state->has_infoframe, |
f99be1b3 | 2246 | crtc_state, conn_state); |
ba88d153 | 2247 | } |
32bdc400 | 2248 | |
1524e93e | 2249 | static void intel_ddi_pre_enable(struct intel_encoder *encoder, |
45e0327e | 2250 | const struct intel_crtc_state *crtc_state, |
5f88a9c6 | 2251 | const struct drm_connector_state *conn_state) |
ba88d153 | 2252 | { |
45e0327e VS |
2253 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
2254 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
2255 | enum pipe pipe = crtc->pipe; | |
30cf6db8 | 2256 | |
45e0327e | 2257 | WARN_ON(crtc_state->has_pch_encoder); |
364a3fe1 JN |
2258 | |
2259 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
2260 | ||
45e0327e VS |
2261 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
2262 | intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); | |
2263 | else | |
2264 | intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); | |
6441ab5f PZ |
2265 | } |
2266 | ||
e725f645 VS |
2267 | static void intel_disable_ddi_buf(struct intel_encoder *encoder) |
2268 | { | |
2269 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2270 | enum port port = intel_ddi_get_encoder_port(encoder); | |
2271 | bool wait = false; | |
2272 | u32 val; | |
2273 | ||
2274 | val = I915_READ(DDI_BUF_CTL(port)); | |
2275 | if (val & DDI_BUF_CTL_ENABLE) { | |
2276 | val &= ~DDI_BUF_CTL_ENABLE; | |
2277 | I915_WRITE(DDI_BUF_CTL(port), val); | |
2278 | wait = true; | |
2279 | } | |
2280 | ||
2281 | val = I915_READ(DP_TP_CTL(port)); | |
2282 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
2283 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2284 | I915_WRITE(DP_TP_CTL(port), val); | |
2285 | ||
2286 | if (wait) | |
2287 | intel_wait_ddi_buf_idle(dev_priv, port); | |
2288 | } | |
2289 | ||
f45f3da7 VS |
2290 | static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, |
2291 | const struct intel_crtc_state *old_crtc_state, | |
2292 | const struct drm_connector_state *old_conn_state) | |
6441ab5f | 2293 | { |
f45f3da7 VS |
2294 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2295 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
2296 | struct intel_dp *intel_dp = &dig_port->dp; | |
2297 | /* | |
2298 | * old_crtc_state and old_conn_state are NULL when called from | |
2299 | * DP_MST. The main connector associated with this port is never | |
2300 | * bound to a crtc for MST. | |
2301 | */ | |
2302 | bool is_mst = !old_crtc_state; | |
2886e93f | 2303 | |
f45f3da7 VS |
2304 | /* |
2305 | * Power down sink before disabling the port, otherwise we end | |
2306 | * up getting interrupts from the sink on detecting link loss. | |
2307 | */ | |
2308 | if (!is_mst) | |
2309 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); | |
c5f93fcf | 2310 | |
f45f3da7 | 2311 | intel_disable_ddi_buf(encoder); |
7618138d | 2312 | |
f45f3da7 VS |
2313 | intel_edp_panel_vdd_on(intel_dp); |
2314 | intel_edp_panel_off(intel_dp); | |
a836bdf9 | 2315 | |
f45f3da7 | 2316 | intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain); |
c5f93fcf | 2317 | |
f45f3da7 VS |
2318 | intel_ddi_clk_disable(encoder); |
2319 | } | |
c5f93fcf | 2320 | |
f45f3da7 VS |
2321 | static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, |
2322 | const struct intel_crtc_state *old_crtc_state, | |
2323 | const struct drm_connector_state *old_conn_state) | |
2324 | { | |
2325 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2326 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
2327 | struct intel_hdmi *intel_hdmi = &dig_port->hdmi; | |
82a4d9c0 | 2328 | |
f45f3da7 | 2329 | intel_disable_ddi_buf(encoder); |
62b69566 | 2330 | |
f45f3da7 VS |
2331 | dig_port->set_infoframes(&encoder->base, false, |
2332 | old_crtc_state, old_conn_state); | |
b2ccb822 | 2333 | |
f45f3da7 | 2334 | intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain); |
b2ccb822 | 2335 | |
f45f3da7 VS |
2336 | intel_ddi_clk_disable(encoder); |
2337 | ||
2338 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
2339 | } | |
2340 | ||
2341 | static void intel_ddi_post_disable(struct intel_encoder *encoder, | |
2342 | const struct intel_crtc_state *old_crtc_state, | |
2343 | const struct drm_connector_state *old_conn_state) | |
2344 | { | |
2345 | /* | |
2346 | * old_crtc_state and old_conn_state are NULL when called from | |
2347 | * DP_MST. The main connector associated with this port is never | |
2348 | * bound to a crtc for MST. | |
2349 | */ | |
2350 | if (old_crtc_state && | |
2351 | intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) | |
2352 | intel_ddi_post_disable_hdmi(encoder, | |
2353 | old_crtc_state, old_conn_state); | |
2354 | else | |
2355 | intel_ddi_post_disable_dp(encoder, | |
2356 | old_crtc_state, old_conn_state); | |
6441ab5f PZ |
2357 | } |
2358 | ||
1524e93e | 2359 | void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2360 | const struct intel_crtc_state *old_crtc_state, |
2361 | const struct drm_connector_state *old_conn_state) | |
b7076546 | 2362 | { |
1524e93e | 2363 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7076546 ML |
2364 | uint32_t val; |
2365 | ||
2366 | /* | |
2367 | * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) | |
2368 | * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, | |
2369 | * step 13 is the correct place for it. Step 18 is where it was | |
2370 | * originally before the BUN. | |
2371 | */ | |
2372 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
2373 | val &= ~FDI_RX_ENABLE; | |
2374 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
2375 | ||
fb0bd3bd VS |
2376 | intel_disable_ddi_buf(encoder); |
2377 | intel_ddi_clk_disable(encoder); | |
b7076546 ML |
2378 | |
2379 | val = I915_READ(FDI_RX_MISC(PIPE_A)); | |
2380 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
2381 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
2382 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); | |
2383 | ||
2384 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
2385 | val &= ~FDI_PCDCLK; | |
2386 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
2387 | ||
2388 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
2389 | val &= ~FDI_RX_PLL_ENABLE; | |
2390 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
2391 | } | |
2392 | ||
15d05f0e VS |
2393 | static void intel_enable_ddi_dp(struct intel_encoder *encoder, |
2394 | const struct intel_crtc_state *crtc_state, | |
2395 | const struct drm_connector_state *conn_state) | |
72662e10 | 2396 | { |
15d05f0e VS |
2397 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2398 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2399 | enum port port = intel_ddi_get_encoder_port(encoder); | |
72662e10 | 2400 | |
15d05f0e VS |
2401 | if (port == PORT_A && INTEL_GEN(dev_priv) < 9) |
2402 | intel_dp_stop_link_train(intel_dp); | |
d6c50ff8 | 2403 | |
15d05f0e VS |
2404 | intel_edp_backlight_on(crtc_state, conn_state); |
2405 | intel_psr_enable(intel_dp, crtc_state); | |
2406 | intel_edp_drrs_enable(intel_dp, crtc_state); | |
3ab9c637 | 2407 | |
15d05f0e VS |
2408 | if (crtc_state->has_audio) |
2409 | intel_audio_codec_enable(encoder, crtc_state, conn_state); | |
2410 | } | |
2411 | ||
2412 | static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, | |
2413 | const struct intel_crtc_state *crtc_state, | |
2414 | const struct drm_connector_state *conn_state) | |
2415 | { | |
2416 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2417 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
2418 | enum port port = intel_ddi_get_encoder_port(encoder); | |
2419 | ||
2420 | intel_hdmi_handle_sink_scrambling(encoder, | |
2421 | conn_state->connector, | |
2422 | crtc_state->hdmi_high_tmds_clock_ratio, | |
2423 | crtc_state->hdmi_scrambling); | |
2424 | ||
2425 | /* In HDMI/DVI mode, the port width, and swing/emphasis values | |
2426 | * are ignored so nothing special needs to be done besides | |
2427 | * enabling the port. | |
2428 | */ | |
2429 | I915_WRITE(DDI_BUF_CTL(port), | |
2430 | dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); | |
7b9f35a6 | 2431 | |
15d05f0e VS |
2432 | if (crtc_state->has_audio) |
2433 | intel_audio_codec_enable(encoder, crtc_state, conn_state); | |
2434 | } | |
2435 | ||
2436 | static void intel_enable_ddi(struct intel_encoder *encoder, | |
2437 | const struct intel_crtc_state *crtc_state, | |
2438 | const struct drm_connector_state *conn_state) | |
2439 | { | |
2440 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
2441 | intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); | |
2442 | else | |
2443 | intel_enable_ddi_dp(encoder, crtc_state, conn_state); | |
5ab432ef DV |
2444 | } |
2445 | ||
33f083f0 VS |
2446 | static void intel_disable_ddi_dp(struct intel_encoder *encoder, |
2447 | const struct intel_crtc_state *old_crtc_state, | |
2448 | const struct drm_connector_state *old_conn_state) | |
5ab432ef | 2449 | { |
33f083f0 | 2450 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
d6c50ff8 | 2451 | |
37255d8d | 2452 | if (old_crtc_state->has_audio) |
33f083f0 | 2453 | intel_audio_codec_disable(encoder); |
2831d842 | 2454 | |
33f083f0 VS |
2455 | intel_edp_drrs_disable(intel_dp, old_crtc_state); |
2456 | intel_psr_disable(intel_dp, old_crtc_state); | |
2457 | intel_edp_backlight_off(old_conn_state); | |
2458 | } | |
15953637 | 2459 | |
33f083f0 VS |
2460 | static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, |
2461 | const struct intel_crtc_state *old_crtc_state, | |
2462 | const struct drm_connector_state *old_conn_state) | |
2463 | { | |
2464 | if (old_crtc_state->has_audio) | |
2465 | intel_audio_codec_disable(encoder); | |
d6c50ff8 | 2466 | |
33f083f0 VS |
2467 | intel_hdmi_handle_sink_scrambling(encoder, |
2468 | old_conn_state->connector, | |
2469 | false, false); | |
2470 | } | |
2471 | ||
2472 | static void intel_disable_ddi(struct intel_encoder *encoder, | |
2473 | const struct intel_crtc_state *old_crtc_state, | |
2474 | const struct drm_connector_state *old_conn_state) | |
2475 | { | |
2476 | if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) | |
2477 | intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); | |
2478 | else | |
2479 | intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); | |
72662e10 | 2480 | } |
79f689aa | 2481 | |
fd6bbda9 | 2482 | static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2483 | const struct intel_crtc_state *pipe_config, |
2484 | const struct drm_connector_state *conn_state) | |
95a7a2ae | 2485 | { |
3dc38eea | 2486 | uint8_t mask = pipe_config->lane_lat_optim_mask; |
95a7a2ae | 2487 | |
47a6bc61 | 2488 | bxt_ddi_phy_set_lane_optim_mask(encoder, mask); |
95a7a2ae ID |
2489 | } |
2490 | ||
ad64217b | 2491 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
c19b0669 | 2492 | { |
ad64217b ACO |
2493 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2494 | struct drm_i915_private *dev_priv = | |
2495 | to_i915(intel_dig_port->base.base.dev); | |
174edf1f | 2496 | enum port port = intel_dig_port->port; |
c19b0669 | 2497 | uint32_t val; |
f3e227df | 2498 | bool wait = false; |
c19b0669 PZ |
2499 | |
2500 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
2501 | val = I915_READ(DDI_BUF_CTL(port)); | |
2502 | if (val & DDI_BUF_CTL_ENABLE) { | |
2503 | val &= ~DDI_BUF_CTL_ENABLE; | |
2504 | I915_WRITE(DDI_BUF_CTL(port), val); | |
2505 | wait = true; | |
2506 | } | |
2507 | ||
2508 | val = I915_READ(DP_TP_CTL(port)); | |
2509 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
2510 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2511 | I915_WRITE(DP_TP_CTL(port), val); | |
2512 | POSTING_READ(DP_TP_CTL(port)); | |
2513 | ||
2514 | if (wait) | |
2515 | intel_wait_ddi_buf_idle(dev_priv, port); | |
2516 | } | |
2517 | ||
0e32b39c | 2518 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 2519 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
64ee2fd2 | 2520 | if (intel_dp->link_mst) |
0e32b39c DA |
2521 | val |= DP_TP_CTL_MODE_MST; |
2522 | else { | |
2523 | val |= DP_TP_CTL_MODE_SST; | |
2524 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2525 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
2526 | } | |
c19b0669 PZ |
2527 | I915_WRITE(DP_TP_CTL(port), val); |
2528 | POSTING_READ(DP_TP_CTL(port)); | |
2529 | ||
2530 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
2531 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
2532 | POSTING_READ(DDI_BUF_CTL(port)); | |
2533 | ||
2534 | udelay(600); | |
2535 | } | |
00c09d70 | 2536 | |
9935f7fa LY |
2537 | bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, |
2538 | struct intel_crtc *intel_crtc) | |
2539 | { | |
2540 | u32 temp; | |
2541 | ||
2542 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { | |
2543 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
2544 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) | |
2545 | return true; | |
2546 | } | |
2547 | return false; | |
2548 | } | |
2549 | ||
6801c18c | 2550 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 2551 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 2552 | { |
fac5e23e | 2553 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 | 2554 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
0cb09a97 | 2555 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
f99be1b3 | 2556 | struct intel_digital_port *intel_dig_port; |
045ac3b5 JB |
2557 | u32 temp, flags = 0; |
2558 | ||
4d1de975 JN |
2559 | /* XXX: DSI transcoder paranoia */ |
2560 | if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) | |
2561 | return; | |
2562 | ||
045ac3b5 JB |
2563 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
2564 | if (temp & TRANS_DDI_PHSYNC) | |
2565 | flags |= DRM_MODE_FLAG_PHSYNC; | |
2566 | else | |
2567 | flags |= DRM_MODE_FLAG_NHSYNC; | |
2568 | if (temp & TRANS_DDI_PVSYNC) | |
2569 | flags |= DRM_MODE_FLAG_PVSYNC; | |
2570 | else | |
2571 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2572 | ||
2d112de7 | 2573 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
2574 | |
2575 | switch (temp & TRANS_DDI_BPC_MASK) { | |
2576 | case TRANS_DDI_BPC_6: | |
2577 | pipe_config->pipe_bpp = 18; | |
2578 | break; | |
2579 | case TRANS_DDI_BPC_8: | |
2580 | pipe_config->pipe_bpp = 24; | |
2581 | break; | |
2582 | case TRANS_DDI_BPC_10: | |
2583 | pipe_config->pipe_bpp = 30; | |
2584 | break; | |
2585 | case TRANS_DDI_BPC_12: | |
2586 | pipe_config->pipe_bpp = 36; | |
2587 | break; | |
2588 | default: | |
2589 | break; | |
2590 | } | |
eb14cb74 VS |
2591 | |
2592 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
2593 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 2594 | pipe_config->has_hdmi_sink = true; |
f99be1b3 | 2595 | intel_dig_port = enc_to_dig_port(&encoder->base); |
bbd440fb | 2596 | |
f99be1b3 | 2597 | if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) |
bbd440fb | 2598 | pipe_config->has_infoframe = true; |
15953637 SS |
2599 | |
2600 | if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) == | |
2601 | TRANS_DDI_HDMI_SCRAMBLING_MASK) | |
2602 | pipe_config->hdmi_scrambling = true; | |
2603 | if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) | |
2604 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
d4d6279a | 2605 | /* fall through */ |
eb14cb74 | 2606 | case TRANS_DDI_MODE_SELECT_DVI: |
d4d6279a ACO |
2607 | pipe_config->lane_count = 4; |
2608 | break; | |
eb14cb74 VS |
2609 | case TRANS_DDI_MODE_SELECT_FDI: |
2610 | break; | |
2611 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
2612 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
90a6b7b0 VS |
2613 | pipe_config->lane_count = |
2614 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
eb14cb74 VS |
2615 | intel_dp_get_m_n(intel_crtc, pipe_config); |
2616 | break; | |
2617 | default: | |
2618 | break; | |
2619 | } | |
10214420 | 2620 | |
9935f7fa LY |
2621 | pipe_config->has_audio = |
2622 | intel_ddi_is_audio_enabled(dev_priv, intel_crtc); | |
9ed109a7 | 2623 | |
6aa23e65 JN |
2624 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && |
2625 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
10214420 DV |
2626 | /* |
2627 | * This is a big fat ugly hack. | |
2628 | * | |
2629 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2630 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2631 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2632 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2633 | * max, not what it tells us to use. | |
2634 | * | |
2635 | * Note: This will still be broken if the eDP panel is not lit | |
2636 | * up by the BIOS, and thus we can't get the mode at module | |
2637 | * load. | |
2638 | */ | |
2639 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2640 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2641 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
10214420 | 2642 | } |
11578553 | 2643 | |
22606a18 | 2644 | intel_ddi_clock_get(encoder, pipe_config); |
95a7a2ae | 2645 | |
cc3f90f0 | 2646 | if (IS_GEN9_LP(dev_priv)) |
95a7a2ae ID |
2647 | pipe_config->lane_lat_optim_mask = |
2648 | bxt_ddi_phy_get_lane_lat_optim_mask(encoder); | |
045ac3b5 JB |
2649 | } |
2650 | ||
5bfe2ac0 | 2651 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
2652 | struct intel_crtc_state *pipe_config, |
2653 | struct drm_connector_state *conn_state) | |
00c09d70 | 2654 | { |
fac5e23e | 2655 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5bfe2ac0 | 2656 | int type = encoder->type; |
eccb140b | 2657 | int port = intel_ddi_get_encoder_port(encoder); |
95a7a2ae | 2658 | int ret; |
00c09d70 | 2659 | |
5bfe2ac0 | 2660 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 2661 | |
eccb140b DV |
2662 | if (port == PORT_A) |
2663 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
2664 | ||
00c09d70 | 2665 | if (type == INTEL_OUTPUT_HDMI) |
0a478c27 | 2666 | ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); |
00c09d70 | 2667 | else |
0a478c27 | 2668 | ret = intel_dp_compute_config(encoder, pipe_config, conn_state); |
95a7a2ae | 2669 | |
cc3f90f0 | 2670 | if (IS_GEN9_LP(dev_priv) && ret) |
95a7a2ae ID |
2671 | pipe_config->lane_lat_optim_mask = |
2672 | bxt_ddi_phy_calc_lane_lat_optim_mask(encoder, | |
b284eeda | 2673 | pipe_config->lane_count); |
95a7a2ae ID |
2674 | |
2675 | return ret; | |
2676 | ||
00c09d70 PZ |
2677 | } |
2678 | ||
2679 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
bf93ba67 ID |
2680 | .reset = intel_dp_encoder_reset, |
2681 | .destroy = intel_dp_encoder_destroy, | |
00c09d70 PZ |
2682 | }; |
2683 | ||
4a28ae58 PZ |
2684 | static struct intel_connector * |
2685 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
2686 | { | |
2687 | struct intel_connector *connector; | |
2688 | enum port port = intel_dig_port->port; | |
2689 | ||
9bdbd0b9 | 2690 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2691 | if (!connector) |
2692 | return NULL; | |
2693 | ||
2694 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
2695 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
2696 | kfree(connector); | |
2697 | return NULL; | |
2698 | } | |
2699 | ||
2700 | return connector; | |
2701 | } | |
2702 | ||
2703 | static struct intel_connector * | |
2704 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
2705 | { | |
2706 | struct intel_connector *connector; | |
2707 | enum port port = intel_dig_port->port; | |
2708 | ||
9bdbd0b9 | 2709 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2710 | if (!connector) |
2711 | return NULL; | |
2712 | ||
2713 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
2714 | intel_hdmi_init_connector(intel_dig_port, connector); | |
2715 | ||
2716 | return connector; | |
2717 | } | |
2718 | ||
c39055b0 | 2719 | void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) |
00c09d70 PZ |
2720 | { |
2721 | struct intel_digital_port *intel_dig_port; | |
2722 | struct intel_encoder *intel_encoder; | |
2723 | struct drm_encoder *encoder; | |
ff662124 | 2724 | bool init_hdmi, init_dp, init_lspcon = false; |
10e7bec3 VS |
2725 | int max_lanes; |
2726 | ||
2727 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { | |
2728 | switch (port) { | |
2729 | case PORT_A: | |
2730 | max_lanes = 4; | |
2731 | break; | |
2732 | case PORT_E: | |
2733 | max_lanes = 0; | |
2734 | break; | |
2735 | default: | |
2736 | max_lanes = 4; | |
2737 | break; | |
2738 | } | |
2739 | } else { | |
2740 | switch (port) { | |
2741 | case PORT_A: | |
2742 | max_lanes = 2; | |
2743 | break; | |
2744 | case PORT_E: | |
2745 | max_lanes = 2; | |
2746 | break; | |
2747 | default: | |
2748 | max_lanes = 4; | |
2749 | break; | |
2750 | } | |
2751 | } | |
311a2094 PZ |
2752 | |
2753 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
2754 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
2755 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
ff662124 SS |
2756 | |
2757 | if (intel_bios_is_lspcon_present(dev_priv, port)) { | |
2758 | /* | |
2759 | * Lspcon device needs to be driven with DP connector | |
2760 | * with special detection sequence. So make sure DP | |
2761 | * is initialized before lspcon. | |
2762 | */ | |
2763 | init_dp = true; | |
2764 | init_lspcon = true; | |
2765 | init_hdmi = false; | |
2766 | DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); | |
2767 | } | |
2768 | ||
311a2094 | 2769 | if (!init_dp && !init_hdmi) { |
500ea70d | 2770 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
311a2094 | 2771 | port_name(port)); |
500ea70d | 2772 | return; |
311a2094 | 2773 | } |
00c09d70 | 2774 | |
b14c5679 | 2775 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
2776 | if (!intel_dig_port) |
2777 | return; | |
2778 | ||
00c09d70 PZ |
2779 | intel_encoder = &intel_dig_port->base; |
2780 | encoder = &intel_encoder->base; | |
2781 | ||
c39055b0 | 2782 | drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, |
580d8ed5 | 2783 | DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); |
00c09d70 | 2784 | |
5bfe2ac0 | 2785 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 | 2786 | intel_encoder->enable = intel_enable_ddi; |
cc3f90f0 | 2787 | if (IS_GEN9_LP(dev_priv)) |
95a7a2ae | 2788 | intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable; |
00c09d70 PZ |
2789 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
2790 | intel_encoder->disable = intel_disable_ddi; | |
2791 | intel_encoder->post_disable = intel_ddi_post_disable; | |
2792 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 2793 | intel_encoder->get_config = intel_ddi_get_config; |
bf93ba67 | 2794 | intel_encoder->suspend = intel_dp_encoder_suspend; |
62b69566 | 2795 | intel_encoder->get_power_domains = intel_ddi_get_power_domains; |
00c09d70 PZ |
2796 | |
2797 | intel_dig_port->port = port; | |
bcf53de4 SM |
2798 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
2799 | (DDI_BUF_PORT_REVERSAL | | |
2800 | DDI_A_4_LANES); | |
00c09d70 | 2801 | |
62b69566 ACO |
2802 | switch (port) { |
2803 | case PORT_A: | |
2804 | intel_dig_port->ddi_io_power_domain = | |
2805 | POWER_DOMAIN_PORT_DDI_A_IO; | |
2806 | break; | |
2807 | case PORT_B: | |
2808 | intel_dig_port->ddi_io_power_domain = | |
2809 | POWER_DOMAIN_PORT_DDI_B_IO; | |
2810 | break; | |
2811 | case PORT_C: | |
2812 | intel_dig_port->ddi_io_power_domain = | |
2813 | POWER_DOMAIN_PORT_DDI_C_IO; | |
2814 | break; | |
2815 | case PORT_D: | |
2816 | intel_dig_port->ddi_io_power_domain = | |
2817 | POWER_DOMAIN_PORT_DDI_D_IO; | |
2818 | break; | |
2819 | case PORT_E: | |
2820 | intel_dig_port->ddi_io_power_domain = | |
2821 | POWER_DOMAIN_PORT_DDI_E_IO; | |
2822 | break; | |
2823 | default: | |
2824 | MISSING_CASE(port); | |
2825 | } | |
2826 | ||
6c566dc9 MR |
2827 | /* |
2828 | * Bspec says that DDI_A_4_LANES is the only supported configuration | |
2829 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP | |
2830 | * wasn't lit up at boot. Force this bit on in our internal | |
2831 | * configuration so that we use the proper lane count for our | |
2832 | * calculations. | |
2833 | */ | |
cc3f90f0 | 2834 | if (IS_GEN9_LP(dev_priv) && port == PORT_A) { |
6c566dc9 MR |
2835 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
2836 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); | |
2837 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; | |
ed8d60f4 | 2838 | max_lanes = 4; |
6c566dc9 MR |
2839 | } |
2840 | } | |
2841 | ||
ed8d60f4 MR |
2842 | intel_dig_port->max_lanes = max_lanes; |
2843 | ||
00c09d70 | 2844 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
79f255a0 | 2845 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 2846 | intel_encoder->port = port; |
f68d697e | 2847 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 2848 | intel_encoder->cloneable = 0; |
00c09d70 | 2849 | |
385e4de0 VS |
2850 | intel_infoframe_init(intel_dig_port); |
2851 | ||
f68d697e CW |
2852 | if (init_dp) { |
2853 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
2854 | goto err; | |
13cf5504 | 2855 | |
f68d697e | 2856 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
ca4c3890 | 2857 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
f68d697e | 2858 | } |
21a8e6a4 | 2859 | |
311a2094 PZ |
2860 | /* In theory we don't need the encoder->type check, but leave it just in |
2861 | * case we have some really bad VBTs... */ | |
f68d697e CW |
2862 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
2863 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
2864 | goto err; | |
21a8e6a4 | 2865 | } |
f68d697e | 2866 | |
ff662124 SS |
2867 | if (init_lspcon) { |
2868 | if (lspcon_init(intel_dig_port)) | |
2869 | /* TODO: handle hdmi info frame part */ | |
2870 | DRM_DEBUG_KMS("LSPCON init success on port %c\n", | |
2871 | port_name(port)); | |
2872 | else | |
2873 | /* | |
2874 | * LSPCON init faied, but DP init was success, so | |
2875 | * lets try to drive as DP++ port. | |
2876 | */ | |
2877 | DRM_ERROR("LSPCON init failed on port %c\n", | |
2878 | port_name(port)); | |
2879 | } | |
2880 | ||
f68d697e CW |
2881 | return; |
2882 | ||
2883 | err: | |
2884 | drm_encoder_cleanup(encoder); | |
2885 | kfree(intel_dig_port); | |
00c09d70 | 2886 | } |